Optimized Structure of MOSFET Based on FinFET Technology and Its Preparation Method

Abstract

The present invention relates to the technical field of MOS semiconductors, and discloses an optimized structure of a MOSFET based on FinFET technology and a preparation method thereof, which comprises a plurality of mutually juxtaposed MOS cells. The MOS cell includes a drain electrode, a semiconductor epitaxial layer, a source electrode, and a gate electrode. The semiconductor epitaxial layer internally includes an N substrate layer, an N drift layer, an N well layer, a P well layer, and a P- layer. The cross-sectional profile of the N substrate layer in a single MOS cell is in a middle-convex shape; a plurality of strip-shaped polysilicons are provided in the P- layer on the left side inside a single MOS cell, and the strip-shaped polysilicons are only in ohmic contact with the source electrode. In the present invention, the strip-shaped polysilicon on the left P- layer and the block-shaped polysilicon on the right are only in ohmic contact with the source electrode to form a low-resistance path, reduce the parasitic resistance, increase the conduction current density, and through the distribution design of the polysilicon, reduce the electric field concentration inside the device, reduce the hot carrier effect, and improve the reliability.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a MOSFET optimized structure based on FinFET technology and a preparation method thereof. Background Art

[0002] FinFET (Fin Field-Effect Transistor) is a three-dimensional transistor structure, whose core feature is to achieve multi-sided wrapping of the gate to the channel (usually three-sided or ring gate) through a vertical fin-shaped (Fin) semiconductor channel. Compared with traditional planar MOSFET, the optimization of FinFET is mainly reflected in: 1. Reducing drain-induced barrier lowering (DIBL) and subthreshold leakage current by enhancing the electrostatic control of the gate to the channel. 2. Increasing the on-current by connecting multiple fins in parallel or increasing the fin height (Hfin). 3. Steeper subthreshold swing (SS) and lower threshold voltage (Vth) fluctuations.

[0003] The existing patent discloses a high-reliability SIC-MOSFET terminal structure (publication number CN222190737U), which belongs to the field of semiconductor device technology. The high-reliability SIC-MOSFET terminal structure includes a source and a drain. The source is the input end of the MOSFET, which is used to supply current in the circuit, and the drain is the output end of the MOSFET, which is used to extract current. The FinFET structure proposed in the technology disclosed in the patent still increases the parasitic resistance due to excessive path resistance, which will further increase the hot carrier effect, causing the device to have exponential performance degradation at high temperatures. Summary of the invention

[0004] In order to solve the existing technical problems, the present invention provides a MOSFET optimized structure based on FinFET technology and a preparation method thereof, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, an optimized MOSFET structure based on FinFET technology, including a plurality of mutually parallel MOS cells, wherein the MOS cell includes a drain, a semiconductor epitaxial layer, a source, and a gate, wherein the semiconductor epitaxial layer includes an N substrate layer, an N drift layer, an N well layer, a P well layer, and a P-layer, and the cross-sectional profile of the N substrate layer in a single MOS cell is a convex shape in the middle;

[0006] A plurality of strip-shaped polysilicon are provided in the P-layer on the left side inside a single MOS cell, and the strip-shaped polysilicon is only in ohmic contact with the source electrode;

[0007] Inside a single MOS cell, there is a bulk polysilicon in the P-layer on the right side, and the bulk polysilicon is only in ohmic contact with the source electrode.

[0008] Furthermore, there is a left high-resistance doping layer in the P-layer on the left side inside a single MOS cell, and there is a right high-resistance doping layer in the P-layer on the right side inside a single MOS cell.

[0009] Furthermore, both the left high-resistance doping layer and the right high-resistance doping layer are located at the junction between the source electrode and the P-layer.

[0010] Furthermore, there are several strip-shaped metals inside the bulk polysilicon, and the top of the strip-shaped metal is in contact with the source electrode.

[0011] Furthermore, there are several composite metals inside the N-well layer, and the top of the composite metal is in contact with the source electrode.

[0012] A preparation method for an optimized structure of a MOSFET based on FinFET technology, the specific steps include:

[0013] S1. Inject phosphorus and arsenic elements on the top silicon layer with a thickness of 20 nm of the semiconductor epitaxial layer to form an active region;

[0014] S2. Use EUV lithography and RIE etching to form an array of strip-shaped polysilicon and bulk polysilicon in the active region;

[0015] S3. Continue to integrate a metal heat dissipation structure of strip-shaped metals and composite metals in the active region;

[0016] S4. Realize doping activation and strain layer protection through pulsed laser annealing;

[0017] S5. Perform a performance improvement detection on the activated MOSFET structure.

[0018] Furthermore, in the step S1, the dose of phosphorus injection is , the energy during injection is 2 keV, and the dose of arsenic injection is , and the energy during injection is 5 keV.

[0019] Furthermore, in the step S5, according to the resistance change amount and response speed of the MOSFET structure to judge the performance improvement size of the MOSFET structure, then there is:

[0020]

[0021] In the formula, represents the performance coefficient of this MOSFET structure; An index used to control the sensitivity of the model formula, an empirical constant that determines the rate of change of the performance coefficient; Represents the change in resistance of the MOSFET structure from 25°C to 100°C, in mΩ; Represents the proportion of the number of MOSFET structures used to detect the change in resistance in the total number of samples; Represents the response speed of the MOSFET structure, in ns; The proportion of the number of MOSFET structures used to detect the response speed in the total number of samples.

[0022] The optimized MOSFET structure based on FinFET technology and its manufacturing method provided by the present invention. Compared with the prior art, the effects achieved by this method are as follows:

[0023] 1. In the present invention, the strip-shaped polysilicon on the left P-layer and the bulk polysilicon on the right are only in ohmic contact with the source electrode, forming a low-resistance path, reducing the parasitic resistance, increasing the on-current density, and through the distribution design of this polysilicon, the electric field concentration inside the device is reduced, the hot carrier effect is reduced, and the reliability is improved.

[0024] 2. In the present invention, the left and right high-resistance doping layers are located at the junction of the source electrode and the P-layer, adjusting the contact resistance and blocking the lateral diffusion of carriers, significantly reducing the leakage current, and this high-resistance layer disperses the thermal effect, reducing the performance degradation at high temperatures, and improving the stability of the device in a wide temperature range.

[0025] 3. In the present invention, the strip-shaped metal inside the bulk polysilicon is directly in contact with the source electrode, enhancing the local heat conduction ability, avoiding the formation of hot spots, improving the power tolerance, and the introduction of this metal structure optimizes the interface contact between the source electrode and the polysilicon, reducing the current transmission loss and increasing the switching speed. Moreover, the collaborative design of the strip-shaped metal and the polysilicon simplifies the process flow, while taking into account both electrical performance and heat dissipation requirements.

[0026] 4. In the present invention, the composite metal inside the N-well layer is directly connected to the source electrode, reducing the contact resistance between the N-well layer and the source electrode, improving the on-efficiency, and the composite metal structure increases the mechanical strength of the device, reducing the stress damage during the manufacturing or packaging process, improving the yield, and the composite metal has both conductive and supporting functions, extending the device life while optimizing the electrical performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic structural diagram of Embodiment 1 in the present invention;

[0028] Figure 2 It is a schematic structural diagram of Embodiment 2 in the present invention;

[0029] Figure 3 It is a schematic structural diagram of Embodiment 3 in the present invention;

[0030] Figure 4 This is a schematic diagram of the structure of Embodiment 4 of the present invention;

[0031] Figure 5 The performance coefficient c in the present invention is subject to the empirical constant , schematic diagram of the influence of resistance change R.

[0032] In the figure: 1. drain; 2. source; 3. gate; 4. N substrate layer; 5. N drift layer; 6. N well layer; 7. P well layer; 8. P-layer; 9. strip polysilicon; 10. block polysilicon; 11. left high-resistance doped layer; 12. right high-resistance doped layer; 13. strip metal; 14. composite metal. DETAILED DESCRIPTION

[0033] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] like Figures 1-5 As shown, the preparation method of the optimized structure of MOSFET based on FinFET technology includes the following specific steps:

[0035] Step 1: Phosphorus and arsenic are implanted on the top silicon layer of the semiconductor epitaxial layer with a thickness of 20 nm to form an active region; the dose of implanted phosphorus is The energy during injection is 2keV, and the dose of injected arsenic is The energy during injection is 5keV.

[0036] Step 2: EUV lithography and RIE etching are used to form an array of strip-shaped polysilicon 9 and block-shaped polysilicon 10 in the active area.

[0037] Step 3: Continue to integrate the metal heat dissipation structure of the strip metal 13 and the composite metal 14 in the active area.

[0038] Step 4: Realize doping activation and strain layer protection through pulsed laser annealing.

[0039] Step 5: Test the performance improvement of the activated MOSFET structure. The performance improvement of the MOSFET structure can be determined based on the resistance change and response speed of the MOSFET structure. Then:

[0040]

[0041] In the formula, represents the performance coefficient of the MOSFET structure; It represents the index used to control the sensitivity of the model formula and the empirical constant that determines the rate of change of the performance coefficient; It represents the change in resistance of the MOSFET structure from 25 °C to 100 °C, with the unit of mΩ; It represents the proportion of the number of MOSFET structures used to detect the change in resistance in the total number of samples; It represents the response speed of the MOSFET structure, with the unit of ns; It represents the proportion of the number of MOSFET structures used to detect the response speed in the total number of samples.

[0042] Among them, for the change in resistance of the MOSFET structure from 25 °C to 100 °C, take (mΩ), and for the proportion of the number of MOSFET structures used to detect the change in resistance in the total number of samples, take . For the response speed of the MOSFET structure, take (ns), and for the proportion of the number of MOSFET structures used to detect the response speed in the total number of samples, take .

[0043] Among them, for the index used to control the sensitivity of this model formula, the empirical constant determining the change rate of the performance coefficient takes , then there is:

[0044]

[0045] It can be known from the above calculation that the performance coefficient of the device detected this time is ; if the performance coefficient of the traditional device detected is , then it means that the performance of this device has increased by 12.4%.

[0046] Example 1

[0047] Such as Figure 1As shown, according to one aspect of the present invention, there is provided an optimized MOSFET structure based on FinFET technology, which is composed of a plurality of juxtaposed MOS cells. Each MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 2, and a gate 3. The semiconductor epitaxial layer internally includes an N substrate layer 4, an N drift layer 5, an N well layer 6, a P well layer 7, and a P- layer 8. The cross-sectional profile of the N substrate layer 4 within a single MOS cell is in a middle-convex shape; within the P- layer 8 on the left side inside a single MOS cell, there are a plurality of strip-shaped polysilicons 9, and the strip-shaped polysilicons 9 are in ohmic contact only with the source 2; within the P- layer 8 on the right side inside a single MOS cell, there is a block-shaped polysilicon 10, and the block-shaped polysilicon 10 is in ohmic contact only with the source 2. The middle-convex cross-sectional profile of the N substrate layer 4 enables the gate to wrap the channel more tightly, enhancing electrostatic control, effectively suppressing drain-induced barrier lowering (DIBL) and subthreshold leakage current. The strip-shaped polysilicons 9 on the left side of the P- layer 8 and the block-shaped polysilicon 10 on the right side are in ohmic contact only with the source, forming a low-resistance path, reducing parasitic resistance, increasing the on-state current density, and through the distribution design of this polysilicon, reducing the electric field concentration inside the device, reducing the hot carrier effect, and enhancing reliability.

[0048] Embodiment 2

[0049] As Figure 2 shown, within the P- layer 8 on the left side inside a single MOS cell, there is a left high-resistance doping layer 11, and within the P- layer 8 on the right side inside a single MOS cell, there is a right high-resistance doping layer 12. Both the left high-resistance doping layer 11 and the right high-resistance doping layer 12 are located at the junction between the source 2 and the P- layer 8. The left and right high-resistance doping layers are located at the junction of the source 2 and the P- layer 8, adjusting the contact resistance and blocking the lateral diffusion of carriers, significantly reducing the leakage current, and this high-resistance layer disperses the thermal effect, reducing the performance degradation at high temperatures, and enhancing the stability of the device within a wide temperature range.

[0050] Embodiment 3

[0051] As Figure 3 shown, within the block-shaped polysilicon 10, there are also a plurality of strip-shaped metals 13, and the top of the strip-shaped metals 13 is in contact with the source 2. The strip-shaped metals 13 within the block-shaped polysilicon 10 are directly in contact with the source 2, enhancing the local heat conduction ability, avoiding the formation of hot spots, enhancing the power tolerance, and the introduction of this metal structure optimizes the interface contact between the source 2 and the polysilicon, reducing the current transmission loss, and increasing the switching speed. Moreover, the collaborative design of the strip-shaped metals 13 and the polysilicon simplifies the process flow while taking into account both electrical performance and heat dissipation requirements.

[0052] Embodiment 4

[0053] As Figure 4As shown, several composite metals 14 are further provided inside the N-well layer 6, and the top of the composite metal 14 is in contact with the source electrode 2. The composite metal 14 in the N-well layer 6 is directly connected to the source electrode 2, reducing the contact resistance between the N-well layer 6 and the source electrode 2, improving the conduction efficiency. Moreover, the structure of the composite metal 14 increases the mechanical strength of the device, reduces the stress damage during the preparation or packaging process, improves the yield. And the composite metal 14 has both conductive and supporting functions, extending the device life while optimizing the electrical performance.

[0054] The above embodiments only represent several implementation manners of the present invention. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the scope of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the appended claims.

Claims

1. The optimized structure of MOSFET based on FinFET technology, which is composed of several juxtaposed MOS cells. Each MOS cell includes a drain (1), a semiconductor epitaxial layer, a source (2), and a gate (3). Inside the semiconductor epitaxial layer, from bottom to top, there are an N substrate layer (4), an N drift layer (5), a P well layer (7), and an N well layer (6) in sequence. The semiconductor epitaxial layer also includes a P- layer (8), and the P- layer (8) is located on both sides of a single MOS cell and contacts the P well layer (7). It is characterized in that: The cross-sectional profile of the N substrate layer (4) within a single MOS cell is in a shape of a middle bulge; Inside the left side of a single MOS cell, there are a number of strip-shaped polysilicons (9) provided within the P- layer (8), and the strip-shaped polysilicons (9) are in ohmic contact only with the source electrode (2); Inside the right side of a single MOS cell, there is a block-shaped polysilicon (10) provided within the P- layer (8), and the block-shaped polysilicon (10) is in ohmic contact only with the source electrode (2).

2. The optimized MOSFET structure based on FinFET technology according to claim 1, characterized in that: Inside the left side of a single MOS cell, there is a left high-resistance doping layer (11) provided within the P- layer (8), and inside the right side of a single MOS cell, there is a right high-resistance doping layer (12) provided within the P- layer (8).

3. The optimized MOSFET structure based on FinFET technology according to claim 2, characterized in that: Both the left high-resistance doping layer (11) and the right high-resistance doping layer (12) are located at the junction between the source electrode (2) and the P- layer (8).

4. The optimized MOSFET structure based on FinFET technology according to claim 1, characterized in that: Inside the block-shaped polysilicon (10), there are also a number of strip-shaped metals (13), and the top of the strip-shaped metals (13) is in contact with the source electrode (2).

5. The optimized MOSFET structure based on FinFET technology according to claim 1 or 2, characterized in that: Inside the N well layer (6), there are also a number of composite metals (14), and the top of the composite metals (14) is in contact with the source electrode (2).

6. Preparation method of optimized structure of MOSFET based on FinFET technology, characterized in that, Applied to the structure described in any one of claims 1-5, the preparation method of the MOSFET optimized structure based on FinFET technology specifically includes the following steps: S1. Inject phosphorus and arsenic elements on the top silicon layer with a thickness of 20 nm of the semiconductor epitaxial layer to form an active region; S2. Use EUV lithography and RIE etching to form an array of strip-shaped polysilicons (9) and block-shaped polysilicons (10) in the active region; S3. Continuously integrate the metal heat dissipation structure of strip-shaped metals (13) and composite metals (14) in the active region; S4. Achieve doping activation and strain layer protection through pulsed laser annealing; S5. Conduct a performance improvement detection on the activated MOSFET structure.

7. The manufacturing method of the optimized structure of MOSFET based on FinFET technology according to claim 6, characterized in that: The dose of phosphorus injected in step S1 is , the energy during injection is 2 keV, and the dose of arsenic injected is , and the energy during injection is 5 keV.

8. The manufacturing method of the optimized structure of MOSFET based on FinFET technology according to claim 6, characterized in that: In the step S5, according to the resistance change amount and response speed of the MOSFET structure to judge the magnitude of the performance improvement of the MOSFET structure, then there is: ； In the formula, represents the performance coefficient of the MOSFET structure; represents the index used to control the sensitivity of the performance coefficient, an empirical constant that determines the rate of change of the performance coefficient; represents the change in resistance of the MOSFET structure when the temperature rises from 25°C to 100°C, with the unit of mΩ; represents the proportion of the number of MOSFET structures used to detect the change in resistance in the total number of samples; represents the response speed of the MOSFET structure, with the unit of ns; represents the proportion of the number of MOSFET structures used to detect the response speed in the total number of samples.

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