Electrostatic discharge protection device and forming method thereof

Abstract

The invention discloses an electrostatic discharge protection device. The electrostatic discharge protection device comprises a semiconductor substrate; a first well region having a first conductivity type and located in the semiconductor substrate; and a second well region having a first conductivity type and located in the semiconductor substrate and adjacent to the first well region, in which a first bottom of the first well region and a second bottom of the second well region are connected to each other and have different profiles, in which the first well region and the second well region have different doping concentrations. According to the invention, the first well region and the second well region with different doping concentrations can be formed in the same process step by using the same mask, so that the electrostatic discharge protection device with lower parasitic capacitance can be formed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an electrostatic discharge protection device and a forming method thereof. Background Art

[0002] Electrostatic discharge (ESD) is the phenomenon of releasing and transferring charge between a semiconductor device (e.g., a semiconductor chip) and an external object (e.g., a human body). ESD releases a large amount of charge in a short period of time, so the energy generated by ESD is much higher than the semiconductor device's tolerance, which may cause temporary functional failure or even permanent damage to the semiconductor device. Therefore, an ESD clamp circuit is set in the semiconductor device to provide an electrostatic discharge path that effectively protects the semiconductor device, thereby improving the reliability and service life of the semiconductor device. However, for high-frequency circuits, parasitic capacitors in traditional ESD protection circuits (using diodes) may be affected by the electrical performance of RF circuits and high-speed circuits. Summary of the invention

[0003] In view of this, the present invention provides an electrostatic discharge protection device to solve the above problem.

[0004] According to a first aspect of the present invention, an electrostatic discharge protection device is disclosed, comprising:

[0005] Semiconductor substrates;

[0006] a first well region having a first conductivity type and located in the semiconductor substrate; and

[0007] A second well region has a first conductivity type and is located in the semiconductor substrate and adjacent to the first well region, wherein a first bottom of the first well region and a second bottom of the second well region are connected to each other and have different profiles, wherein the first well region and the second well region have different doping concentrations.

[0008] Furthermore, the first doping concentration of the first well region is less than the second doping concentration of the second well region, so that the capacitance value of the first parasitic capacitor formed by the first well region can be reduced, thereby reducing operating loss and protecting the internal circuit.

[0009] Furthermore, the first bottom of the first well region has a corrugated bottom surface, and the second bottom of the second well region has an arc-shaped bottom surface. Thus, when manufacturing the first well region, a mask with a different pattern from that of the second well region can be used, so that the first well region and the second well region with different doping concentrations and bottom surfaces can be formed in the same process.

[0010] Further, the waveform bottom surface of the first well region includes a plurality of wave peaks and a plurality of wave valleys, wherein the wave peaks are closer to the upper surface of the semiconductor substrate than the wave valleys. Thus, a mask with a different pattern from that of the second well region can be used when manufacturing the first well region, so that the first well region and the second well region with different doping concentrations and bottom surfaces can be formed in the same manufacturing process.

[0011] Further, the first well region has a first sub-region and a second sub-region arranged alternately with the first sub-region, wherein the wave valley is the bottom surface of the first sub-region, and the wave peak is the bottom surface of the second sub-region. Thus, a mask with a different pattern from that of the second well region can be used when manufacturing the first well region, so that the first well region and the second well region with different doping concentrations and bottom surfaces can be formed in the same manufacturing process.

[0012] Further, the first sub-region has a first depth, and the second sub-region has a second depth different from the first depth. Thus, a mask with a different pattern from that of the second well region can be used when manufacturing the first well region, so that the first well region and the second well region with different doping concentrations and bottom surfaces can be formed in the same manufacturing process.

[0013] Further, the first depth is measured from the lowest point of one of the wave valleys to the upper surface of the first well region, and the second depth is measured from the highest point of one of the wave peaks to the upper surface of the first well region. Thus, a mask with a different pattern from that of the second well region can be used when manufacturing the first well region, so that the first well region and the second well region with different doping concentrations and bottom surfaces can be formed in the same manufacturing process.

[0014] Further, the arc-shaped bottom surface of the second well region includes only one wave valley, and the one wave valley protrudes in a direction away from the upper surface of the semiconductor substrate. Thus, a mask with a different pattern from that of the second well region can be used when manufacturing the first well region, so that the first well region and the second well region with different doping concentrations and bottom surfaces can be formed in the same manufacturing process.

[0015] Further, a third depth measured from the lowest point of the wave valley of the second well region to the upper surface of the second well region is equal to the first depth. Therefore, the first well region and the second well region with different doping concentrations and bottom surfaces can be formed in the same manufacturing process.

[0016] Further, it further includes:

[0017] A third well region, having a second conductivity type, and being located in the semiconductor substrate and separated from the first well region and the second well region; and

[0018] A fourth well region, having a second conductivity type, is located in the semiconductor substrate and is separated from the first well region and the second well region. The third bottom of the third well region is connected to the fourth bottom of the fourth well region, and the third bottom of the third well region and the fourth bottom of the fourth well region have different profiles and different doping concentrations. Thus, a second ESD protection unit that jointly protects the internal circuit with the first ESD protection unit is formed, and the second ESD protection unit corresponds to or is similar to the first ESD protection unit.

[0019] Further, the third bottom of the third well region has a waveform bottom surface, and the fourth bottom of the fourth well region has an arc-shaped bottom surface.

[0020] Further, the waveform bottom surface of the third well region includes a plurality of wave peaks and a plurality of wave valleys, where the wave peaks are closer to the upper surface of the semiconductor substrate than the wave valleys. The arc-shaped bottom surface of the fourth well region includes only one wave valley, and the one wave valley protrudes in a direction away from the upper surface of the semiconductor substrate.

[0021] Further, a fourth depth measured from the lowest point of one of the wave valleys of the third well region to the upper surface of the third well region is equal to a fifth depth measured from the lowest point of the one wave valley of the fourth well region to the upper surface of the fourth well region.

[0022] According to a second aspect of the present invention, an electrostatic discharge protection device is disclosed, including:

[0023] A semiconductor substrate;

[0024] A first well region, having a first conductivity type, and located in the semiconductor substrate; and

[0025] A second well region, having a first conductivity type, and located in the semiconductor substrate and adjacent to the first well region. The first number of the first arc-shaped bottoms of the first well region is different from the second number of the second arc-shaped bottoms of the second well region, and the first well region and the second well region have different doping concentrations. In the present invention, the first well region and the second well region with different numbers of arc-shaped bottoms and doping concentrations are formed in the same manufacturing process, so that manufacturing steps and mask costs can be saved, facilitating the formation of an ESD protection device with lower parasitic capacitance, improving the protection of the internal circuit, and reducing production costs at the same time.

[0026] Further, the first number of the first arc-shaped bottoms of the first well region is greater than or equal to 2, and the second number of the second arc-shaped bottoms of the second well region is equal to 1. Thus, the first well region and the second well region can be formed simultaneously in the same manufacturing steps using the same mask during manufacturing.

[0027] Further, the first arc-shaped bottoms are sequentially connected to form the waveform bottom surface of the first well region.

[0028] Further, a first depth measured from a lowest point of one of the first arcuate bottoms of the first well region to an upper surface of the first well region is equal to a second depth measured from a lowest point of the second arcuate bottom of the second well region to an upper surface of the second well region.

[0029] According to a third aspect of the present invention, a method for forming an electrostatic discharge protection device is disclosed, including:

[0030] Providing a semiconductor substrate;

[0031] Performing an implantation process to simultaneously form a first doped region and a second doped region in the semiconductor substrate, wherein the first doped region and the second doped region have the first conductivity type and are adjacent to each other, and wherein a first discontinuous portion is present in the first doped region; and

[0032] Performing an annealing process to form a first well region from the first doped region and a second well region from the second doped region, wherein the first well region and the second well region have different doping concentrations. Thus, the first well region and the second well region can be simultaneously formed in the same manufacturing step using the same mask during manufacturing.

[0033] Further, the first well region is formed by diffusing a part of the first dopants in the first doped region into the first discontinuous portion. Thus, the doping concentration of the first well region will be relatively low, lower than that of the second well region.

[0034] Further, the second doped region is formed without a discontinuous portion inside. Thus, the mask pattern for forming the second well region is different from that of the first well region, and the doping concentration of the first well region will be relatively low, lower than that of the second well region.

[0035] The electrostatic discharge protection device of the present invention includes: a semiconductor substrate; a first well region having the first conductivity type and located in the semiconductor substrate; and a second well region having the first conductivity type and located in the semiconductor substrate and adjacent to the first well region, wherein a first bottom of the first well region and a second bottom of the second well region are connected to each other and have different profiles, and wherein the first well region and the second well region have different doping concentrations. The present invention can form the first well region and the second well region with different doping concentrations in the same manufacturing step using the same mask, so as to form an ESD protection device with a lower parasitic capacitance. The present invention does not need to form well regions with different doping concentrations in two manufacturing steps using two masks respectively, nor does it need to form an ESD device by connecting multiple diodes in series. Therefore, the present invention can reduce the mask cost and manufacturing steps, and has a smaller device size. Description of the Drawings

[0036] Figure 1 Schematic connection diagram of an electrostatic discharge protection device provided by an embodiment of the present invention;

[0037] Figure 2 is according to some embodiments of the present invention Figure 1 Schematic cross-sectional view of an electrostatic discharge protection device;

[0038] Figure 3 and Figure 4 is a schematic cross-sectional view of an intermediate stage of forming an electrostatic discharge protection device according to some embodiments of the present invention; and

[0039] Figure 5A 、 Figure 5B and Figure 5C are Figure 3 Plan views showing the arrangement of discontinuous portions of doping regions for forming a well region with a lighter doping concentration of an electrostatic discharge protection device according to some embodiments of the present invention. Detailed Description of the Invention

[0040] In the following detailed description of the embodiments of the present invention, reference is made to the accompanying drawings, which form a part of the present invention and in which are shown, by way of illustration, specific preferred embodiments in which the present invention may be practiced. The embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it should be understood that other embodiments may be utilized and that mechanical, structural, and procedural changes may be made without departing from the spirit and scope of the present invention. The present invention. Accordingly, the following detailed description should not be construed as limiting, and the scope of the embodiments of the present invention is defined only by the appended claims. The drawings described are merely illustrative and not restrictive. In the drawings, for purposes of illustration, the dimensions of some elements may be exaggerated and not drawn to scale. In the practice of the present invention, the dimensions and relative dimensions do not correspond to actual dimensions.

[0041] It will be understood that although the terms "first", "second", "third", "primary", "secondary", etc. may be used herein to describe various components, components, regions, layers, and / or parts, these components, components, regions, these layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one component, component, region, layer, or part from another region, layer, or part. Thus, without departing from the teachings of the inventive concept, the first or primary component, component, region, layer, or part discussed below may be referred to as the second or secondary component, component, region, layer, or part.

[0042] In addition, for ease of description, spatial relative terms such as "below", "beneath", "under", "above", "over" and the like may be used herein to describe the relationship of one component or feature to another as shown in the figures. The spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. Additionally, it will be understood that when a "layer" is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.

[0043] The terms "about", "substantially" and "approximately" generally mean within ±20% of a specified value, or within ±10% of the specified value, or within ±5% of the specified value, or within ±3% of the specified value, or within ±2% of the specified value, or within ±1% of the specified value, or within ±0.5% of the specified value. The specified values of the present invention are approximate values. When not specifically described, the specified values include the meanings of "about", "substantially" and "approximately". The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present invention. As used herein, the singular terms "a", "an" and "the", "said" are also intended to include the plural forms unless the context clearly indicates otherwise. The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the inventive concept. As used herein, the singular forms "a", "an" and "the", "said" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0044] It will be understood that when a "component" or "layer" is referred to as being "on", "connected to", "coupled to" or "adjacent to" another component or layer, it may be directly on, connected to, coupled to or adjacent to the other component or layer, or there may be intervening components or layers. In contrast, when a component is referred to as being "directly on", "directly connected to", "directly coupled to" or "immediately adjacent to" another component or layer, there are no intervening components or layers.

[0045] Note: (i) Like features will be represented by like reference numerals throughout the figures and need not be described in detail in each figure in which they appear, and (ii) a series of figures may show different aspects of a single item, each aspect being associated with various reference labels that may appear throughout the sequence or may appear only in selected figures of the sequence.

[0046] An electrostatic discharge (ESD) device is usually disposed between an input / output (IO) pad and an internal circuit to protect the internal circuit. One current ESD device is composed of diodes formed by the low-voltage P-type well region / N-type well region of a metal-oxide-semiconductor (MOS) device sharing the internal circuit. However, in high-frequency circuit applications, the parasitic capacitance of the ESD device may cause an increase in signal loss, thus affecting the performance of the internal circuit.

[0047] There are two methods to solve the above problems. The first is to use two different masks to separately form the P-type / N-type well regions of the MOS device and the P-type well / N-type well regions of the ESD device in different implantation processes. The P-type well / N-type well regions of the ESD device can have a reduced doping concentration, thereby reducing the parasitic capacitance of the diode. The second is to form an ESD device including two or more diodes connected in series to reduce the total capacitance of the parasitic capacitor of the ESD device. However, the first method results in an increase in mask cost and manufacturing cost. The second method results in an increase in the area of the semiconductor device. According to the requirements of high-frequency circuit applications, it becomes increasingly necessary to provide an ESD device that reduces parasitic capacitance without adding an extra mask and maintains a small device size.

[0048] Figure 1 FIG. 7 is a schematic connection diagram of an electrostatic discharge (ESD) protection device 500 disposed in a system 600 according to some embodiments of the present invention. Figure 2 is according to some embodiments of the present invention Figure 1 FIG. 11 is a schematic cross-sectional view of the ESD protection device 500 according to some embodiments of the present invention. The system 600 includes an internal circuit 400 and an electrostatic discharge (ESD) protection device 500 for protecting the internal circuit 400. The internal circuit 400 is electrically connected to the input / output terminal IO (I / O), the power supply terminal VDD, and the ground terminal VSS of the system 600. In some embodiments, the ESD protection device 500 includes a first ESD protection unit 500-1 and a second ESD protection unit 500-2. The first ESD protection unit 500-1 is electrically connected between the input / output terminal IO and the power supply terminal VDD of the system 600 to prevent an electrostatic discharge current from flowing through the internal circuit 400. The second ESD protection unit 500-2 is electrically connected between the input / output terminal IO and the ground terminal VSS of the system 600 to prevent an electrostatic discharge current from flowing through the internal circuit 400.

[0049] As Figure 2As shown, the ESD protection device 500 includes a semiconductor substrate 200, and a first ESD protection unit 500-1 and a second ESD protection unit 500-2 disposed in the semiconductor substrate 200. In some embodiments, the semiconductor substrate 200 may be a P-type semiconductor substrate 200. The first ESD protection unit 500-1 includes a first well region NW1, a first heavily doped region P1, a second well region NW2, and a second heavily doped region N1. The first well region NW1 and the second well region NW2 are located in the semiconductor substrate 200. In some embodiments, both the first well region NW1 and the second well region NW2 have a first conductivity type. For example, when the first conductivity type is N-type, the first well region NW1 and the second well region NW2 are N-type. Additionally, the first well region NW1 and the second well region NW2, and the semiconductor substrate 200 may have opposite conductivity types. Each of the first well region NW1 and the second well region NW2 has a heavily doped region formed thereon. For example, the first heavily doped region P1 is located on the first well region NW1. The second heavily doped region N1 is located on the second well region NW2. In some embodiments, the first heavily doped region P1 has a second conductivity type, and the second heavily doped region N1 has a first conductivity type. For example, when the first conductivity type is N-type and the second conductivity type is P-type, the first heavily doped region P1 is a P-type heavily doped region P1, and the second heavily doped region N1 is an N-type heavily doped region N1. In some embodiments, the semiconductor substrate 200 may be a silicon substrate.

[0050] The first well region NW1 and the second well region NW2 are arranged side by side along a direction 100 (a direction substantially parallel to the upper surface 200T of the semiconductor substrate 200) and are adjacent to each other. In some embodiments, the second heavily doped region N1 and the first heavily doped region P1 are spaced apart from each other by an isolation member 201 (e.g., a shallow trench isolation (STI)). An interface 202 may exist between the first well region NW1 and the second well region NW2, and the interface 202 may be located below the isolation member 201. In some embodiments, a first bottom NW1B of the first well region NW1 is connected to and in contact with (direct contact) a second bottom NW2B of the second well region NW2.

[0051] In some embodiments, the first bottom NW1B of the first well region NW1 and the second bottom NW2B of the second well region NW2 have different profiles. For example, the first bottom NW1B of the first well region NW1 may have a wavy surface (or undulating surface). The second bottom NW2B of the second well region NW2 may have an arc surface. The first bottom NW1B of the first well region NW1 may have a Figure 2The waveform profile (or wavy profile) shown. The second bottom NW2B of the second well region NW2 may have an arc profile as shown in Figure 2 . In some embodiments, the first bottom NW1B of the first well region NW1 may be referred to as the wave bottom surface, and the bottom surface of the second bottom NW2B of the second well region NW2 may be referred to as the arc bottom surface. In some embodiments, the first well region NW1 has a first sub-region SR1 and a second sub-region SR2 arranged alternately with the first sub-region SR1. In some embodiments, the number of the first sub-regions SR1 is greater than or equal to 2, and the number of the first sub-regions SR1 is greater than or equal to 2. The first sub-region SR1 may have a first depth (or height) H1. The second sub-region SR2 may have a second depth H2 different from the first depth H1. For example, the first sub-region SR1 may have a convex bottom, and the second sub-region SR2 may have a concave bottom. The convex bottom of the first sub-region SR1 protrudes in a direction away from the upper surface 200T of the semiconductor substrate 200 (or the upper surface of the first well region NW1). The concave bottom of the second sub-region SR2 is recessed in a direction close to the upper surface 200T of the semiconductor substrate 200 (or the upper surface of the first well region NW1). In addition, the first depth H1 of the first sub-region SR1 having a convex bottom may be deeper than the second depth H2 of the second sub-region SR2 having a concave bottom. In some embodiments, the first depth H1 is measured from the bottommost part of the convex bottom of the first sub-region SR1 to the upper surface of the first well region NW1. In some embodiments, the second depth H2 is measured from the topmost part of the concave bottom of the second sub-region SR2 to the upper surface of the first well region NW1. In some embodiments, as shown in Figure 2As shown, the waveform (corrugated or wavy) contour of the first bottom NW1B (or the waveform bottom surface of the first well region NW1) includes a plurality of wave peaks 210 and a plurality of wave valleys 220. The wave valleys 210 are closer to the upper surface of the first well region NW1 (or the upper surface 200T of the semiconductor substrate 200) than the wave valleys 220. In some embodiments, the wave valleys 220 are the contours of the bottoms of the first sub-regions SR1, and the wave peaks 210 are the contours of the bottoms of the second sub-regions SR2. In some embodiments, the wave valleys 220 are the bottom surfaces of the first sub-regions SR1, and the wave peaks 210 are the bottom surfaces of the second sub-regions SR2. The first depth H1 is the distance measured from one of the wave valleys 220 (or the lowest point of one of the wave valleys 220) to the upper surface of the first well region NW1, and the second depth H2 is the distance measured from one of the wave peaks 210 (or the highest point of one of the wave peaks 210) to the upper surface of the first well region NW1. In some embodiments, the number of wave peaks 210 is greater than or equal to 2, and the number of wave valleys 220 is greater than or equal to 2. In some embodiments, the first well region NW1 has points (the bottommost points) of at least two wave valleys 220, and each wave valley 220 has the first depth H1; the second well region NW2 has points (the highest points) of at least two wave peaks 210, and each wave peak 210 has the second depth H2. In some embodiments, Figure 2 The numbers of the wave peaks 210 and the wave valleys 220 in Figure 2 are for illustration only, and the numbers of the wave peaks 210 and the wave valleys 220 are not limited to Figure 2 the numbers in

[0052] As shown, the arc-shaped contour of the second bottom NW2B (or the arc-shaped bottom surface of the second well region NW2) includes only one wave valley 230, and the wave valley 230 protrudes in a direction away from the upper surface 200T of the semiconductor substrate 200 (or the upper surface of the second well region NW2). In some embodiments, the second bottom NW2B includes only the lowest point of the wave valley 230, and the third depth H3 measured from this lowest point to the upper surface of the second well region NW2 can be equal to the first depth H1. In one embodiment, the upper surface of the first well region NW1 is substantially flush with the upper surface of the second well region NW2. Since the first well region NW1 and the second well region NW2 are formed in the same process, the first depth H1 can be equal to the third depth H3. The method of this embodiment can save manufacturing steps and costs (such as photomask costs), and improve manufacturing efficiency and manufacturing precision. In some embodiments, the first well region NW1 having a waveform bottom (the first bottom NW1B) and the second well region NW2 having a circular (or arc-shaped) bottom (the second bottom NW2B) may have different doping concentrations. For example, the doping concentration of the first well region NW1 may be less than the doping concentration of the second well region NW2.

[0053] In Figure 2In some of the illustrated embodiments, the first well region NWl and the second well region NW2 may have different numbers of arcuate bottoms. For example, the first well region NW1 may have a plurality of arcuate bottoms. The second well region NW2 may have a single arcuate bottom. Thus, the number of arcuate bottoms of the first well region NW1 may be greater than the number of arcuate bottoms of the second well region NW2. In some embodiments, the end of one arcuate bottom may be connected to an adjacent end of another arcuate bottom. The arcuate bottom of the first well region NW1 adjacent to the second well region NW2 is connected to and in contact with the arcuate bottom of the second well region NW2. In some embodiments, the number of arcuate bottoms of the first well region NW1 may be greater than or equal to 2. In some embodiments, the plurality of arcuate bottoms are connected in sequence to form a wavy bottom surface of the first well region NW1 (or a wavy profile of the first bottom NW1B of the first well region NW1). In some embodiments, a first depth H1 measured from the lowest point of one of the arcuate bottoms of the first well region NW1 to the upper surface of the first well region NW1 is equal to a third depth H3 measured from the lowest point of the single arcuate bottom of the second well region NW2 to the upper surface of the second well region NW2. In one embodiment, the upper surface of the first well region NW1 is substantially flush with the upper surface of the second well region NW2. Since the first well region NW1 and the second well region NW2 are formed in the same process, the first depth H1 is equal to the third depth H3. The method of this embodiment can save manufacturing steps and costs (such as photomask costs), and improve manufacturing efficiency and manufacturing accuracy.

[0054] The first heavily doped region P1 is located on the first well region NW1, the second heavily doped region N1 is located on the second well region NW2, the first heavily doped region P1 and the second heavily doped region N1 are arranged along the direction 100, and are spaced apart from each other by the isolation member 201. In this embodiment, the first heavily doped region P1 is electrically connected to the input / output terminal IO, and the second heavily doped region N1 is electrically connected to the power supply terminal VDD.

[0055] As Figure 2As shown, the second ESD protection unit 500-2 includes a third well region PW1, a third heavily doped region N2, a fourth well region PW2, and a fourth heavily doped region P2. The third well region PW1 and the fourth well region PW2 are located in the semiconductor substrate 200 and are separated (spaced apart) from the first well region NW1 and the second well region NW2 by the isolation member 201. In some embodiments, both the third well region PW1 and the fourth well region PW2 have a second conductivity type. For example, when the first conductivity type is N-type and the second conductivity type is P-type, the third well region PW1 and the fourth well region PW2 are P-type well regions. Additionally, the third well region PW1 and the fourth well region PW2, as well as the semiconductor substrate 200, may have the same conductivity type. Each of the third well region PW1 and the fourth well region PW2 has a heavily doped region formed thereon. For example, the third heavily doped region N2 is located on the third well region PW1. The fourth heavily doped region P2 is located on the fourth well region PW2. In some embodiments, the third heavily doped region N2 has a first conductivity type, and the fourth heavily doped region P2 has a second conductivity type. For example, when the first conductivity type is N-type and the second conductivity type is P-type, the third heavily doped region N2 is an N-type heavily doped region N2, and the fourth heavily doped region P2 is a P-type heavily doped region P2.

[0056] The third well region PW1 and the fourth well region PW2 are arranged side by side along the direction 100 (a direction substantially parallel to the upper surface 200T of the semiconductor substrate 200) and are adjacent to each other. In some embodiments, the third heavily doped region N2 and the third heavily doped region N2 are spaced apart from each other by the isolation member 201. An interface 204 may exist between the third well region PW1 and the fourth well region PW2, and the interface 204 may be located below the isolation member 201. In some embodiments, the third bottom PW1B of the third well region PW1 is connected to and contacts the fourth bottom PW2B of the fourth well region PW2.

[0057] In some embodiments, the third bottom PW1B of the third well region PW1 and the fourth bottom PW2B of the fourth well region PW2 have different profiles. For example, the third bottom PW1B of the third well region PW1 may have a wavy surface. The fourth bottom PW2B of the fourth well region PW2 may have an arc-shaped (or circular) surface. The third bottom PW1B of the third well region PW1 may have a Figure 2 wavy profile as shown. The fourth bottom PW2B of the fourth well region PW2 may have a Figure 2The arc-shaped contour shown. In some embodiments, the bottom surface of the third bottom PW1B of the third well region PW1 may be referred to as a waveform bottom surface, and the bottom surface of the fourth bottom PW2B of the fourth well region PW2 may be referred to as an arc-shaped bottom surface. In some embodiments, the third well region PW1 has a third sub-region SR3 and a fourth sub-region SR4 arranged alternately with the third sub-region SR3. In some embodiments, the number of the third sub-regions SR3 is greater than or equal to 2, and the number of the fourth sub-regions SR4 is greater than or equal to 2. The third sub-region SR3 may have a fourth depth H4. The fourth sub-region SR4 may have a fifth depth H5 different from the fourth depth H4. For example, the third sub-region SR3 may have a convex bottom, and the fourth sub-region SR4 may have a concave bottom. The convex bottom of the third sub-region SR3 protrudes in a direction away from the upper surface 200T of the semiconductor substrate 200 (or the upper surface of the third well region PWl). The concave bottom of the fourth sub-region SR4 is recessed in a direction close to the upper surface 200T of the semiconductor substrate 200 (or the upper surface of the third well region PWl). In addition, the fourth depth H4 of the third sub-region SR3 with a convex bottom may be deeper than the fifth depth H5 of the fourth sub-region SR4 with a concave bottom. In some embodiments, the fourth depth H4 is measured from the bottommost point of the convex bottom of the third sub-region SR3 to the upper surface of the third well region PW1. In some embodiments, the fifth depth H5 is measured from the topmost point of the concave bottom of the fourth sub-region SR4 to the upper surface of the third well region PW1. In some embodiments, as Figure 2 shown, the waveform contour of the third bottom PW1B (or the waveform bottom surface of the third well region PW1) includes a plurality of wave peaks 240 and a plurality of wave valleys 250, where the wave peaks 240 are closer to the upper surface of the third well region PWl (or the upper surface 200T of the semiconductor substrate 200) than the wave valleys 250. In some embodiments, the wave valleys 250 are the contours of the bottoms of the third sub-regions SR3, and the wave peaks 240 are the contours of the bottoms of the fourth sub-regions SR4. In some embodiments, the wave valleys 250 are the bottom surfaces of the third sub-regions SR3, and the wave peaks 240 are the bottom surfaces of the fourth sub-regions SR4. The fourth depth H4 is the distance measured from one of the wave valleys 250 (or the lowest point of one of the wave valleys 250) to the upper surface of the third well region PWl, and the fifth depth H5 is the distance measured from one of the wave peaks 240 (or the highest point of one of the wave peaks 240) to the upper surface of the third well region PWl. In some embodiments, the number of the wave peaks 240 is greater than or equal to 2, and the number of the wave valleys 250 is greater than or equal to 2. In some embodiments, the third well region PW1 has points (the bottommost points) with at least two wave valleys 250, each wave valley 250 having a fourth depth H4; the fourth well region PW2 has points (the highest points) with at least two wave peaks 240, each wave peak 240 having a fifth depth H5. In some embodiments, Figure 2The number of peaks 240 and valleys 250 in Figure 2 is for illustration only, and the number of peaks 240 and valleys 250 is not limited to Figure 2 the number in

[0058] In some embodiments, as

[0059] shown, the arc profile of the fourth bottom PW2B (or the arc-shaped bottom surface of the fourth well region PW2) includes only one valley 260, and the valley 260 protrudes in a direction away from the upper surface 200T of the semiconductor substrate 200 (or the upper surface of the fourth well region PW2). In some embodiments, the fourth bottom PW2B includes only the lowest point of the valley 260, and the sixth depth H6 measured from this lowest point to the upper surface of the fourth well region PW2 may be equal to the fourth depth H4. In one embodiment, the upper surface of the third well region PW1 is substantially flush with the upper surface of PW2B. Since the third well region PW1 and the fourth well region PW2 are formed in the same process, the fourth depth H4 is equal to the sixth depth H6. The method of this embodiment can save manufacturing steps and costs (such as photomask costs), and improve manufacturing efficiency and manufacturing precision. Figure 2In some of the illustrated embodiments, the third well region PW1 and the fourth well region PW2 may have different numbers of arcuate bottoms. For example, the third well region PW1 may have multiple arcuate bottoms. The fourth well region PW2 may have a single arcuate bottom. Thus, the number of arcuate bottoms of the third well region PW1 may be greater than the number of arcuate bottoms of the fourth well region PW2. In some embodiments, the end of one arcuate bottom may be connected to an adjacent end of another arcuate bottom. The arcuate bottom of the third well region PW1 adjacent to the fourth well region PW2 is connected to and in contact with the arcuate bottom of the fourth well region PW2. In some embodiments, the number of arcuate bottoms of the third well region PW1 may be greater than or equal to 2. In some embodiments, the multiple arcuate bottoms are sequentially connected to form a waveform bottom surface of the third well region PW1 (or a waveform profile of the third bottom PW1B of the third well region PW1). In some embodiments, a fourth depth H4 measured from the lowest point of one of the arcuate bottoms of the third well region PW1 to the upper surface of the third well region PW1 is equal to a sixth depth H6 measured from the lowest point of the single arcuate bottom of the fourth well region PW2 to the upper surface of the fourth well region PW2. In one embodiment, the upper surface of the third well region PW1 is substantially flush with the upper surface of the fourth well region PW2. Since the third well region PW1 and the fourth well region PW2 are formed in the same process, the fourth depth H4 is equal to the sixth depth H6. The method of this embodiment can save manufacturing steps and costs (such as photomask costs), and improve manufacturing efficiency and manufacturing accuracy.

[0060] The third heavily doped region N2 is located on the third well region PW1, the fourth heavily doped region P2 is located on the fourth well region PW2, the third heavily doped region N2 and the fourth heavily doped region P2 are arranged along the direction 100, and are spaced apart from each other by the isolation component 201. In this embodiment, the third heavily doped region N2 is electrically connected to the input / output terminal IO, and the fourth well region PW2 is electrically connected to the ground terminal VSS.

[0061] Figure 2 Also shown is an equivalent discharge circuit diagram of the ESD protection device 500 when an electrostatic discharge (ESD) event occurs between the input / output terminal IO and the power supply terminal VDD or between the ground terminal VSS and the input / output terminal IO. In addition, Figure 2 The parasitic elements of the equivalent discharge circuits at the corresponding positions of the first and second ESD protection units 500-1 and 500-2 of the ESD protection device 500 are shown. As Figure 2As shown, a first parasitic diode D1 is formed by the first well region NW1, the second well region NW2, and the first heavily doped region P1 of the first ESD protection unit 500-1. When an electrostatic discharge event occurs between the input / output terminal IO and the power supply terminal VDD, the first parasitic diode D1 is triggered to conduct (ON), so as to form a current path PH1 from the input / output terminal IO to the power supply terminal VDD, in order to discharge the electrostatic charge from the internal circuit 400.

[0062] As Figure 2 shown, a second parasitic diode D2 is formed by the third well region PW1, the fourth well region PW2, and the third heavily doped region N2 of the second ESD protection unit 500-2. When an electrostatic discharge event occurs between the ground terminal VSS and the input / output terminal IO, the second parasitic diode D2 is triggered to conduct, forming a current path PH2 from the ground terminal VSS to the input / output terminal IO, in order to discharge the electrostatic charge from the internal circuit 400.

[0063] When the internal circuit 400 is in normal operation (or normal working) (without an electrostatic discharge event), the PN junction formed by the first well region NW1 and the first heavily doped region P1 of the first ESD protection unit 500-1 can be in a reverse bias state and form a first parasitic capacitor C1. Additionally, the PN junction formed by the third well region PW1 and the third heavily doped region N2 of the second ESD protection unit 500-2 can be under reverse bias conditions and form a second parasitic capacitor C2. In some embodiments, the doping concentration of the first well region NW1 becomes lower than that of the second well region NW2. The doping concentration of the third well region PW1 becomes lower than that of the fourth well region PW2. Therefore, the first parasitic capacitor C1 and the second parasitic capacitor C2 can have a lower parasitic capacitance (i.e., depletion capacitance). Thus, the electrostatic discharge (ESD) protection device 500 can have reduced signal loss in high-speed applications.

[0064] A method for forming the ESD protection device 500 is described below. Figure 3 and Figure 4 are schematic cross-sectional views of intermediate stages of forming the ESD protection device 500 according to some embodiments of the present invention. Referring to Figure 3, a semiconductor substrate 200 is provided. The semiconductor substrate 200 has a first device region 200-1 and a second device region 200-2 separated (partitioned) from the first device region 200-1 by an isolation member 201. The first device region 200-1 can provide a first ESD protection unit 500-1 formed in the first device region 200-1, and the second device region 200-2 can provide a second ESD protection unit 500-2 formed in the second device region 200-2. Next, an implantation process 1000 is performed to simultaneously form a first doped region ND1 and a second doped region ND2 in the semiconductor substrate 200, and the first doped region ND1 and the second doped region ND2 are adjacent to each other. The first doped region ND1 can be connected to the second doped region ND2. In some embodiments, the first doped region ND1 has at least one discontinuous portion DP1 therein. The second doped region ND2 can be formed without any discontinuous portions inside. In some embodiments, the second doped region ND2 is a continuous doped region, and there are no other portions having a different type or composition from the second doped region ND2 inside the second doped region ND2. Additionally, an implantation process 1010 is performed to simultaneously form a third doped region PD1 and a fourth doped region PD2 in the semiconductor substrate 200, and the third doped region PD1 and the fourth doped region PD2 are adjacent to each other. The third doped region PD1 can be connected to the fourth doped region PD2. In some embodiments, the third doped region PD1 has at least one discontinuous portion DP2 therein. The fourth doped region PD2 can be formed without any discontinuous portions inside. In some embodiments, the fourth doped region PD2 is a continuous doped region, and there are no other portions having a different type or composition from the fourth doped region PD2 inside the fourth doped region PD2. In some embodiments, the implantation process 1000 and the implantation process 1010 are different ion implantation processes and are implanted with dopants of different conductive types. For example, the first doped region ND1 and the second doped region ND2 can have a first conductive type by implanting an N-type dopant, and the N-type dopant can include phosphorus, arsenic, nitrogen, antimony, or a combination thereof. For example, the third doped region PD1 and the fourth doped region PD2 can have a second conductive type (i.e., P-type) by implanting a P-type dopant, and the P-type dopant can include boron, gallium, aluminum, indium, boron trifluoride ions (BF3+), or a combination thereof.

[0065] Figure 5A , Figure 5B and Figure 5C is Figure 3The plan view shows the arrangement of the discontinuous part DP1 (or the discontinuous part DP2 of the third doped region PD1) of the first doped region ND1 for forming the first well region NW1. According to some embodiments of the present invention, the adjacent second doped region ND2 (or the third well region PW1) and the adjacent second doped region ND2 for forming the second well region NW2 of the ESD protection device 500 (or the fourth doped region PD2 for forming the fourth well region PW2). For illustrative purposes, the isolation feature 201 is hidden. Additionally, Figure 3 The orientations of the shown first well region NW1 (or the third well region PW1) and the adjacent second well region NW2 (or the fourth well region PW2) are merely examples and are not limited to the disclosed embodiments. In some embodiments, the first doped region ND1 (or the third doped region PD1) surrounds the discontinuous part DP1 (or the discontinuous part DP2). In some embodiments, the discontinuous parts DP1 (or the discontinuous parts DP2) can be separated from each other and have various shapes in a top view. As Figure 5A shown, the first doped region ND1 (or the third doped region PD1) can have a strip-shaped discontinuous part DP1 (or the discontinuous part DP2) arranged along the direction 100, and the strip-shaped discontinuous part DP1 (or the discontinuous part DP2) extends along a direction 110 different from the direction 100. As Figure 5B shown, the first doped region ND1 (or the third doped region PD1)) can have a strip-shaped discontinuous part DP1 arranged along the direction 110 and a discontinuous part DP2 (or the discontinuous part DP2) extending along the direction 100. As Figure 5C shown, the first doped region ND1 (or the third doped region PD1) can have a square discontinuous part DP1 (or the discontinuous part DP2). The discontinuous part DP2) is arranged along the direction 110 and the direction 100. In some embodiments, the discontinuous part DP1 (or the discontinuous part DP2) can be circular, elliptical, or polygonal. It is noted that the shape of the first doped region ND1 (or the third doped region PD1) is not limited to the disclosed embodiments.

[0066] Next, referring to Figure 4 , an annealing process 1020 is performed to form the first well region NW1 from the first doped region ND1 ( Figure 3 ), form the second well region NW2 from the second doped region ND2 ( Figure 3 ), form the third well region PW1 from the third doped region PD1 ( Figure 3 ), and form the fourth well region PW2 from the fourth doped region PD2 ( Figure 3 ). In some embodiments, the first well region NW1 is formed by diffusing a part of the dopants (e.g., N-type dopants) in the first doped region ND1 into the discontinuous part DP1 ( Figure 3In addition, the third well region PW1 is formed by diffusing a portion of dopants (eg, P-type dopants) in the third doping region PD1 into the discontinuous portion DP2. Figure 3 ). Therefore, the first well region NW1 and the adjacent second well region NW2 may have different bottom profiles and doping concentrations. For example, the first well region NW1 may have a wavy bottom (first bottom NW1B), and the second well region NW2 may have an arc-shaped (or circular) bottom (second bottom NW2B). The doping concentration of the first well region NW1 may be less than the doping concentration of the second well region NW2. In addition, the third well region PW1 and the adjacent fourth well region PW2 may have different bottom profiles and doping concentrations. For example, the third well region PW1 may have a wavy bottom (first bottom PW1B), and the fourth well region PW2 may have an arc-shaped (or circular) bottom (second bottom PW2B). The doping concentration of the third well region PW1 may be less than the doping concentration of the fourth well region PW2. In some embodiments, since the first well region NW1 and the second well region NW2 (or the third well region PW1 and the fourth well region PW2) with different doping concentrations are formed simultaneously without additional masks and process steps, the method of this embodiment can save manufacturing steps and costs (such as photomask costs) and improve manufacturing efficiency and manufacturing accuracy. Specifically, for example, when performing the implantation process 1000, the same mask can be used and the first well region NW1 ( Figure 2 ) and the mask region corresponding to the second well region NW2 ( Figure 2 ) of the mask region to form different patterns, for example, corresponding to the second well region NW2 ( Figure 2 ) is completely hollowed out, and the pattern corresponding to the first well region NW1 ( Figure 2 ) is partially hollowed out. Figure 3 The figure corresponds to the first well region NW1 ( Figure 2 ) of the semiconductor substrate 200 to form a region composed of the first doped region ND1 and the discontinuous portion DP1; and in the region corresponding to the second well region NW2 ( Figure 2 ) of the semiconductor substrate 200 to form a region with only the second doping region ND2. Figure 2 ) and the fourth well region PW2( Figure 2) The regions are similar and will not be described again here. Therefore, in the embodiments of the present invention, the same mask can be used to form well regions with different doping concentrations in the same manufacturing process (step), so as to form an ESD protection device with lower parasitic capacitance. Thus, in the embodiments of the present invention, it is not necessary to form well regions with different doping concentrations in two manufacturing steps by using two masks respectively, nor is it necessary to form an ESD device by connecting multiple diodes in series (for example, the first ESD protection unit 500-1 in the embodiments of the present invention has only one diode D1, and the second ESD protection unit 500-2 has only one diode D2). Therefore, the embodiments of the present invention can reduce the cost of masks and manufacturing steps and have a smaller device size.

[0067] Next, as Figure 2 shown, multiple ion implantation processes can be performed to form a first heavily doped region P1, a second heavily doped region N1, a third heavily doped region N2, and a fourth heavily doped region P2. The first heavily doped region P1 having a second conductivity type (e.g., P-type) is located on the first well region NW1. The second heavily doped region N1 has a first conductivity type (e.g., N-type) and is located on the second well region NW2. In some embodiments, the first heavily doped region P1 and the second heavily doped region N1 are arranged side by side and spaced apart from each other by an isolation member 201. The third heavily doped region N2 has a first conductivity type (e.g., N-type) and is located on the third well region PW1. The fourth heavily doped region P2 has a second conductivity type (e.g., P-type) and is located on the fourth well region PW2. In some embodiments, the third heavily doped region N2 and the fourth heavily doped region P2 are arranged side by side and spaced apart from each other by an isolation member 201. After the above process, an ESD device 500 including the first and second ESD protection units 500-1 and 500-2 is formed.

[0068] An embodiment of the present invention provides an electrostatic discharge (ESD) protection device and a method for forming the same. When an electrostatic discharge event occurs between an input / output terminal IO and a power supply terminal VDD, or between a ground terminal VSS and the input / output terminal IO, the ESD protection device can release electrostatic charges from the internal circuit. The ESD protection device includes a semiconductor substrate, adjacent first and second well regions of a first conductivity type located in the semiconductor substrate, a first heavily doped region of a second conductivity type located on the first well region, and a second heavily doped region of the first conductivity type located on the second well region. In some embodiments, the first well region and the second well region with different doping concentrations are formed simultaneously without additional masks and process steps. The first well region can be formed by annealing a first doped region of at least one first discontinuous portion inside. Some of the first dopants in the first doped region can diffuse into the first discontinuous portion, thereby forming the first well region. Additionally, the second well region can be formed by annealing a second doped region without discontinuous portions inside. Therefore, the first and second well regions can have different profiles. For example, in a cross-sectional view, the first bottom of the first well region can have a waveform profile, and the second bottom of the second well region can have an arc profile. In some embodiments, the doping concentration of the first well region is less than that of the second well region.

[0069] When an electrostatic discharge (ESD) event occurs between the input / output terminal IO and the power supply terminal VDD, the parasitic diode (first parasitic diode D1) formed by the first heavily doped region and the first well region is triggered to be ON (conductive) to form a current path from the input / output terminal IO to the power supply terminal VDD to discharge the electrostatic charges from the internal circuit. When an electrostatic discharge event occurs between the ground terminal VSS and the input / output terminal IO, the parasitic diode (second parasitic diode D2) formed by the third heavily doped region and the third well region is triggered to conduct, forming a current path from the ground terminal VSS to the input / output terminal IO to discharge the electrostatic charges from the internal circuit.

[0070] When the internal circuit is operating normally (without an electrostatic discharge event), the depletion capacitances of the parasitic capacitors (first parasitic capacitor C1) formed at the reverse-biased PN junction between the first well region NW1 and the first doped region P1, and the parasitic capacitors (second parasitic capacitor C2) formed at the reverse-biased PN junction between the third well region PW1 and the third heavily doped region N2 can both have reduced parasitic capacitances (i.e., depletion capacitances). Therefore, the electrostatic discharge (ESD) protection device can have reduced signal loss in high-speed applications and maintain a smaller device size without adding additional masks.

[0071] While the present invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Accordingly, the scope of the appended claims should be accorded the broadest interpretation so as to cover all such modifications and similar arrangements.

Claims

1. An electrostatic discharge protection device, characterized in that, comprising: a semiconductor substrate; a first well region having a first conductivity type and located in the semiconductor substrate; and a second well region having a first conductivity type and located in the semiconductor substrate and adjacent to the first well region, wherein a first bottom of the first well region and a second bottom of the second well region are connected to each other and have different profiles, and wherein the first well region and the second well region have different doping concentrations.

2. The electrostatic discharge protection device according to claim 1, characterized in that, a first doping concentration of the first well region is less than a second doping concentration of the second well region.

3. The electrostatic discharge protection device according to claim 1, characterized in that, the first bottom of the first well region has a waveform bottom surface, and the second bottom of the second well region has an arc-shaped bottom surface.

4. The electrostatic discharge protection device according to claim 3, characterized in that, the waveform bottom surface of the first well region includes a plurality of wave peaks and a plurality of wave valleys, wherein the wave peaks are closer to an upper surface of the semiconductor substrate than the wave valleys.

5. The electrostatic discharge protection device according to claim 4, characterized in that, the first well region has a first sub-region and a second sub-region arranged alternately with the first sub-region, wherein the wave valleys are bottom surfaces of the first sub-region, and the wave peaks are bottom surfaces of the second sub-region.

6. The electrostatic discharge protection device according to claim 5, characterized in that, the first sub-region has a first depth, and the second sub-region has a second depth different from the first depth.

7. The electrostatic discharge protection device according to claim 6, characterized in that, the first depth is measured from a lowest point of one of the wave valleys to an upper surface of the first well region, and the second depth is measured from a highest point of one of the wave peaks to an upper surface of the first well region.

8. The electrostatic discharge protection device according to claim 6, characterized in that, the arc-shaped bottom surface of the second well region includes only one wave valley, and the one wave valley protrudes in a direction away from the upper surface of the semiconductor substrate.

9. The electrostatic discharge protection device according to claim 8, characterized in that, a third depth measured from a lowest point of the wave valley of the second well region to an upper surface of the second well region is equal to the first depth.

10. The electrostatic discharge protection device according to claim 1, characterized in that, further comprising: a third well region having a second conductivity type and located in the semiconductor substrate and separated from the first well region and the second well region; and a fourth well region having a second conductivity type and located in the semiconductor substrate and separated from the first well region and the second well region, wherein a third bottom of the third well region is connected to a fourth bottom of the fourth well region, and wherein the third bottom of the third well region and the fourth bottom of the fourth well region have different profiles and different doping concentrations.

11. The electrostatic discharge protection device according to claim 10, characterized in that, the third bottom of the third well region has a waveform bottom surface, and the fourth bottom of the fourth well region has an arc-shaped bottom surface.

12. The electrostatic discharge protection device according to claim 11, characterized in that, The waveform bottom surface of the third well region includes a plurality of wave peaks and a plurality of wave valleys, wherein the wave peaks are closer to the upper surface of the semiconductor substrate than the wave valleys, and wherein the arc-shaped bottom surface of the fourth well region includes only one wave valley that protrudes away from the upper surface of the semiconductor substrate.

13. The electrostatic discharge protection device according to claim 12, wherein, a fourth depth measured from the lowest point of one of the wave valleys of the third well region to the upper surface of the third well region is equal to a fifth depth measured from the lowest point of the one wave valley of the fourth well region to the upper surface of the fourth well region.

14. An electrostatic discharge protection device, wherein, comprising: a semiconductor substrate; a first well region having a first conductivity type and located in the semiconductor substrate; and a second well region having a first conductivity type and located in the semiconductor substrate and adjacent to the first well region, wherein a first quantity of a first arc-shaped bottom of the first well region is different from a second quantity of a second arc-shaped bottom of the second well region, and wherein the first well region and the second well region have different doping concentrations.

15. The electrostatic discharge protection device according to claim 14, wherein, the first quantity of the first arc-shaped bottom of the first well region is greater than or equal to 2, and the second quantity of the second arc-shaped bottom of the second well region is equal to 1.

16. The electrostatic discharge protection device according to claim 15, wherein, the first arc-shaped bottoms are connected in sequence to form the waveform bottom surface of the first well region.

17. The electrostatic discharge protection device according to claim 16, wherein, a first depth measured from the lowest point of one of the first arc-shaped bottoms of the first well region to the upper surface of the first well region is equal to a second depth measured from the lowest point of the second arc-shaped bottom of the second well region to the upper surface of the second well region.

18. A method for forming an electrostatic discharge protection device, wherein, comprising: providing a semiconductor substrate; performing an implantation process to simultaneously form a first doped region and a second doped region in the semiconductor substrate, wherein the first doped region and the second doped region have the first conductivity type and are adjacent to each other, and wherein the first doped region has a first discontinuous portion therein; and performing an annealing process to form a first well region from the first doped region and a second well region from the second doped region, wherein the first well region and the second well region have different doping concentrations.

19. The method for forming an electrostatic discharge protection device according to claim 18, wherein, the first well region is formed by diffusing a part of the first dopants in the first doped region into the first discontinuous portion.

20. The method for forming an electrostatic discharge protection device according to claim 18, wherein, the second doped region is formed without any discontinuous portion inside.

Images