Method for improving trimming defects

Abstract

The invention provides a method for improving trimming defects, which comprises the following steps of: providing a device wafer, forming a device structure on the front surface of the device wafer, and forming a first dielectric layer with positive electricity on the front surface of the device wafer; forming a second dielectric layer which is electronegative in wet cleaning on the first dielectric layer; the edge of the device wafer is subjected to edge cutting treatment, so that the sharp appearance of the edge in the subsequent thinning process is avoided; and removing silicon chips on the device wafer by wet cleaning. According to the invention, Si chip residues on the surface of the device wafer can be effectively removed, and subsequent bonding defects are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for improving trimming defects. Background Art

[0002] In a traditional CMOS image sensor, light needs to pass through the metal wiring and transistor layer of the sensor to reach the photosensitive area. In the BSI technology, the sensor is flipped so that light can directly enter the photosensitive area, thereby improving the sensor sensitivity and image quality. As the size of the sensor pixel continues to decrease, the requirements for performance and process are also getting higher and higher. Image sensors below 2um mostly adopt the BSI (Back-Side Illuminated Image Sensor) structure. During the process of wafer grinding and thinning, sharp edges will be generated, and the stress will concentrate on the edges, which may cause fracture risks during and after thinning. Therefore, in order to prevent breakage, the original bevel shape can be cut off by trimming to improve the quality and stability of the BSI wafer, and to ensure the performance and reliability of the final product.

[0003] During the trimming process, a grinding liquid is sprayed on the surface of the device wafer to keep the device wafer in a wet state, and trimming is performed on the edge part while the device wafer is rotating. After that, the back and surface of the device wafer will be cleaned in the cleaning unit to remove the residual Si chips. However, through scanning, it is found that a large amount of Si chips still remain on the wafer surface and are not washed clean. These Si chips will cause bubbles in the subsequent bonding and break during the thinning process, greatly affecting the product yield.

[0004] To solve the above problems, a new method for improving trimming defects needs to be proposed. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for improving trimming defects, which is used to solve the problem that a large amount of Si chips still remain on the wafer surface and are not washed clean in the prior art. These Si chips will cause bubbles in the subsequent bonding and break during the thinning process, greatly affecting the product yield.

[0006] To achieve the above purpose and other related purposes, the present invention provides a method for improving trimming defects, including:

[0007] Step 1: Provide a device wafer, with a device structure formed on the front surface of the device wafer, and a positively charged first dielectric layer formed on the front surface of the device wafer;

[0008] Step 2: Form a second dielectric layer that is negatively charged in wet cleaning on the first dielectric layer;

[0009] Step 3: Trim the edge of the device wafer to avoid sharp topography at the edge during subsequent thinning;

[0010] Step 4: Use wet cleaning to remove silicon chips on the device wafer.

[0011] Preferably, the material of the first dielectric layer in Step 1 is silicon nitride.

[0012] Preferably, the material of the second dielectric layer in Step 2 is TEOS.

[0013] Preferably, the trimming method in Step 3 includes: spraying abrasive liquid on the surface of the device wafer to keep the device wafer in a wet state, and trimming the edge part while the device wafer is rotating.

[0014] Preferably, the solution for wet cleaning in Step 4 is a weakly acidic solution with pH > 2.5.

[0015] Preferably, the method further includes: Step 5: Bond the front side of the device wafer to a carrier wafer; Step 6: Thin the back side of the device wafer.

[0016] Preferably, the wafer device is thinned by grinding in Step 6.

[0017] Preferably, the grinding method in Step 6 is chemical mechanical planarization grinding.

[0018] As described above, the method for improving trimming defects of the present invention has the following beneficial effects:

[0019] The present invention can effectively remove the residual Si chips on the surface of the device wafer and improve subsequent bonding defects. Description of the Drawings

[0020] Figure 1 Schematic diagram showing the cleaning effect of the prior art;

[0021] Figure 2 Schematic diagram showing the process flow of the present invention;

[0022] Figure 3 Schematic diagram showing the cleaning effect of the present invention;

[0023] Figure 4 Schematic diagram showing the comparison of bonding defects after cleaning between an embodiment and the prior art. Detailed Embodiments

[0024] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0025] Please refer to Figure 2 , the present invention provides a method for improving trimming defects, including:

[0026] Step 1: Provide a device wafer. A device structure is formed on the front surface of the device wafer, and a positively charged first dielectric layer is formed on the front surface of the device wafer;

[0027] In some embodiments, the material of the first dielectric layer in Step 1 is silicon nitride. Please refer to Figure 1 , since SiN is positively charged and Si is negatively charged, electrostatic adsorption will occur, and a large amount of Si chips will still remain after cleaning. In other embodiments, the first dielectric layer can also be other positively charged materials.

[0028] Step 2: Form a second dielectric layer that is negatively charged during wet cleaning on the first dielectric layer. The second dielectric layer makes the surface of the device wafer negatively charged, reducing the adsorption of Si chips;

[0029] In some embodiments, the material of the second dielectric layer in Step 2 is TEOS. In other embodiments, the second dielectric layer can also use other well-known negatively charged materials.

[0030] Step 3: Trim the edge of the device wafer to avoid the appearance of sharp topography at the edge during subsequent thinning;

[0031] In some embodiments, the trimming method in Step 3 includes: spraying abrasive liquid on the surface of the device wafer to keep the device wafer in a wet state, and trimming the edge part while the device wafer is rotating.

[0032] Step 4: Use wet cleaning to remove the silicon chips on the device wafer.

[0033] In some embodiments, the solution for wet cleaning in Step 4 is a weakly acidic solution with pH > 2.5.

[0034] In some embodiments, the method further includes: Step 5: Bond the front surface of the device wafer to a carrier wafer. The carrier wafer is a wafer or glass. Each wafer can include a substrate, and the substrate is usually a silicon substrate; Step 6: Thin the back surface of the device wafer.

[0035] In some embodiments, the wafer device is thinned by grinding in Step 6.

[0036] In some embodiments, the grinding method in step six is chemical mechanical planarization grinding.

[0037] Please refer to Figure 3 , when Si chips are in a weakly acidic solution, they show electronegativity, while the SiN layer is positively charged. Inevitably, electrostatic adsorption will occur. The TEOS layer becomes negatively charged when the pH > 2.5. Like charges repel each other, and the Si chips greatly weaken the electrostatic adsorption on the surface, effectively weakening the adsorption of negatively charged Si chips on the surface of the positively charged SiN layer, thereby achieving the purpose of effectively removing the residual Si chips on the surface of the device wafer.

[0038] Please refer to Figure 4 , which shows a comparison diagram of the bonding defects after cleaning between an embodiment of the present invention and the prior art. It can be seen that the present invention can effectively remove the residual Si chips on the surface of the device wafer and improve the subsequent bonding defects.

[0039] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and proportion of each component in actual implementation can be arbitrarily changed, and the layout type of its components may also be more complex.

[0040] In summary, the present invention can effectively remove the residual Si chips on the surface of the device wafer and improve the bonding defects. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0041] The above embodiments are only used to illustrate the principle and efficacy of the present invention by way of example, rather than to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving cutting edge defects, characterized in that: At least: Step 1: providing a device wafer, forming a device structure on the front side of the device wafer, and forming a positively charged first dielectric layer on the front side of the device wafer; Step 2: forming a second dielectric layer which is negatively charged during wet cleaning on the first dielectric layer; Step 3: trimming the edge of the device wafer to avoid sharp edges during subsequent thinning; Step 4: remove silicon scraps on the device wafer by wet cleaning.

2. The method for improving cutting edge defects according to claim 1, characterized in that: The material of the first dielectric layer in step 1 is silicon nitride.

3. The method for improving cutting edge defects according to claim 1, characterized in that: The material of the second dielectric layer in step 2 is TEOS.

4. The method for improving cutting edge defects according to claim 1, characterized in that: The trimming method in step three includes: spraying abrasive liquid on the surface of the device wafer to keep the device wafer in a wet state, and trimming the edge portion while the device wafer is rotating.

5. The method for improving cutting edge defects according to claim 3, characterized in that: The wet cleaning solution in step 4 is a weakly acidic solution with a pH value greater than 2.

5.

6. The method for improving cutting edge defects according to claim 1, characterized in that: The method further includes: step five, bonding the front side of the device wafer to a carrier; and step six, thinning the back side of the device wafer.

7. The method for improving cutting edge defects according to claim 6, characterized in that: In step six, the wafer device is thinned by grinding.

8. The method for improving cutting edge defects according to claim 6, characterized in that: The grinding method in step six is ​​chemical mechanical planarization grinding.

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