Solar cell with hybrid architecture including differentiated p-type and n-type regions

Abstract

The invention relates to a solar cell having a hybrid architecture including differentiated p-type and n-type regions. Specifically, a solar cell and a method of manufacturing the same are disclosed. The solar cell may include a substrate having a light receiving surface and a back surface. The solar cell includes: a first dielectric layer; a first semiconductor region; a second dielectric layer; a second semiconductor region; a third dielectric layer; a first conductive contact; and a second conductive contact.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 201980059206.2, titled "Solar Cell with Hybrid Architecture Comprising Differentiated p-Type and n-Type Regions", with a filing date of September 27, 2019.

[0002] Cross - reference to related applications

[0003] This application claims the priority of U.S. Non - Provisional Application No. 16 / 586,509, filed on September 27, 2019, which claims the benefit of U.S. Provisional Application No. 62 / 739,077, filed on September 28, 2018, the entire content of which is hereby incorporated by reference. Background of the Invention

[0004] Photovoltaic (PV) cells (commonly known as solar cells) are devices used to convert solar radiation into electrical energy. Generally, solar radiation that irradiates on the surface of a solar cell substrate and enters the substrate forms electron - hole pairs in the substrate body. The electron - hole pairs migrate to the p - type doped region and n - type doped region in the substrate, thereby forming a voltage difference between the doped regions. The doped regions are connected to conductive regions on the solar cell to conduct the current from the cell to an external circuit. When PV cells are combined in an array such as a PV module, the electrical energy collected from all the PV cells can be combined in series and parallel arrangements to provide a power source with a certain voltage and current. Brief Description of the Drawings

[0005] Figure 1 A cross - sectional view showing a portion of a solar cell according to some embodiments is shown.

[0006] Figure 2 Is a flowchart according to some embodiments, which lists the operations in a method of manufacturing a solar cell.

[0007] Figure 3 Is a flowchart according to some embodiments, which lists the operations in forming a first semiconductor region of a solar cell.

[0008] Figure 4 Is a flowchart according to some embodiments, which lists the operations in forming a second semiconductor region of a solar cell.

[0009] Figure 5 Is a flowchart according to some embodiments, which lists the operations in forming a conductive contact structure for a solar cell.

[0010] Figures 6 - 16 Shows cross - sectional views of various stages in the manufacture of a solar cell according to some embodiments. Detailed Description

[0011] Efficiency is an important characteristic of solar cells because it is directly related to the ability of the solar cell to generate electricity. Likewise, the efficiency of producing solar cells is directly related to the cost-effectiveness of such solar cells. Therefore, techniques for improving the efficiency of solar cells or techniques for improving the efficiency of manufacturing solar cells are generally needed. Some embodiments of the present disclosure allow for improving the manufacturing efficiency of solar cells by providing new processes for manufacturing solar cell structures. Some embodiments of the present disclosure allow for improving the efficiency of solar cells by providing new solar cell structures.

[0012] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter of the present application or the use of such embodiments. As used herein, the word "exemplary" means "used as an example, instance, or illustration". Any embodiment described herein as exemplary is not necessarily understood to be preferred or advantageous over other embodiments. In addition, it is not intended to be bound by any express or implied theory presented in the aforementioned technical field, background technology, summary of the invention, or the following detailed description.

[0013] This specification contains references to "one embodiment" or "an embodiment." The appearance of the phrase "in one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

[0014] Terminology. The following paragraphs provide definitions and / or context for terms found in this disclosure (including the appended claims):

[0015] "Comprising". This term is open ended. As used in the appended claims, this term does not exclude other structures or steps.

[0016] "Configured to". Various units or components may be described or stated as being "configured to" perform one or more tasks. In such contexts, "configured to" is used to imply structure by indicating that the unit / component includes structure to perform one or more of those tasks during operation. Thus, the unit / component may be said to be configured to perform a task even when the specified unit / component is not currently in operation (e.g., not turned on / activated). Reciting a unit / circuit / component as "configured to" perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112, sixth paragraph, with respect to that unit / component.

[0017] "First", "second", etc. As used herein, these terms are used as labels for the nouns that follow them and do not imply any type of order (e.g., spatial, temporal, logical, etc.). For example, referring to a "first" semiconductor region does not necessarily mean that the semiconductor region is the first semiconductor region in a certain sequence; rather, the term "first" is used to distinguish the semiconductor region from another semiconductor region (e.g., the "second" semiconductor region). As used herein, a semiconductor region can be a polysilicon emitter region, for example, polysilicon doped with P-type or N-type dopants. In one example, the first semiconductor region can be a first polysilicon emitter region, where multiple polysilicon emitter regions (e.g., a second polysilicon emitter region) can be formed.

[0018] "Based on". As used herein, this term is used to describe one or more factors that affect a determination result. This term does not exclude additional factors that can affect the determination result. That is, the determination result can be based only on those factors or at least partially on those factors. Consider the phrase "determine A based on B". Although B can be a factor affecting the determination of A, such a phrase does not exclude the possibility that the determination result of A is also based on C. In other examples, A can be determined based only on B.

[0019] "Coupled" - The following description refers to elements or nodes or structural features being "coupled" together. As used herein, unless otherwise expressly specified, "coupled" means that one element / node / feature is directly or indirectly connected to another element / node / feature (or directly or indirectly in communication with it), and is not necessarily a mechanical connection.

[0020] "Prevent" - As used herein, prevent is used to describe reducing an influence or minimizing it. When a component or feature is described as preventing an action, movement, or condition, it can completely prevent a certain result or consequence or future state. Additionally, "prevent" can also refer to reducing or minimizing a certain consequence, performance, and / or effect that might occur. Thus, when a component, element, or feature is said to prevent a result or state, it does not necessarily completely prevent or eliminate that result or state.

[0021] In addition, certain terms may be used only for reference purposes in the following description, and thus these terms are not intended to be limiting. For example, terms such as "upper", "lower", "above", and "below" refer to the directions provided for reference in the drawings. Terms such as "front / front side", "back", "rear", "side / lateral side", "outer side", and "inner side" describe the orientation and / or position of certain parts of a component within a consistent but arbitrary reference system, and the orientation and / or position can be clearly understood by referring to the text describing the component in question and the relevant drawings. Such terms can include the words specifically mentioned above, their derivatives, and words with similar meanings.

[0022] This document describes methods for fabricating the semiconductor regions of a solar cell and the resulting solar cell. In the following description, numerous specific details such as specific process flow operations are set forth in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known fabrication techniques such as lithography and patterning techniques are not described in detail to avoid unnecessarily obscuring embodiments of the present disclosure. Additionally, it should be understood that the various embodiments shown in the figures are exemplary presentations and are not necessarily drawn to scale.

[0023] Figure 1 A cross-sectional view of a portion of a solar cell 100 in accordance with some embodiments is shown. In one embodiment, the solar cell 100 may include a substrate 106 having a front surface 102 and a back surface 104 (the front surface 102 being opposite the back surface 104). In some embodiments, the front surface 102 may be referred to as the front face, and the back surface 104 may be referred to as the back face. In one embodiment, the front surface may have a textured surface. The textured surface 130 may be a surface having a regular or irregular shape that is used to scatter incident light and reduce the amount of light reflected from the light receiving surface and / or exposed surface of the solar cell 100.

[0024] Referring again to Figure 1 , in one embodiment, the solar cell 100 may include a first dielectric layer 114 disposed on the back surface 104 of the substrate 106. In some embodiments, the first dielectric layer 114 may be referred to as the first thin dielectric layer. In one instance, the first dielectric layer 114 may be a thin oxide layer such as a tunnel dielectric layer (e.g., tunnel oxide, silicon oxynitride, silicon oxide). In one embodiment, the first dielectric layer 114 may have a thickness of about 2 nanometers or less.

[0025] Referring again to Figure 1 , in one embodiment, the solar cell 100 may include a first semiconductor region 108 disposed on the first dielectric layer 114. In one embodiment, the first semiconductor region 108 may be a first polysilicon emitter region. In one embodiment, the first semiconductor region may include a first conductivity type. In one instance, the first semiconductor region 108 may be a first polysilicon emitter region of a first conductivity type. In a specific embodiment, the first conductivity type is N-type (e.g., formed using phosphorus atoms or arsenic impurity atoms). In some embodiments, the first conductivity type may be P-type (e.g., formed using boron).

[0026] Referring again to Figure 1, in some embodiments, the solar cell 100 may include a second dielectric layer 120 disposed on the back surface 104 of the substrate 106. In some embodiments, the second dielectric layer 120 may be partially disposed 116, 118 on portions 117, 115 of the first semiconductor region 108. In some embodiments, the second dielectric layer 120 may be referred to as a second thin dielectric layer. In one example, the second dielectric layer 120 may be a thin oxide layer, such as a tunnel dielectric layer (e.g., tunnel oxide, silicon oxynitride, silicon oxide). In some embodiments, the second dielectric layer 120 may have a thickness of about 2 nanometers or less.

[0027] Referring again to Figure 1 , in some embodiments, portions 116, 118 may alternatively be referred to as another dielectric layer (e.g., a third, fourth, or fifth dielectric layer, etc.). In one embodiment, portions 116, 118 may be part of the second dielectric layer 120. In some embodiments, portions 116, 118 may alternatively be separate and distinct layers different from the second dielectric layer 120. In some embodiments, portions 116, 118 may alternatively be part of the first dielectric layer 114. In one example, portions 116, 118 may be distinct layers that are the same as or different from the first dielectric layer 114 and / or the second dielectric layer 120. In some embodiments, the first dielectric layer 114 and the second dielectric layer 120 may be different and distinct layers. In some embodiments, the first dielectric layer 114 and the second dielectric layer 120 may be the same dielectric layer. In one example, the first dielectric layer 114 and the second dielectric layer 120 may be a single continuous dielectric layer. In one example, the first dielectric layer 114, the second dielectric layer 120, and layers 116, 118 may be a single continuous dielectric layer.

[0028] Still referring again to Figure 1, in one embodiment, the solar cell 100 may include a second semiconductor region 112 disposed above the back surface of the solar cell 100. In one embodiment, the second semiconductor region 112 may be disposed on a second dielectric layer 120. In one embodiment, the second semiconductor region 112 may be a second polysilicon emitter region. In one embodiment, the second semiconductor region 112 may include a second conductivity type. In one instance, the second semiconductor region 112 may be a second polysilicon emitter region of a second conductivity type. In a specific embodiment, the second conductivity type is P-type (e.g., formed using boron impurity atoms). In one embodiment, the second conductivity type may be N-type (e.g., formed using phosphorus atoms or arsenic impurity atoms). In one embodiment, the second dielectric layer 120 may include a portion disposed above 118, which is an outer portion 117 of the first semiconductor region 108. In one embodiment, the second dielectric layer 120 may include a portion 116 disposed laterally above a lateral portion 115 of the first semiconductor region 108. In one embodiment, portions 118, 116 of the second dielectric layer 120 may be interposed between the first semiconductor region 108 and the second semiconductor region 112. In one instance, dielectric layers 116, 118 may be the boundaries of a metallurgical junction between the first semiconductor region 108 and the second semiconductor region 112. In one instance, dielectric layer 116 may be the boundary of a metallurgical junction between the first semiconductor region 108 and the second semiconductor region 112 (e.g., without dielectric layer 118). In some embodiments, the second semiconductor region is a pre-doped polysilicon emitter region. In one such embodiment, a second semiconductor region of a specific conductivity type (e.g., P-type or N-type) is formed.

[0029] Referring again to Figure 1 , in one embodiment, a third dielectric layer 125 may be disposed on the second semiconductor region 112. In one embodiment, the third dielectric layer may be a dopant layer. In one embodiment, the dopant layer may have a second conductivity type. In one embodiment, the dopant layer has the same conductivity type as the second semiconductor region 112. In one instance, the dopant layer is N-type (e.g., formed using phosphorus atoms or arsenic impurity atoms). In one embodiment, the dopant layer may be P-type (e.g., formed using boron impurity atoms). In one embodiment, a portion of the second semiconductor region 112 and the dopant layer 125 may be disposed between a first conductive contact 128 and a second conductive contact 129. In some embodiments, the second semiconductor region 112 and the dopant layer 125 may be aligned with an edge of the insulating layer 110. In one embodiment, the third dielectric layer 125 may be a discontinuous layer (e.g., as Figure 1As shown). In one example, the third dielectric layer 125 may be divided into discrete portions and may still be referred to as a single dielectric layer or dopant layer. In some embodiments, it may not be necessary to form the third dielectric layer (e.g., where the second semiconductor region includes a pre-doped polycrystalline emitter region). In one embodiment, the third dielectric layer 125 may include silicon oxide, silicon oxynitride, and silicon nitride. In one example, the third dielectric layer 125 may include an insulator and / or insulating material.

[0030] Referring again to Figure 1 , in one example, the solar cell 100 may further include an insulating region 110 disposed on the first semiconductor region 108. In one instance, the insulating region 110 may be silicon dioxide.

[0031] Referring again to Figure 1 , in one example, the solar cell 100 may include a first conductive contact 128 disposed above the first semiconductor region 108. In one example, the first conductive contact 128 may be disposed through the insulating region 110, as Figure 1 depicted. In one embodiment, the first conductive contact 128 is disposed through a contact hole 121 in the insulating region 110.

[0032] In one example, a second conductive contact 129 may be disposed above the second semiconductor region 112. In one embodiment, the second conductive contact 129 is disposed through the third dielectric layer 125. In one example, the second conductive contact 129 is disposed through a contact hole 123 in the third dielectric layer 125.

[0033] In one embodiment, the first conductive contact 128 and the second conductive contact 129 may include plated metal. In one example, the first conductive contact 128 and the second conductive contact 129 may include copper, tin, titanium, tungsten, and / or nickel and other metals. In some embodiments, the first conductive contact 128 and the second conductive contact 129 may include deposited metal or metal foil. In one example, the first conductive contact 128 and the second conductive contact 129 may include aluminum or aluminum foil. In one embodiment, the first conductive contact 128 and the second conductive contact 129 may include wires, thermocompression wires, and / or aluminum wires.

[0034] In one embodiment, a portion 124 of the second semiconductor region 112 and / or the third dielectric layer 125 may be disposed between the first conductive contact 128 and the second conductive contact 129. In some embodiments, the second semiconductor region 112 and the third dielectric layer 125 may alternatively be laterally aligned with the second conductive contact 129, e.g., with Figure 1As compared to that shown, it does not extend from the second conductive contact 129. In one embodiment, the second semiconductor region 112 and the third dielectric layer 125 may be misaligned. In an instance, at portion 124, the second semiconductor region 112 may extend further from the second conductive contact 129 than the third dielectric layer 125. In an embodiment, as shown at 124, the second conductive contact 129 may be formed over the first semiconductor region 108 and the second semiconductor region 112. In contrast, in some embodiments, the second conductive contact 129 may be formed only over the second semiconductor region 112. In an embodiment, the second conductive contact 139 may be formed over the third dielectric layer 125 and the second semiconductor region 112.

[0035] Referring again to Figure 1 , in an embodiment, the solar cell 100 may further include a fourth dielectric layer 132 disposed on the front face 102. In an embodiment, the fourth dielectric layer 132 may be an antireflection coating (ARC). In an instance, the layer 132 may include silicon nitride. In an embodiment, the fourth dielectric layer 132 may include silicon oxide. In an instance, an oxide layer (e.g., tunneling oxide) may be formed on the front face 102. In an embodiment, a silicon layer may be disposed over the fourth dielectric layer 132 (e.g., over the oxide layer). In an instance, the silicon layer may include amorphous silicon and / or polycrystalline silicon. In an embodiment, an antireflection layer may be disposed over the silicon layer (e.g., silicon nitride).

[0036] Referring again to Figure 1 , in some embodiments, the first semiconductor region 108 may be an N-type polycrystalline silicon emitter region. In one embodiment, the second semiconductor region 112 may be a P-type polycrystalline silicon emitter region. In an embodiment, the substrate 106 may be an N-type single crystal silicon substrate. In some embodiments, the second semiconductor region 112 may be a P-type polycrystalline silicon emitter region. In an embodiment, the substrate 106 may be a P-type single crystal silicon substrate. In an embodiment, the first dielectric layer 114, the second dielectric layer 120, and the third dielectric layer 125 may include silicon oxide. In an embodiment, the insulating region 110 includes silicon dioxide. In embodiments where the third dielectric layer 125 may include a dopant layer, the dopant layer 125 may include phosphorus or boron.

[0037] Referring again to Figure 1, in some embodiments, the first conductive contact 128 and / or the second conductive contact 129 may include deposited metal. In some embodiments, the deposited metal may be aluminum-based. In one such embodiment, the aluminum-based deposited metal may have a thickness in the range of approximately 0.3 microns to 20 microns, and include an aluminum content greater than about 97%, and a silicon content in the range of approximately 0% to 2%. In some instances, the aluminum-based deposited metal may include copper, titanium, titanium tungsten, nickel, and / or aluminum and other metals. In some embodiments, the aluminum-based deposited metal is formed by a blanket deposition process. In some embodiments, the aluminum-based deposited metal may be a metal seed layer. In some instances, the deposited metal may be deposited aluminum. In one embodiment, each of the first conductive contact 128 and the second conductive contact 129 may include copper, tin, nickel, and / or aluminum and other metals.

[0038] Referring again to Figure 1 , in some embodiments, each of the first conductive contact 128 and / or the second conductive contact 129 includes a metal foil. In some embodiments, the metal foil is an aluminum (Al) foil having a thickness in the range of about 5 - 100 microns. In one embodiment, the Al foil is an aluminum alloy foil containing aluminum and a second element (such as, but not limited to, copper, manganese, silicon, magnesium, zinc, tin, lithium, or combinations thereof). In one embodiment, the Al foil is a temper grade foil, such as, but not limited to, F grade (free state), O grade (fully soft), H grade (strain hardened), or T grade (heat treated). In one embodiment, the aluminum foil is an anodized aluminum foil. In another embodiment, the aluminum foil is not anodized.

[0039] Still referring again to Figure 1 , in some embodiments, each of the first conductive contact 128 and / or the second conductive contact 129 includes a wire. In some embodiments, the wire may include a conductive material (e.g., a metal such as aluminum, copper, or another suitable conductive material, with or without a coating such as tin, silver, nickel, or an organic solderability protectant). In some instances, the wire may be bonded to the first semiconductor region and the second semiconductor region by a thermocompression bonding, ultrasonic bonding, or thermosonic bonding process. In some instances, the wire may include an aluminum wire.

[0040] Turning to Figure 2 , a flowchart 200 is shown, which illustrates a method for manufacturing a solar cell according to some embodiments. In various embodiments, Figure 2 the method described may include additional (or fewer) blocks than those shown.

[0041] Referring to operation 202 of flowchart 200, a method of manufacturing a solar cell may include performing a texturing process on a front side of a substrate. In an example, a hydroxide-based wet etchant may be used to form a textured surface on the front side of the substrate. However, it should be understood that texturing of the front side may be omitted from the process flow. In an embodiment, cleaning, polishing, planarizing, and / or thinning of the substrate may be performed before or within the same or a single process step as the texturing process. In an example, a wet chemical cleaning process may be performed before and / or after the texturing process. Although shown as being performed at the beginning of the manufacturing process as illustrated, in another embodiment, the texturing process may be performed at another step of the manufacturing process. In an example, alternatively, the texturing process may be performed after a patterning process. In one example, the texturing process may be performed before a thermal process. In one such example, the texturing process may be performed after patterning (e.g., patterning of a polysilicon region) and before a thermal process.

[0042] In an embodiment, although operation 202 is shown as being performed before operation 204, operation 202 may also be performed in the middle or at the end of the method described herein. For example, operation 202 may be performed after operation 208. In an example, operation 202 may be performed after operation 210 and before operation 212. In an embodiment, operation 202 may be performed at the start, middle, end, or any other time of the process described in flowchart 202.

[0043] Referring to operation 204 of flowchart 200, a method of manufacturing a solar cell may include forming a first dielectric layer on a back side of the substrate. In an embodiment, the first dielectric layer may be formed during an oxidation process and be a thin oxide layer such as a tunnel dielectric layer (e.g., silicon oxide). In one embodiment, the first dielectric layer may be formed during a deposition process. In an embodiment, the first dielectric layer is a thin oxide layer (e.g., silicon oxide) or a silicon oxynitride layer. In an embodiment, forming the first dielectric layer may include forming a first dielectric layer having a thickness of about 2 nanometers or less. In an example, a thermal process or an oven may be used to grow the first dielectric layer. As used herein, the first dielectric layer may also be referred to as the first thin dielectric layer.

[0044] Referring to operation 206 of flowchart 200, a method of manufacturing a solar cell may include forming a first semiconductor region on the first dielectric layer. In an embodiment, forming the first semiconductor region may include forming a first polysilicon emitter region. In an embodiment, forming the first semiconductor region may include: forming a first silicon layer on the first dielectric layer; forming an insulator layer over the first silicon layer; and subsequently, patterning the first silicon layer, the insulator layer, and the first dielectric layer to form an insulating region and the first semiconductor region (e.g., a first polysilicon emitter region having an insulating region thereon). In the followingFigure 3 Further details of the operations for forming the first semiconductor region are shown in flowchart 300. In certain embodiments, operations 204 and 206 may be performed in the same process step or in different (e.g., separate) process steps.

[0045] Referring to operation 208 of flowchart 200, a method of manufacturing a solar cell may include forming a second dielectric layer on a portion of the first semiconductor region and on a portion of the substrate. In certain embodiments, the second dielectric layer may be formed during an oxidation process and be a thin oxide layer such as a tunnel dielectric layer (e.g., silicon oxide). In one embodiment, the second dielectric layer may be formed during a deposition process. In certain embodiments, the second dielectric layer is a thin oxide layer (e.g., silicon oxide) or a silicon oxynitride layer. In certain embodiments, the second dielectric layer may have a thickness of about 2 nanometers or less. In certain instances, forming the second dielectric layer on a portion of the first semiconductor region and on a portion of the substrate may include forming the second dielectric layer on an exposed portion of the first semiconductor region and on an exposed portion of the substrate. In one instance, after performing a patterning process at operation 206, exposed regions of the first semiconductor region and the substrate may be formed. As used herein, the second dielectric layer may also be referred to as the second thin dielectric layer.

[0046] Referring again to operation 208 of flowchart 200, in certain embodiments, forming the second dielectric layer on a portion of the first semiconductor region may alternatively include forming a separate, different, and / or distinct dielectric layer on a portion of the first semiconductor region. In certain instances, forming the second dielectric layer on a portion of the first semiconductor region may include forming another dielectric layer on a portion of the first semiconductor region. In certain embodiments, the dielectric layer may be referred to as the fourth dielectric layer or the fifth dielectric layer.

[0047] Referring to operation 210 of flowchart 200, a method of manufacturing a solar cell may include forming a second semiconductor region above the back side of the substrate. In certain embodiments, forming the second semiconductor region above the back side of the substrate includes forming the second semiconductor region on or above the second dielectric layer. Forming the second semiconductor region may include: forming a second silicon layer on or above the second dielectric layer; forming a third dielectric layer above the second silicon layer; patterning the second silicon layer, the third dielectric layer, and the second dielectric layer; and subsequently performing a thermal process to drive dopants from a dopant layer into the second silicon layer to form the second semiconductor region. In certain embodiments, as described herein, the third dielectric layer may include a dopant layer, where patterning the second silicon layer, the third dielectric layer, and the second dielectric layer may include patterning the second silicon layer, the dopant layer, and the second dielectric layer. In the following Figure 4 Further details of the operations for forming the second semiconductor region are shown in flowchart 400 below.

[0048] Referring to operation 212 of flowchart 200, a method of manufacturing a solar cell may include forming a conductive contact structure over a first semiconductor region and a second semiconductor region. In some embodiments, forming the conductive contact structure may include: performing a sputtering process; locally depositing metal; performing a blanket deposition process; performing a plating process; bonding a metal foil and / or bonding wire to the first semiconductor region and the second semiconductor region. In some instances, the conductive contact structure may include locally deposited aluminum, aluminum foil, and / or aluminum wire. In some embodiments, the conductive contact structure may include one or more metals and / or metal alloys. In some instances, the conductive contact structure may include aluminum, titanium tungsten, and / or copper and other metals. In some embodiments, the conductive contact structure may include one, two, or more metal layers. In some instances, the conductive contact structure may include a metal seed layer. In some embodiments, the metal seed layer may include a first layer, a second layer, and a third layer, where the first layer includes copper, the second layer includes tungsten, and the third layer includes aluminum.

[0049] Referring again to operation 212 of flowchart 200, a method of manufacturing a solar cell may include patterning an insulating region and a third dielectric layer (e.g., a dopant layer) to expose portions of a first semiconductor emitter region and a second semiconductor emitter region, where a first conductive contact and a second conductive contact may be electrically connected to the exposed portions of the first semiconductor region and the second semiconductor region, respectively. In Figure 5 Further details of operations for forming a conductive contact structure over a first semiconductor region and a second semiconductor region are shown in flowchart 500 of

[0050] Referring Figure 3 to, flowchart 300 is shown, which illustrates operations for forming a first semiconductor region according to some embodiments. In various embodiments, Figure 3 the method described may include additional (or fewer) blocks than those shown. Although one embodiment for forming a first semiconductor region (e.g., a first polycrystalline emitter region) is shown below, other operations may be used. In some instances, compared to the operations of flowchart 300, screen printing, inkjet printing, or any other process for directly depositing patterned silicon may be used to form the first semiconductor region.

[0051] Referring to operation 302 of flow chart 300, forming the first semiconductor region may include forming a first silicon layer on a first dielectric layer. In some embodiments, the first dielectric layer is formed over the back side of a substrate (e.g., a silicon substrate). In one embodiment, the first dielectric layer is a thin oxide layer. In some embodiments, the first silicon layer may be deposited over the first dielectric layer. In one example, the first silicon layer may be deposited over the first dielectric layer using a low pressure chemical vapor deposition process. In some embodiments, the first silicon layer is grown on the first dielectric layer in a thermal process and / or an oven. In one embodiment, the first dielectric layer and the first silicon layer may be formed (e.g., grown) in the same or a single oven and / or in the same or a single process step. In some embodiments, the first dielectric layer and the first silicon layer may be formed on the back side, the front side, and / or the side edges of the substrate, where subsequent patterning (e.g., operation 306) or cleaning processes may be performed to remove the first dielectric layer and the first semiconductor layer from the front side and / or the side edges of the substrate.

[0052] Referring again to operation 302 of flow chart 300, forming the first semiconductor region may include, in some embodiments, forming a first silicon layer having a first conductivity type. In one example, forming the first silicon layer may include growing an N-type silicon layer over a first dielectric layer (e.g., a thin oxide layer). In other embodiments, the first silicon layer may be a P-type silicon layer. In some embodiments, the first silicon layer is an amorphous silicon layer. In one such embodiment, the amorphous silicon layer is formed using low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). In some embodiments, the first silicon layer may be amorphous silicon and / or polycrystalline silicon. In some embodiments, the first silicon layer is grown on the first dielectric layer in a thermal process and / or an oven. In one embodiment, the first dielectric layer and the first silicon layer may be grown in the same or a single oven and / or in the same or a single process step.

[0053] Referring again to operation 302 of flow chart 300, in another embodiment, the first silicon layer may be formed undoped. In one such embodiment, a dopant layer may be formed on the first silicon layer, and a thermal process may be performed to drive the dopant from the dopant layer into the first silicon layer, thereby producing a first silicon layer having a first conductivity type (e.g., N-type or P-type).

[0054] Referring to operation 304 of flow chart 300, forming the first semiconductor region may include forming an insulator layer on the first silicon layer. In some embodiments, the insulator layer may include silicon dioxide. In one example, a blanket deposition process may be performed to form the insulator layer. In some embodiments, the insulator layer may be formed to have a thickness less than or equal to about 1000 angstroms.

[0055] Referring to operation 306 of flow chart 300, the insulator layer, the first silicon layer, and the first dielectric layer may be patterned to form a first semiconductor region. In some embodiments, the first semiconductor region may have an insulating region formed above the first semiconductor region. In some embodiments, the insulating region may be formed by patterning the insulator layer of operation 304. In some embodiments, photolithography or screen printing masks and subsequent etching processes may be used to pattern the insulator layer and the first silicon layer. In another embodiment, a laser ablation process (e.g., direct write) may be used to pattern the insulator layer, the first silicon layer, and / or the first dielectric layer.

[0056] Referring Figure 4 , flow chart 400 is shown, which illustrates operations for forming a second semiconductor region according to some embodiments. In various embodiments, Figure 4 the method described may include additional (or fewer) blocks than those shown. Although one embodiment for forming a second semiconductor region (e.g., a second polycrystalline emitter region) is shown below, other operations may be used. In one example, compared to the operations of flow chart 400, screen printing, inkjet printing, or any other process for directly depositing patterned silicon may be used to form the second semiconductor region.

[0057] Referring to operation 402 of flow chart 400, forming the second semiconductor region may include forming a second silicon layer above the back side of the substrate. In some embodiments, forming the second silicon layer above the back side of the substrate may include forming the second silicon layer on the second dielectric layer and an insulating region disposed on the back side of the substrate. In some embodiments, the second dielectric layer is formed by the operations described above in flow charts 200 and 300. In one embodiment, the second dielectric layer is a thin oxide layer. In one embodiment, the second silicon layer may be deposited above the second dielectric layer. In one example, a low-pressure chemical vapor deposition process (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) may be used to deposit the second silicon layer above the second dielectric layer. In some embodiments, the second silicon layer may be polysilicon. In some embodiments, the second silicon layer is grown on the second dielectric layer in a thermal process and / or an oven. In one embodiment, the second dielectric layer and the second silicon layer may be grown in the same or a single oven and / or in the same or a single process step. In some embodiments, the second silicon layer may be formed undoped. In some embodiments, the second silicon layer is an amorphous silicon layer. In one such embodiment, the amorphous silicon layer is formed using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0058] Referring again to operation 402 of flowchart 400, in another embodiment, forming the second semiconductor region may include forming a second silicon layer having a second conductivity type different from that of the first semiconductor region. In one such example, forming the second silicon layer may include forming a pre-doped silicon layer. In one instance, forming the second silicon layer may include growing a P-type silicon layer over a second dielectric layer (e.g., a thin oxide layer).

[0059] Referring again to operation 402 of flowchart 400, the second dielectric layer and the second silicon layer may be formed on the back, front, and / or side edges of the substrate, and subsequent patterning or cleaning processes (e.g., operation 406) may be performed to remove the second dielectric layer and the second semiconductor layer from the front and / or side edges of the substrate.

[0060] Referring to operation 404 of flowchart 400, forming the second semiconductor region may include forming a third dielectric layer on the second silicon layer. In some embodiments, the third dielectric layer may include a dopant layer. In one such embodiment, the dopant layer may have a second conductivity type. In one embodiment, the second conductivity type may be P-type. In one instance, the dopant layer may be a boron layer. In some embodiments, the second conductivity type may be N-type (e.g., a phosphorus layer). In some embodiments, a deposition process may be performed to form the third dielectric layer (e.g., the dopant layer). In one instance, a low-pressure chemical vapor deposition process may be used to deposit the third dielectric layer over the second silicon layer. In one embodiment, the third dielectric layer may include silicon oxide or silicon oxynitride. In some embodiments, the third dielectric layer may include an insulator and / or an insulating material.

[0061] Referring to operation 406 of flowchart 400, forming the second semiconductor region may include patterning the dopant layer and the second silicon layer to form the second semiconductor region. In some embodiments, lithography or a mask (e.g., screen printing, inkjet printing) may be used, and after the mask, an etching process may be used to pattern the dopant layer, the second silicon layer, and the second thin dielectric layer. In another embodiment, a laser process (e.g., laser ablation, direct writing, etc.) may be used in the patterning. In one embodiment, the patterning may also include an etching process (e.g., wet chemical etching). In some embodiments, the patterning may also include a subsequent cleaning process. In some embodiments, the patterning may form a second semiconductor region of a second conductivity type (e.g., P-type). In some embodiments, patterning or operation 406 may not be required.

[0062] Referring to operation 408 of flow chart 400, wherein the third dielectric layer may include a dopant layer, and forming the second semiconductor region may include performing a thermal process to drive dopants from the dopant layer into the second silicon layer. In certain embodiments, the second conductivity type may be P-type. In one example, the dopant layer may be a boron layer. In certain examples, the thermal process may include heating to a temperature of about greater than or equal to 900 °C to drive dopants from the dopant layer into the second silicon layer. In some embodiments, patterning or operation 406 may be performed after the thermal process or operation 408. In some embodiments, for example, where the silicon layer is pre-doped or formed to include an N-type or P-type conductivity type, the thermal process need not be performed.

[0063] Referring Figure 5 , flow chart 500 is shown, which shows operations in forming a conductive contact structure over a first semiconductor region and a second semiconductor region according to some embodiments. In various embodiments, Figure 5 the methods described may include additional (or fewer) blocks than those shown.

[0064] Referring to operation 502 of flow chart 500, forming a conductive contact structure over the first semiconductor region and the second semiconductor region may include patterning an insulating region and a third dielectric layer formed over the first semiconductor region and the second semiconductor region, respectively (e.g., as shown in flow charts 200, 300, and 400 above). In certain embodiments, patterning the insulating region and the third dielectric layer forms contact holes through the insulating region and the third dielectric layer. In certain embodiments, a mask and an etching process may be used to form the contact holes. In one example, a mask may be formed, and a subsequent wet chemical etching process may be performed to form the contact holes. In some embodiments, a wet chemical cleaning process may be performed to remove the mask. In one embodiment, patterning may include performing a laser patterning process (e.g., laser ablation) to form contact holes in the insulating region and the third dielectric layer. In one embodiment, the patterning process for forming contact holes in the insulating region and the third dielectric layer may be performed in the same or a single step (e.g., using a laser in the same or a single laser processing chamber), or alternatively may be performed separately (e.g., separate laser patterning processes may be used to form contact holes in the insulating region and the third dielectric layer). In certain embodiments, where the third dielectric layer may include a dopant layer, patterning may include patterning the insulating region and the dopant layer in a single step or separately to form contact holes through the insulating region and the dopant layer.

[0065] Referring to operation 504 of flowchart 500, forming a conductive contact above the first semiconductor region may include forming a first conductive contact above the first semiconductor region. In one example, forming the first conductive contact above the first semiconductor region may include forming the first conductive contact on the first polysilicon emitter region. In one embodiment, the first semiconductor region (e.g., the first polysilicon emitter region) may have a first conduction type (e.g., N-type). In one embodiment, the first conductive contact may be formed through one or more metallization processes. In one embodiment, the first conductive contact may have the same conduction type as the first semiconductor region. In one example, the first conductive contact may be an N-type metal contact and the conduction type of the first semiconductor region may be N-type. In another example, the first conductive contact may be a P-type metal contact and the conduction type of the first semiconductor region may be P-type.

[0066] Referring to operation 506 of flowchart 500, forming a conductive contact above the second semiconductor region may include forming a second conductive contact above the second semiconductor. In one example, forming the second conductive contact above the second semiconductor region may include forming the second conductive contact on the second polysilicon emitter region. In one embodiment, the second semiconductor region (e.g., the second polysilicon emitter region) may have a second conduction type (e.g., P-type). In one embodiment, the second conductive contact may be formed through one or more metallization processes. In one embodiment, the second conductive contact may have the same conduction type as the second semiconductor region. In one example, the second conductive contact may be a P-type metal contact and the conduction type of the second semiconductor region may also be P-type. In another example, the second conductive contact may be an N-type metal contact and the conduction type of the second semiconductor region may be N-type.

[0067] Referring again to operations 504, 506 of flowchart 500, forming the first conductive contact and the second conductive contact may include performing a sputtering process, locally depositing metal, blanket depositing a process, plating a process, bonding a metal foil, and / or bonding a wire to form the first semiconductor region and the second semiconductor region (e.g., as described above). In one example, the first conductive contact and the second conductive contact may include locally depositing aluminum, aluminum foil, and / or aluminum wire. In one embodiment, a thermocompression process may be used to electrically connect the first conductive contact and the second conductive contact to the first semiconductor region and the second semiconductor region (e.g., the first polysilicon emitter region and the second polysilicon emitter region). In one example, a thermocompression process may be used to adhere one or more wires to the first semiconductor region and the second semiconductor region. In one embodiment, a metal foil may be bonded (e.g., welded) to the first semiconductor region and the semiconductor region. In one embodiment, forming the first conductive contact and the second conductive contact may include performing a blanket deposition process. In one example, forming the first conductive contact and the second conductive contact may include performing an electroplating process. In some examples, forming the first conductive contact and the second conductive contact may include performing a blanket deposition process to form a metal seed layer. In the same example, a plating process may then be performed to plate metal onto the metal seed layer. In the same example, a patterning process may be performed after forming the metal seed layer and performing the plating process to form the first conductive contact and the second conductive contact.

[0068] Referring again to operations 504, 506 of flowchart 500, the above methods may be used separately in operations 504 and 506 or used in the same or a single process step. In one example, using a plating process to form the first conductive contact and the second conductive contact may include placing a substrate in a bath to plate metal onto the substrate and form the first conductive contact and the second conductive contact. In another embodiment, a local metal deposition process may be used to form the first conductive contact and the second conductive contact in one process step. In one embodiment, wires may be placed and thermally bonded to the first conductive contact and the second conductive contact. In one embodiment, wires may be placed and thermally bonded to the first conductive contact and the second conductive contact in the same or a single process step.

[0069] The present invention discloses a method of manufacturing a solar cell. In an exemplary process flow, Figures 6 to 16 Cross-sectional views of various stages in the manufacture of a solar cell according to some embodiments are shown. In various embodiments, Figures 6 to 16 the method may include additional (or fewer) blocks than those shown. For example, in some embodiments, Figure 14 and Figure 15 the patterning processes may alternatively be combined into a single patterning process or performed in the same or a single process step.

[0070] Referring Figure 6, A method of manufacturing a solar cell 600 may include performing a texturing process to form a textured surface 630 on a front surface 602 of a substrate 606. In certain embodiments, the substrate 606 is a silicon substrate. In certain instances, the substrate 606 may be a single crystal silicon substrate, such as a bulk single crystal N-type doped silicon substrate. In another instance, the substrate 606 may be a bulk single crystal P-type doped silicon substrate. However, it should be understood that the substrate 606 may be a layer disposed over an entire solar cell substrate, such as a polysilicon layer. In certain embodiments, the substrate 606 may have a front surface 602 and a back surface 604, where the front surface 602 is opposite the back surface 604. In one embodiment, the front surface 602 may be referred to as a light receiving surface 602, and the back surface may be referred to as a back surface 604. In certain embodiments, the substrate 606 may also have side edges 641, e.g., the edges of a wafer or substrate, as shown.

[0071] Referring again to Figure 6 , in certain embodiments, performing the texturing process may include forming the textured surface 630 on the front surface 602 of the substrate 606 using a hydroxide-based wet etchant. The textured surface 630 may be a surface having a regular or irregular shape that is configured to scatter incident light and reduce the amount of light reflected from the light receiving surface and / or exposed surfaces of the solar cell 600. In certain embodiments, as Figure 6 shown, a single-sided texturing process may be performed to form the textured surface 630 on the front surface 602 of the substrate 606. In certain embodiments, the texturing process may be performed on both the front surface 602 and the back surface 604 of the substrate 600. In one such embodiment, the substrate may be cleaned, polished, planarized, and / or thinned before or within the same or a single process step of the texturing process. In some embodiments, the texturing process may not be required.

[0072] Referring again to Figure 6 , in certain embodiments, although the texturing process is shown as being performed at the beginning of the process flow, the texturing process may also be performed in the middle or at the end of the methods described herein. For example, the texturing process may be performed after the process described in Figure 15 .

[0073] Referring to Figure 6 , in certain embodiments, a method of manufacturing a solar cell 600 may include forming a first dielectric layer 614 on the back surface 604 of the substrate 606. In certain embodiments, the first dielectric layer 614 may be formed during an oxidation process. In one embodiment, the first dielectric layer 614 may be formed during a deposition process. In certain embodiments, the first dielectric layer 614 is a thin oxide layer, a silicon oxide layer, or a silicon oxynitride layer. In certain embodiments, the first dielectric layer 614 may have a thickness of about 2 nanometers or less. In certain embodiments, the first dielectric layer 614 is a tunnel oxide layer.

[0074] Referring again to Figure 7 , in certain embodiments, a method of fabricating a solar cell 600 may include forming a first silicon layer 609 on a first dielectric layer 614. In certain embodiments, the first silicon layer 605 may be a polysilicon layer. In certain embodiments, the first silicon layer 605 may be doped in-situ or doped after a low-pressure chemical vapor deposition process, deposition implantation, or a combination thereof to have a first conductivity type. In a particular embodiment, the first conductivity type is N-type (e.g., formed using phosphorus atoms or arsenic impurity atoms). In another embodiment, the first silicon layer 609 may be formed undoped. In one such embodiment, a dopant layer may be formed on the first silicon layer 609, and a thermal process may be performed to drive the dopant from the dopant layer into the first silicon layer 609, thereby creating a first silicon layer having a first conductivity type (e.g., N-type or P-type).

[0075] Referring again to Figure 7 , in certain embodiments, the first silicon layer 605 may be an amorphous silicon layer such as a hydrogenated silicon layer represented by a-Si:H, which is implanted with a dopant of the first conductivity type after deposition of the amorphous silicon layer. In one such embodiment, the first silicon layer 605 may subsequently be annealed (at least at a subsequent stage in the process flow) to ultimately form a polysilicon layer. In certain embodiments, for either the polysilicon layer or the amorphous silicon layer, if post-deposition implantation can be performed, the implantation is performed by using ion beam implantation or plasma immersion implantation. In one such embodiment, a shadow mask may be used for the implantation. In certain embodiments, the first silicon layer 605 may have a thickness greater than or equal to about 300 angstroms.

[0076] Referring again to Figure 7 , an insulator layer 609 may be formed on the first silicon layer 605. In certain embodiments, the insulator layer 609 may include silicon dioxide. In certain instances, a deposition process may be performed to form the insulator layer 609. In certain instances, a blanket deposition process may be performed to form the insulator layer 609.

[0077] Referring to Figure 8, A method of manufacturing a solar cell 600 may include patterning an insulator layer 609, a first silicon layer 605, and a first dielectric layer 614. In some embodiments, patterning may include forming a mask 611 over the insulator layer 609, the first silicon layer 605, and the first thin dielectric layer 614. In some instances, screen printing, inkjet printing, and / or any suitable masking process may be used to form the mask 611. In some embodiments, the mask 611 may be patterned to protect portions and expose other portions 603 of the insulator layer 609, the first silicon layer 605, and the first dielectric layer 614 during an etching process. After etching, the mask 611 may subsequently be removed. For example, photolithography or screen printing masks and subsequent wet chemical etching processes may be used to pattern the insulator layer 609, the first silicon layer 605, and the first dielectric layer 614, and then the mask 611 may be removed (e.g., in a cleaning step). In another embodiment, a laser process (e.g., laser ablation, direct writing) may be used to pattern the insulator layer 609, the first silicon layer 605, and the first thin dielectric layer 614. Figure 9 Shows the first semiconductor region 608, the insulating region 610, and the first dielectric layer 614 after the patterning process described above. Figure 8

[0078] Referring again to Figure 8 , in one embodiment, the first dielectric layer 614 and the first silicon layer 605 may be formed on the back surface 604, the front surface 602, and / or the side edges 641 of the substrate, and subsequent patterning or cleaning processes may be performed to remove the first dielectric layer 614 and the first silicon layer 605 from the front surface 602 and / or the side edges 641 of the substrate 606.

[0079] Referring to Figure 9 , shows the insulating region 610, the first semiconductor region 608, and the first dielectric layer 614 after the patterning process according to some embodiments. In some embodiments, as described above, the first semiconductor region may be a first polysilicon emitter region. In a specific embodiment, the first semiconductor region 608 may have a first conductivity type of N-type (e.g., formed using phosphorus atoms or arsenic impurity atoms). In some embodiments, the first semiconductor region 608 may have a first conductivity type of P-type. In some embodiments, the insulating region 610 may include silicon dioxide. In some embodiments, the insulating region 610 may include other insulating materials, such as polyimide. As Figure 8 shown, portions 615, 617 of the first semiconductor region 608 may be exposed after the patterning process (e.g., masking and etching, laser patterning, etc.) described above. Similarly, as also shown in the figure, portions 619 of the substrate 606 may also be exposed after patterning. Figure 9 Figure 9

[0080] In connection with​​​Figure 8 And Figure 9 compared to the process shown, other patterning processes may be used. For example, it is not necessary to form a Figure 8 mask 611. In one example, a laser patterning process (e.g., without using mask 611) may be used to pattern the insulator layer 609, the first silicon layer 605, and the first thin dielectric layer 614.

[0081] Referring Figure 10 , a method of manufacturing a solar cell 600 may include forming a second dielectric layer 620 over a portion of the first semiconductor region 608 and over a portion of the substrate 606. In certain embodiments, the second dielectric layer 620 may be formed during an oxidation process and be a thin oxide layer such as a tunnel dielectric layer (e.g., silicon oxide). In one embodiment, the second dielectric layer 620 may be formed during a deposition process. In certain embodiments, the second dielectric layer 620 is a thin oxide layer or a silicon oxynitride layer. In certain embodiments, the second dielectric layer 620 may have a thickness of about 2 nanometers or less. Referring Figure 9 and Figure 10 , in certain embodiments, the second dielectric layer 620 may be formed at 616, 618 over exposed portions 615, 617 of the first semiconductor region 608. Similarly, the second dielectric layer 620 may be formed over an exposed portion 619 of the substrate 606. As used herein, the second dielectric layer 620 may also be referred to as a second thin dielectric layer.

[0082] Referring again to operation 208 of flowchart 200, in certain embodiments, forming a second dielectric layer over a portion of the first semiconductor region 608 may alternatively include forming separate, different, and / or distinct dielectric layers 616, 618 over a portion of the first semiconductor region 608. In certain examples, forming a second dielectric layer over a portion of the first semiconductor region may alternatively include forming another dielectric layer 616, 618 over a portion of the first semiconductor region 608. In certain embodiments, the dielectric layers 616, 618 may be referred to as a fourth dielectric layer or a fifth dielectric layer that is separate and different from the second dielectric layer 620.

[0083] Referring again to Figure 11, a method of manufacturing a solar cell 600 may include forming a second silicon layer 607 over a back surface 604 of a substrate 606. In certain embodiments, forming the second silicon layer 607 over the back surface 604 of the substrate 606 may include forming the second silicon layer 607 over or on a second dielectric layer 620 and over an insulating region 610. In one embodiment, the second silicon layer 607 may be deposited over the second dielectric layer 620. In one example, a low-pressure chemical vapor deposition (LPCVD) process or a plasma-enhanced chemical vapor deposition (PECVD) process may be used to deposit the silicon layer 607. In certain embodiments, the second silicon layer 607 may be polysilicon. In one embodiment, Figure 10 and Figure 12 processes may be performed in a single chamber and / or manufacturing step. In one example, the second dielectric layer 620 may be grown and subsequently, the second silicon layer 607 may be deposited over the second dielectric layer 620 in the same or a single processing chamber and / or manufacturing process. In certain embodiments, the second silicon layer 607 may be formed undoped. In certain embodiments, the second silicon layer 607 may be an amorphous silicon layer. In one such embodiment, the amorphous silicon layer is formed using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). In certain embodiments, the second silicon layer 607 may have a thickness greater than or equal to about 300 angstroms.

[0084] Referring again to Figure 11 , in certain embodiments, a method of manufacturing a solar cell 600 may include forming a second silicon layer 607 having a second conductivity type different from that of a first semiconductor region 608. In one such example, forming the second silicon layer 607 may include forming a pre-doped silicon layer. In one example, forming the second silicon layer 607 may include growing a P-type silicon layer over a second dielectric layer (e.g., a thin oxide layer).

[0085] Referring to Figure 12, A method of manufacturing a solar cell 600 may include forming a third dielectric layer 625 over the back side of a substrate. In certain embodiments, forming the third dielectric layer may include forming the third dielectric layer over a second silicon layer 607 and an insulating region 610. In one embodiment, the third dielectric layer 625 may include silicon oxide, silicon oxynitride, and silicon nitride. In certain embodiments, the third dielectric layer 625 may be a dopant layer. In one such embodiment, the dopant layer 625 may have a second conductivity type. In certain embodiments, the second conductivity type may be P-type. In one example, the dopant layer 625 may include boron. In certain embodiments, a deposition process may be performed to form the dopant layer 625. In one example, a chemical vapor deposition process may be used to form the dopant layer 625. In one embodiment, the dopant layer may have a thickness in the range of about 100 to 2000 angstroms. In certain embodiments, the dopant layer 625 has a conductivity type opposite to that of the first semiconductor region 608.

[0086] Reference Figure 13 , A method of manufacturing a solar cell 600 may include patterning the third dielectric layer and the second silicon layer to form a second semiconductor region. As described herein, in certain embodiments, patterning the third dielectric layer may include patterning the dopant layer (e.g., where the third dielectric layer includes a dopant or a dopant layer). In certain embodiments, patterning may include forming a mask 613 over the dopant layer 625. In certain embodiments, the mask 613 may be patterned to protect portions of the dopant layer 625, the second silicon layer 607, and the second thin dielectric layer 620 during an etching process. After etching, the mask 613 may subsequently be removed. For example, photolithography or screen printing masks and subsequent wet chemical etching processes may be used to pattern the dopant layer 625 and the second silicon layer 607. In another embodiment, a laser patterning process (e.g., laser ablation, direct write) may be used to pattern the dopant layer 625, the second silicon layer 607, and the second thin dielectric layer 620. Figure 14 The structure shown illustrates the second semiconductor region 612 formed after the patterning process described above in Figure 13 .

[0087] Referring again to Figure 13 , in one embodiment, the second dielectric layer 620 and the second silicon layer 607 may be formed on the back side 604, the front side 602, and / or the side 641 of the substrate 606, where subsequent patterning or cleaning processes may be performed to remove the second dielectric layer 620 and the second silicon layer 607 from the front side 602 and / or the side 641 of the substrate 606.

[0088] Compared with Figure 13 and Figure 14 the processes shown, other patterning processes may be used. For example, it is not necessary to formFigure 13 and Figure 14 mask 613. In one example, a laser patterning process (e.g., without using mask 613) can be used to pattern Figure 13 the dopant layer 625 and the second silicon layer 607 of

[0089] Referring to Figure 14 , after the patterning process described in Figure 13 , a portion of the insulating region 610 from Figure 13 can be exposed, for example, between the mask portions 613. Additionally, although not shown, mask 613 can be removed. In one example, after the patterning of Figure 13 and Figure 14 , mask 613 can be removed through a cleaning process. In one example, a wet chemical cleaning or an ink stripping process can be used to remove mask 613.

[0090] Still referring again to Figure 13 and Figure 14 , where the third dielectric layer can include a dopant layer, a method of manufacturing the solar cell 600 can include performing a thermal process to drive the dopant from the dopant layer 625. In the same embodiment, the mask portions 613 of Figure 13 and Figure 14 can be removed before performing the thermal process. In one embodiment, after the thermal process, the second silicon layer 612 can have the same conductivity type as the dopant layer 625. In one such embodiment, the second conductivity type can be P-type. In one example, the thermal process can include heating to a temperature greater than or equal to about 900 °C. In one embodiment, the heating temperature can be in the range of about 900 °C - 1100 °C. In another embodiment, a laser doping process can be used to drive the dopant from the dopant layer 625 into the second silicon layer 607. In one embodiment, the thermal process can be performed after the above patterning and / or cleaning processes.

[0091] Referring again to Figure 13 and Figure 14, according to some embodiments, a method of manufacturing a solar cell 600 may include forming a second semiconductor region 612 after the above thermal process. In certain embodiments, the second semiconductor region 612 may be a second polysilicon emitter region. In one embodiment, the second semiconductor region 612 may have a second conductivity type. In certain embodiments, the second semiconductor region 612 may have the same conductivity type as the third dielectric layer 625, such as where the third dielectric layer includes a dopant (e.g., a dopant layer). In one embodiment, the second conductivity type is P-type. In certain embodiments, the second conductivity type may be N-type. In one embodiment, the second semiconductor region may be a pre-doped polysilicon emitter region. In one such example, a second semiconductor region including N-type or P-type conductivity may be formed directly, where the third dielectric layer does not include a dopant layer or the third dielectric layer is not fully formed.

[0092] Reference Figure 15 , a method of manufacturing a solar cell 600 may include patterning an insulating region 610 and a third dielectric layer (e.g., a dopant layer in some embodiments) 625 to form contact holes 621, 623 through the insulating region 610 and the dopant layer 625. In certain embodiments, patterning may form a contact hole 621 above the first semiconductor region 608. In certain embodiments, patterning may form a contact hole 623 above the second semiconductor emitter region 612. In certain embodiments, a mask and etching process, a laser process, or any other suitable patterning process may be used to form the contact holes.

[0093] Reference Figure 16 , a method of manufacturing a solar cell 600 may include forming a first conductive contact 638 above the first semiconductor region 608. In certain embodiments, the first conductive contact 638 may be formed through one or more metallization processes. In certain instances, the first conductive contact 638 may be formed by performing a sputtering process, locally depositing metal, a blanket deposition process, a plating process, bonding a metal foil, and / or performing a wire bonding process. In certain embodiments, the first conductive contact 638 may have the same conductivity type as the first semiconductor region 608 (e.g., the first polysilicon emitter region). In certain instances, the first conductive contact 638 may be an N-type metal contact, and the conductivity type of the first semiconductor region 608 may also be N-type.

[0094] Again reference Figure 16, A method of manufacturing a solar cell 600 may include forming a second conductive contact 639 over a second semiconductor region. In certain embodiments, the second conductive contact 639 may be formed by one or more metallization processes. In certain instances, the second conductive contact 639 may be formed by performing a sputtering process, locally depositing metal, blanket depositing a metal, plating, bonding a metal foil, and / or performing a wire bonding process. In certain embodiments, the second conductive contact 639 may have the same conductivity type as the second semiconductor region 612 (e.g., the second polysilicon emitter region). In certain instances, the second conductive contact may be a P-type metal contact, and the conductivity type of the second semiconductor region may also be P-type. In certain embodiments, as shown at 624, the second conductive contact may be formed over the first and second semiconductor regions. In contrast, in some embodiments, the second conductive contact may be formed only over the second semiconductor region. In certain embodiments, the second conductive contact 639 may be formed over a third dielectric layer 625 and the second semiconductor region 612. In one instance, the second conductive contact 639 may be formed over a dopant layer and the second semiconductor region 612 (e.g., a dopant layer disposed on the second semiconductor region 612).

[0095] Referring again to Figure 16 , in certain embodiments, the first conductive contact 638 and the second conductive contact 639 may include one or more metals and / or metal alloys. In certain instances, the first conductive contact 638 and the second conductive contact 639 may include aluminum, titanium tungsten, nickel, and / or copper, among other metals. In certain embodiments, the first conductive contact 638 and the second conductive contact 639 may include one, two, or more metal layers. In certain instances, the metal seed layer may include a first layer, a second layer, and a third layer, where the first layer includes copper, the second layer includes tungsten, and the third layer includes aluminum. In certain instances, the first conductive contact 638 and the second conductive contact 639 may include locally deposited aluminum, aluminum foil, aluminum wire, blanket deposited metal (e.g., a metal seed layer), and / or plated metal.

[0096] Referring again to Figure 16 , a fourth dielectric layer 632 may be formed on the front face 602 of the solar cell 600. In certain embodiments, the fourth dielectric layer 632 may be an antireflection coating (ARC). In one instance, the fourth dielectric layer 632 may include silicon nitride. In some embodiments, other layers may be formed over the front face 602. In certain instances, an amorphous silicon layer or another polysilicon layer may be formed over the front face 602.

[0097] Referring again to Figure 16 , shown using the same as Figure 2 , Figure 3 , Figure 4 and Figure 5Methods corresponding to flowcharts 200, 300, 400, and 500, and Figures 6 to 16 A method for manufacturing a solar cell 600. As shown in the figure, Figure 16 The solar cell 600 has reference numerals similar to those of the Figure 1 Components of the solar cell 100, where in all the figures, similar reference numerals refer to similar components. In one embodiment, Figure 16 The structure of the solar cell 600 is substantially similar to Figure 1 The structure of the solar cell 100, with differences as described above. Therefore, Figure 1 The description of the corresponding parts of Figure 16 Equally applies to the description of Figure 16 The first semiconductor region 608 of Figure 1 May correspond to the first semiconductor region 108 of Figure 16 The third dielectric layer 625 of Figure 1 May correspond to the third dielectric layer 125 of

[0098] As disclosed above, the third dielectric layer 625 may include a doped layer. In some embodiments, the third dielectric layer 625 may include silicon oxide or silicon oxynitride. In one embodiment, the third dielectric layer 625 may include an insulator layer or insulating material. In one embodiment, the portion of the second semiconductor region 612 at 624 may be disposed between the first conductive contact 628 and the second conductive contact 629. In one embodiment, the portion of the third dielectric layer 625 at 624 may also be disposed between the first conductive contact 628 and the second conductive contact 629.

[0098] Although specific embodiments have been described above, even if only a single embodiment is described with respect to a particular feature, these embodiments are not intended to limit the scope of the present disclosure. Unless otherwise specified, the examples of the features provided in the present disclosure are intended to be exemplary rather than restrictive. The above description is intended to cover those alternative forms, modifications, and equivalent forms that will be apparent to those skilled in the art and that have the beneficial effects of the present disclosure.

[0099] The scope of the present disclosure includes any feature or combination of features (explicitly or implicitly) disclosed herein, or any generalization thereof, regardless of whether it alleviates any or all of the problems addressed herein. Thus, new claims may be presented during the examination of this application (or an application claiming its priority) for any such combination of features. In particular, referring to the appended claims, the features from the dependent claims may be combined with those of the independent claims, and the features from the corresponding independent claims may be combined in any suitable manner, not just in the specific forms enumerated in the appended claims.

Claims

1. A solar cell, comprising: a first dielectric layer disposed on the back surface of a substrate; a first semiconductor region disposed on the first dielectric layer; a second dielectric layer disposed on a portion of the first semiconductor region and a portion of the back surface of the substrate; a second semiconductor region disposed on the second dielectric layer, wherein a portion of the second dielectric layer is disposed between the first semiconductor region and the second semiconductor region; a third dielectric layer disposed on the second semiconductor region; a first conductive contact disposed above the first semiconductor region but not above the third dielectric layer; and a second conductive contact disposed above the third dielectric layer and the second semiconductor region, wherein the second conductive contact is disposed through the third dielectric layer.

2. The solar cell according to claim 1, wherein the third dielectric layer comprises a doped layer.

3. The solar cell according to claim 2, wherein the second semiconductor region and the doped layer have the same conductivity type.

4. The solar cell according to claim 2, wherein the doped layer comprises an N-type dopant or a P-type dopant.

5. The solar cell according to claim 1, wherein the third dielectric layer comprises an insulator layer.

6. The solar cell according to claim 1, wherein the third dielectric layer comprises a dielectric selected from the group consisting of silicon oxide, silicon oxynitride, and silicon nitride.

7. The solar cell according to claim 1, wherein a portion of the second semiconductor region and a portion of the third dielectric layer are disposed between the first conductive contact structure and the second conductive contact structure.

8. The solar cell according to claim 1, wherein a portion of the second semiconductor region and a portion of the third dielectric layer are disposed above the first semiconductor region.

9. The solar cell according to claim 1, further comprising an insulating region disposed on the first semiconductor region, wherein the first conductive contact is disposed through the insulating region.

10. The solar cell according to claim 1, wherein the first conductive contact and the second conductive contact each comprise a metal foil or a wire.

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