A back-contact battery and photovoltaic module

Abstract

This invention discloses a back-contact solar cell and a photovoltaic module, relating to the field of photovoltaic technology, to achieve a high light-trapping effect on the side of the second passivation layer facing away from the semiconductor substrate, and to achieve a high passivation effect of the first passivation layer on the isolation region. The back-contact solar cell includes a semiconductor substrate, a first doped semiconductor portion, a second doped semiconductor portion, a first passivation layer, and a second passivation layer. The first passivation layer covers the first doped semiconductor portion, the second doped semiconductor portion, and the isolation region. On the side of the first passivation layer facing away from the semiconductor substrate, the surface corresponding to the isolation region is a first region surface. The second passivation layer covers the second surface. The first region surface has a textured area and multiple planar areas formed by different pyramid-like structures surrounding the textured area. The surface of the second passivation layer facing away from the semiconductor substrate is textured, and adjacent pyramid-like structures on the side of the second passivation layer facing away from the semiconductor substrate are in contact with each other.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and more particularly to a back-contact battery and a photovoltaic module. Background Technology

[0002] A back-contact solar cell is a type of solar cell where the light-facing side of the cell has no electrodes, and both the positive and negative electrodes are located on the back side of the cell. This reduces the shading of the cells by the electrodes, increases the short-circuit current, and improves the energy conversion efficiency of the cell. Furthermore, on the back side of the back-contact solar cell, an isolation region is provided to separate the first and second doped semiconductor sections with opposite conductivity types, and to separate the first and second doped semiconductor sections from the side boundary of the cell. This reduces the risk of leakage and lowers the carrier recombination rate.

[0003] However, in existing back-contact batteries, the first passivation layer on the back side has a poor passivation effect on the isolation area, which is not conducive to reducing the number of surface defects in the isolation area, resulting in poor performance of the back-contact battery. Summary of the Invention

[0004] The purpose of this invention is to provide a back-contact battery and a photovoltaic module, which, while having a high light-trapping effect on the side of the second passivation layer away from the semiconductor substrate, also enables the first passivation layer to have a high passivation effect on the isolation area, reducing the number of surface defects in the isolation area and thus improving the working performance of the back-contact battery.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a back-contact battery comprising: a semiconductor substrate, a first doped semiconductor portion, a second doped semiconductor portion, a first passivation layer, and a second passivation layer. The semiconductor substrate includes a first surface and a second surface opposite to each other. The first surface includes a first region, a second region, and an isolation region. The first region and the second region are alternately distributed. The first surface has a boundary, and the isolation region is located between the first region and the second region, and between the boundary and the outermost first region and the outermost second region, respectively. The first doped semiconductor portion is disposed within or on the first region. The second doped semiconductor portion is disposed within or on the second region. The second doped semiconductor portion and the first doped semiconductor portion have opposite conductivity types. The first passivation layer covers the first doped semiconductor portion, the second doped semiconductor portion, and the isolation region. On the side of the first passivation layer facing away from the semiconductor substrate, the surface corresponding to the isolation region is the surface of the first region. The second passivation layer covers the second surface. The surface of the first region has a textured area and a plurality of planar regions formed by different pyramid-shaped structures included in the textured area. The surface of the second passivation layer facing away from the semiconductor substrate is textured, and the adjacent pyramid-shaped structures on the side of the second passivation layer facing away from the semiconductor substrate are in contact with each other.

[0006] In the back contact battery provided by the present invention, the first surface of the semiconductor substrate is provided with a first doped semiconductor portion and a second doped semiconductor portion. Based on this, it can be understood that the first surface of the semiconductor substrate corresponds to the back surface of the back contact battery, and the second surface of the semiconductor substrate corresponds to the front surface of the back contact battery. In this case, the second passivation layer of the back contact battery covers the second surface, and the surface of the second passivation layer facing away from the semiconductor substrate is textured. Adjacent pyramid-shaped structures on the side of the second passivation layer facing away from the semiconductor substrate are in contact with each other. At this time, the distribution density of the pyramid-shaped structures on the side of the second passivation layer facing away from the semiconductor substrate is relatively large, which is beneficial to increasing the specific surface area of ​​the side of the second passivation layer facing away from the semiconductor substrate, resulting in a good light-trapping effect on the side of the second passivation layer facing away from the semiconductor substrate, and thus a high light utilization rate on the front surface of the back contact battery.

[0007] In addition, the back contact battery also includes a first passivation layer disposed on the first doped semiconductor portion, the second doped semiconductor portion, and the isolation region. On the side of the first passivation layer facing away from the semiconductor substrate, the surface of the first region corresponding to the isolation region not only has a textured area to give the surface of the first region a certain light-trapping effect, but also has multiple planar areas formed by different pyramid-shaped structures included in the textured area. The planar areas and textured areas are flatter, so the surface of the first region has a lower surface roughness than the surface of the second passivation layer facing away from the semiconductor substrate. In the actual manufacturing process, the first passivation layer is usually formed on the first doped semiconductor portion, the second doped semiconductor portion, and the isolation region by a deposition process. The surface morphology of the first region of the first passivation layer can reflect the surface morphology of the isolation region of the semiconductor substrate to a certain extent. Therefore, when the surface of the first region has planar areas and its own roughness is relatively small, the surface roughness of the isolation region is also relatively small. This is beneficial to improving the formation quality and passivation effect of the first passivation layer on the isolation region, reducing the number of surface defects in the isolation region, and improving the working performance of the back contact battery.

[0008] As one possible implementation, among all pyramid-like structures on the surface of the second passivation layer away from the semiconductor substrate and on the surface of the first region, pyramid-like structures with at least four diagonally distributed side ridges are considered complete pyramid-like structures, while the remaining pyramid-like structures are considered incomplete pyramid-like structures. Furthermore, the proportion of complete pyramid-like structures per unit area on the surface of the second passivation layer away from the semiconductor substrate is greater than the proportion of complete pyramid-like structures per unit area on the surface of the first region.

[0009] With the above technical solution, the proportion of complete pyramid-shaped structures per unit area on the surface of the first region is relatively small, resulting in a greater number of undulating microstructures at the apex of the incomplete pyramid-shaped structures on the surface of the first region. This is beneficial for improving the light trapping effect of the surface of the first region and increasing the bifaciality of the back contact battery.

[0010] As one possible implementation, within the velvety area included on the surface of the first region, at least one side of a pyramid-shaped structure has a sheet-like protrusion. Along the direction extending from the side of the pyramid-shaped structure, the cross-sectional shape of the sheet-like protrusion is approximately triangular.

[0011] In the case of the above technical solution, in addition to the pyramid-shaped structure, at least one side of the pyramid-shaped structure within the textured area of ​​the first region surface has a sheet-like protrusion. This sheet-like protrusion can superimpose its own undulation on the original pyramid-shaped structure, and its cross-sectional shape is triangular. Compared to smooth shapes such as hemispherical shapes, the triangular shape has a certain sharp microstructure, which is beneficial for further increasing the surface roughness of the first region, improving the light-trapping effect of the first region surface, and thus improving the bifaciality of the back-contact battery.

[0012] As one possible implementation, the apex angle of at least one pyramid-like structure on the surface of the first region is greater than the apex angle of the pyramid-like structure on the side of the second passivation layer away from the semiconductor substrate.

[0013] When the above technical solution is adopted, compared with the pyramid-shaped structure on the side of the second passivation layer away from the semiconductor substrate, the first region surface has at least one pyramid-shaped structure with a relatively large apex angle. At this time, the sharpness of the top of the at least one pyramid-shaped structure on the surface of the first region is small, which is conducive to making the surface undulation of the isolation region less sharp, thereby reducing the stress of the first passivation layer at the undulation of the isolation region, reducing the risk of damage of the first passivation layer in the isolation region, and further improving the passivation effect of the first passivation layer on the isolation region.

[0014] As one possible implementation, the one-dimensional dimension of at least one pyramid-like structure on the surface of the first region is larger than the one-dimensional dimension of the pyramid-like structure on the side of the second passivation layer away from the semiconductor substrate.

[0015] When the above technical solution is adopted, compared with the pyramid-shaped structure on the side of the second passivation layer away from the semiconductor substrate, the first region surface has at least one pyramid-shaped structure with a relatively large one-dimensional size, which is beneficial to reduce the number of pyramid-shaped structures on the first region surface and reduce the undulation density of the first region surface. Correspondingly, it is beneficial to make the undulation density of the isolation region surface lower, thereby reducing the stress of the first passivation layer at the undulation of the isolation region, reducing the risk of damage of the first passivation layer in the isolation region, and further improving the passivation effect of the first passivation layer on the isolation region.

[0016] As one possible implementation, the first doped semiconductor portion is an emitter-doped portion. The isolation region surface includes a first sub-surface located between the boundary and the first region at the outermost edge, and a second sub-surface located between the boundary and the second region at the outermost edge. On the surface of the first passivation layer facing away from the semiconductor substrate, the region surface corresponding to the first sub-surface is the first sub-region surface, and the region surface corresponding to the second sub-surface is the second sub-region surface. The first and second sub-region surfaces have a pyramid-like structure. Specifically, the one-dimensional dimension of the pyramid-like structure within the first sub-region surface is larger than the one-dimensional dimension of the pyramid-like structure within the second sub-region surface; and / or, the uniformity of the one-dimensional dimension of the pyramid-like structure within the first sub-region surface is greater than the uniformity of the one-dimensional dimension of the pyramid-like structure within the second sub-region surface; and / or, the apex angle of the pyramid-like structure within the first sub-region surface is smaller than the apex angle of the pyramid-like structure within the second sub-region surface.

[0017] When the above technical solution is adopted, on the surface of the first passivation layer away from the semiconductor substrate, the first sub-region surface corresponding to the first sub-surface (near the emitter doped portion) has at least one of the following: one-dimensional dimension, one-dimensional dimension uniformity, and apex angle of the pyramid-like structure, which is larger than the one-dimensional dimension, one-dimensional dimension uniformity, and apex angle of the second sub-region surface. This is beneficial for increasing the undulation and surface roughness of the first sub-region surface, improving the light-trapping effect of the first sub-region surface, and allowing more light to be refracted into the first doped semiconductor portion adjacent to the first sub-region surface, thereby improving the bifaciality of the back contact cell. Simultaneously, the first doped semiconductor portion is the emitter doped portion. Since the emitter doped portion is used to provide electron-hole pair injection and separation, when more light is incident into the emitter doped portion, it is beneficial for exciting more photogenerated carriers, thereby improving the conversion efficiency of the back contact cell. The second sub-region surface corresponding to the second sub-surface has relatively low surface roughness, and correspondingly, the second sub-surface also has low surface roughness, which is beneficial for improving the deposition quality and passivation effect of the first passivation layer on the second sub-surface.

[0018] As one possible implementation, the isolation region surface includes a first sub-surface located between the boundary and the first region at the outermost edge, a second sub-surface located between the boundary and the second region at the outermost edge, and a third sub-surface located between the first and second regions. Furthermore, in the surface of the first passivation layer on the side facing away from the semiconductor substrate, the region surface corresponding to the portion of the first sub-surface is the first sub-region surface, the region surface corresponding to the portion of the second sub-surface is the second sub-region surface, and the region surface corresponding to the portion of the third sub-surface is the third sub-region surface. The second and third sub-region surfaces have a pyramidal structure. When the second doped semiconductor portion and the semiconductor substrate have the same conductivity type, the one-dimensional dimension of the pyramidal structure of the second sub-region surface is smaller than the one-dimensional dimension of the pyramidal structure of the third sub-region surface, and / or, the apex radius curvature of the pyramidal structure of the second sub-region surface is greater than the apex radius curvature of the pyramidal structure of the third sub-region surface.

[0019] When the above technical solution is adopted, the portion of the isolation region located between the first and second regions is mainly used to isolate the first and second doped semiconductor portions with opposite conductivity types, thereby reducing leakage current between them. Therefore, when the surface of the third sub-region corresponding to the third sub-surface in the side of the first passivation layer away from the semiconductor substrate has a relatively large one-dimensional size and a small apex corner radius, the surface of the third sub-region has a relatively large surface roughness, and correspondingly, the third sub-surface also has a large undulating morphology. This results in a higher etching degree of the isolation region in the area corresponding to the third sub-surface, which is beneficial for further reducing the leakage current risk between the first and second doped semiconductor portions. In addition, the second sub-region surface has a small pyramidal structure and a large apex corner radius, which is beneficial for the second sub-region surface and the second sub-surface to have low surface roughness, improving the passivation effect of the first passivation layer on the second sub-surface and reducing the number of defects on the second sub-surface.

[0020] As one possible implementation, the first surface is rectangular. Along the extension direction parallel to the long side of the rectangular shape, the width of the portion of the first sub-region surface and the second sub-region surface adjacent to one short side of the rectangular shape is greater than the width of the portion of the first sub-region surface and the second sub-region surface adjacent to the other short side of the rectangular shape.

[0021] When the above technical solution is adopted, if the width of the portion of the first sub-region surface and the second sub-region surface adjacent to one short side of the rectangle is greater than the width of the portion of the first sub-region surface and the second sub-region surface adjacent to the other short side of the rectangle, it indicates that the etching amounts of the first doped semiconductor portion and the second doped semiconductor portion are different at the two short sides along the extension direction parallel to the long side of the rectangle. This difference in etching amount is due to the influence of liquid churn when removing the coating on the second surface of the semiconductor substrate using equipment such as chain cleaning. This results in a larger amount of liquid churn at the leading edge along the etching direction, leading to a larger etching amount at the corresponding short sides of the first and second doped semiconductor portions at the etching leading edge. Therefore, having the extension direction of the long side of the rectangle aligned with the etching direction can reduce the impact of structural vibrations and other factors on etching accuracy during the etching process, improve etching stability and accuracy, and thus improve the yield of back contact batteries.

[0022] As one possible implementation, along the extension direction parallel to the long side, the width of the portion of the first sub-region surface and the second sub-region surface adjacent to one short side of the rectangular prism is greater than or equal to 10 μm and less than or equal to 50 μm; and / or, the width of the portion of the first sub-region surface and the second sub-region surface adjacent to another short side of the rectangular prism is greater than or equal to 3 μm and less than or equal to 10 μm. In this case, while ensuring that the coating layer around the semiconductor substrate can be completely removed by etching, the edge portions of the first and second doped semiconductor portions can be kept at a certain distance from the boundary of the first surface, which helps to reduce the risk of leakage. In addition, it can also prevent the area ratio of the first and second doped semiconductor portions on the first surface from being affected by the aforementioned excessive width, which is beneficial for the first and second doped semiconductor portions to have higher carrier collection capacity and field passivation effect.

[0023] As one possible implementation, the second doped semiconductor section has a wavy, alternating concave-convex structure along its edge at at least one corner near the first surface. In this case, it is not necessary to strictly control manufacturing precision to obtain a straight edge, which helps reduce the difficulty of the manufacturing process. Furthermore, the second doped semiconductor section also has a protrusion along the direction near the corner along its edge at at least one corner near the first surface, which can increase the area ratio of the second doped semiconductor section on one side of the first surface, thus improving the carrier collection capability and field passivation effect of the second doped semiconductor section.

[0024] As one possible implementation, both the first region and the second region include strip-shaped regions and connecting regions. The strip-shaped regions in both the first and second regions extend along a first direction and are alternately distributed along a second direction. The first direction is different from the second direction. The connecting regions in both the first and second regions extend along the second direction and are alternately distributed along the first direction. The connecting regions in the first region are connected to at least a portion of the strip-shaped regions in the first region, and the connecting regions in the second region are connected to at least a portion of the strip-shaped regions in the second region. The strip-shaped regions in the first region are discontinuous at their intersection with the connecting regions in the second region, and the strip-shaped regions in the second region are also discontinuous at their intersection with the connecting regions in the first region. The first surface has a chamfer, and the first region has an extension at the chamfer, the extension extending along the second direction, and the extension and the strip-shaped regions in the second region are spaced apart along the first direction. In the first doped semiconductor portion, the edge line near the chamfer has a first undulating morphology, and the edge line near the contour line continuous with the chamfer has a second undulating morphology. Wherein, along the direction from the edge of the first surface to the center, the undulation height of the first undulation is greater than the undulation height of the second undulation, and / or, the width of the protrusion in the first undulation is less than the width of the protrusion in the second undulation.

[0025] With the above technical solution, there is no need to strictly control manufacturing precision to obtain straight edges, which helps to reduce the difficulty of the manufacturing process. In addition, due to the influence of cutting and other factors, there are more surface defects at the chamfer of the first face. Therefore, when the undulation height of the first undulation near the chamfer is greater than the undulation height of the second undulation near the contour line continuous with the chamfer, the distance between the concave portion of the first doped semiconductor portion and the chamfer boundary is larger, which helps to reduce the risk of leakage. When the width of the convex portion in the first undulation is smaller than the width of the convex portion in the second undulation, the density of the concave portion in the first undulation is greater, which can also reduce the risk of leakage.

[0026] As one possible implementation, the undulation height of the first undulation is greater than or equal to 3 μm and less than or equal to 10 μm; and / or, the width of the protrusion in the first undulation is greater than or equal to 15 μm and less than or equal to 40 μm. In this case, while further reducing the risk of leakage current, the first doped semiconductor portion can have a large area ratio on one side of the first surface, which is beneficial to improving the carrier collection capability and field passivation effect of the first doped semiconductor portion.

[0027] In a second aspect, the present invention provides a photovoltaic module comprising a back contact battery provided in the first aspect and various implementations thereof.

[0028] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0029] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0030] Figure 1 A longitudinal cross-sectional view of a first structure of a back-contact battery provided in an embodiment of the present invention;

[0031] Figure 2 This is a SEM image of a portion of the second passivation layer on the side facing away from the semiconductor substrate in a back-contact battery provided in an embodiment of the present invention.

[0032] Figure 3 This is a SEM image of a portion of the surface of the first region in the back contact battery provided in an embodiment of the present invention;

[0033] Figure 4 This is a SEM image of a portion of the surface of the first sub-region in the back contact battery provided in an embodiment of the present invention;

[0034] Figure 5 This is a SEM image of a portion of the surface of the second sub-region in a back-contact battery provided in an embodiment of the present invention.

[0035] Figure 6 A schematic diagram of the distribution relationship between the first region and the second region in the back contact battery provided in an embodiment of the present invention. Figure 1 ;

[0036] Figure 7 A schematic diagram of the distribution relationship between the first region and the second region in the back contact battery provided in an embodiment of the present invention. Figure 2 ;

[0037] Figure 8 A schematic diagram of the distribution relationship between the first region and the second region in the back contact battery provided in an embodiment of the present invention. Figure 3 ;

[0038] Figure 9 A longitudinal cross-sectional view of a second structure of a back-contact battery provided in an embodiment of the present invention;

[0039] Figure 10 A longitudinal cross-sectional view of a third structure of a back-contact battery provided in an embodiment of the present invention;

[0040] Figure 11 A longitudinal cross-sectional view of the fourth structure of the back contact battery provided in an embodiment of the present invention;

[0041] Figure 12 A longitudinal cross-sectional view of the fifth structure of the back contact battery provided in an embodiment of the present invention;

[0042] Figure 13 This is a schematic diagram showing the distribution relationship between a portion of the first doped semiconductor portion and a portion of the second doped semiconductor portion in a back contact battery provided in an embodiment of the present invention.

[0043] Figure 14 This is a schematic diagram showing the distribution of a portion of the second doped semiconductor in a back contact battery provided in an embodiment of the present invention;

[0044] Figure 15 This is a longitudinal cross-sectional schematic diagram of the sixth structure of the back contact battery provided in an embodiment of the present invention;

[0045] Figure 16 This is a longitudinal cross-sectional schematic diagram of the seventh structure of the back contact battery provided in an embodiment of the present invention;

[0046] Figure 17 This is a longitudinal cross-sectional view of the eighth structure of the back contact battery provided in an embodiment of the present invention.

[0047] Reference numerals: 11 Semiconductor substrate, 12 First region, 13 Second region, 14 Isolation region, 15 First doped semiconductor portion, 16 Second doped semiconductor portion, 17 First passivation layer, 18 Second passivation layer, 19 First region surface, 20 Textured region, 21 Planar region, 22 Complete pyramid-like structure, 23 Incomplete pyramid-like structure, 24 Sheet-like protrusion, 25 First sub-surface, 26 Second sub-surface, 27 Third sub-surface, 28 First sub-region surface, 29 Second sub-region surface, 30 Third sub-region surface, 31 Strip-shaped region, 32 Connection region, 33 Extension, 34 First surface passivation layer, 35 First antireflection layer, 36 First transparent conductive layer, 37 Second surface passivation layer, 38 Second antireflection layer, 39 First interface passivation layer, 40 Second interface passivation layer. Detailed Implementation

[0048] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0049] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0050] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0052] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0053] A solar cell is a device that converts sunlight into electrical energy. Specifically, when a solar cell is in operation, sunlight shines on the semiconductor pn junction, forming new electron-hole pairs. Under the influence of the built-in electric field of the pn junction, photogenerated holes flow to the p-region, and photogenerated electrons flow to the n-region. When the circuit is connected, an electric current is generated. Solar cells where both the positive and negative electrodes are located on the back side of the cell are called back-contact cells. Compared to double-sided contact solar cells, the front side of a back-contact cell has no metal electrodes to block the light, resulting in higher light utilization on the light-facing side. Therefore, back-contact cells have higher short-circuit current and photoelectric conversion efficiency, making them one of the current technological directions for achieving high-efficiency crystalline silicon solar cells.

[0054] Specifically, a back-contact battery typically includes a semiconductor substrate, a first doped semiconductor portion, a second doped semiconductor portion, and a first passivation layer. The first and second doped semiconductor portions are alternately distributed on one side of the semiconductor substrate corresponding to the back side of the battery. Furthermore, the back-contact battery has isolation regions between the first and second doped semiconductor portions (which have opposite conductivity types) and between the first and second doped semiconductor portions and the side boundaries of the semiconductor substrate, respectively, to reduce leakage risk and decrease carrier recombination rate. The first passivation layer covers the side of the first and second doped semiconductor portions away from the semiconductor substrate and also covers the isolation regions, reducing the number of defects on the contact surface and decreasing the carrier recombination rate.

[0055] Furthermore, to improve the light utilization rate of back-contact batteries, texturing is typically performed on the light-facing side of the battery and the isolation area to enhance the light-trapping effect in these two areas. In actual manufacturing, to improve production efficiency, texturing of the light-facing side and the isolation area is often performed simultaneously. This results in a larger specific surface area and higher surface undulation in the isolation area, leading to a poor passivation effect of the first passivation layer. This hinders the reduction of surface defects in the isolation area, resulting in poor performance of the back-contact battery.

[0056] To address the aforementioned technical problems, in a first aspect, embodiments of the present invention provide a back-contact battery. For example... Figures 1 to 5As shown, the back contact battery provided in this embodiment of the invention includes: a semiconductor substrate 11, a first doped semiconductor portion 15, a second doped semiconductor portion 16, a first passivation layer 17, and a second passivation layer 18. The semiconductor substrate 11 includes a first surface and a second surface facing each other. The first surface includes a first region 12, a second region 13, and an isolation region 14. The first region 12 and the second region 13 are alternately distributed. The first surface has a boundary, and the isolation region 14 is located between the first region 12 and the second region 13, and between the boundary and the outermost first region 12 and the outermost second region 13, respectively. The first doped semiconductor portion 15 is disposed within or on the first region 12. The second doped semiconductor portion 16 is disposed within or on the second region 13. The second doped semiconductor portion 16 and the first doped semiconductor portion 15 have opposite conductivity types. The first passivation layer 17 covers the first doped semiconductor portion 15, the second doped semiconductor portion 16, and the isolation region 14. On the side of the first passivation layer 17 facing away from the semiconductor substrate 11, the surface corresponding to the portion of the isolation region 14 is the first region surface 19. A second passivation layer 18 covers the second surface. The first region surface 19 has a textured region 20 and a plurality of planar regions 21 formed by different pyramid-like structures surrounding the textured region 20. The surface of the second passivation layer 18 facing away from the semiconductor substrate 11 is textured, and adjacent pyramid-like structures within the second passivation layer 18 facing away from the semiconductor substrate 11 are in contact with each other.

[0057] When the above technical solution is adopted, such as Figures 1 to 5 As shown, in the back contact battery provided in this embodiment of the invention, a first doped semiconductor portion 15 and a second doped semiconductor portion 16 are provided on one side of the first surface of the semiconductor substrate 11. Based on this, it can be understood that the first surface of the semiconductor substrate 11 corresponds to the back side of the back contact battery, and the second surface of the semiconductor substrate 11 corresponds to the front side of the back contact battery. In this case, the second passivation layer 18 included in the back contact battery covers the second surface, and the surface of the second passivation layer 18 facing away from the semiconductor substrate 11 is textured. Adjacent pyramid-shaped structures within the second passivation layer 18 facing away from the semiconductor substrate 11 are in contact with each other. At this time, the distribution density of the pyramid-shaped structures within the second passivation layer 18 facing away from the semiconductor substrate 11 is relatively large, which is beneficial to increasing the specific surface area of ​​the second passivation layer 18 facing away from the semiconductor substrate 11, so that the second passivation layer 18 facing away from the semiconductor substrate 11 has a good light-trapping effect, and the front side of the back contact battery has a high light utilization rate. Furthermore, as... Figures 1 to 5As shown, the back contact battery also includes a first passivation layer 17 disposed on the first doped semiconductor portion 15, the second doped semiconductor portion 16, and the isolation region 14. On the side of the first passivation layer 17 facing away from the semiconductor substrate 11, the first region surface 19 corresponding to the isolation region 14 not only has a textured region 20 to give the first region surface 19 a certain light trapping effect, but also has a plurality of planar regions 21 formed by different pyramid-shaped structures included in the textured region 20. The planar regions 21 are flatter than the textured region 20, so that the first region surface 19 has a lower surface roughness than the surface of the second passivation layer 18 facing away from the semiconductor substrate 11. In the actual manufacturing process, the first passivation layer 17 is usually formed on the first doped semiconductor portion 15, the second doped semiconductor portion 16 and the isolation region 14 by deposition process. The morphology of the first region surface 19 of the first passivation layer 17 can reflect the surface morphology of the isolation region 14 of the semiconductor substrate 11 to a certain extent. Therefore, when the first region surface 19 has a planar region 21 and its roughness is relatively small, the surface roughness of the isolation region 14 is also relatively small. This is beneficial to improving the formation quality and passivation effect of the first passivation layer 17 on the isolation region 14, reducing the number of surface defects in the isolation region 14, and improving the working performance of the back contact battery.

[0058] In practical applications, the embodiments of the present invention do not specifically limit the material and conductivity type of the semiconductor substrate. For example, the semiconductor substrate can be a silicon substrate. Alternatively, the semiconductor substrate can be a germanium-silicon substrate, a germanium substrate, or a gallium arsenide substrate, or any other semiconductor material. Furthermore, the semiconductor substrate can be a P-type semiconductor substrate, an N-type semiconductor substrate, or an intrinsic semiconductor substrate.

[0059] Secondly, the aforementioned semiconductor substrate includes a first surface and a second surface, with the first surface corresponding to the back side of the back contact battery and the second surface corresponding to the front side of the back contact battery. The distribution of the first region, the second region, and the isolation region on the first surface can be determined based on the distribution of the first doped semiconductor portion and the second doped semiconductor portion formed on one side of the first surface. Specifically, since the first doped semiconductor portion of the back contact battery is disposed within or on the first region, the distribution range of the first region on the first surface can be determined based on the distribution requirements of the first doped semiconductor portion in the actual application scenario. Since the second doped semiconductor portion of the back contact battery is disposed within or on the second region of the first surface, the distribution range of the second region on the first surface can be determined based on the distribution requirements of the second doped semiconductor portion on one side of the first surface of the semiconductor substrate in the actual application scenario. As for the isolation region, after the ranges of the first and second regions are determined, the range of the isolation region on the first surface can also be determined.

[0060] It is understandable that in the first surface of the semiconductor substrate, one of the first region and the second region roughly corresponds to the emitter region, and the other roughly corresponds to the back field region. Among them, one of the first region and the second region corresponds to the P-region, and the other corresponds to the N-region. The isolation region is the other regions in the first surface besides the P-region and the N-region.

[0061] The shapes of the first area, the second area, and the isolation area can be determined based on the actual application scenario; no specific limitations are made here. For example: Figure 6 As shown, the first region 12 and the second region 13 can be distributed in an alternating strip pattern. For example: Figure 7 and Figure 8 As shown, at least some regions in the first region 12 and the second region 13 can also be distributed in an alternating, interdigitated pattern.

[0062] Regarding the specific surface morphology of the second side of the semiconductor substrate, it is understood that the second passivation layer is formed on the second side using a deposition process. The surface undulation morphology of the side of the second passivation layer away from the semiconductor substrate can, to some extent, reflect the surface undulation morphology of the second side of the semiconductor substrate. Therefore, the surface morphology of the second side can be referenced to the surface morphology of the side of the second passivation layer away from the semiconductor substrate. In some examples, such as... Figure 1 As shown, because the surface of the second passivation layer 18 facing away from the semiconductor substrate 11 is textured, and adjacent pyramid-like structures within the second passivation layer 18 facing away from the semiconductor substrate 11 are in contact with each other, the second surface of the semiconductor substrate 11 is textured, and adjacent pyramid-like structures within the second surface are in contact with each other. For the specific morphology, one-dimensional dimensions, and distribution of the pyramid-like structures on the second surface, please refer to the information below regarding the specific morphology, one-dimensional dimensions, and distribution of the pyramid-like structures on the surface of the second passivation layer 18 facing away from the semiconductor substrate 11; these details will not be repeated here.

[0063] Regarding the specific morphology of the first surface of the semiconductor substrate, as mentioned above, the surface undulation morphology of the first passivation layer on the side facing away from the semiconductor substrate can, to a certain extent, reflect the surface undulation morphology of the first surface of the semiconductor substrate. Therefore, the surface morphology of the first doped semiconductor portion and the second doped semiconductor portion on the side facing away from the semiconductor substrate, as well as the surface morphology of the isolation region in the first surface, can be referenced to the surface morphology of the first passivation layer on the side facing away from the semiconductor substrate. In some examples, the surface of the first region corresponding to the isolation region on the side of the first passivation layer facing away from the semiconductor substrate has a textured region and multiple planar regions formed by different pyramid-like structures included in the textured region. Therefore, in the first surface of the semiconductor substrate, the surface of the isolation region has a textured region and multiple planar regions formed by different pyramid-like structures included in the textured region, in order to improve the passivation effect of the first passivation layer on the isolation region and reduce the carrier recombination rate at the isolation region. The information regarding the extent and distribution of the velvety and planar areas in the isolation region, as well as the one-dimensional dimensions, morphology, and distribution of the pyramid-like structure in the velvety area, can be found in the information below regarding the extent and distribution of the velvety and planar areas on the surface of the first region, as well as the one-dimensional dimensions, morphology, and distribution of the pyramid-like structure in the velvety area. For example, the planar area can include one of a planar structure, a regular or irregular pyramidal base structure, as long as it is flatter and has lower roughness than the velvety area.

[0064] In addition, for quarantine areas, such as Figure 1 As shown, the surface of the isolation region includes a first sub-surface 25 located between the boundary and the first region 12 at the outermost edge, a second sub-surface 26 located between the boundary and the second region 13 at the outermost edge, and a third sub-surface 27 located between the first region 12 and the second region 13. Correspondingly, in the surface of the first passivation layer 17 on the side facing away from the semiconductor substrate 11, the region surface corresponding to the first sub-surface 25 is the first sub-region surface 28, the region surface corresponding to the second sub-surface 26 is the second sub-region surface 29, and the region surface corresponding to the third sub-surface 27 is the third sub-region surface 30. The surface morphologies of the first sub-surface 25, second sub-surface 26, and third sub-surface 27 of the isolation region 14 can be referred to below for the surface morphologies of the first sub-surface 28, second sub-surface 29, and third sub-surface 30 in the side of the first passivation layer 17 facing away from the semiconductor substrate 11, and will not be repeated here.

[0065] Regarding the first doped semiconductor portion and the second doped semiconductor portion described above, in terms of conductivity type, the embodiments of the present invention do not specifically limit the conductivity type of the first doped semiconductor portion and the second doped semiconductor portion, as long as the conductivity types of the first doped semiconductor portion and the second doped semiconductor portion are opposite. Specifically, the conductivity type of the first doped semiconductor portion can be N-type, and the conductivity type of the second doped semiconductor portion can be P-type. Alternatively, the conductivity type of the first doped semiconductor portion can also be P-type, and the conductivity type of the second doped semiconductor portion can be N-type.

[0066] In terms of formation location, such as Figure 1 , Figures 9 to 11 As shown, the first doped semiconductor portion 15 can be a doped region disposed in the first region 12, or it can be a doped semiconductor layer formed on the first region 12. Secondly, the second doped semiconductor portion 16 can be a doped region disposed in the second region 13, or it can be a doped semiconductor layer formed on the second region 13.

[0067] The first doped semiconductor portion and the second doped semiconductor portion can both be doped regions formed in the semiconductor substrate; they can both be doped semiconductor layers formed on the semiconductor substrate; or one of the first doped semiconductor portion and the second doped semiconductor portion can be a doped region and the other a doped semiconductor layer.

[0068] When the first doped semiconductor portion and / or the second doped semiconductor portion are doped semiconductor layers, the material of the doped semiconductor layer may include any semiconductor material such as silicon, germanium silicon, germanium, or gallium arsenide. In terms of the arrangement of matter, the crystal phase of the doped semiconductor layer may be amorphous, microcrystalline, nanocrystalline, single crystal, or polycrystalline.

[0069] When both the first doped semiconductor section and the second doped semiconductor section are doped semiconductor layers, the materials of the first doped semiconductor section and the second doped semiconductor section can be the same or different.

[0070] For example, the materials of the first doped semiconductor section and the second doped semiconductor section can both be polycrystalline silicon or amorphous silicon.

[0071] For example, one of the first doped semiconductor section and the second doped semiconductor section is made of polycrystalline silicon, and the other is made of amorphous silicon.

[0072] Secondly, such as Figure 1 As shown, when the first doped semiconductor portion 15 is a doped semiconductor layer, the first doped semiconductor portion 15 can be directly disposed on the first region 12. Alternatively, as... Figure 12As shown, the aforementioned back contact battery may further include a first interface passivation layer 39 located between the first doped semiconductor portion 15 and the semiconductor substrate 11. In this case, the passivated contact structure formed by the first interface passivation layer 39 and the first doped semiconductor portion 15 has excellent interface passivation effect and can achieve selective collection of charge carriers, reduce the carrier recombination rate of the first region 12 on the first surface of the semiconductor substrate 11, and further improve the photoelectric conversion efficiency of the back contact battery. The material and thickness of the first interface passivation layer 39 can be set according to the material of the first doped semiconductor portion 15 and actual needs, and are not specifically limited here. For example, when the material of the first doped semiconductor portion is doped polycrystalline silicon, the first interface passivation layer is a tunneling oxide layer. As another example, when the material of the first doped semiconductor portion includes at least one of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the first interface passivation layer is an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, an intrinsic nanocrystalline silicon layer, or a mixture of the above three layers.

[0073] As for the second doped semiconductor section, such as Figure 1 As shown, when the second doped semiconductor portion 16 is a doped semiconductor layer, the second doped semiconductor portion 16 can be directly disposed on the second region 13. Alternatively, as... Figure 12 As shown, the aforementioned back contact battery may further include a second interface passivation layer 40, which is located between the semiconductor substrate 11 and the second doped semiconductor portion 16. In this case, the passivated contact structure composed of the second interface passivation layer 40 and the second doped semiconductor portion 16 can achieve selective collection of charge carriers and reduce the carrier recombination rate in the second region 13 of the first surface of the semiconductor substrate 11. The principle for setting the material and thickness of the second interface passivation layer 40 can refer to the principle for setting the material and thickness of the first interface passivation layer 39 described above, and will not be repeated here.

[0074] As for the edge morphology of the first doped semiconductor portion and the second doped semiconductor portion near the isolation region, it can be determined based on the morphology of the first region and the second region, the conductivity type of the first doped semiconductor portion and the second doped semiconductor portion, and their manufacturing order, and no specific limitation is made here.

[0075] For example, such as Figure 7 and Figure 8As shown, the first surface has a first region 12 and a second region 13, both of which include strip-shaped regions 31 and connecting regions 32. The strip-shaped regions 31 in the first region 12 and the second region 13 both extend along a first direction and are alternately distributed along a second direction. The first direction is different from the second direction. Furthermore, the connecting regions 32 in the first region 12 and the second region 13 both extend along the second direction and are alternately distributed along the first direction. The connecting regions 32 in the first region 12 are connected to at least a portion of the strip-shaped regions 31 in the first region 12, and the connecting regions 32 in the second region 13 are connected to at least a portion of the strip-shaped regions 31 in the second region 13. The strip-shaped regions 31 in the first region 12 are disconnected at their intersection with the connecting regions 32 in the second region 13, and the strip-shaped regions 31 in the second region 13 are also disconnected at their intersection with the connecting regions 32 in the first region 12. In the above case, as... Figure 13 As shown, the first surface has a chamfer, and the first region 12 has an extension 33 at the chamfer. The extension 33 extends along a second direction, and the extension 33 and the strip-shaped region 31 included in the second region 13 are spaced apart along the first direction. In the first doped semiconductor region 15, the edge line near the chamfer has a first undulating morphology, and the edge line near the contour line continuous with the chamfer has a second undulating morphology. Specifically, along the direction from the edge to the center of the first surface, the undulation height of the first undulation morphology is greater than the undulation height of the second undulation morphology, and / or, the width of the protrusion in the first undulation morphology is smaller than the width of the protrusion in the second undulation morphology.

[0076] With the above technical solution, there is no need to strictly control manufacturing precision to obtain straight edges, which helps to reduce the difficulty of the manufacturing process. In addition, due to the influence of cutting and other factors, there are more surface defects at the chamfer of the first face. Therefore, when the undulation height of the first undulation near the chamfer is greater than the undulation height of the second undulation near the contour line continuous with the chamfer, the distance between the concave portion of the first doped semiconductor portion and the chamfer boundary is larger, which helps to reduce the risk of leakage. When the width of the convex portion in the first undulation is smaller than the width of the convex portion in the second undulation, the density of the concave portion in the first undulation is greater, which can also reduce the risk of leakage.

[0077] Specifically, the first direction and the second direction can be any two directions parallel to the first surface and different from each other. Optionally, the first direction and the second direction can be orthogonal.

[0078] In addition, the lengths of the connecting areas in the first region and the connecting areas in the second region, the number of rows of the connecting areas in the first region and the strip-shaped areas arranged along the second direction in the first region, and the number of rows of the connecting areas in the second region and the strip-shaped areas arranged along the second direction in the second region can be determined according to the morphological requirements of the positive and negative electrodes in the actual application scenario, and are not specifically limited here.

[0079] The shape and size of the strip-shaped area and the connecting area included in the first region and the second region, the distance between the connecting area included in the first region and the adjacent strip-shaped area included in the second region, and the distance between the connecting area included in the second region and the adjacent strip-shaped area included in the first region can be determined according to the shape of the first doped semiconductor part and the second doped semiconductor part on one side of the first surface in the actual application scenario, and no specific limitation is made here.

[0080] As for the extension at the chamfer of the first region, the shape of the extension, the length of the extension along the second direction, and the distance between the extension and the strip-shaped area included in the second region along the first direction can be determined based on the area ratio of the first doped semiconductor part on the first side of the actual application scenario, and the leakage prevention requirements between the first doped semiconductor part and the semiconductor substrate and the second doped semiconductor part, respectively. No specific limitation is made here.

[0081] As for the type of undulation, height of undulation, and width of undulation in the first undulation morphology and the second undulation morphology of the first doped semiconductor part, these dimensions can be determined based on the actual manufacturing process and the leakage risk and passivation effect requirements of the first doped semiconductor part at the chamfer of the first surface in the actual application scenario. No specific limitations are made here.

[0082] For example, the first undulation morphology and / or the second undulation morphology can be a sawtooth undulation morphology, a wave-like undulation morphology, or a trapezoidal broken-line undulation morphology, etc.

[0083] For example, the height of the first undulation can be greater than or equal to 3 μm and less than or equal to 10 μm. For instance, the height of the first undulation can be 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm. In this case, while further reducing the risk of leakage current, the first doped semiconductor portion can have a larger area ratio on one side of the first surface, which is beneficial for improving the carrier collection capability and field passivation effect of the first doped semiconductor portion.

[0084] For example, the width of the protrusion in the first undulation morphology is greater than or equal to 15 μm and less than or equal to 40 μm. The width of the protrusion in the first undulation morphology can be 15 μm, 18 μm, 20 μm, 22 μm, 25 μm, 28 μm, 30 μm, 32 μm, 35 μm, 38 μm, or 40 μm, etc. In this case, while further reducing the risk of leakage current, the first doped semiconductor portion can have a large area ratio on one side of the first surface, which is beneficial to improving the carrier collection capability and field passivation effect of the first doped semiconductor portion.

[0085] For example, such as Figure 14 As shown, the second doped semiconductor portion 16 may have a wavy, alternating concave-convex structure on its edge at at least one corner near the first surface. In this case, it is not necessary to strictly control manufacturing precision to obtain a straight edge, which helps to reduce the difficulty of the manufacturing process. In addition, the second doped semiconductor portion 16 also has a protrusion along the direction near the corner in the edge at at least one corner near the first surface, which can increase the area ratio of the second doped semiconductor portion 16 on the first surface side, which helps to improve the carrier collection capability and field passivation effect of the second doped semiconductor portion 16.

[0086] Of course, the edge of the second doped semiconductor section at at least one corner near the first surface may also be in the form of a straight line or a broken line.

[0087] Regarding the aforementioned second passivation layer, its specific structure and materials can be determined based on the type of solar cell and the actual application scenario, and are not specifically limited here. For example, the passivation layer may include a second surface passivation layer and / or a second anti-reflection layer.

[0088] like Figure 15 As shown, when the second passivation layer 18 includes a second surface passivation layer 37 and / or a second antireflection layer 38, the surface of the second passivation layer 18 facing away from the semiconductor substrate 11 is the outermost surface of the films included in the second passivation layer 18 (i.e., the surface with the largest distance from the semiconductor substrate 11 along the thickness direction of the semiconductor substrate 11). A pyramid-shaped structure is provided on the outermost surface of the second passivation layer 18.

[0089] For example: Figure 15As shown, when the second passivation layer 18 includes only the second surface passivation layer 37 and the second antireflection layer 38, and the second antireflection layer 38 is disposed on the side of the second surface passivation layer 37 facing away from the semiconductor substrate 11, the surface of the second passivation layer 18 facing away from the semiconductor substrate 11 is the surface of the second antireflection layer 38 facing away from the semiconductor substrate 11. The surface of the second antireflection layer 38 facing away from the semiconductor substrate 11 is textured.

[0090] Furthermore, the materials of the aforementioned second surface passivation layer and antireflection layer can be selected according to actual needs. For example, the material of the second surface passivation layer may include any material with passivation properties, such as silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride. The material of the second antireflection layer may include silicon nitride or silicon oxynitride.

[0091] The embodiments of the present invention do not specifically limit the morphology, one-dimensional size and distribution of the pyramid-shaped structure on the side of the second passivation layer away from the semiconductor substrate. The morphology can be determined according to the requirements of the light trapping effect on the front side of the back contact battery in the actual application scenario.

[0092] For example, the side length of the bottom surface or the diagonal length of the bottom surface of at least one pyramid-shaped structure in the side of the second passivation layer away from the semiconductor substrate can be greater than or equal to 0.05 μm and less than or equal to 4 μm;

[0093] For example, the height of at least one pyramid-like structure on the side of the second passivation layer away from the semiconductor substrate can be greater than or equal to 0.1 μm and less than or equal to 3 μm.

[0094] For example, the apex angle of at least one pyramid-like structure on the side of the second passivation layer away from the semiconductor substrate can be greater than or equal to 65° and less than or equal to 100°.

[0095] The base of the pyramid-like structure on the side of the second passivation layer away from the semiconductor substrate can be a polygon such as a quadrilateral, pentagon, or hexagon. The adjacent sides of the polygon can be of equal or unequal length. The pyramid-like structure on the side of the second passivation layer away from the semiconductor substrate can have relatively sharp side edges and apex corners, or it can have smooth transitions at the side edges and apex corners.

[0096] Furthermore, among all pyramid-like structures on the surface of the second passivation layer facing away from the semiconductor substrate, a pyramid-like structure with at least four diagonally distributed side ridges is defined as a complete pyramid-like structure, and the remaining pyramid-like structures are defined as incomplete pyramid-like structures. The proportion of complete pyramid-like structures per unit area on the side of the second passivation layer facing away from the semiconductor substrate can be set according to the light-trapping effect requirements of the surface in the actual application scenario, and is not specifically limited here. The size of the aforementioned unit area can be defined according to actual needs and is not specifically limited here. For example, the unit area can be less than or equal to 5 μm. 2 and less than or equal to 5000μm 2 Any value in the range. For example, the unit area can be greater than or equal to 30μm. 2 and less than or equal to 2000μm 2 .

[0097] For example, among all pyramid-shaped structures on the surface of the second passivation layer away from the semiconductor substrate, the proportion of complete pyramid-shaped structures in a unit area on the side of the second passivation layer away from the semiconductor substrate can be greater than or equal to 40% and less than or equal to 90%.

[0098] Regarding the first passivation layer, its specific structure and materials can be determined based on the materials of the first and second doped semiconductor portions, as well as the actual application scenario; no specific limitations are made here. For example, the first passivation layer may include at least one of a first surface passivation layer, a first antireflection layer, and a first transparent conductive layer.

[0099] like Figure 16 and Figure 17 As shown, when the first passivation layer 17 includes at least one of the first surface passivation layer 34, the first antireflection layer 35, and the first transparent conductive layer 36, the side surface of the first passivation layer 17 facing away from the semiconductor substrate 11 is the outermost of the layers included in the first passivation layer 17 (i.e., the one with the largest distance from the semiconductor substrate 11 along the thickness direction of the semiconductor substrate 11), and it faces away from the semiconductor substrate 11. The textured region 20 and the planar region 21 on the side of the first passivation layer 17 facing away from the semiconductor substrate 11 are disposed on the outermost of the layers included in the first passivation layer 17, and it faces away from the semiconductor substrate 11.

[0100] For example: Figure 16As shown, when the first passivation layer 17 includes only the first surface passivation layer 34 and the first antireflection layer 35, and the first antireflection layer 35 is disposed on the side of the first surface passivation layer 34 facing away from the semiconductor substrate 11, the side surface of the first passivation layer 17 facing away from the semiconductor substrate 11 is the side surface of the first antireflection layer 35 facing away from the semiconductor substrate 11. The textured region 20 and the planar region 21 of the side surface of the first passivation layer 17 facing away from the semiconductor substrate 11 are disposed on the side surface of the first antireflection layer 35 facing away from the semiconductor substrate 11.

[0101] For example: Figure 17 As shown, when the first passivation layer 17 includes only the first transparent conductive layer 36, the side surface of the first passivation layer 17 facing away from the semiconductor substrate 11 is the side surface of the first transparent conductive layer 36 facing away from the semiconductor substrate 11. The textured region 20 and the planar region 21 of the side surface of the first passivation layer 17 facing away from the semiconductor substrate 11 are disposed on the side surface of the first transparent conductive layer 36 facing away from the semiconductor substrate 11.

[0102] Furthermore, the materials of the first surface passivation layer, the first antireflective layer, and the first transparent conductive layer can be selected according to actual needs. For example, the material of the first surface passivation layer may include any material with passivation properties such as silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride. The material of the first antireflective layer may include silicon nitride or silicon oxynitride. The material of the first transparent conductive layer may include at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide.

[0103] It should be noted that when the first passivation layer includes a first transparent conductive layer, the portion of the first transparent conductive layer corresponding to the first region is electrically insulated from the portion of the first transparent conductive layer corresponding to the second region to prevent short circuits.

[0104] As can be understood, as mentioned earlier, on the side of the first passivation layer facing away from the semiconductor substrate, the surface of the first region corresponding to the isolation area not only has a textured area to provide a certain light-trapping effect, but also has multiple planar areas formed by different pyramid-like structures surrounding the textured area. The planar and textured areas are flatter, resulting in a lower surface roughness on the surface of the first region compared to the side of the second passivation layer facing away from the semiconductor substrate. Consequently, the surface roughness of the isolation area is also relatively small, which is beneficial for improving the formation quality and passivation effect of the first passivation layer on the isolation area and reducing the number of surface defects in the isolation area. Therefore, based on the requirements for the light-trapping effect of the first region surface and the passivation effect of the first passivation layer on the isolation area in the actual application scenario, the area ratio of the textured and planar areas, the distribution of the planar areas, and the size and morphology of the pyramid-like structures included in the textured area on the side of the first passivation layer facing away from the semiconductor substrate can be determined. No specific limitations are made here.

[0105] For example, such as Figures 2 to 5 As shown, among all pyramid-like structures within the surface 19 of the first region, a pyramid-like structure with at least four diagonally distributed side ridges is defined as a complete pyramid-like structure 22, and the remaining pyramid-like structures are defined as incomplete pyramid-like structures 23. Furthermore, the proportion of complete pyramid-like structures 22 per unit area on the side of the second passivation layer 18 facing away from the semiconductor substrate 11 can be greater than the proportion of complete pyramid-like structures 22 per unit area on the surface 19 of the first region. In this case, the proportion of complete pyramid-like structures 22 per unit area on the surface 19 of the first region is smaller, resulting in a greater number of ridge-undulating microstructures at the apex of the incomplete pyramid-like structures 23 within the surface 19 of the first region. This is beneficial for improving the light-trapping effect of the surface 19 of the first region and increasing the bifaciality of the back contact cell.

[0106] The proportion of complete pyramid-shaped structures per unit area on the surface of the first region, and the difference between the proportion of complete pyramid-shaped structures on the side of the second passivation layer away from the semiconductor substrate and on the surface of the first region, can be determined based on the light-trapping effect requirements of the side of the second passivation layer away from the semiconductor substrate and the surface of the first region in the actual application scenario, and are not specifically limited here.

[0107] Specifically, the proportion of complete pyramid-shaped structures in the first sub-region surface, the second sub-region surface, and the third sub-region surface of the first region may all be greater than the proportion of complete pyramid-shaped structures in the surface of the second passivation layer facing away from the semiconductor substrate. Alternatively, the proportion of complete pyramid-shaped structures in any one or both of these areas may be greater than the proportion of complete pyramid-shaped structures in the surface of the second passivation layer facing away from the semiconductor substrate.

[0108] Optionally, the proportion of complete pyramid-like structures on the surface of the third sub-region is greater than the proportion of complete pyramid-like structures on the surface of the second passivation layer facing away from the semiconductor substrate.

[0109] For example, the proportion of complete pyramid-shaped structures in a unit area of ​​the surface of the third sub-region can be greater than or equal to 5% and less than or equal to 40% of all pyramid-shaped structures.

[0110] For example, the proportion of complete pyramid-shaped structures in a unit area of ​​the surface of the first sub-region can be greater than or equal to 40% and less than or equal to 90% of all pyramid-shaped structures.

[0111] For example, the proportion of complete pyramid-shaped structures in a unit area of ​​the second sub-region surface can be greater than or equal to 40% and less than or equal to 80% of all pyramid-shaped structures.

[0112] Of course, the proportion of the number of complete pyramid-shaped structures in a unit area on the side of the second passivation layer away from the semiconductor substrate can also be less than or equal to the proportion of the number of complete pyramid-shaped structures in a unit area on the surface of the first region (which can be at least one of the first sub-region surface, the second sub-region surface, and the third sub-region surface included in the first region surface) of all pyramid-shaped structures.

[0113] Furthermore, the embodiments of the present invention do not specifically limit the morphology of the non-complete pyramid-shaped structure on the side surface of the second passivation layer away from the semiconductor substrate and on the surface of the first region, and can be set according to actual needs.

[0114] For example, such as Figures 3 to 5As shown, within the textured area 20 of the first region surface 19, at least one pyramid-shaped structure has a sheet-like protrusion 24 on its side surface. Extending along the side surface of the pyramid-shaped structure, the cross-sectional shape of the sheet-like protrusion 24 is triangular. In this case, in addition to the pyramid-shaped structure, at least one pyramid-shaped structure within the textured area 20 of the first region surface 19 has a sheet-like protrusion 24 on its side surface. This sheet-like protrusion 24 can superimpose its own undulation on the originally undulating pyramid-shaped structure, and its triangular cross-sectional shape, compared to a smooth shape such as a hemispherical shape, has a certain sharp microstructure, which is beneficial for further increasing the roughness of the first region surface 19, improving the light-trapping effect of the first region surface 19, and thus improving the bifaciality of the back contact battery.

[0115] The dimensions of the aforementioned sheet-like protrusions can be determined based on the light-trapping effect requirements of the first region's surface in the actual application scenario, and are not specifically limited here. Furthermore, the sidewalls and apex corners of the sheet-like protrusions can have sharp transitions or smooth transitions.

[0116] For example, the apex angle of at least one pyramidal structure on the surface of the first region can be larger than the apex angle of the pyramidal structure on the side of the second passivation layer facing away from the semiconductor substrate. In this case, compared with the pyramidal structure on the side of the second passivation layer facing away from the semiconductor substrate, the at least one pyramidal structure on the surface of the first region has a relatively large apex angle. At this time, the sharpness of the apex of the at least one pyramidal structure on the surface of the first region is smaller, which is beneficial to make the surface undulation of the isolation region less sharp, thereby reducing the stress of the first passivation layer at the undulation of the isolation region, reducing the risk of damage to the first passivation layer in the isolation region, and further improving the passivation effect of the first passivation layer on the isolation region.

[0117] For example, the one-dimensional dimension of at least one pyramid-like structure on the surface of the first region can be larger than the one-dimensional dimension of the pyramid-like structure on the side of the second passivation layer facing away from the semiconductor substrate. In this case, compared with the pyramid-like structure on the side of the second passivation layer facing away from the semiconductor substrate, the at least one pyramid-like structure on the surface of the first region has a relatively larger one-dimensional dimension, which is beneficial to reducing the number of pyramid-like structures on the surface of the first region, reducing the undulation density of the surface of the first region, and correspondingly, making the undulation density of the surface of the isolation region lower, thereby reducing the stress of the first passivation layer at the undulations of the isolation region, reducing the risk of damage to the first passivation layer in the isolation region, and further improving the passivation effect of the first passivation layer on the isolation region.

[0118] The one-dimensional dimension of the pyramid-like structure on the surface of the first region can be the base side length, base diagonal length, base perimeter, base diameter, side edge length, or height of the pyramid-like structure.

[0119] As for the apex angle and one-dimensional dimensions of the pyramid-shaped structure within the surface of the first region, they can be determined based on the light-trapping effect of the surface of the first region and the passivation effect of the first passivation layer on the isolated region in the actual application scenario, and no specific limitations are made here.

[0120] Furthermore, the apex angles and one-dimensional dimensions of the pyramid-like structures in the first sub-region surface, the second sub-region surface, and the third sub-region surface included in the first region surface can be the same or different. When the apex angles and / or one-dimensional dimensions of the pyramid-like structures in the first sub-region surface, the first sub-region surface, and the third sub-region surface are different, they can be set according to the conductivity type of the first doped semiconductor part and the second doped semiconductor part, as well as actual needs, and no specific limitation is made here.

[0121] For example, when the first doped semiconductor portion is an emitter doped portion, the one-dimensional dimension of the pyramid-like structure on the surface of the first sub-region can be larger than the one-dimensional dimension of the pyramid-like structure on the surface of the second sub-region.

[0122] For example, when the first doped semiconductor portion is an emitter doped portion, the one-dimensional size uniformity of the pyramid-like structure on the surface of the first sub-region is greater than that of the one-dimensional size uniformity of the pyramid-like structure on the surface of the second sub-region.

[0123] For example, the apex angle of the pyramid-like structure on the surface of the first sub-region is smaller than the apex angle of the pyramid-like structure on the surface of the second sub-region.

[0124] When the above technical solution is adopted, on the surface of the first passivation layer away from the semiconductor substrate, the first sub-region surface corresponding to the first sub-surface (near the emitter doped portion) has at least one of the following: one-dimensional dimension, one-dimensional dimension uniformity, and apex angle of the pyramid-like structure, which is larger than the one-dimensional dimension, one-dimensional dimension uniformity, and apex angle of the second sub-region surface. This is beneficial for increasing the undulation and surface roughness of the first sub-region surface, improving the light-trapping effect of the first sub-region surface, and allowing more light to be refracted into the first doped semiconductor portion adjacent to the first sub-region surface, thereby improving the bifaciality of the back contact cell. Simultaneously, the first doped semiconductor portion is the emitter doped portion. Since the emitter doped portion is used to provide electron-hole pair injection and separation, when more light is incident into the emitter doped portion, it is beneficial for exciting more photogenerated carriers, thereby improving the conversion efficiency of the back contact cell. The second sub-region surface corresponding to the second sub-surface has relatively low surface roughness, and correspondingly, the second sub-surface also has low surface roughness, which is beneficial for improving the deposition quality and passivation effect of the first passivation layer on the second sub-surface.

[0125] The one-dimensional dimensions, one-dimensional uniformity, and apex angle of the pyramid-like structure on the surface of the first sub-region and the surface of the second sub-region can be determined according to the requirements of the photogenerated carriers excited by the emitter doping part of the back contact battery in the actual application scenario, and no specific limitation is made here.

[0126] For example, the side length of the base or the diagonal length of the base of the pyramid-shaped structure within the surface of the first sub-region can be greater than or equal to 0.05 μm and less than or equal to 4 μm.

[0127] For example, the side length of the base or the diagonal length of the base of the pyramid-shaped structure within the surface of the second sub-region can be greater than or equal to 0.05 μm and less than or equal to 3 μm.

[0128] For example, the height of the pyramid-like structure on the surface of the first sub-region can be greater than or equal to 0.1 μm and less than or equal to 2.5 μm.

[0129] For example, the height of the pyramid-like structure on the surface of the second sub-region can be greater than or equal to 0.01 μm and less than or equal to 2.5 μm.

[0130] For example, the apex angle of a pyramid-like structure within the surface of the first sub-region can be greater than or equal to 70° and less than or equal to 100°.

[0131] For example, the apex angle of the pyramid-like structure within the surface of the second sub-region can be greater than or equal to 70° and less than or equal to 100°.

[0132] For example, when the second doped semiconductor portion and the semiconductor substrate have the same conductivity type, the one-dimensional dimension of the pyramid-like structure on the surface of the second sub-region can be smaller than the one-dimensional dimension of the pyramid-like structure on the surface of the third sub-region. In this case, the portion of the isolation region located between the first and second regions is mainly used to isolate the first and second doped semiconductor portions with opposite conductivity types, reducing leakage current between them. Therefore, when the surface of the third sub-region corresponding to the third sub-surface has a relatively large one-dimensional dimension and a small apex corner radius on the side of the first passivation layer away from the semiconductor substrate, the surface of the third sub-region has a relatively large surface roughness, and the corresponding third sub-surface also has a large undulating morphology, thereby making the etching degree of the isolation region in the region corresponding to the third sub-surface higher, which is beneficial to further reduce the leakage current risk between the first and second doped semiconductor portions.

[0133] For example, the apex fillet curvature of the pyramid-like structure on the surface of the second sub-region can be greater than that on the surface of the pyramid-like structure of the third sub-region. In this case, the second sub-region surface has a smaller pyramid-like structure and a larger apex fillet curvature, which helps to make the second sub-region surface and the second sub-surface have lower surface roughness, improve the passivation effect of the first passivation layer on the second sub-surface, and reduce the number of defects on the second sub-surface.

[0134] As for the one-dimensional dimensions and apex size of the pyramid-like structure on the surface of the third sub-region, as well as the apex radius curvature of the pyramid-like structures on the surfaces of the second and third sub-regions, these can be determined based on the light-trapping effect of the second and third sub-regions in the actual application scenario, and the passivation effect of the first passivation layer on the second and third sub-surfaces. Specific limitations are made here.

[0135] For example, the base side length or base diagonal length of the pyramid-shaped structure within the surface of the third sub-region can be greater than or equal to 0.05 μm and less than or equal to 6 μm.

[0136] For example, the height of the pyramid-like structure on the surface of the third sub-region can be greater than or equal to 0.1 μm and less than or equal to 4 μm.

[0137] For example, the apex angle of a pyramid-like structure within the surface of the third sub-region can be greater than or equal to 70° and less than or equal to 100°.

[0138] In some cases, the first surface is rectangular. Along the extension direction parallel to the long side of the rectangular shape, the width of the portion of the first and second sub-region surfaces adjacent to one short side of the rectangular shape can be greater than the width of the portion of the first and second sub-region surfaces adjacent to the other short side of the rectangular shape. In this case, when the width of the portion of the first and second sub-region surfaces adjacent to one short side of the rectangular shape is greater than the width of the portion of the first and second sub-region surfaces adjacent to the other short side of the rectangular shape, it indicates that the etching amounts of the first and second doped semiconductor portions at the two short sides are different along the extension direction parallel to the long side of the rectangular shape. This difference in etching amount is because when using equipment such as a chain cleaner to remove the coating on the second surface of the semiconductor substrate, the liquid level fluctuation results in a larger liquid level fluctuation at the leading edge along the travel direction, leading to a larger etching amount at the corresponding short edges of the first and second doped semiconductor portions at the etching leading edge. Therefore, it can be seen that the extension direction of the long side of the quasi-rectangle is consistent with the etching direction, which can reduce the impact of factors such as structural vibration on the etching accuracy during the etching process, improve etching stability and etching accuracy, and thus help improve the yield of back contact batteries.

[0139] Wherein, along the extension direction parallel to the long side of the rectangle, the widths of the portions of the first sub-region surface and the second sub-region surface adjacent to the two short sides of the rectangle can be determined according to the actual manufacturing process, and are not specifically limited here.

[0140] For example, along the extension direction parallel to the long side, the width of the portion of the first sub-region surface and the second sub-region surface adjacent to one short side of the rectangular prism is greater than or equal to 10 μm and less than or equal to 50 μm; and / or, the width of the portion of the first sub-region surface and the second sub-region surface adjacent to another short side of the rectangular prism is greater than or equal to 3 μm and less than or equal to 10 μm. In this case, while ensuring that the coating around the semiconductor substrate can be completely removed by etching, the portion of the first doped semiconductor portion and the second doped semiconductor portion at the edge can be kept at a certain distance from the boundary of the first surface, which helps to reduce the risk of leakage. In addition, it can also prevent the area ratio of the first doped semiconductor portion and the second doped semiconductor portion on the first surface from being affected by the above-mentioned excessive width, which is beneficial to the first doped semiconductor portion and the second doped semiconductor portion having higher carrier collection capability and field passivation effect.

[0141] For example, along the extension direction parallel to the long side, the width of the portion of the first sub-region surface and the second sub-region surface adjacent to a short side in the rectangle can be 10μm, 20μm, 30μm, 40μm or 50μm, etc.

[0142] For example, the widths of the portions of the first and second sub-region surfaces that are adjacent to the other short side of the rectangle can be 3μm, 5μm, 6μm, 7μm, 8μm, 9μm, or 10μm, etc.

[0143] Secondly, embodiments of the present invention provide a photovoltaic module, which includes a back contact battery provided in the first aspect and various implementations thereof.

[0144] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0145] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0146] The embodiments of the present invention have been described above. However, these embodiments are merely for clarity and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A back contact cell, characterized in that, Comprise: a semiconductor substrate comprising opposite first and second faces; the first face comprising first regions, second regions and isolation regions; the first and second regions are alternately and spacedly distributed; the first face has a boundary, and the isolation regions are located between the first regions and the second regions, and between the boundary and the most marginal first regions and the most marginal second regions respectively; a first doped semiconductor portion provided in or on the first regions; a second doped semiconductor portion provided in or on the second regions; the second doped semiconductor portion and the first doped semiconductor portion have opposite conductive types; a first passivation layer covering the first doped semiconductor portion, the second doped semiconductor portion and the isolation regions; a surface of a portion of the first passivation layer away from the semiconductor substrate corresponds to a first region surface of the isolation regions; a second passivation layer covering the second face; wherein the first region surface has a textured area, and a plurality of planar areas surrounded by different pyramidal structures included in the textured area; a surface of the second passivation layer away from the semiconductor substrate is textured, and adjacent pyramidal structures in the second passivation layer away from the semiconductor substrate contact each other, and the textured surface of the second passivation layer away from the semiconductor substrate is different from the textured area of the first region surface.

2. The back contact cell of claim 1, wherein, Among all the pyramidal structures in the surface of the second passivation layer away from the semiconductor substrate and the first region surface, at least the pyramidal structures with four diagonal side ridges are complete pyramidal structures, and the rest are incomplete pyramidal structures; The proportion of the number of complete pyramidal structures in the unit area of the surface of the second passivation layer away from the semiconductor substrate to all the pyramidal structures is greater than the proportion of the number of complete pyramidal structures in the unit area of the first region surface to all the pyramidal structures.

3. The back contact cell of claim 1, wherein, In the textured area of the first region surface, at least one side of the pyramidal structure has a sheet-shaped protruding portion; and the cross-sectional shape of the sheet-shaped protruding portion is triangular along the extension direction of the side of the pyramidal structure.

4. The back contact cell of claim 1, wherein, The top angle of at least one pyramidal structure of the first region surface is greater than the top angle of the pyramidal structure of the surface of the second passivation layer away from the semiconductor substrate; And / or, the one-dimensional size of at least one pyramidal structure of the first region surface is greater than the one-dimensional size of the pyramidal structure of the surface of the second passivation layer away from the semiconductor substrate.

5. The back contact cell of claim 1, wherein, The first doped semiconductor portion is an emitter doped portion; the surface of the isolation region comprises a first sub-surface between the boundary and the most marginal first regions, and a second sub-surface between the boundary and the most marginal second regions; The first passivation layer has a surface facing away from the semiconductor substrate, and the surface has a first sub-region surface corresponding to a portion of the first sub-surface and a second sub-region surface corresponding to a portion of the second sub-surface; the first sub-region surface and the second sub-region surface have a pyramidal structure. The one-dimensional size of the pyramidal structure in the first sub-region surface is greater than the one-dimensional size of the pyramidal structure in the second sub-region surface; and / or the one-dimensional size uniformity of the pyramidal structure in the first sub-region surface is greater than the one-dimensional size uniformity of the pyramidal structure in the second sub-region surface; and / or the vertex angle of the pyramidal structure in the first sub-region surface is smaller than the vertex angle of the pyramidal structure in the second sub-region surface.

6. The back contact cell of claim 1, wherein, The isolation region surface includes a first sub-surface between the boundary and the first region at the most edge, a second sub-surface between the boundary and the second region at the most edge, and a third sub-surface between the first region and the second region; the first passivation layer has a surface facing away from the semiconductor substrate, and the surface has a first sub-region surface corresponding to a portion of the first sub-surface, a second sub-region surface corresponding to a portion of the second sub-surface, and a third sub-region surface corresponding to a portion of the third sub-surface; the second sub-region surface and the third sub-region surface have a pyramidal structure. In the case where the second doped semiconductor part has the same conductivity type as the semiconductor substrate, the second sub-region surface has a pyramidal structure with a one-dimensional size smaller than the one-dimensional size of the pyramidal structure of the third sub-region surface, and / or the second sub-region surface has a pyramidal structure with a vertex angle roundness greater than the vertex angle roundness of the pyramidal structure of the third sub-region surface.

7. The back contact cell of claim 6, wherein, The first face has a rectangular shape; along the extension direction parallel to the long side of the rectangular shape, the width of the portion of the first sub-region surface and the second sub-region surface adjacent to one short side of the rectangular shape is greater than the width of the portion of the first sub-region surface and the second sub-region surface adjacent to the other short side of the rectangular shape.

8. The back contact cell of claim 7, wherein, Along the extension direction parallel to the long side, the width of the portion of the first sub-region surface and the second sub-region surface adjacent to one short side of the rectangular shape is greater than or equal to 10 μm and less than or equal to 50 μm; And / or the width of the portion of the first sub-region surface and the second sub-region surface adjacent to the other short side of the rectangular shape is greater than or equal to 3 μm and less than or equal to 10 μm.

9. The back contact cell of claim 6, wherein, The second doped semiconductor part has a wavy concave-convex alternating structure at the edge line of at least one corner close to the first face.

10. The back contact cell of claim 6, wherein, The first region and the second region each include strip regions and connecting regions; the strip regions included in the first region and the strip regions included in the second region each extend along a first direction and are alternately and spacedly distributed along a second direction; the first direction is different from the second direction; the connecting regions included in the first region and the connecting regions included in the second region each extend along the second direction and are alternately and spacedly distributed along the first direction; the connecting regions included in the first region are connected with at least part of the strip regions included in the first region, and the connecting regions included in the second region are connected with at least part of the strip regions included in the second region; the strip regions included in the first region are disconnected at intersections with the connecting regions included in the second region, and the strip regions included in the second region are disconnected at intersections with the connecting regions included in the first region; The first surface has a chamfer, the first region has an extension at the chamfer, the extension extends along the second direction, and the extension and the strip regions included in the second region are spacedly distributed along the first direction; in the first doped semiconductor part, the edge line of the part close to the chamfer has a first undulating topography, and the edge line of the part close to the contour line continuous with the chamfer has a second undulating topography; Wherein, along the direction from the edge to the center of the first surface, the undulating height of the first undulating topography is greater than the undulating height of the second undulating topography, and / or the width of the convex part in the first undulating topography is less than the width of the convex part in the second undulating topography.

11. The back contact cell of claim 10, wherein, The undulating height of the first undulating topography is greater than or equal to 3 μm and less than or equal to 10 μm; And / or the width of the convex part in the first undulating topography is greater than or equal to 15 μm and less than or equal to 40 μm.

12. A photovoltaic module, characterized by The back contact cell includes the back contact cell as claimed in any one of claims 1-11. The back contact cell includes the back contact cell as claimed in any one of claims 1-11.

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