Display panel and manufacturing method thereof

Abstract

The present application provides a display panel and a method for manufacturing the same. The present application provides a first light-emitting array chip and a driver array chip; the first light-emitting array chip and the driver array chip are bonded to obtain a first bonding structure; in the first bonding structure, a first wiring layer and a driver wiring layer are in contact and are flip-chip connected; the first bonding structure is bonded to a second light-emitting array chip to obtain a second bonding structure; in the second bonding structure, a red pixel unit array is formed on one side of the second light-emitting array chip to obtain a display panel. By disposing the driver array chip between the first light-emitting array chip and the second light-emitting array chip and using interlayer connection technology to enable the driver unit to drive the light-emitting units, the difficulty of the electrical connection process can be reduced, mass transfer technology is no longer required, manufacturing costs can be reduced, the yield of the display panel can be improved, and full-color display can be achieved, resulting in a better display effect of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display panels, and in particular to a display panel and a method for manufacturing the same. Background Art

[0002] With increasing demand for display device performance, micro-light-emitting diode (LED) display technology has gradually developed. However, integrating RGB pixels and achieving full-color display in micro-LEDs presents significant challenges, addressed primarily by monolithic integration and mass transfer technologies.

[0003] As far as monolithic integration technology is concerned, due to the difference in epitaxial materials between red micro-LEDs and blue-green micro-LEDs, it is impossible to directly grow and prepare full-color micro-LED display panels from the same epitaxial material. Therefore, mass transfer technology has become the most direct way to manufacture full-color micro-LED display panels. Mass transfer technology requires the precise transfer of millions of micron-scale RGB three-color LED chips from the growth substrate to the target substrate, but it has problems such as high manufacturing cost, low yield, low production efficiency, difficulty in detection and repair, and poor reliability. Therefore, providing a suitable display panel preparation method has become a technical problem that urgently needs to be solved. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a display panel and a manufacturing method thereof, which can reduce the difficulty of the electrical connection process, realize full-color display, and improve the display effect of the display panel. The specific scheme is as follows:

[0005] In one aspect, the present application provides a method for preparing a display panel, comprising:

[0006] A first light-emitting array chip and a driver array chip are provided; the first light-emitting array chip includes a first light-emitting array layer and a first wiring layer sequentially stacked along a first direction, the first light-emitting array layer including a plurality of first light-emitting units; the driver array chip includes a driving wiring layer and a driving unit layer sequentially stacked along the first direction, the driving unit layer including a plurality of driving units, each of the driving units being used to drive one of the first light-emitting units to emit light;

[0007] Bonding the first light-emitting array chip and the driving array chip to obtain a first bonding structure; in the first bonding structure, the first wiring layer and the driving wiring layer are in contact with each other, and the two are flip-chip connected;

[0008] The first bonding structure is bonded to a second light-emitting array chip to obtain a second bonding structure; the second light-emitting array chip includes a second wiring layer and a second light-emitting array layer stacked in sequence along the first direction, the second light-emitting array layer includes a plurality of second light-emitting units, and one driving unit is used to drive one second light-emitting unit to emit light; in the second bonding structure, the driving array chip is located between the first light-emitting array chip and the second light-emitting array chip, the second wiring layer is in contact with the driving unit layer, and the second wiring layer and the driving wiring layer are connected to each other.

[0009] A red pixel unit array is formed on one side of the second light-emitting array chip in the second bonding structure to obtain a display panel; the red pixel unit array includes a plurality of red pixel units.

[0010] In one possible implementation, a first light-emitting array chip is provided, including:

[0011] Providing a first epitaxial wafer; the first epitaxial wafer comprises a first substrate and a first light-emitting layer stacked in sequence along the first direction, the first light-emitting layer comprising a first buffer layer, an n-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a p-type GaN layer stacked in sequence along the first direction;

[0012] Based on the first array arrangement pattern of the plurality of first light-emitting units, etching the to-be-removed area of ​​the first epitaxial wafer down to the n-type GaN layer to obtain a plurality of light-emitting structures arranged in an array;

[0013] forming a first p-electrode on the p-type GaN layer of the light-emitting structure and forming a first n-electrode on the n-type GaN layer to obtain a plurality of the first light-emitting units arranged in an array;

[0014] depositing a first passivation layer;

[0015] forming a first wiring layer and a second passivation layer in sequence on the first passivation layer;

[0016] A first through hole is formed in the second passivation layer, and a first bonding solder layer is formed in the first through hole; the first bonding solder layer is connected to the first wiring layer.

[0017] In one possible implementation, the first light-emitting array chip includes a first bonding solder layer and a second passivation layer, the first bonding solder layer is located in a first through-hole of the second passivation layer, the first bonding solder layer is connected to the first wiring layer, the surface of the first bonding solder layer is higher than the surface of the second passivation layer, and the first bonding solder layer has a protruding structure; the driving array chip includes a fifth passivation layer covering the driving wiring layer, the fifth passivation layer having a concave hole, and the concave hole is used to expose a portion of the driving wiring layer;

[0018] The first light-emitting array chip and the driving array chip are bonded to obtain a first bonding structure, comprising:

[0019] The protruding structure of the first light-emitting array chip is aligned with the concave hole of the driving array chip, and hot pressing welding is performed under conditions that meet a preset temperature range and a preset pressure range to obtain the first bonding structure.

[0020] In a possible implementation, the driving array chip is a GaN / AlGaN-based HEMT active addressing driving chip, the GaN / AlGaN-based HEMT is an enhancement mode structure, and the driving array chip is a 1T structure;

[0021] Provide driver array chips, including:

[0022] Providing a second epitaxial wafer; the second epitaxial wafer includes a second substrate and a driving layer stacked in sequence along a second direction; the driving layer includes a second buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a p-type GaN cap layer stacked in sequence along the second direction; the second direction is opposite to the first direction;

[0023] Based on the second array arrangement pattern of the plurality of driving units, etching the to-be-removed area of ​​the second epitaxial wafer until reaching the second buffer layer, and then etching until reaching the AlGaN barrier layer, to obtain a plurality of driving structures arranged in an array;

[0024] forming a source electrode and a drain electrode on the AlGaN barrier layer of the driving structure, and forming a gate electrode on the p-type GaN cap layer to obtain a plurality of driving units arranged in an array;

[0025] depositing a third passivation layer;

[0026] Etching the third passivation layer and the driving layer in the to-be-removed area of ​​the second epitaxial wafer to obtain a second through hole;

[0027] forming a fourth passivation layer and a through-hole metal layer in sequence in the second through-hole;

[0028] The driving wiring layer and the fifth passivation layer are formed in sequence.

[0029] In a possible implementation, bonding the first bonding structure to the second light-emitting array chip to obtain a second bonding structure includes:

[0030] Thinning the first bonding structure until the surface of the through-hole metal layer is exposed to obtain a first through-hole metal connection area;

[0031] The second wiring layer of the second light-emitting array chip is bonded to the first through-hole metal connection area to obtain the second bonding structure.

[0032] In a possible implementation, the first light-emitting array chip includes a first bonding solder layer and a second passivation layer, the first bonding solder layer is located in a first through hole of the second passivation layer, the first bonding solder layer is connected to the first wiring layer, and a surface of the first bonding solder layer is flush with a surface of the second passivation layer;

[0033] The driving array chip includes a fifth passivation layer covering the driving wiring layer, and a second bonding solder layer located in a third through hole of the fifth passivation layer; the second bonding solder layer is connected to the driving wiring layer;

[0034] The first light-emitting array chip and the driving array chip are bonded to obtain a first bonding structure, comprising:

[0035] The first bonding solder layer of the first light-emitting array chip is aligned with the second bonding solder layer of the driving array chip, and hot pressing welding is performed under conditions that meet a preset temperature range and a preset pressure range to obtain the first bonding structure.

[0036] In one possible implementation, the drive array chip is a GaN / AlGaN-based HEMT active addressing drive chip, the GaN / AlGaN-based HEMT is an enhancement mode structure, and the drive array chip is a 2T1C structure; the drive unit layer includes a plurality of drive units and a plurality of switch units, and one switch unit is used to control the conduction and cutoff of one drive unit;

[0037] Provide driver array chips, including:

[0038] Providing a second epitaxial wafer; the second epitaxial wafer includes a second substrate and a driving layer stacked in sequence along the second direction, the driving layer includes a second buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a p-type GaN cap layer stacked in sequence along the second direction;

[0039] Based on the third array arrangement pattern of the plurality of the driving units and the plurality of the switching units, etching the area to be removed of the second epitaxial wafer to the AlGaN barrier layer, and then performing ion implantation on the area to be isolated to the second buffer layer, thereby obtaining a plurality of driving structures and a plurality of switching structures arranged in an array;

[0040] forming a source electrode and a drain electrode on the AlGaN barrier layer of the driving structure; forming a source electrode and a drain electrode on the AlGaN barrier layer of the switch structure;

[0041] Depositing a third passivation layer; forming a gate on the third passivation layer at the position of the p-type GaN cap layer of the driving structure to obtain a plurality of the driving units arranged in an array; forming a gate on the third passivation layer at the position of the p-type GaN cap layer of the switch structure to obtain a plurality of the switch units arranged in an array;

[0042] forming the driving wiring layer and the fifth passivation layer on the third passivation layer; and including a capacitor in the driving wiring layer;

[0043] A third through hole is formed in the fifth passivation layer, and a second bonding solder layer is formed in the third through hole; the second bonding solder layer is connected to the driving wiring layer.

[0044] In a possible implementation, bonding the first bonding structure to the second light-emitting array chip to obtain a second bonding structure includes:

[0045] Performing through-hole etching on the first bonding structure to obtain a fourth through-hole;

[0046] forming a fourth passivation layer and a through-hole metal layer in sequence in the fourth through-hole to obtain a second through-hole metal connection area;

[0047] The second wiring layer of the second light-emitting array chip is bonded to the second through-hole metal connection area to obtain the second bonding structure.

[0048] In a possible implementation, the display panel further includes a filter layer, the filter layer includes a plurality of filter units, and the filter units are configured to allow red light, blue light, or green light to pass through;

[0049] The filter layer is located on a side of the red pixel unit array away from the second light emitting array chip.

[0050] In another aspect, an embodiment of the present application further provides a display panel, comprising:

[0051] A first light-emitting array chip, a driver array chip, a second light-emitting array chip, and a red pixel unit array are sequentially stacked along a first direction; the first light-emitting array layer includes a plurality of first light-emitting units; the driver array chip includes a driver wiring layer and a driver unit layer sequentially stacked along the first direction, the driver unit layer includes a plurality of driver units, each driver unit is used to drive one of the first light-emitting units to emit light; the first wiring layer and the driver wiring layer are in contact, and the two are flip-chip connected;

[0052] The second light-emitting array chip includes a second wiring layer and a second light-emitting array layer stacked sequentially along the first direction, the second light-emitting array layer includes a plurality of second light-emitting units, and one driving unit is used to drive one second light-emitting unit to emit light; the second wiring layer is in contact with the second light-emitting array layer, and the second wiring layer and the driving wiring layer are interlayer connected;

[0053] The red pixel unit array includes a plurality of red pixel units.

[0054] The embodiment of the present application provides a display panel and a manufacturing method thereof, providing a first light-emitting array chip and a driving array chip; the first light-emitting array chip includes a first light-emitting array layer and a first wiring layer sequentially stacked along a first direction, the first light-emitting array layer includes a plurality of first light-emitting units; the driving array chip includes a driving wiring layer and a driving unit layer sequentially stacked along the first direction, the driving unit layer includes a plurality of driving units, and one driving unit is used to drive one first light-emitting unit to emit light; the first light-emitting array chip and the driving array chip are bonded to obtain a first bonding structure; in the first bonding structure, the first wiring layer and the driving wiring layer are in contact, and the two are flip-chip connected; the first bonding The structure is bonded to the second light-emitting array chip to obtain a second bonding structure; the second light-emitting array chip includes a second wiring layer and a second light-emitting array layer stacked in sequence along a first direction, the second light-emitting array layer includes a plurality of second light-emitting units, and a driving unit is used to drive a second light-emitting unit to emit light; in the second bonding structure, the driving array chip is located between the first light-emitting array chip and the second light-emitting array chip, the second wiring layer is in contact with the second light-emitting array layer, and the second wiring layer and the driving wiring layer are interlayer connected; a red pixel unit array is formed on one side of the second light-emitting array chip in the second bonding structure to obtain a display panel; the red pixel unit array includes a plurality of red pixel units.

[0055] It can be seen from this that by setting the driving array chip between the first light-emitting array chip and the second light-emitting array chip, and realizing the driving of the first light-emitting unit by the driving unit through the flip-chip connection technology, and realizing the driving of the second light-emitting unit by the driving unit through the interlayer connection technology, since the interlayer connection forms a vertical connection between different chips, the process difficulty of the electrical connection can be reduced, and the mass transfer technology is no longer used, which can reduce the manufacturing cost, improve the yield of the display panel, and realize full-color display, and the display effect of the display panel is better. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0057] Figure 1 A schematic diagram showing a process of a method for manufacturing a display panel provided in an embodiment of the present application is shown;

[0058] Figure 2 A partial structural diagram of a first light-emitting array chip according to an embodiment of the present application is shown;

[0059] Figure 3A A schematic diagram of a partial structure of a manufacturing drive array chip provided in an embodiment of the present application is shown;

[0060] Figure 3B A partial structural diagram of another method for preparing a drive array chip provided in an embodiment of the present application is shown;

[0061] Figure 4 A partial structural diagram of another method for preparing a drive array chip provided in an embodiment of the present application is shown;

[0062] Figure 5 A partial structural diagram of another method for preparing a drive array chip provided in an embodiment of the present application is shown;

[0063] Figure 6 A partial structural diagram of a second light-emitting array chip according to an embodiment of the present application is shown;

[0064] Figure 7 A partial structural diagram of a first bonding structure provided in an embodiment of the present application is shown;

[0065] Figure 8 A schematic diagram of a partial structure of a first through-hole metal connection area prepared according to an embodiment of the present application is shown;

[0066] Figure 9 A partial structural diagram of a second bonding structure provided in an embodiment of the present application is shown;

[0067] Figure 10 A partial structural diagram of another second bonding structure provided in an embodiment of the present application is shown;

[0068] Figure 11 A partial structural diagram of another second bonding structure provided in an embodiment of the present application is shown;

[0069] Figure 12 A schematic diagram of a partial structure of a filter layer prepared according to an embodiment of the present application is shown;

[0070] Figure 13 A schematic diagram of a partial structure of a display panel provided in an embodiment of the present application is shown;

[0071] Figure 14 A partial structural diagram of another method for preparing a first light-emitting array chip provided in an embodiment of the present application is shown;

[0072] Figure 15 A partial structural diagram of another method for preparing a drive array chip provided in an embodiment of the present application is shown;

[0073] Figure 16 A partial structural diagram of another method for preparing a second light-emitting array chip provided in an embodiment of the present application is shown;

[0074] Figure 17 A partial structural diagram of another second bonding structure provided in an embodiment of the present application is shown;

[0075] Figure 18 A schematic diagram of a partial structure of a second through-hole metal connection area prepared according to an embodiment of the present application is shown;

[0076] Figure 19 A partial structural diagram of another method for preparing a second through-hole metal connection area provided in an embodiment of the present application is shown;

[0077] Figure 20 A partial structural diagram of another method for preparing a second through-hole metal connection area provided in an embodiment of the present application is shown;

[0078] Figure 21 A partial structural diagram of another second bonding structure provided in an embodiment of the present application is shown;

[0079] Figure 22 A partial structural diagram of another second bonding structure provided in an embodiment of the present application is shown;

[0080] Figure 23 A schematic diagram of a partial structure of another method for preparing a filter layer provided in an embodiment of the present application is shown;

[0081] Figure 24 A partial structural diagram of a method for preparing a red pixel unit array provided in an embodiment of the present application is shown;

[0082] Figure 25 A partial structural diagram of another display panel provided in an embodiment of the present application is shown;

[0083] Figure 26 A circuit diagram of periodically arranged pixel units provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0084] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0085] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0086] Secondly, this application is described in detail with reference to schematic diagrams. When describing the embodiments of this application, for ease of explanation, cross-sectional views of device structures may be partially enlarged and not to scale. Furthermore, these schematic diagrams are merely illustrative and should not limit the scope of protection of this application. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0087] Next, the reference numerals used in this application are briefly described.

[0088] 101 - first substrate, 102 - first light-emitting layer, 103 - first p-electrode, 104 - first n-electrode, 105 - first passivation layer, 106 - first wiring layer, 107 - first bonding solder layer, 108 - first light-emitting unit;

[0089] 201 - second substrate, 202 - driving layer, 203 - driving structure, 204 - gate, 205 - source and drain, 206 - third passivation layer, 207 - driving wiring layer, 208 - second bonding solder layer, 209 - driving unit, 210 - second through hole, 211 - switch structure, 212 - switch unit;

[0090] 301 - third substrate, 302 - second light-emitting layer, 303 - second p-electrode, 304 - second n-electrode, 305 - seventh passivation layer, 306 - second wiring layer, 307 - third bonding solder layer, 308 - second light-emitting unit;

[0091] 401-red pixel unit;

[0092] 501-fourth passivation layer, 502-through-hole metal layer, 503-fifth passivation layer, 504-eighth passivation layer, 505-first through-hole metal connection area, 506-fourth through hole, 507-second through-hole metal connection area;

[0093] 601 - glass substrate; 602 - blue filter unit, 603 - green filter unit, 604 - red filter unit, 605 - passivation layer of the filter layer.

[0094] For ease of understanding, a display panel and a manufacturing method thereof provided in an embodiment of the present application are described in detail below with reference to the accompanying drawings.

[0095] refer to Figure 1 1 is a flow chart of a method for preparing a display panel provided in an embodiment of the present application. The method may include the following steps.

[0096] S101, providing a first light-emitting array chip and a driving array chip.

[0097] The first light-emitting array chip may include a first light-emitting array layer and a first wiring layer 106 stacked in sequence along a first direction. The first direction may be from bottom to top, that is, the first light-emitting array layer is at the bottom and the first wiring layer 106 is at the top. The first light-emitting array layer may include a plurality of first light-emitting units 108. The first light-emitting unit 108 may be a micro LED or an ordinary LED. The first light-emitting unit 108 is used to emit light, and may emit blue light or green light. For ease of explanation, the following explanation will be based on the example of the first light-emitting unit 108 emitting blue light. In this case, the first light-emitting array chip is also a blue LED array chip. The first wiring layer 106 may include a large number of metal traces to connect the first light-emitting unit 108 to the driving unit 209. The preparation size of the first light-emitting unit 108 may be greater than 0μm and less than 500μm.

[0098] The driver array chip is used to drive the first light-emitting array chip. The driver array chip may include a driver wiring layer 207 and a driver unit layer stacked sequentially along a first direction. Specifically, the driver unit layer may be located above the driver wiring layer 207. The driver unit layer may include multiple driver units 209. Each driver unit 209 is used to drive each first light-emitting unit 108 to emit light. Driver units 209 may be, for example, thin film transistors (TFTs). The driver wiring layer 207 includes a large number of metal traces, which electrically connect the driver units 209 to the first light-emitting units 108.

[0099] S102 , bonding the first light-emitting array chip and the driving array chip to obtain a first bonding structure.

[0100] Specifically, the first wiring layer 106 in the first light-emitting array chip and the driving wiring layer 207 in the driving array chip can be bonded (Bonding) to obtain a first bonding structure. In the first bonding structure, the first wiring layer 106 and the driving wiring layer 207 are in contact with each other, and the two are a flip-chip (FC) structure. In this way, a vertical connection can be achieved between the first light-emitting array chip and the driving array chip, which can reduce the connection distance and improve the current transmission efficiency.

[0101] S103 , performing a bonding process on the first bonding structure and the second light emitting array chip to obtain a second bonding structure.

[0102] The second light-emitting array chip may include a second wiring layer 306 and a second light-emitting array layer stacked in sequence along the first direction, that is, the second light-emitting array layer may be located above the second wiring layer 306. The second light-emitting array layer may include a plurality of second light-emitting units 308. The second light-emitting units 308 may emit blue light or green light. For ease of explanation, the following description will take the second light-emitting unit 308 emitting green light as an example. In this case, the second light-emitting array chip is also a green LED array chip. The second wiring layer 306 may include a large number of metal traces to connect the second light-emitting units 308 to the driving unit 209. The fabrication size of the second light-emitting unit 308 may be greater than 0 μm and less than 500 μm.

[0103] One driving unit 209 is used to drive one second light emitting unit 308 to emit light. That is, in the driving array chip, some driving units 209 are used to drive the first light emitting unit 108 , and some driving units 209 are used to drive the second light emitting unit 308 .

[0104] Specifically, in the process of bonding the first bonding structure to the second light-emitting array chip, the driving array chip and the second light-emitting array chip can be brought into contact to obtain a second bonding structure, that is, in the second bonding structure, the driving array chip is located between the first light-emitting array chip and the second light-emitting array chip, and the second wiring layer 306 in the second light-emitting array chip is in contact with the driving unit layer in the driving array chip.

[0105] The second wiring layer 306 and the drive wiring layer 207 are connected through through-silicon vias (TSVs). This means that the second wiring layer 306 can be electrically connected to the drive wiring layer 207 via through-holes within the drive unit layer. In short, the second bonding structure includes a first light-emitting array layer, a first wiring layer 106, a drive wiring layer 207, a drive unit layer, a second wiring layer 306, and a second light-emitting array layer, stacked in sequence along a first direction.

[0106] In this way, the driving unit layer in the driving array chip can, on the one hand, supply power downward to the first light-emitting unit 108 through the flip-chip connection between the driving wiring layer 207 and the first wiring layer 106, and on the other hand, supply power upward to the second light-emitting unit 308 through the interlayer connection between the driving wiring layer 207 and the second wiring layer 306, thereby realizing the display of blue light and green light.

[0107] S104 , forming a red pixel unit array on one side of the second light-emitting array chip in the second bonding structure to obtain a display panel.

[0108] By providing two light emitting array chips, the display panel can emit blue light and green light. In order to achieve full-color display, a red pixel unit array can be formed on the surface of the second light emitting array chip.

[0109] The red pixel unit array may include a plurality of red pixel units 401 arranged in an array, each configured to emit red light. The red pixel units 401 may be formed of a red color conversion film, capable of emitting red light under the stimulation of blue light. The red color conversion film may be a quantum dot photoresist or a red phosphor. The dimensions of the red pixel units 401 may be consistent with, or slightly larger than, the dimensions of the first light-emitting unit 108, which provides the blue light source for the unit, to ensure a sufficiently large light-emitting area for the red pixel units 401.

[0110] In this way, by arranging the driving array chip between the first light-emitting array chip and the second light-emitting array chip, and realizing the driving of the first light-emitting unit 108 by the driving unit 209 through the flip-chip technology, and realizing the driving of the second light-emitting unit 308 by the driving unit 209 through the interlayer connection technology, since the interlayer connection forms a vertical connection between different chips, the process difficulty of the electrical connection can be reduced, and the mass transfer technology is no longer used, which can reduce the manufacturing cost, improve the yield of the display panel, and realize the full-color display of red, green and blue, and the display effect of the display panel is better.

[0111] In one possible implementation, the display panel may further include a filter layer, which may include multiple filter units. The filter units are configured to allow red light, blue light, or green light to pass through. Specifically, when the first light-emitting unit 108 emits blue light and the second light-emitting unit 308 emits green light, a blue filter unit 602 may be positioned above the first light-emitting unit 108 to allow blue light to pass through and filter out stray light. Similarly, a green filter unit 603 may be positioned above the second light-emitting unit 308 to allow green light to pass through and filter out stray light. A red filter unit 604 may be positioned above the red pixel unit 401 to allow red light to pass through and filter out stray light.

[0112] The filter layer can be located on a side of the red pixel unit array away from the second light emitting array chip. The material of the filter unit includes but is not limited to colored glass, organic light absorbing material, perovskite, etc.

[0113] In a possible implementation, S101 provides a first light emitting array chip, which may specifically include S201-S206. Figure 2 , which is a schematic diagram of a first light-emitting array chip provided in an embodiment of the present application.

[0114] S201, providing a first epitaxial wafer.

[0115] The first epitaxial wafer may include a first substrate 101 and a first light-emitting layer 102 stacked in sequence along a first direction. The first substrate 101 may be a sapphire substrate, which is a transparent substrate, thereby enabling dual-sided light emission of the display panel and improving the display effect. The first substrate 101 may also be a silicon substrate, etc.

[0116] The first light emitting layer 102 may include a first buffer layer, an n-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a p-type GaN layer sequentially stacked along a first direction. Figure 2 The individual film layers are not specifically shown.

[0117] S202 , based on the first array arrangement pattern of the plurality of first light-emitting units 108 , etching the area to be removed of the first epitaxial wafer down to the n-type GaN layer to obtain a plurality of light-emitting structures arranged in an array.

[0118] The first array arrangement pattern can be a preset arrangement pattern of multiple first light-emitting units 108, which can be used to determine the formation position of each first light-emitting unit 108. According to the first array arrangement pattern, the area to be removed of the first epitaxial wafer can be etched. The area to be removed is also the area where the first array arrangement pattern is not located, that is, the position where the first light-emitting unit 108 will not be formed. The area to be removed is etched until the n-type GaN layer is reached, that is, in the area to be removed, the multi-quantum well layer, the electron blocking layer and the p-type GaN layer are etched away to expose the surface of the n-type GaN layer, thereby obtaining a plurality of array-arranged light-emitting structures. Among them, the light-emitting structure is Figure 2 Not specifically marked in Figure 2 There are two light-emitting structures in the device. The etching method can be inductively coupled plasma (ICP) etching, which achieves high precision, high selectivity, high speed and low damage.

[0119] S203 , forming a first p-electrode 103 on the p-type GaN layer of the light-emitting structure, and forming a first n-electrode 104 on the n-type GaN layer, to obtain a plurality of first light-emitting units 108 arranged in an array.

[0120] For each light-emitting structure, a p-electrode can be formed on the surface of the exposed p-type GaN layer, which is referred to as the first p-electrode 103 (i.e., the anode). The material of the first p-electrode 103 can be indium tin oxide. An n-electrode can be formed on the surface of the n-type GaN layer exposed by etching, which is referred to as the first n-electrode 104 (i.e., the cathode). The material of the first n-electrode 104 can be titanium aluminum nickel gold. In this way, multiple first light-emitting units 108 can be obtained. Figure 2 Two first light emitting units 108 are shown.

[0121] S204 , depositing a first passivation layer 105 .

[0122] A first passivation layer 105 is deposited on the first light-emitting layer 102. The first passivation layer 105 can passivate and fill the first light-emitting layer 102, and cover and isolate the first p-electrode 103 and the first n-electrode 104, thereby protecting the first light-emitting unit 108 from damage. The deposition process can be plasma-enhanced chemical vapor deposition (PECVD), which improves the passivation layer's flatness and deposition speed. The material for the first passivation layer 105 can be silicon dioxide, and the materials for subsequent passivation layers can also be silicon dioxide. This will not be further described.

[0123] After the first passivation layer 105 is formed, since the first passivation layer 105 covers the first p-electrode 103 and the first n-electrode 104, the positions of the first p-electrode 103 and the first n-electrode 104 can be etched in the first passivation layer 105 to form a p-electrode hole and an n-electrode hole, so as to realize the lead-out of the two electrodes.

[0124] S205 , sequentially forming a first wiring layer 106 and a second passivation layer on the first passivation layer 105 .

[0125] A first wiring layer 106 is formed on the surface of the first passivation layer 105. The first wiring layer 106 includes a large number of metal traces, some of which are used for electrode extraction. These traces are located above the first p-electrode 103 and the first n-electrode 104. Specifically, metal can be deposited inside and around the through-holes in the first passivation layer 105 to form the metal traces. The first wiring layer 106 is electrically connected to the first p-electrode 103 and the first n-electrode 104 through the p-electrode holes and the n-electrode holes, respectively.

[0126] After forming the first wiring layer 106, a second passivation layer needs to be deposited to form a flat surface. The second passivation layer can isolate adjacent metal traces. In addition, the number of layers of the first wiring layer 106 is not limited here, and can be one layer or multiple layers. The number of layers of the second passivation layer is set accordingly according to the number of layers of the first wiring layer 106. Figure 2 In the embodiment, the first wiring layer 106 includes two layers, and the second passivation layer also includes two layers.

[0127] The first wiring layer 106 mainly includes three circuit connection layouts. The first circuit connection layout is used to realize the circuit connection between the first light-emitting unit 108 and the driving unit 209, that is, the anode of the first light-emitting unit 108 is connected to the source of the driving unit 209, so that the current in the driving unit 209 can flow to the first light-emitting unit 108 through the source to ensure normal light emission.

[0128] The second circuit connection layout is mainly used to realize the circuit connection between the first light-emitting unit 108 and the second light-emitting unit 308, that is, the cathodes of these two types of light-emitting units are connected so that all the light-emitting units can share a negative electrode and realize common grounding. In this way, the circuit connection can be simplified and there is no need for each light-emitting unit to be grounded separately.

[0129] The third circuit connection layout is mainly for the circuit connection layout of the pads required when the driving array chip is connected to the external circuit. The external circuit is used to realize power supply, for example, to realize the connection between the source and drain 205 of the transistor and the column line of the external circuit, and the gate 204 of the transistor and the row line of the external circuit.

[0130] S206 , forming a first through hole in the second passivation layer, and forming a first bonding solder layer 107 in the first through hole.

[0131] Specifically, in order to realize the extraction of the first wiring layer 106, a first through hole can be formed in the second passivation layer. The first through hole is located above the metal trace in the first wiring layer 106. Figure 2 Not specifically marked. A first bonding solder layer 107 is formed within the first through hole and is connected to the first wiring layer 106. The material of the first bonding solder layer 107 can be indium metal or other materials. The first bonding solder layer 107 is used to achieve subsequent bonding with the drive array chip. Materials for the first bonding solder layer 107 and the subsequent third bonding solder layer 307 include, but are not limited to, Au, Sn, In, Ag, Cu, Al, Cu, and metal oxides.

[0132] In this way, by setting the specific positions of the first light-emitting unit 108 and the first wiring layer 106 in the first light-emitting array chip, the first light-emitting array chip can be manufactured more simply, with lower manufacturing costs and better chip quality.

[0133] In one possible implementation, the driver array chip can be a GaN / AlGaN-based high electron mobility transistor (HEMT) active-address driver chip. This type of driver array chip not only controls the light emission of light-emitting units through transistors, but also allows each transistor to drive each light-emitting unit to emit light. This means that each light-emitting unit is independently controlled, enabling the location of the light-emitting units. This allows for more diverse display effects on the display panel, allowing light-emitting units in a specific area to emit light. Furthermore, the transparency of this type of chip allows integration into a display panel to achieve the advantages of thinness, good transparency, and high integration, improving the integration level of full-color active-address driver displays. Furthermore, the chip offers the advantages of a full-color, transparent light-emitting surface. This type of chip has significant advantages and broad application prospects, particularly in the fields of virtual reality (VR) and augmented reality (AR) displays. It can effectively address the technical issues of full-color display chip transfer difficulties and the impact of driver chips on full-color micro-LED displays, significantly improving the display quality of the display panel.

[0134] Specifically, the driver array chip can have a 1T structure or a 2T1C structure. The 1T structure can be understood as one transistor controlling one light-emitting unit. This structure requires fewer transistors, which can simplify the process steps and manufacturing costs. The 2T1C structure can be understood as two transistors and one capacitor controlling one light-emitting unit. This structure can achieve more precise control of the light-emitting unit.

[0135] When the driving array chip is a GaN / AlGaN-based HEMT active addressing driving chip, and the GaN / AlGaN-based HEMT is an enhancement mode structure and a 1T structure, S101 provides the driving array chip, which may specifically include S301-S307.

[0136] S301, providing a second epitaxial wafer.

[0137] The second epitaxial wafer may include a second substrate 201 and a driving layer 202 stacked in sequence along a second direction. The second direction may be opposite to the first direction. For example, if the first direction is from bottom to top, the second direction may be from top to bottom. The second substrate 201 may be a sapphire substrate, and the driving layer 202 may include a second buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a p-type GaN cap layer stacked in sequence along the second direction. Figure 3A As shown, from top to bottom, it includes a stacked second substrate 201 and a driving layer 202. The layers of the driving layer 202 are not specifically shown. The second buffer layer of the driving layer 202 is in contact with the second substrate 201. The p-type GaN cap layer is used to realize the transistor is in the off state under normal conditions. The GaN channel layer can form a two-dimensional electron gas, that is, carriers, under the action of the AlGaN barrier layer. The AlN insertion layer is used to achieve lattice matching between the GaN channel layer and the AlGaN barrier layer.

[0138] S302 , based on the second array arrangement pattern of the plurality of driving units 209 , etching the area to be removed of the second epitaxial wafer until reaching the second buffer layer, and then etching until reaching the AlGaN barrier layer, to obtain a plurality of driving structures 203 arranged in an array.

[0139] The second array arrangement pattern can be understood as a preset arrangement pattern of multiple drive units 209, which can be used to determine the formation position of each drive unit 209. According to the second array arrangement pattern, the area to be removed of the second epitaxial wafer can be etched, wherein the area to be removed may be a position where no drive unit 209 is formed. The area to be removed is etched until the second buffer layer is exposed. Then, it is necessary to etch part of the p-type GaN cap layer until the AlGaN barrier layer is exposed, and retain part of the p-type GaN cap layer, thereby obtaining a plurality of drive structures 203 arranged in an array. The drive structure 203 is Figure 3A Not specifically indicated.

[0140] S303 , forming a source and drain 205 on the AlGaN barrier layer of the driving structure 203 , and forming a gate 204 on the p-type GaN cap layer, to obtain a plurality of driving units 209 arranged in an array.

[0141] Next, for each driving structure 203, a source-drain electrode 205 is formed on the exposed AlGaN barrier layer. The material of the source-drain electrode 205 can be metal, etc. For ease of representation, the source-drain electrode 205 includes a source and a drain. The source and the drain are not distinguished by marks. If the metal on the left is the drain, the metal on the right is the source. The material of the source-drain electrode 205 can be titanium aluminum nickel gold. In addition, it is necessary to form a gate 204 on the surface of the exposed p-type GaN cap layer. The gate 204 can specifically be a nickel gold gate 204, so as to obtain a complete transistor structure (that is, a GaN / AlGaN-based HEMT), that is, to obtain a driving unit 209. A source-drain gate is formed on each driving structure 203, so as to obtain multiple driving units 209. In Figure 3A 3 driving units 209 are shown in FIG. In addition, the size of the driving unit 209 and the subsequent switch unit 212 can be larger than 0 μm and smaller than 50 μm.

[0142] S304 , depositing a third passivation layer 206 .

[0143] A third passivation layer 206 is formed on the plurality of driving units 209. The third passivation layer 206 can cover and isolate the GaN / AlGaN-based HEMT to protect each transistor from damage. The material of the third passivation layer 206 can be silicon dioxide, for example.

[0144] S305 , etching the third passivation layer 206 and the driving layer 202 in the area to be removed of the second epitaxial wafer to obtain a second through hole 210 .

[0145] In order for the GaN / AlGaN-based HEMT to drive and control the second light-emitting unit 308 located on the upper layer thereof, the GaN / AlGaN-based HEMT needs to be electrically connected to the second light-emitting unit 308 .

[0146] The GaN / AlGaN-based HEMT will not be set in the area to be removed of the second epitaxial wafer. Therefore, the third passivation layer 206 and the driving layer 202 located in this area can be etched to obtain the second through hole 210. The etching stop layer can be the second buffer layer or other film layers. The etching process can be an ICP process. Figure 3B As shown, a second through hole 210 is formed in the third passivation layer 206 and the driving layer 202 .

[0147] S306 , forming a fourth passivation layer 501 and a through-hole metal layer 502 in sequence in the second through-hole 210 .

[0148] Specifically, a fourth passivation layer 501 may be deposited in the second through hole 210, and then a metal such as copper may be sputtered in the second through hole 210, and the metal may be electroplated to form a through hole metal layer 502, which completely fills the second through hole 210. Figure 4 As shown, a fourth passivation layer 501 is formed on the sidewalls and bottom wall of the second through hole 210 , and a through hole metal layer 502 completely fills the interior of the second through hole 210 .

[0149] S307 , forming a driving wiring layer 207 and a fifth passivation layer 503 in sequence.

[0150] Next, a drive wiring layer 207 can be formed on the surface of the third passivation layer 206. The drive wiring layer 207 can be, for example, a metal wiring layer. The drive wiring layer 207 mainly includes two circuit connection layouts. The first circuit connection layout is mainly used to achieve electrical connection between the drive unit 209 and the first light-emitting unit 108, that is, connecting the source electrode of the drive unit 209 to the anode of the first light-emitting unit 108. The second circuit connection layout is mainly used to achieve electrical connection between the drive unit 209 and the second light-emitting unit 308, that is, connecting the source electrode of the drive unit 209 to the anode of the second light-emitting unit 308. Specifically, when achieving electrical connection, it is necessary to open holes at the corresponding positions of the source and drain electrodes 205 and the gate electrode 204 so that metal traces can be connected to them. Figure 5 As shown, a driving wiring layer 207 and a fifth passivation layer 503 are formed.

[0151] In this way, the prepared GaN / AlGaN-based HEMT active site selection driver chip has a relatively small number of transistors, a relatively simple overall preparation process, and can achieve vertical electrical connections upward and downward, greatly reducing the process difficulty of electrical connections.

[0152] In one possible implementation, the first light-emitting array chip may include a first bonding solder layer 107 and a second passivation layer, the first bonding solder layer 107 is located in a first through hole of the second passivation layer, the first bonding solder layer 107 is connected to the first wiring layer 106, the surface of the first bonding solder layer 107 is higher than the surface of the second passivation layer, and the first bonding solder layer 107 has a protruding structure.

[0153] Specifically, refer to Figure 2As shown, the first bonding solder layer 107 not only fills the first through-hole but also forms a protruding structure. In practice, before forming the first bonding solder layer 107, a photoresist layer can be formed on the surface of the second passivation layer. The photoresist layer is then exposed and developed to form a patterned photoresist layer. The pattern of the photoresist layer is consistent with the pattern of the second passivation layer having the first through-hole. Next, a layer of solder layer material is deposited, and the photoresist layer is removed, thereby forming the first bonding solder layer 107 having the protruding structure.

[0154] The drive array chip may include a fifth passivation layer 503 covering the drive wiring layer 207. The fifth passivation layer 503 has a concave hole, which is used to expose part of the drive wiring layer 207. Specifically, in order to lead out the drive wiring layer 207, a concave hole can be formed at the location where the metal wiring of the drive wiring layer 207 is located, that is, the fifth passivation layer 503 is etched to form the concave hole. The etching process can be reactive ion etching (RIE) or the like. In this way, the drive wiring layer 207 can be partially exposed at the bottom of the concave hole. The drive array chip with a concave hole is not specifically shown. The drive array chip with a concave hole is different from the drive array chip with a concave hole. Figure 5 The main difference is that a concave hole is formed at a corresponding position in the fifth passivation layer 503 to expose the driving wiring layer 207.

[0155] S102 performs a bonding process on the first light-emitting array chip and the driving array chip to obtain a first bonding structure, which may specifically include S1021.

[0156] S1021 , aligning the protruding structure of the first light-emitting array chip with the concave hole of the driving array chip, and performing hot pressing welding under conditions that meet a preset temperature range and a preset pressure range to obtain a first bonding structure.

[0157] Specifically, when bonding the first light-emitting array chip and the driving array chip, the protruding structure of the first bonding solder layer 107 can be aligned with the concave hole in the fifth passivation layer 503 , so that the first bonding solder layer 107 can be connected to the first driving wiring layer 207 .

[0158] Specifically, hot pressing welding can be performed under conditions that meet a preset temperature range and a preset pressure range to obtain a first bonding structure. The preset temperature range is a suitable temperature range for bonding, which can be higher than the bonding temperature of the bonding material layer, for example, 250°C to 400°C. The preset pressure range is a suitable pressure range for bonding, for example, 10 kPa to 100 MPa. The hot pressing welding time can be 5 minutes to 60 minutes, so that the first light-emitting array chip and the driver array chip can be completely bonded to obtain the first bonding structure.

[0159] refer to Figure 7 FIG. 1 shows a first bonding structure obtained by bonding the first light-emitting array chip and the driver array chip. A small gap may exist between the two chips, and the gap may be filled with underfill to improve the firmness of the first bonding structure. Of course, the two chips should be as close as possible.

[0160] In this way, the first bonding structure is obtained by this concave-convex bonding method, and during the bonding process, rapid alignment can be achieved according to the position of the convex structure and the position of the concave hole, which greatly improves the bonding efficiency and ensures the stability of the bonding.

[0161] Next, the formation and bonding process of the second light-emitting array chip are described in detail.

[0162] The formation process of the second light-emitting array chip is similar to that of the first light-emitting array chip. The main difference between the two lies in the composition of the multi-quantum well layer. The multi-quantum well layer includes alternating layers of gallium nitride (GaN) and indium gallium nitride (InGaN). The main difference between the first and second light-emitting array chips lies in the different indium content in the InGaN.

[0163] refer to Figure 6 As shown, a schematic diagram of a second light-emitting array chip is shown. During the formation process, a second epitaxial wafer can be provided. The second epitaxial wafer may include a third substrate 301 and a second light-emitting layer 302 stacked in sequence along the second direction. The second light-emitting layer 302 includes a third buffer layer, an n-type GaN layer, a multi-quantum well layer, an electron blocking layer and a p-type GaN layer stacked in sequence along the second direction. Based on the third array arrangement pattern of the plurality of second light-emitting units 308, the area to be removed of the second epitaxial wafer is etched until the n-type GaN layer, so as to obtain a plurality of light-emitting structures arranged in an array; a second p-electrode 303 is formed on the p-type GaN layer of the light-emitting structure, and a second n-electrode 304 is formed on the n-type GaN layer, so as to obtain a plurality of second light-emitting units 308 arranged in an array; a seventh passivation layer 305 is deposited; a second wiring layer 306 and an eighth passivation layer 504 are sequentially formed on the seventh passivation layer 305; a fifth through hole is formed in the eighth passivation layer 504, and a third bonding solder layer 307 is formed in the fifth through hole; the third bonding solder layer 307 is connected to the second wiring layer 306.

[0164] The second wiring layer 306 primarily includes two circuit connection layouts. The first circuit connection layout primarily connects the second light-emitting unit 308 to the driver unit 209. The other circuit connection layout primarily connects the second light-emitting unit 308 to the first light-emitting unit 108. Specifically, the second light-emitting unit 308 and the first light-emitting unit 108 are connected to each other for common grounding. In actual manufacturing, metal connecting wires can be formed in the driver array chip to connect the cathodes of the two types of light-emitting units.

[0165] Although Figure 6 The various film layers are located below the third substrate 301. However, in the actual process, the various film layers are formed in sequence above the third substrate 301. Figure 6 The prepared second light emitting array chip is turned upside down to illustrate the subsequent bonding process. Figure 6 The structure shown is bonded directly to the first bonding structure.

[0166] In a possible implementation, S103 performs a bonding process on the first bonding structure and the second light-emitting array chip to obtain a second bonding structure, which may specifically include S1031 - S1032 .

[0167] S1031 , thinning the first bonding structure until the surface of the through-hole metal layer 502 is exposed, thereby obtaining a first through-hole metal connection area 505 .

[0168] Specifically, in the first bonding structure, the second substrate 201 of the driving array chip can be removed by wire cutting or laser cutting, and the driving array chip is thinned by a thinning and polishing process until the surface of the through-hole metal layer 502 is exposed, thereby obtaining the first through-hole metal connection area 505. Figure 8 As shown, a first through-hole metal connection area 505 is obtained through thinning. The first through-hole metal connection area 505 is also the area where the through-hole metal layer 502 is located. Since the location of the first through-hole metal connection area 505 does not form a light-emitting unit, that is, the connection area is located around the light-emitting unit, thereby avoiding blocking the front light. The presence of the connection area can also cut off the propagation of light in the gallium nitride layer, preventing the adjacent light-emitting units from emitting weakly when one light-emitting unit is lit, thereby preventing optical crosstalk.

[0169] S1032 , bonding the second wiring layer 306 of the second light-emitting array chip to the first through-hole metal connection area 505 to obtain a second bonding structure.

[0170] refer to Figure 9As shown, when integrating the second light emitting array chip, the second wiring layer 306 and the first through-hole metal connection area 505 can be connected through the third bonding solder layer 307 to obtain a second bonding structure.

[0171] During the bonding process, the preset temperature range can be 250°C ~ 400°C, the preset pressure range can be 10kPa ~ 100 MPa, and the hot pressing welding time can be 5 min ~ 60 min, so that the second light-emitting array chip and the driving array chip are completely bonded.

[0172] Next, the bonding of the red pixel unit array is described, which mainly includes the processes of peeling off the third substrate 301 of the second light emitting array chip, preparing the red pixel unit array, preparing the filter layer, and integrating the filter layer.

[0173] refer to Figure 10 FIG. 3 is a schematic diagram showing a method of peeling off the third substrate 301 of the second light emitting array chip. Specifically, the third substrate 301 of the second light emitting array chip after bonding can be removed by laser lift-off technology to obtain Figure 10 In the structure shown, the second light-emitting array layer is exposed, thereby facilitating light emission from the top surface of the three-dimensional stacked full-color active site selection driven display panel.

[0174] Next, prepare the red pixel unit array, refer to Figure 11 As shown. After peeling off the third substrate 301, the third buffer layer in the second light-emitting array layer is exposed. A photoresist can be coated on the third buffer layer. Based on the specific positions of the first light-emitting units 108 that provide light sources for the red pixel units 401, the photoresist is patterned and exposed and developed to form a patterned photoresist array. For example, a red phosphor can be used as a red color conversion film. The red phosphor can be spin-coated, and after peeling off the photoresist, patterned red pixel units 401 are formed, thereby obtaining a red pixel unit array.

[0175] Then prepare the filter layer. Take the filter layer located above the red pixel unit array as an example. In this case, the red pixel unit array can be formed separately. Figure 12 As shown, a blue filter unit 602, a green filter unit 603, and a red filter unit 604 can be prepared on a glass substrate 601, which are respectively located above the red, green, and blue micro LED units; a passivation layer 605 of the filter layer is deposited to obtain an array-distributed filter layer.

[0176] Fix the filter layer on the red pixel unit array, refer to Figure 13As shown, a display panel is obtained in which the first light-emitting array chip, the driving array chip, the second light-emitting array chip, the red pixel unit array and the filter layer are stacked in sequence. The light-emitting surface is the upper surface of the display panel. Since the filter layer is closest to the light-emitting side, the emitted light can reduce stray light to the greatest extent, the luminous color is purer, and the displayed color is more realistic.

[0177] Next, another embodiment of forming a display panel is described in detail, referring to Figure 14-Figure 25 shown.

[0178] refer to Figure 14 FIG. 1 is another schematic diagram of preparing a first light emitting array chip, and FIG. Figure 2 The main difference is that the first bonding solder layer 107 does not have a protruding structure, that is, the surface of the first bonding solder layer 107 is flush with the surface of the second passivation layer.

[0179] In the process of forming the driver array chip, in one possible implementation, the driver array chip is a GaN / AlGaN-based HEMT active addressing driver chip, the GaN / AlGaN-based HEMT is an enhancement type structure, and the driver array chip can be a 2T1C structure; the driver unit layer can include multiple driver units 209 and multiple switch units 212, and each switch unit 212 can be used to control the conduction and cutoff of each driver unit 209. The driver unit 209 and the switch unit 212 can be a metal-insulator-semiconductor (MIS) structure, which can reduce the leakage current of the gate 204 and improve the performance.

[0180] That is, for each light emitting unit (the first light emitting unit 108 or the second light emitting unit 308 ), light emission can be controlled by a driving unit 209 , and the driving unit 209 is controlled to be turned on and off by the switch unit 212 .

[0181] Then, S101 provides a driving array chip, which may specifically include S401-S406.

[0182] S401, providing a second epitaxial wafer.

[0183] The second epitaxial wafer may include a second substrate 201 and a driving layer 202 sequentially stacked along the second direction, and the driving layer 202 includes a second buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a p-type GaN cap layer sequentially stacked along the second direction. Figure 15 shown.

[0184] S402, based on the third array arrangement pattern of multiple driving units 209 and multiple switching units 212, the area to be removed of the second epitaxial wafer is etched to the AlGaN barrier layer, and then ion implantation is performed on the area to be isolated until the second buffer layer, thereby obtaining multiple driving structures 203 and multiple switching structures 211 arranged in an array.

[0185] The third array arrangement pattern can be understood as a preset arrangement pattern of the drive unit 209 and the switch unit 212, which can reflect the position of each drive unit 209 and the position of each switch unit 212. The area to be removed of the second epitaxial wafer is the area outside the gate of the drive unit 209 and the switch unit 212. This area can be etched until the AlGaN barrier layer is exposed. The area to be isolated of the second epitaxial wafer is the area where the drive unit 209 and the switch unit 212 are not set. Fluorine ions can be implanted in this area until the second buffer layer is formed, thereby obtaining multiple drive structures 203 and multiple switch structures 211 arranged in an array.

[0186] S403 , forming a source and a drain on the AlGaN barrier layer of the driving structure 203 ; and forming a source and a drain on the AlGaN barrier layer of the switch structure 211 .

[0187] Specifically, for each driver structure 203, a source / drain 205 can be formed on the exposed AlGaN barrier layer. The source / drain 205 can be made of metal, for example. For ease of illustration, the source / drain 205 is represented by the same reference numerals in the figure. If the metal on the left is the drain, the metal on the right is the source. The source / drain 205 can be made of titanium aluminum nickel gold. For each switch structure 211, a source / drain 205 can be formed on the exposed AlGaN barrier layer.

[0188] In an actual process, the source and drain electrodes 205 of the switch unit 212 , and the source and drain electrodes 205 and the gate electrode 204 of the driving unit 209 are in the same film layer and can be formed simultaneously.

[0189] S404, depositing a third passivation layer 206, forming a gate 204 on the third passivation layer 206 at the position of the p-type GaN cap layer of the driving structure 203, to obtain a plurality of the driving units 209 arranged in an array; forming a gate 204 on the third passivation layer 206 at the position of the p-type GaN cap layer of the switch structure 211, to obtain a plurality of the switch units 212 arranged in an array.

[0190] Specifically, a third passivation layer 206 is formed on the multiple driving structures 203 and the multiple switching structures 211. The third passivation layer 206 can cover and isolate the source and drain electrodes 205 of the driving unit 209 and the switching structure 211, and can also serve as an insulating layer for the MIS structure enhancement mode GaN / AlGaN-based HEMT. The material of the third passivation layer 206 can be, for example, aluminum oxide. For each driving structure 203, a gate 204 can be formed on the p-type GaN cap layer covered by the third passivation layer 206. The gate 204 can specifically be a nickel-gold gate 204, thereby obtaining a complete transistor structure that can be used for driving, that is, a driving unit 209. For each switching structure 211, a gate 204 can be formed on the p-type GaN cap layer covered by the third passivation layer 206, thereby obtaining a switching unit 212.

[0191] In actual process, the gate 204 of the switch unit 212 and the gate 204 of the drive unit 209 are in the same film layer and can be formed at the same time. Figure 15 , three groups of transistor structures are shown. Each group of transistor structures includes a switch unit 212 and a drive unit 209. The transistor on the left is the switch unit 212, and the transistor on the right is the drive unit 209. The source of the switch unit 212 is electrically connected to the gate 204 of the drive unit 209, thereby controlling the gate 204 of the drive unit 209. In addition, both the switch unit 212 and the drive unit 209 are enhancement-mode GaN / AlGaN-based HEMTs with a MIS structure.

[0192] S405 , forming a driving wiring layer 207 and a fifth passivation layer 503 on the third passivation layer 206 .

[0193] A driving wiring layer 207 can be formed on the third passivation layer 206. The driving wiring layer 207 is used to lead out the source and drain electrodes 205 and the gate electrode 204. Then, a fifth passivation layer 503 is deposited. The number of layers of the fifth passivation layer 503 and the driving wiring layer 207 is not limited. Figure 15 There are two layers of fifth passivation layers 503 and two layers of driving wiring layers 207.

[0194] The driving wiring layer 207 includes capacitors, that is, in the process of forming the driving wiring layer 207, some metal traces can form capacitors. Figure 15 A flat plate capacitor is shown in FIG. The capacitor can also be a deep trench capacitor.

[0195] S406 , forming a third through hole in the fifth passivation layer 503 , and forming a third bonding solder layer 307 in the third through hole; the third bonding solder layer 307 is connected to the driving wiring layer 207 .

[0196] A third through hole (not specifically marked in the figure) can be formed in the fifth passivation layer 503, and the third through hole is used to expose part of the metal routing. A third bonding solder layer 307 is formed in the third through hole, and the third bonding solder layer 307 can be electrically connected to the driving wiring layer 207.

[0197] In this way, the prepared driving array chip has a switching unit 212 and a driving unit 209. The switching unit 212 can control the magnitude of the current of the gate 204 of the driving unit 209, thereby being able to more finely regulate the source-drain current of the driving unit 209, thereby being able to finely regulate the luminous brightness of the light-emitting unit, and making the display effect more controllable.

[0198] In one possible implementation, the first light-emitting array chip may include a first bonding solder layer 107 and a second passivation layer. The first bonding solder layer 107 is located within a first through-hole in the second passivation layer. The first bonding solder layer 107 is connected to the first wiring layer 106. The surface of the first bonding solder layer 107 is flush with the surface of the second passivation layer. The driving array chip may include a fifth passivation layer 503 covering the driving wiring layer 207, and a third bonding solder layer 307 located within a third through-hole in the fifth passivation layer 503. The third bonding solder layer 307 is connected to the driving wiring layer 207.

[0199] Then, S102 bonds the first light-emitting array chip and the driving array chip to obtain a first bonding structure, which can be specifically as follows: S1022 aligns the first bonding solder layer 107 of the first light-emitting array chip with the third bonding solder layer 307 of the driving array chip, and performs hot pressing welding under conditions that meet a preset temperature range and a preset pressure range to obtain a first bonding structure.

[0200] Specifically, refer to Figure 17 As shown, during bonding, the first bonding solder layer 107 can be aligned with the third bonding solder layer 307 of the drive array chip. During this bonding process, since the bonding is between two planes, not only the bonding solder layers can be bonded to each other, but also the passivation layers can be bonded to each other. This results in a better bonding effect for the first bonding structure, and the two can be more tightly combined to avoid gaps in the middle, resulting in higher bonding strength. The preset temperature range and the preset pressure range can refer to the above description.

[0201] Next, the process of integrating the second light-emitting array chip is described in detail.

[0202] First, the preparation process of the second light emitting array chip is described. Figure 16 FIG. 1 is a schematic diagram of the second light-emitting array chip prepared. The preparation process thereof refers to the preparation process of the second light-emitting array chip described above. Figure 16 and Figure 6The main difference is that the third bonding solder layer 307 has no protruding structure, thereby achieving plane-to-plane bonding.

[0203] In a possible implementation, S103 performs a bonding process on the first bonding structure and the second light-emitting array chip to obtain a second bonding structure, which may specifically include S1033 to S1035.

[0204] S1033 , performing through-hole etching on the first bonding structure to obtain a fourth through-hole 506 .

[0205] Specifically, the second substrate 201 in the first bonding structure can be removed, and the driving unit layer can be thinned. The substrate can be removed by wire cutting or laser cutting, and the driving array chip can be thinned to 2um through a thinning and polishing process. Figure 18 As shown, it is the first bonding structure after thinning.

[0206] Next, refer to Figure 19 As shown, the first bonding structure may be subjected to through-hole etching, and the etching method may be an ICP process, until the driving wiring layer 207 is exposed, thereby obtaining a fourth through-hole 506 .

[0207] S1034 , sequentially forming a fourth passivation layer 501 and a through-hole metal layer 502 in the fourth through-hole 506 to obtain a second through-hole metal connection region 507 .

[0208] Then, a fourth passivation layer 501 is formed on the surface of the first bonding structure. The fourth passivation layer 501 covers the bottom wall and side walls of the fourth through hole 506. The fourth passivation layer 501 on the bottom wall is removed. Figure 19 Then, metal is formed in the fourth through hole 506 to obtain a through hole metal layer 502. The through hole metal layer 502 is completely filled in the fourth through hole 506. Thus, a second through hole metal connection area 507 can be obtained. Figure 20 shown.

[0209] S1035 , bonding the second wiring layer 306 of the second light-emitting array chip to the second through-hole metal connection area 507 to obtain a second bonding structure.

[0210] refer to Figure 21 As shown, the second wiring layer 306 of the second light-emitting array chip is aligned with the second through-hole metal connection area 507, and bonding is performed under certain temperature and pressure conditions to obtain a second bonding structure.

[0211] Next, the formation of the filter layer and the red pixel unit array will be described in detail.

[0212] refer to Figure 22As shown, the third substrate 301 in the second bonding structure can be removed, which is beneficial for the top surface light output of the three-dimensional stacked full-color active site selection drive display panel. Figure 23 As shown, prepare the filter layer, the specific process is the same as Figure 12 The process shown is the same.

[0213] refer to Figure 24 As shown, a red pixel unit array is formed on the filter layer, with red pixel unit 401 being a quantum dot photoresist as an example. Red quantum dot photoresist can be coated on the filter layer, and patterned exposure and development are performed on the red quantum dot photoresist according to the position corresponding to the first light-emitting unit 108 providing light source for the red pixel unit 401. This forms a patterned red quantum dot photoresist array, resulting in a red color conversion film, i.e., a red pixel unit array, and then a passivation layer is formed.

[0214] refer to Figure 25 As shown, the structure integrating the filter layer and the red pixel unit array is fixed to the second bonding structure to obtain a display panel.

[0215] In this way, by forming a red pixel unit array on the filter layer, since the filter layer is relatively thin and the distance between the filter layer and the red pixel unit 401 is sufficiently close, the position of the filter layer can be aligned with the position of the red pixel unit 401 with higher precision, which enables the filter layer to better play a filtering role, making the red light redder and the display effect of the display panel more delicate.

[0216] refer to Figure 26 As shown, a circuit schematic diagram of a periodically arranged pixel unit provided in an embodiment of the present application shows 6 rows and 6 columns of pixel units, where the pixel units are R pixels, B pixels and G pixels. For a single pixel unit, it includes a switching unit (transistor on the left) and a driving unit (transistor on the right). The drain of the switching unit is connected to the column line, the gate of the switching unit is connected to the row line, the capacitor connects the drain of the driving unit to the gate 204, the source of the driving unit 209 is connected to the light-emitting diode, and the negative electrode of the light-emitting diode is grounded.

[0217] The present application also provides a display panel, which may include:

[0218] A first light-emitting array chip, a driver array chip, a second light-emitting array chip, and a red pixel unit array are sequentially stacked along a first direction; the first light-emitting array layer includes a plurality of first light-emitting units; the driver array chip includes a driver wiring layer and a driver unit layer sequentially stacked along the first direction, the driver unit layer includes a plurality of driver units, each driver unit is used to drive one of the first light-emitting units to emit light; the first wiring layer and the driver wiring layer are in contact, and the two are flip-chip connected;

[0219] The second light-emitting array chip includes a second wiring layer and a second light-emitting array layer stacked sequentially along the first direction, the second light-emitting array layer includes a plurality of second light-emitting units, and one driving unit is used to drive one second light-emitting unit to emit light; the second wiring layer is in contact with the second light-emitting array layer, and the second wiring layer and the driving wiring layer are interlayer connected;

[0220] The red pixel unit array includes a plurality of red pixel units.

[0221] The various embodiments in this specification are described in a progressive manner. Similar portions between the various embodiments can be referenced to each other. Each embodiment focuses on the differences from the other embodiments. In particular, the display panel embodiment is described briefly because it is generally similar to the fabrication method embodiment. For relevant details, refer to the description of the fabrication method embodiment.

[0222] The above is only a preferred embodiment of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above-disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of protection of the technical solution of the present application.

Claims

1. A method for preparing a display panel, characterized in that: include: Providing a first light-emitting array chip and a driving array chip; The first light-emitting array chip includes a first light-emitting array layer and a first wiring layer sequentially stacked along a first direction, the first light-emitting array layer including a plurality of first light-emitting units; the driving array chip includes a driving wiring layer and a driving unit layer sequentially stacked along the first direction, the driving unit layer including a plurality of driving units, one of the driving units being used to drive one of the first light-emitting units to emit light; the driving array chip is a GaN / AlGaN-based HEMT active addressing driver chip, the GaN / AlGaN-based HEMT is an enhancement-mode structure, the driving unit layer includes a second buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a p-type GaN cap layer sequentially stacked along a second direction, the second direction being opposite to the first direction; Bonding the first light-emitting array chip and the driving array chip to obtain a first bonding structure; in the first bonding structure, the first wiring layer and the driving wiring layer are electrically connected, and the two are flip-chip connected; Bonding the first bonding structure to a second light-emitting array chip to obtain a second bonding structure; the second light-emitting array chip includes a second wiring layer and a second light-emitting array layer stacked in sequence along the first direction, the second light-emitting array layer includes a plurality of second light-emitting units, and one of the driving units is used to drive one of the second light-emitting units to emit light; In the second bonding structure, the driving array chip is located between the first light-emitting array chip and the second light-emitting array chip, the second wiring layer is electrically connected to the driving unit layer, and the second wiring layer and the driving wiring layer are interlayer connected; forming a red pixel unit array on one side of the second light-emitting array chip in the second bonding structure to obtain a display panel; the red pixel unit array includes a plurality of red pixel units; The first light-emitting array chip includes a first bonding solder layer and a second passivation layer, the first bonding solder layer is located in a first through-hole of the second passivation layer, the first bonding solder layer is connected to the first wiring layer, the surface of the first bonding solder layer is higher than the surface of the second passivation layer, and the first bonding solder layer has a convex structure; the driving array chip includes a fifth passivation layer covering the driving wiring layer, the fifth passivation layer has a concave hole, and the concave hole is used to expose a portion of the driving wiring layer; The first light-emitting array chip and the driving array chip are bonded to obtain a first bonding structure, comprising: Aligning the protruding structure of the first light-emitting array chip with the concave hole of the driving array chip, and performing hot pressing welding under conditions that meet a preset temperature range and a preset pressure range to obtain the first bonding structure; Alternatively, the first light-emitting array chip includes a first bonding solder layer and a second passivation layer, the first bonding solder layer is located in a first through hole of the second passivation layer, the first bonding solder layer is connected to the first wiring layer, and a surface of the first bonding solder layer is flush with a surface of the second passivation layer; The driving array chip includes a fifth passivation layer covering the driving wiring layer, and a second bonding solder layer located in a third through hole of the fifth passivation layer; the second bonding solder layer is connected to the driving wiring layer; The first light-emitting array chip and the driving array chip are bonded to obtain a first bonding structure, comprising: The first bonding solder layer of the first light-emitting array chip is aligned with the second bonding solder layer of the driving array chip, and hot pressing welding is performed under conditions that meet a preset temperature range and a preset pressure range to obtain the first bonding structure.

2. The method according to claim 1, characterized in that A first light-emitting array chip is provided, comprising: Providing a first epitaxial wafer; the first epitaxial wafer comprises a first substrate and a first light-emitting layer stacked in sequence along the first direction, the first light-emitting layer comprising a first buffer layer, an n-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a p-type GaN layer stacked in sequence along the first direction; Based on the first array arrangement pattern of the plurality of first light-emitting units, etching the to-be-removed area of ​​the first epitaxial wafer down to the n-type GaN layer to obtain a plurality of light-emitting structures arranged in an array; forming a first p-electrode on the p-type GaN layer of the light-emitting structure and forming a first n-electrode on the n-type GaN layer to obtain a plurality of the first light-emitting units arranged in an array; depositing a first passivation layer; forming a first wiring layer and a second passivation layer in sequence on the first passivation layer; A first through hole is formed in the second passivation layer, and a first bonding solder layer is formed in the first through hole; the first bonding solder layer is connected to the first wiring layer.

3. The method according to claim 1, characterized in that The drive array chip is a GaN / AlGaN-based HEMT active addressing drive chip, the GaN / AlGaN-based HEMT is an enhancement mode structure, and the drive array chip is an 1T structure; Provides driver array chips, including: Providing a second epitaxial wafer; the second epitaxial wafer includes a second substrate and a driving layer stacked in sequence along a second direction; the driving layer includes a second buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a p-type GaN cap layer stacked in sequence along the second direction; the second direction is opposite to the first direction; Based on the second array arrangement pattern of the plurality of driving units, etching the to-be-removed area of ​​the second epitaxial wafer until reaching the second buffer layer, and then etching until reaching the AlGaN barrier layer, to obtain a plurality of driving structures arranged in an array; forming a source electrode and a drain electrode on the AlGaN barrier layer of the driving structure, and forming a gate electrode on the p-type GaN cap layer to obtain a plurality of driving units arranged in an array; depositing a third passivation layer; Etching the third passivation layer and the driving layer in the to-be-removed area of ​​the second epitaxial wafer to obtain a second through hole; forming a fourth passivation layer and a through-hole metal layer in sequence in the second through-hole; The driving wiring layer and the fifth passivation layer are formed in sequence.

4. The method according to claim 3, characterized in that Bonding the first bonding structure to the second light-emitting array chip to obtain a second bonding structure, comprising: Thinning the first bonding structure until the surface of the through-hole metal layer is exposed to obtain a first through-hole metal connection area; The second wiring layer of the second light-emitting array chip is bonded to the first through-hole metal connection area to obtain the second bonding structure.

5. The method according to claim 1, wherein The driving array chip is a GaN / AlGaN-based HEMT active addressing driving chip, the GaN / AlGaN-based HEMT is an enhancement mode structure, and the driving array chip is a 2T1C structure; the driving unit layer includes a plurality of driving units and a plurality of switching units, and one switching unit is used to control the conduction and cutoff of one driving unit; Provides driver array chips, including: Providing a second epitaxial wafer; the second epitaxial wafer includes a second substrate and a driving layer stacked in sequence along the second direction, the driving layer includes a second buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a p-type GaN cap layer stacked in sequence along the second direction; Based on the third array arrangement pattern of the plurality of the driving units and the plurality of the switching units, etching the area to be removed of the second epitaxial wafer to the AlGaN barrier layer, and then performing ion implantation on the area to be isolated up to the second buffer layer, thereby obtaining a plurality of driving structures and a plurality of switching structures arranged in an array; forming a source electrode and a drain electrode on the AlGaN barrier layer of the driving structure; forming a source electrode and a drain electrode on the AlGaN barrier layer of the switch structure; Depositing a third passivation layer; forming a gate on the third passivation layer at the position of the p-type GaN cap layer of the driving structure to obtain a plurality of the driving units arranged in an array; forming a gate on the third passivation layer at the position of the p-type GaN cap layer of the switch structure to obtain a plurality of the switch units arranged in an array; forming the driving wiring layer and the fifth passivation layer on the third passivation layer; and including a capacitor in the driving wiring layer; A third through hole is formed in the fifth passivation layer, and a second bonding solder layer is formed in the third through hole; the second bonding solder layer is connected to the driving wiring layer.

6. The method according to claim 5, characterized in that Bonding the first bonding structure to the second light-emitting array chip to obtain a second bonding structure, comprising: Performing through-hole etching on the first bonding structure to obtain a fourth through-hole; forming a fourth passivation layer and a through-hole metal layer in sequence in the fourth through-hole to obtain a second through-hole metal connection area; The second wiring layer of the second light-emitting array chip is bonded to the second through-hole metal connection area to obtain the second bonding structure.

7. The method according to claim 1, characterized in that The display panel further includes a filter layer, the filter layer including a plurality of filter units, the filter units being configured to allow red light, blue light or green light to pass through; The filter layer is located on a side of the red pixel unit array away from the second light emitting array chip.

8. A display panel, characterized in that: include: A first light emitting array chip, a driving array chip, a second light emitting array chip, and a red pixel unit array are sequentially stacked along a first direction; The first light-emitting array chip includes a first light-emitting array layer and a first wiring layer sequentially stacked along a first direction, the first light-emitting array layer including a plurality of first light-emitting units; the driving array chip includes a driving wiring layer and a driving unit layer sequentially stacked along the first direction, the driving unit layer including a plurality of driving units, one of the driving units being used to drive one of the first light-emitting units to emit light; the first wiring layer and the driving wiring layer are electrically connected, and the two are flip-chip connected; the driving array chip is a GaN / AlGaN-based HEMT active addressing driver chip, the GaN / AlGaN-based HEMT is an enhancement-mode structure, and the driving unit layer includes a second buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a p-type GaN cap layer sequentially stacked along a second direction, the second direction being opposite to the first direction; The second light-emitting array chip includes a second wiring layer and a second light-emitting array layer stacked sequentially along the first direction, the second light-emitting array layer includes a plurality of second light-emitting units, and one driving unit is used to drive one second light-emitting unit to emit light; the second wiring layer is electrically connected to the second light-emitting array layer, and the second wiring layer and the driving wiring layer are interlayer connected; The red pixel unit array includes a plurality of red pixel units; The first light-emitting array chip includes a first bonding solder layer and a second passivation layer, the first bonding solder layer is located in a first through-hole of the second passivation layer, the first bonding solder layer is connected to the first wiring layer, the surface of the first bonding solder layer is higher than the surface of the second passivation layer, and the first bonding solder layer has a convex structure; the driving array chip includes a fifth passivation layer covering the driving wiring layer, the fifth passivation layer has a concave hole, and the concave hole is used to expose a portion of the driving wiring layer; The protruding structure of the first light-emitting array chip is aligned with the concave hole of the driving array chip; Alternatively, the first light-emitting array chip includes a first bonding solder layer and a second passivation layer, the first bonding solder layer is located in a first through hole of the second passivation layer, the first bonding solder layer is connected to the first wiring layer, and a surface of the first bonding solder layer is flush with a surface of the second passivation layer; The driving array chip includes a fifth passivation layer covering the driving wiring layer, and a second bonding solder layer located in a third through hole of the fifth passivation layer; the second bonding solder layer is connected to the driving wiring layer; The first bonding solder layer of the first light emitting array chip is aligned with the second bonding solder layer of the driving array chip.

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