Array substrate and display device

Abstract

The invention discloses an array substrate and a display device. The array substrate comprises a substrate (13), a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, wherein the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer are sequentially stacked on one side of the substrate (13); the fourth conducting layer comprises a common electrode (21), the fourth conducting layer is made of a transparent conducting oxide material, the third conducting layer is made of a metal conducting material, and at least part of the surface of the side, away from the substrate (13), of the third conducting layer makes contact with at least part of the surface of the side, close to the substrate (13), of the fourth conducting layer.

Description

Array substrate and display device Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] Liquid Crystal Display (LCD) is a common type of display. LCDs use two sheets of polarized material with a liquid crystal solution between them. Passing an electric current through the liquid causes the crystals to rearrange, preventing light from passing through them. Thus, each crystal acts like a Venetian blind, allowing light to pass through but also blocking it. Currently, LCDs are being developed to be lightweight, thin, short, and compact.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide an array substrate and a display device.

[0006] In one aspect, embodiments of the present disclosure provide an array substrate. The array substrate includes a substrate, and a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially stacked on one side of the substrate; the fourth conductive layer includes a common electrode, the fourth conductive layer is made of a transparent conductive oxide material, the third conductive layer is made of a metallic conductive material, and at least a portion of a surface of the third conductive layer away from the substrate contacts at least a portion of a surface of the fourth conductive layer closer to the substrate.

[0007] In an exemplary embodiment, the third conductive layer includes at least one signal line extending along a first direction, or the third conductive layer includes at least one signal line extending along a second direction, and the first direction intersects the second direction;

[0008] At least a portion of a surface of the at least one signal line that is away from the substrate contacts at least a portion of a surface of the common electrode that is close to the substrate.

[0009] In an exemplary embodiment, the second conductive layer includes a plurality of gate lines, and the plurality of gate lines extend along the first direction and are arranged at intervals along the second direction; the at least one signal line includes at least one common electrode line, and the at least one common electrode line extends along the first direction, and at least a portion of the surface of the at least one common electrode line away from the substrate contacts at least a portion of the surface of the common electrode close to the substrate.

[0010] In an exemplary embodiment, an orthographic projection of the common electrode line on the array substrate is located within an orthographic projection of the gate line on the array substrate.

[0011] In an exemplary embodiment, the first conductive layer includes a plurality of data lines, and the plurality of data lines are arranged at intervals along the first direction and extend along the second direction; the at least one signal line includes at least one touch line, and the at least one touch line extends along the second direction, and at least a portion of the surface of the at least one touch line away from the substrate side contacts at least a portion of the surface of the common electrode close to the substrate side.

[0012] In an exemplary embodiment, an orthographic projection of the touch line on the array substrate at least partially overlaps with an orthographic projection of the data line on the array substrate.

[0013] In an exemplary embodiment, the orthographic projection of the touch line on the array substrate is located within the orthographic projection of the data line on the array substrate.

[0014] In an exemplary embodiment, the array substrate includes a display area and a frame area located around the display area; the display area includes at least one first transistor, the first transistor includes a first active layer and a first gate, the first active layer is located between the first conductive layer and the second conductive layer, the first gate is located in the second conductive layer, and the first conductive layer includes a plurality of data lines;

[0015] The first active layer is electrically connected to the data line via a data connection electrode, and at least a portion of the data connection electrode is located in the third conductive layer.

[0016] In an exemplary embodiment, the data connection electrode includes a bottom connection electrode and a top connection electrode that are stacked, and the bottom connection electrode is located in the third conductive layer, the top connection electrode is located in the fourth conductive layer, and at least a portion of the surface of the bottom connection electrode away from the substrate is in contact with at least a portion of the surface of the top connection electrode close to the substrate.

[0017] In an exemplary embodiment, the orthographic projection of the top connecting electrode on the array substrate includes the orthographic projection of the bottom connecting electrode on the array substrate.

[0018] In an exemplary embodiment, the array substrate includes a display area and a frame area located around the display area; the frame area includes at least one second transistor, the second transistor includes a second active layer and a second gate, the second active layer is located between the first conductive layer and the second conductive layer, and the second gate is located in the second conductive layer;

[0019] The frame area includes a first connecting electrode, the second active layer is electrically connected to the first connecting electrode, and at least a portion of the first connecting electrode is located in the third conductive layer.

[0020] In an exemplary embodiment, the first connecting electrode includes a first sub-electrode and a second sub-electrode arranged in a stacked manner, and the first sub-electrode is located in the third conductive layer, the second sub-electrode is located in the fourth conductive layer, and at least a portion of the surface of the first sub-electrode away from the substrate is in contact with at least a portion of the surface of the second sub-electrode close to the substrate.

[0021] In an exemplary embodiment, the orthographic projection of the second sub-electrode on the array substrate includes the orthographic projection of the first sub-electrode on the array substrate.

[0022] In an exemplary embodiment, the array substrate includes a display area and a frame area located around the display area; the frame area includes at least one second transistor, the second transistor includes a second active layer and a second gate, the second active layer is located between the first conductive layer and the second conductive layer, and the second gate is located in the second conductive layer;

[0023] The frame area further includes a first auxiliary electrode, which is located in the second conductive layer and electrically connected to the second active layer via a first connecting electrode. At least a portion of the first connecting electrode is located in the third conductive layer.

[0024] In an exemplary embodiment, the first connecting electrode includes a first sub-electrode and a second sub-electrode arranged in a stacked manner, and the first sub-electrode is located in the third conductive layer, the second sub-electrode is located in the fourth conductive layer, and at least a portion of the surface of the first sub-electrode away from the substrate is in contact with at least a portion of the surface of the second sub-electrode close to the substrate.

[0025] In another aspect, an embodiment of the present disclosure provides a display device comprising the array substrate, an opposing substrate, and a liquid crystal layer according to any of the above embodiments; the array substrate and the opposing substrate are disposed opposite each other, and the liquid crystal layer is located between the array substrate and the opposing substrate.

[0026] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0027] Summary of the Figures

[0028] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0029] FIG1 is a schematic front view of an array substrate according to an embodiment of the present disclosure;

[0030] FIG2 is a partial cross-sectional schematic diagram of a display area of ​​an array substrate according to an embodiment of the present disclosure;

[0031] FIG3 is a partial cross-sectional schematic diagram of a second border region of an array substrate according to an embodiment of the present disclosure;

[0032] FIG4 is a partial cross-sectional schematic diagram of a second border region of an array substrate according to another embodiment of the present disclosure;

[0033] 5A is a schematic top view of a display area of ​​an array substrate in which a first conductive layer pattern is partially formed according to an embodiment of the present disclosure;

[0034] 5B is a cross-sectional schematic diagram of a display area of ​​an array substrate partially forming a first conductive layer pattern according to an embodiment of the present disclosure;

[0035] 5C is a cross-sectional schematic diagram of a second border region of an array substrate partially forming a first conductive layer pattern according to an embodiment of the present disclosure;

[0036] 6A is a schematic top view of a semiconductor layer pattern formed partially in a display area of ​​an array substrate according to an embodiment of the present disclosure;

[0037] 6B is a cross-sectional view of a semiconductor layer pattern formed partially in the display region of the array substrate according to an embodiment of the present disclosure;

[0038] 6C is a cross-sectional schematic diagram of a semiconductor layer pattern partially formed in the second border region of the array substrate according to an embodiment of the present disclosure;

[0039] 7A is a schematic top view of a display area of ​​an array substrate in which a second conductive layer pattern is partially formed according to an embodiment of the present disclosure;

[0040] 7B is a cross-sectional schematic diagram of a second conductive layer pattern formed partially in the display area of ​​the array substrate according to an embodiment of the present disclosure;

[0041] 7C is a cross-sectional diagram of a second conductive layer pattern formed partially in the second border region of the array substrate according to an embodiment of the present disclosure;

[0042] 8A is a schematic top view of a display area of ​​an array substrate in which a third insulating layer pattern is partially formed according to an embodiment of the present disclosure;

[0043] 8B is a cross-sectional schematic diagram of a display area of ​​an array substrate partially forming a third insulating layer pattern according to an embodiment of the present disclosure;

[0044] 8C is a cross-sectional schematic diagram of a third insulating layer pattern formed partially in the second border region of the array substrate according to an embodiment of the present disclosure;

[0045] 9A is a schematic top view of a display area of ​​an array substrate partially forming a third conductive layer pattern according to an embodiment of the present disclosure;

[0046] 9B is a cross-sectional schematic diagram of a display area of ​​an array substrate partially forming a third conductive layer pattern according to an embodiment of the present disclosure;

[0047] 9C is a cross-sectional schematic diagram showing a third conductive layer pattern formed partially in the second border region of the array substrate according to an embodiment of the present disclosure;

[0048] FIG10A is a schematic top view of a display area of ​​an array substrate in which a fourth conductive layer pattern is partially formed according to an embodiment of the present disclosure;

[0049] 10B is a cross-sectional schematic diagram of a display area of ​​an array substrate partially forming a fourth conductive layer pattern according to an embodiment of the present disclosure;

[0050] 10C is a cross-sectional schematic diagram showing a fourth conductive layer pattern formed partially in the second border region of the array substrate according to an embodiment of the present disclosure;

[0051] 11 is a cross-sectional schematic diagram of a second conductive layer pattern partially formed in a second border region of an array substrate according to another embodiment of the present disclosure;

[0052] 12 is a cross-sectional schematic diagram of a third insulating layer pattern formed partially in the second border region of an array substrate according to another embodiment of the present disclosure;

[0053] 13A is a schematic top view of a display area of ​​an array substrate according to another embodiment of the present disclosure showing a partial formation of a third conductive layer pattern;

[0054] 13B is a cross-sectional schematic diagram of a display area of ​​an array substrate partially forming a third conductive layer pattern according to another embodiment of the present disclosure;

[0055] 13C is a cross-sectional schematic diagram of a third conductive layer pattern formed partially in the second border region of an array substrate according to another embodiment of the present disclosure;

[0056] 14A is a schematic top view of a display area of ​​an array substrate according to another embodiment of the present disclosure showing a partial formation of a fourth conductive layer pattern;

[0057] 14B is a cross-sectional schematic diagram of a display area of ​​an array substrate partially forming a fourth conductive layer pattern according to another embodiment of the present disclosure;

[0058] 14C is a cross-sectional schematic diagram showing a fourth conductive layer pattern formed partially in the second border region of an array substrate according to another embodiment of the present disclosure;

[0059] FIG15 is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure.

[0060] Reference Signs: 10 - pixel electrode, 11 - first transistor, 12 - second transistor, DL - data line, DL-1 - extension segment, DL-2 - protruding segment, GL - gate line, 13 - substrate, 14 - first insulating layer, 15 - second insulating layer, 16 - third insulating layer, 17 - first light shielding block; 18 - first active layer, 18 - 1 - first region, 18 - 2 - second region, 18 - 3 - first channel region, 18 - 4 - first region, 18 - 5 - second region, 18 - 6 - third region; 19 - first gate electrode, 20 - data connection electrode, 20 - 1 - bottom connection electrode, 20 - 2 - top connection electrode, 21 - common electrode, 21 - 1 - connection portion, 21 - 2 - comb-tooth portion, 22 - common electrode line, 23 - second light shielding block, 24 - second active layer, 24 - 1 - second channel region, 24 - 2 - third region, 24 - 3 - fourth region; 25-Second gate, 26-First connecting electrode, 26-1-First sub-electrode, 26-2-Second sub-electrode, 27-Second connecting electrode, 27-3-Third sub-electrode, 27-4-Fourth sub-electrode, 28-First auxiliary electrode, 29-Second auxiliary electrode, 30-Touch line, 30-1-Straight segment, 30-2-Bent segment; 1-Countering substrate, 2-Liquid crystal layer, 3-Black matrix, 4-Color filter layer.

[0061] Details

[0062] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other in any way.

[0063] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0064] The ordinal numbers such as "first," "second," and "third" in this disclosure are provided to avoid confusion among constituent elements, and are not intended to limit the number. The "plurality" in this disclosure includes two or more.

[0065] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements are appropriately changed according to the direction in which the constituent elements are described. Therefore, the words and phrases are not limited to those described in the specification and can be appropriately replaced according to the circumstances.

[0066] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0067] In this disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0068] In this disclosure, a transistor refers to a device comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0069] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in the present disclosure, "source electrode" and "drain electrode" may be interchanged.

[0070] In this disclosure, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0071] In this disclosure, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0072] In the present disclosure, “about” and “approximately” refer to values ​​that are not strictly defined but allow for process and measurement errors.

[0073] The triangles, rectangles, trapezoids, pentagons or hexagons in the present disclosure are not strictly defined, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0074] An embodiment of the present disclosure provides an array substrate. The array substrate includes a substrate and a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer stacked sequentially on one side of the substrate. The fourth conductive layer includes a common electrode. The fourth conductive layer is made of a transparent conductive oxide material. The third conductive layer is made of a metallic conductive material. At least a portion of the surface of the third conductive layer away from the substrate contacts at least a portion of the surface of the fourth conductive layer closer to the substrate.

[0075] The array substrate provided in the embodiment of the present disclosure can reduce the resistance of the fourth conductive layer and improve the contact and water and oxygen resistance of the fourth conductive layer by providing a third conductive layer having a material different from that of the fourth conductive layer, and making at least a portion of the surface of the third conductive layer away from the substrate contact at least a portion of the surface of the fourth conductive layer close to the substrate.

[0076] Figure 1 is a schematic front view of an array substrate according to one embodiment of the present disclosure. As shown in Figure 1 , the array substrate may include a display area AA and a border area BB located around the display area AA. The border area BB may include a first border area B1 located on one side of the display area AA and a second border area B2 located on the remaining sides of the display area AA. For example, the first border area B1 may include the bottom border of the array substrate, and the second border area B2 may include the top, left, and right borders of the array substrate.

[0077] In one exemplary embodiment, as shown in FIG1 , the display area AA may include: a plurality of data lines DL and a plurality of gate lines GL disposed on a substrate. The plurality of gate lines GL may extend along a first direction X and be sequentially arranged along a second direction Y different from the first direction X. The plurality of data lines DL may extend along the second direction Y and be sequentially arranged along the first direction X. The first direction X and the second direction Y may intersect; for example, the first direction X may be perpendicular to the second direction Y. The plurality of data lines DL and the plurality of gate lines GL may be located in different film layers; for example, the plurality of data lines DL may be located on a side of the plurality of gate lines GL closer to the substrate.

[0078] In an exemplary embodiment, as shown in FIG1 , a plurality of data lines DL and a plurality of gate lines GL may intersect to form a plurality of sub-pixel areas. The area defined by the intersection of adjacent data lines DL and adjacent gate lines GL may be a sub-pixel area. A sub-pixel may be provided in a corresponding sub-pixel area. The sub-pixel area may include an opening area and a non-opening area surrounding the opening area. The non-opening area may be an area blocked by the black matrix of the opposing substrate of the array substrate, and the opening area may be an area not blocked by the black matrix of the opposing substrate. Adjacent gate lines GL and data lines DL may both be located within the non-opening area. The array substrate of the disclosed embodiment may be used to implement a display function, and the opening area of ​​each sub-pixel area may be configured for display. The non-opening area surrounds the opening area and does not display. However, the disclosed embodiment is not limited to this. In some examples, the array substrate may be used to implement other functions.

[0079] In one exemplary embodiment, the display area AA may include: a plurality of pixel units disposed on a substrate. At least one pixel unit may include: three sub-pixels (e.g., a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along a first direction X). The three sub-pixels of the pixel unit may be, for example, a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the three sub-pixels may be arranged sequentially in the order of blue sub-pixel, green sub-pixel, and red sub-pixel. As shown in FIG1 , at least one sub-pixel may include: a pixel electrode 10 and a common electrode (not shown in FIG1 ), and the orthographic projections of the pixel electrode 10 and the common electrode of the sub-pixel on the substrate may overlap. The common electrode of the plurality of sub-pixels in the display area AA may be a single-piece structure. For example, the common electrode may be located on a side of the pixel electrode 10 away from the substrate. The sub-pixel may also include a first transistor 11. The first transistor 11 may be located adjacent to the intersection of a data line DL and a gate line GL. The first transistor 11 may include a first gate, a first electrode, and a second electrode. The first gate may be electrically connected to the gate line GL, the first electrode of the first transistor 11 may be electrically connected to the data line DL, and the second electrode may be electrically connected to the pixel electrode 10 of the sub-pixel. The first transistor 11 may be configured to provide a data signal transmitted by the data line DL to the pixel electrode 10 of the sub-pixel under the control of the gate line GL.

[0080] In an exemplary embodiment, the second border area B2 may include at least a gate drive circuit (e.g., including a plurality of cascaded shift registers), and the plurality of shift registers may be electrically connected to the plurality of gate lines GL in the display area AA. The gate drive circuit may further include a second transistor. The second transistor may include a second gate, a third electrode, and a fourth electrode. In the present disclosure, the third electrode may be a drain electrode and the fourth electrode may be a source electrode, or the third electrode may be a source electrode and the fourth electrode may be a drain electrode.

[0081] Liquid crystal display devices have various display modes, such as ADS (Advanced Super Dimension Switch) mode, TN (twisted nematic) mode, and VA (Vertical Alignment) mode. In the ADS mode, the pixel electrode and common electrode are both located on one side of the array substrate. In the TN and VA modes, the pixel electrode and common electrode are respectively arranged on opposite sides of the liquid crystal layer, with the pixel electrode located on one side of the array substrate and the common electrode on the opposite substrate.

[0082] The ADS mode operates on the principle that liquid crystal molecules lie in a plane parallel to the glass substrate. When no voltage is applied, light passing through the lower polarizer becomes linearly polarized, parallel to the short axis of the liquid crystal molecules. This polarization cannot be rotated, and is therefore absorbed by the upper polarizer and prevented from exiting. When voltage is applied, a transverse electric field forms on the liquid crystal, aligning the liquid crystal molecules along the direction of the electric field. After passing through the lower polarizer and the liquid crystal layer, the light becomes elliptically polarized, allowing it to pass through the upper polarizer and exit.

[0083] The TN mode operates under the principle that in the absence of voltage, the liquid crystal molecules are twisted into a 90° alignment by the alignment films. Light passes through the lower polarizer and the liquid crystal molecules before exiting through the upper polarizer. When voltage is applied, most of the liquid crystal molecules, except for those near the upper and lower polarizers, align vertically. Light passing through the lower polarizer passes through the liquid crystal layer without deflection. However, since its polarization axis is parallel to the upper polarizer, the light is absorbed and cannot be emitted.

[0084] The VA mode operates on the principle that liquid crystal molecules are aligned perpendicular to the glass substrate. When no voltage is applied, light passing through the lower polarizer forms linear polarization parallel to the short axis of the liquid crystal molecules. This polarization cannot be rotated, and is therefore absorbed by the upper polarizer and prevented from being emitted. When voltage is applied, the liquid crystal molecules are deflected in the direction of the electric field. Light passing through the lower polarizer and liquid crystal layer becomes elliptically polarized, allowing it to pass through the upper polarizer and be emitted.

[0085] The structure of the array substrate is described below by taking the ADS mode array substrate structure as an example.

[0086] Figure 2 is a partial cross-sectional schematic diagram of the display area of ​​an array substrate according to an embodiment of the present disclosure. As shown in Figure 2, the display area of ​​the array substrate may include a substrate 13 and a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on one side of the substrate 13. The display area of ​​the array substrate may further include a first insulating layer 14 located between the first conductive layer and the semiconductor layer, a second insulating layer 15 located between the semiconductor layer and the second conductive layer, and a third insulating layer 16 located between the second conductive layer and the third conductive layer. In the embodiment of the present disclosure, the first insulating layer may also be referred to as a buffer layer, the second insulating layer may also be referred to as a gate insulating (GI) layer, and the third insulating layer may also be referred to as a planarization (PLN) layer. The first conductive layer may include a data line DL and a first light shielding block 17. The semiconductor layer may include a first active layer 18 of the first transistor 11, and the pixel electrode 10 and the first active layer 18 may be an interconnected, integral structure. The second conductive layer may include a first gate electrode 19 of the first transistor 11, and the first active layer 18 may be electrically connected to the data line DL via a data connection electrode 20. The third conductive layer may include a portion of the data connection electrode 20, and the fourth conductive layer may include the common electrode 21 and another portion of the data connection electrode 20. In other examples, the data line DL and the first light shielding block 17 may be located in different film layers. For example, the first light shielding block may be located on the side of the data line close to the substrate. In the embodiment of the present disclosure, by disposing the data line DL on the side of the first transistor close to the substrate 13, the capacitance between the data line DL and the pixel electrode 10 can be reduced, the power consumption of the data line can be reduced, and the performance of the array substrate can be improved.

[0087] In an exemplary embodiment, as shown in FIG. 2 , the data line DL and the first light shielding block 17 can be provided as a same-layer structure, which can simplify the manufacturing process of the array substrate, reduce the number of masks used, and lower the manufacturing cost of the display substrate.

[0088] In an exemplary embodiment, substrate 13 may provide support for film layers other than substrate 13 in the array substrate. For example, substrate 13 may be a transparent substrate. For example, substrate 13 may be a rigid substrate or a flexible substrate. For example, the material of the rigid substrate may include, but is not limited to, one or more of glass and quartz. The material of the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. However, the disclosed embodiments are not limited thereto.

[0089] In an exemplary embodiment, the materials of the first conductive layer, the second conductive layer, and the third conductive layer can be metal materials, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Alternatively, the materials of the first conductive layer, the second conductive layer, and the third conductive layer can be alloy materials of metal materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), such as aluminum-neodymium alloy (AlNd), molybdenum-niobium alloy (MoNb), and molybdenum-nickel-titanium alloy (MoNiTi). The first conductive layer, the second conductive layer, and the third conductive layer can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, Mo / Nb / Cu, MoNiTi / Cu, MoNb / Cu / MoNiTi, or MoNiTi / Cu / MoNiTi, etc.

[0090] In one exemplary embodiment, the fourth conductive layer may be made of a transparent conductive oxide material, which may include indium tin oxide (ITO) or indium zinc oxide (IZO). For example, the fourth conductive layer may be a single-layer structure or a multi-layer composite structure, such as ITO / Al / ITO.

[0091] In an exemplary embodiment, as shown in Figure 2, the orthographic projection of the first insulating layer 14 on the array substrate may include the orthographic projection of the first conductive layer on the array substrate. The first insulating layer 14 can prevent water and oxygen from corroding the data line DL and the first light-shielding block 17, thereby improving the reliability of the array substrate.

[0092] In an exemplary embodiment, the first insulating layer 14 and the second insulating layer 15 may be made of inorganic materials. For example, silicon oxynitride (SiO x N y ) or silicon nitride (SiN x ) or silicon oxide (SiO x ) and the like. The first insulating layer 14 and the second insulating layer 15 can be made of an organic material. Examples of organic materials include any one or more of epoxy resin, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, and polyether resin. The first insulating layer 14 and the second insulating layer 15 can be a single layer, multiple layers, or a composite layer.

[0093] In an exemplary embodiment, the third insulating layer 16 may be made of an organic material. Examples of such organic materials include any one or more of epoxy resin, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, and polyether resin. The third insulating layer 16 may be a single layer, multiple layers, or a composite layer.

[0094] In an exemplary embodiment, as shown in FIG2 , the orthographic projection of the first active layer 18 on the array substrate may overlap with the orthographic projections of the data line DL and the first light shielding block 17 on the array substrate. The first active layer 18 may include a first channel region 18-3, a first region 18-1 and a second region 18-2 located on opposite sides of the first channel region 18-3. For example, in the process of preparing the array substrate, a portion of the first active layer 18 may be subjected to a conductorization treatment so that portions of the first active layer 18 form the first region 18-1 and the second region 18-2, respectively. The first region 18-1 of the first active layer 18 may be used as the first electrode of the first transistor, and the second region 18-2 of the first active layer 18 may be used as the second electrode of the first transistor. The embodiments of the present disclosure do not limit the conductorization process of the semiconductor layer.

[0095] In an exemplary embodiment, the first active layer 18 may include two or more sub-active layers. For example, the first active layer 18 may include two sub-active layers, or the first active layer 18 may include three sub-active layers.

[0096] In one exemplary embodiment, the material of the first active layer 18 may include a metal oxide semiconductor material. The materials of the multiple sub-active layers may be the same or different. The metal oxide semiconductor material may include one or more metal oxide materials such as indium gallium zinc oxide (IGZO), zinc oxynitride (ZnON), and indium zinc tin oxide (IZTO). However, the present disclosure is not limited to metal oxide semiconductor materials.

[0097] In one exemplary embodiment, as shown in FIG2 , the data connection electrode 20 can be electrically connected to the data line DL and the first region 18-1 via a via located in the third insulating layer 16 . The data connection electrode 20 can have a stacked structure and include a bottom connection electrode 20-1 and a top connection electrode 20-2 stacked in sequence. The bottom connection electrode 20-1 can be located in the third conductive layer, and the top connection electrode 20-2 can be located in the fourth conductive layer. As shown in FIG2 , the orthographic projection of the top connection electrode 20-2 on the array substrate can include the orthographic projection of the bottom connection electrode 20-1 on the array substrate. For example, the orthographic projection of the top connection electrode 20-2 on the array substrate can overlap with the orthographic projection of the bottom connection electrode 20-1 on the array substrate. By providing a stacked data connection electrode structure, and using a metal conductive material with good contact and water-resistance, the data connection electrode can have a relatively stable resistance at the via hole, thereby ensuring the switching characteristics of the first transistor.

[0098] In one exemplary embodiment, as shown in FIG2 , the third conductive layer may further include a common electrode line 22. The common electrode line 22 may be electrically connected to the common electrode 21 of multiple sub-pixels. A portion of the surface of the common electrode line 22 facing away from the substrate 13 may be in contact with a portion of the surface of the common electrode 21 facing closer to the substrate 13. This eliminates the need for vias to connect the common electrodes to the common electrode lines. This reduces the resistance of the common electrodes, improves the uniformity of the common electrode voltage, and reduces the size of the non-aperture area, thereby increasing the aperture ratio of the display area.

[0099] In an exemplary embodiment, the common electrode line 22 may extend along the first direction X, and the orthographic projection of the common electrode line 22 on the array substrate may at least partially overlap with the orthographic projection of the gate line GL on the array substrate. For example, the orthographic projection of the common electrode line 22 on the array substrate may be located within the orthographic projection of the gate line GL on the array substrate.

[0100] Figure 3 is a partial cross-sectional schematic diagram of the second border region of the array substrate according to an embodiment of the present disclosure. As shown in Figure 3, the second border region of the array substrate may include a substrate 13 and a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer arranged on one side of the substrate 13. The second border region of the array substrate may also include a first insulating layer 14 located between the first conductive layer and the semiconductor layer, a second insulating layer 15 located between the semiconductor layer and the second conductive layer, and a third insulating layer 16 located between the second conductive layer and the third conductive layer. The first conductive layer may include a second light shielding block 23. The semiconductor layer may include a second active layer 24 of the second transistor 12. The second conductive layer may include a second gate electrode 25 of the second transistor 12. The third conductive layer may include a portion of the first connecting electrode 26 and a portion of the second connecting electrode 27, and the fourth conductive layer may include another portion of the first connecting electrode 26 and another portion of the second connecting electrode 27.

[0101] In one exemplary embodiment, as shown in FIG3 , the orthographic projection of the second active layer 24 on the array substrate may at least partially overlap with the orthographic projection of the second light shielding block 23 on the array substrate. The second active layer 24 may include a second channel region 24-1, a third region 24-2 located on opposite sides of the second channel region 24-1, and a fourth region 24-3. For example, during the process of manufacturing the array substrate, a portion of the second active layer 24 may be subjected to a conductorization process so that portions of the second active layer 24 form the third region 24-2 and the fourth region 24-3, respectively. The third region 24-2 of the second active layer 24 may serve as the third electrode of the second transistor, and the fourth region 24-3 of the second active layer 24 may serve as the fourth electrode of the second transistor. The presently disclosed embodiments do not limit the conductorization process for the semiconductor layer. As shown in FIG3 , the first connection electrode 26 may be electrically connected to the third region 24-2 of the second active layer 24, and the second connection electrode 27 may be electrically connected to the fourth region 24-3 of the second active layer 24.

[0102] In one exemplary embodiment, as shown in FIG3 , the first connecting electrode 26 can be electrically connected to the third region 24-2 of the second active layer 24 via a via located in the third insulating layer 16 . The first connecting electrode 26 can have a stacked structure and include a first sub-electrode 26-1 and a second sub-electrode 26-2 stacked in sequence. The first sub-electrode 26-1 can be located in the third conductive layer, and the second sub-electrode 26-2 can be located in the fourth conductive layer. As shown in FIG3 , the orthographic projection of the second sub-electrode 26-2 on the array substrate can include the orthographic projection of the first sub-electrode 26-1 on the array substrate. For example, the orthographic projection of the second sub-electrode 26-2 on the array substrate can overlap with the orthographic projection of the first sub-electrode 26-1 on the array substrate. By providing a stacked first connecting electrode made of a metallic conductive material with good contact and water-resistance, the first connecting electrode can have a relatively stable resistance at the via hole, thereby ensuring the switching characteristics of the second transistor.

[0103] In one exemplary embodiment, as shown in FIG3 , the second connecting electrode 27 can be electrically connected to the fourth region 24-3 of the second active layer 24 via a via located in the third insulating layer 16 . The second connecting electrode 27 can have a stacked structure and include a third sub-electrode 27-3 and a fourth sub-electrode 27-4 stacked in sequence. The third sub-electrode 27-3 can be located in the third conductive layer, and the fourth sub-electrode 27-4 can be located in the fourth conductive layer. As shown in FIG3 , the orthographic projection of the fourth sub-electrode 27-4 on the array substrate can include the orthographic projection of the third sub-electrode 27-3 on the array substrate. For example, the orthographic projection of the fourth sub-electrode 27-4 on the array substrate can overlap with the orthographic projection of the third sub-electrode 27-3 on the array substrate. By providing a stacked second connecting electrode, and using a metallic conductive material with good contact and oxygen-resistance, the second connecting electrode can have a relatively stable resistance at the via hole, thereby ensuring the switching characteristics of the second transistor.

[0104] Figure 4 is a partial cross-sectional schematic diagram of the second border region of an array substrate according to another embodiment of the present disclosure. As shown in Figure 4, the second border region of the array substrate may include a substrate 13 and a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer arranged on one side of the substrate 13. The second border region of the array substrate may also include a first insulating layer 14 located between the first conductive layer and the semiconductor layer, a second insulating layer 15 located between the semiconductor layer and the second conductive layer, and a third insulating layer 16 located between the second conductive layer and the third conductive layer. The first conductive layer may include a second light shielding block 23. The semiconductor layer may include a second active layer 24 of the second transistor 12. The second conductive layer may include a second gate 25 of the second transistor 12. The third conductive layer may include a portion of the first connecting electrode 26 and a portion of the second connecting electrode 27, and the fourth conductive layer may include another portion of the first connecting electrode 26 and another portion of the second connecting electrode 27.

[0105] In an exemplary embodiment, as shown in FIG4 , the second conductive layer may further include a first auxiliary electrode 28 and a second auxiliary electrode 29. The first connecting electrode 26 may be electrically connected to the third region 24-2 of the second active layer 24 and the first auxiliary electrode 28 via a via hole located in the third insulating layer 16. The second connecting electrode 27 may be electrically connected to the fourth region 24-3 of the second active layer 24 and the second auxiliary electrode 29 via a via hole located in the third insulating layer 16.

[0106] The structure of the array substrate is described below using an example of its fabrication process. The "patterning process" referred to in the embodiments of this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metal, inorganic, or transparent conductive materials. For organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed by any one or more of spray coating, spin coating, and inkjet printing; and etching can be performed by any one or more of dry etching and wet etching, although this disclosure does not limit this. A "thin film" refers to a thin layer of a material formed on a substrate using deposition, coating, or other processes. If a "thin film" does not require a patterning process during the entire fabrication process, it can also be referred to as a "layer." If a "thin film" requires a patterning process during the entire fabrication process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The term "A and B in the same layer structure" referred to in this disclosure means that A and B are formed through the same patterning process.

[0107] The preparation process of the array substrate may include the following steps:

[0108] (11) Forming a first conductive layer pattern. Forming the first conductive layer pattern may include: depositing a first conductive film on one side of the substrate 13, and patterning the first conductive film through a patterning process to form a first conductive layer pattern located on one side of the substrate 13. The first conductive layer may include a data line DL, a first light shielding block 17, and a second light shielding block 23, as shown in Figures 5A, 5B, and 5C. Figure 5B is a schematic cross-sectional view of the area marked AA in Figure 5A.

[0109] As shown in Figure 5A, the data line DL may include an extension segment DL-1 and a protruding segment DL-2. The extension segment DL-1 and the protruding segment DL-2 may be interconnected integral structures. The extension segment DL-1 may be in the shape of a line extending along the second direction Y. The first end of the protruding segment DL-2 may be connected to the extension segment DL-1, and the second end of the protruding segment DL-2 may extend in the opposite direction of the first direction X. The protruding segment DL-2 may be rectangular in shape. The protruding segment DL-2 may be configured to be electrically connected to a subsequently formed data connection electrode. As shown in Figure 5A, the first light shielding block 17 may be rectangular in shape.

[0110] (12) Forming a semiconductor layer pattern. Forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on one side of the substrate 13 on which the aforementioned pattern is formed, and patterning the semiconductor film through a patterning process to form a first insulating layer 14 located on a side of the first conductive layer away from the substrate 13, and a semiconductor layer pattern located on a side of the first insulating layer 14 away from the substrate 13. The semiconductor layer may include a first active layer 18 of a first transistor and a second active layer 24 of a second transistor, as shown in FIG6A, FIG6B, and FIG6C. FIG6B is a schematic cross-sectional view of the portion marked AA in FIG6A.

[0111] As shown in Figure 6A, the first active layer 18 may include a first region 18-4, a second region 18-5, and a third region 18-6. The second region 18-5 may be located between the first region 18-4 and the third region 18-6, and the first region 18-4, the second region 18-5, and the third region 18-6 may be connected in sequence. The first region 18-4 may be rectangular, the second region 18-5 may be L-shaped, and the third region 18-6 may be rectangular. The first end of the first region 18-4 may be connected to the first end of the second region 18-5, and the second end of the first region 18-4 may extend in a direction opposite to the first direction X. The first end of the third region 18-6 may be connected to the second end of the second region 18-5, and the second end of the third region 18-6 may extend in the second direction Y. The first region 18-4 may be configured to be electrically connected to a subsequently formed data connection electrode, and at least a portion of the third region 18-6 may be configured to function as a pixel electrode after being subjected to a conductive process.

[0112] As shown in Figure 6B, the orthographic projection of the first light-shielding block 17 on the array substrate may include the orthographic projection of the first channel region of the first active layer 18 on the array substrate, which can prevent light from irradiating the first channel region from the side close to the substrate and avoid the influence of light on the performance of the first transistor.

[0113] (13) Forming a second conductive layer pattern. Forming the second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on one side of the substrate 13 on which the aforementioned pattern is formed, and patterning the second conductive film through a patterning process to form a second insulating layer 15 located on the side of the semiconductor layer away from the substrate 13, and a second conductive layer pattern located on the side of the second insulating layer 15 away from the substrate 13. The second conductive layer may include a gate line GL, a first gate 19 of the first transistor, and a second gate 25 of the second transistor, as shown in FIG7A, FIG7B, and FIG7C. FIG7B is a schematic cross-sectional view of the portion marked AA in FIG7A.

[0114] As shown in FIG. 7A , the gate line GL and the first gate electrode 19 may be an integrated structure connected to each other, and a portion where the gate line GL overlaps with the first channel region of the first active layer 18 may serve as the first gate electrode 19 .

[0115] In an exemplary embodiment, as shown in FIG7B , forming the second conductive layer pattern may further include using the first gate 19 as a mask to perform a conductorization process on a portion of the first active layer 18. The conductorization process may be performed on a portion of the first active layer 18 so that portions of the first active layer 18 form a first region 18-1 and a second region 18-2, respectively. The first region 18-1 of the first active layer 18 may be used as a first electrode of the first transistor, and the second region 18-2 of the first active layer 18 may be used as a second electrode of the first transistor. The presently disclosed embodiment does not limit the conductorization process for the semiconductor layer. The first active layer 18 may further include a first channel region 18-3 located between the first region 18-1 and the second region 18-2.

[0116] In an exemplary embodiment, as shown in FIG7B , the pixel electrode 10 and the first active layer 18 can be an integrated structure connected to each other, which can avoid providing a via hole on the insulating layer for connecting the pixel electrode and the first active layer, can improve the water and oxygen resistance of the array substrate, and can make the pixel electrode have a stable resistance.

[0117] In an exemplary embodiment, as shown in FIG7C , forming the second conductive layer pattern may further include using the second gate 25 as a mask to perform a conductor treatment on a portion of the second active layer 24. The second active layer 24 may include a second channel region 24-1, a third region 24-2, and a fourth region 24-3 located on opposite sides of the second channel region 24-1. The conductor treatment is performed on a portion of the second active layer 24 so that portions of the second active layer 24 form the third region 24-2 and the fourth region 24-3, respectively. The third region 24-2 of the second active layer 24 can be used as the third electrode of the second transistor, and the fourth region 24-3 of the second active layer 24 can be used as the fourth electrode of the second transistor. The embodiments of the present disclosure do not limit the conductorization process of the semiconductor layer.

[0118] (14) Forming a third insulating layer pattern. Forming the third insulating layer pattern may include: depositing a third insulating film on one side of the substrate 13 on which the aforementioned pattern is formed, and patterning the third insulating film through a patterning process using a half-tone mask to form a third insulating layer pattern located on the side of the second conductive layer away from the substrate 13, as shown in FIG8A, FIG8B, and FIG8C. FIG8B is a schematic cross-sectional view taken at the position marked AA in FIG8A.

[0119] The third insulating layer 16 may include a plurality of via holes, and the plurality of via holes may include at least one first via hole K1 and two second via holes K2. The via holes may be circular holes, elliptical holes, rectangular holes, etc. As shown in FIG8A , the orthographic projection of the first via hole K1 on the array substrate overlaps with the orthographic projections of the data line DL and the first active layer 18 on the array substrate. As shown in FIG8B , the third insulating film and the first insulating layer in the first via hole K1 are etched away, exposing a portion of the surface of the first region 18-1 of the first active layer 18 away from the substrate 13, and a portion of the surface of the data line DL away from the substrate 13. The first via hole K1 allows the subsequently formed data connection electrode to be electrically connected to the data line DL and the first region 18-1 of the first active layer 18 via the via hole.

[0120] As shown in Figure 8C, two second via holes K2 can be arranged on opposite sides of the second channel region 24-1. The third insulating film within each of the two second via holes K2 is etched away, exposing a portion of the surface of the third region 24-2 on the side away from the substrate 13, and a portion of the surface of the fourth region 24-3 on the side away from the substrate 13. One second via hole K2 can electrically connect a subsequently formed first connection electrode to the third region 24-2 via this via hole, while the other second via hole K2 can electrically connect a subsequently formed second connection electrode to the fourth region 24-3 via this via hole.

[0121] (15) Forming a third conductive layer pattern. Forming the third conductive layer pattern may include: depositing a third conductive film on one side of the substrate 13, and patterning the third conductive film through a patterning process to form a third conductive layer pattern located on a side of the third insulating layer 16 away from the substrate 13. The third conductive layer may include a bottom connecting electrode 20-1, a common electrode line 22, a first sub-electrode 26-1, and a third sub-electrode 27-3, as shown in Figures 9A, 9B, and 9C. Figure 9B is a schematic cross-sectional view of the area marked AA in Figure 9A.

[0122] As shown in FIG9A , the common electrode line 22 may be in the shape of a line extending along the first direction X. The orthographic projection of the common electrode line 22 on the array substrate may at least partially overlap with the orthographic projection of the gate line on the array substrate. For example, the orthographic projection of the common electrode line 22 on the array substrate may be located within the orthographic projection of the gate line on the array substrate, thereby reducing or avoiding the occupation of the pixel opening area by the common electrode line, thereby improving the display performance of the array substrate.

[0123] As shown in FIG9A , the orthographic projection of the bottom connection electrode 20-1 on the array substrate can be rectangular and can cover the first via hole K1. As shown in FIG9B , the bottom connection electrode 20-1 can be in contact and connected to a portion of the surface of the first region 18-1 away from the substrate 13 through the first via hole K1, and can also be in contact and connected to a portion of the surface of the data line DL away from the substrate 13.

[0124] As shown in FIG9C , the first sub-electrode 26-1 may cover one second via hole K2, and the first sub-electrode 26-1 is in contact with and connected to a portion of the surface of the third region 24-2 away from the substrate 13 through the second via hole K2. The third sub-electrode 27-3 may cover one second via hole K2, and the third sub-electrode 27-3 is in contact with and connected to a portion of the surface of the fourth region 24-3 away from the substrate 13 through the second via hole K2.

[0125] (16) Forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include: depositing a fourth conductive film on one side of the substrate 13, and patterning the fourth conductive film through a patterning process to form a fourth conductive layer pattern located on the side of the third conductive layer away from the substrate 13. The fourth conductive layer may include a top connection electrode 20-2, a common electrode 21, a second sub-electrode 26-2, and a fourth sub-electrode 27-4. As shown in Figures 10A, 10B, and 10C. Figure 10B is a schematic cross-sectional view of the portion marked AA in Figure 10A.

[0126] As shown in Figure 10A, the orthographic projection of the top connecting electrode 20-2 on the array substrate and the orthographic projection of the bottom connecting electrode 20-1 on the array substrate at least partially overlap. For example, the orthographic projection of the top connecting electrode 20-2 on the array substrate may include the orthographic projection of the bottom connecting electrode 20-1 on the array substrate.

[0127] In some exemplary embodiments, the common electrode 21 may have multiple slits. As shown in FIG10A , the common electrode 21 may include a connecting portion 21-1 and multiple comb-tooth portions 21-2, with slits formed between adjacent comb-tooth portions 21-2. The first end of the comb-tooth portion 21-2 is connected to the connecting portion 21-1, and the second end of the comb-tooth portion 21-2 extends along the second direction Y. The multiple comb-tooth portions 21-2 are arranged at intervals along the first direction X. For example, the multiple comb-tooth portions 21-2 may be arranged at equal intervals along the first direction X.

[0128] As shown in Figure 10C, the orthographic projection of the second sub-electrode 26-2 on the array substrate at least partially overlaps with the orthographic projection of the first sub-electrode 26-1 on the array substrate. For example, the orthographic projection of the second sub-electrode 26-2 on the array substrate may include the orthographic projection of the first sub-electrode 26-1 on the array substrate.

[0129] As shown in Figure 10C, the orthographic projection of the fourth sub-electrode 27-4 on the array substrate at least partially overlaps with the orthographic projection of the third sub-electrode 27-3 on the array substrate. For example, the orthographic projection of the fourth sub-electrode 27-4 on the array substrate may include the orthographic projection of the third sub-electrode 27-3 on the array substrate.

[0130] In another embodiment of the present disclosure, a process for preparing an array substrate may include the following steps:

[0131] (21) A first conductive layer pattern and a semiconductor layer pattern are formed in sequence. This step can be referred to the description of the aforementioned embodiment and will not be elaborated here.

[0132] (22) Forming a second conductive layer pattern. Forming the second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on one side of the substrate 13 on which the aforementioned pattern is formed, and patterning the second conductive film through a patterning process to form a second insulating layer 15 located on the side of the semiconductor layer away from the substrate 13, and a second conductive layer pattern located on the side of the second insulating layer 15 away from the substrate 13. The second conductive layer located in the display area may refer to the description of the aforementioned embodiment. The second conductive layer located in the second frame area may include a second gate 25 of the second transistor, a first auxiliary electrode 28, and a second auxiliary electrode 29, as shown in FIG11 .

[0133] As shown in Figure 11, the second gate electrode 25, the first auxiliary electrode 28, and the second auxiliary electrode 29 are arranged at intervals. Forming the second conductive layer pattern may also include conducting a portion of the second active layer 24 so that the portion of the second active layer 24 forms a third region 24-2 and a fourth region 24-3. The third region 24-2 can be used as the third electrode of the second transistor, and the fourth region 24-3 can be used as the fourth electrode of the second transistor. The present embodiment does not limit the conductorization process of the semiconductor layer. The third region 24-2 and the first auxiliary electrode 28 can be electrically connected via a first connecting electrode formed subsequently, and the fourth region 24-3 and the second auxiliary electrode 29 can be electrically connected via a second connecting electrode formed subsequently.

[0134] (23) Forming a third insulating layer pattern. Forming the third insulating layer pattern may include: depositing a third insulating film on one side of the substrate 13 on which the aforementioned pattern is formed, and patterning the third insulating film by a patterning process using a half-tone mask to form a third insulating layer pattern located on the side of the second conductive layer away from the substrate 13. The third insulating layer located in the display area may refer to the aforementioned embodiment. The third insulating layer located in the second frame area may include at least two third vias K3, as shown in FIG12 . The third vias may be circular holes, elliptical holes, rectangular holes, etc.

[0135] As shown in Figure 12, two third via holes K3 can be arranged on opposite sides of the second channel region 24-1. The third insulating film within each of the two third via holes K3 is etched away. One third via hole K3 exposes a portion of the surface of the third region 24-2 on the side away from the substrate 13, as well as a portion of the surface of the first auxiliary electrode 28 on the side away from the substrate 13. The other third via hole K3 exposes a portion of the surface of the fourth region 24-3 on the side away from the substrate 13, as well as a portion of the surface of the second auxiliary electrode 29 on the side away from the substrate 13. One third via hole K3 can electrically connect a subsequently formed first connecting electrode to the third region 24-2 and the first auxiliary electrode 28 via this via hole. The other third via hole K3 can electrically connect a subsequently formed second connecting electrode to the fourth region 24-3 and the second auxiliary electrode 29 via this via hole.

[0136] (24) Forming a third conductive layer pattern. Forming the third conductive layer pattern may include: depositing a third conductive film on one side of the substrate 13, and patterning the third conductive film through a patterning process to form a third conductive layer pattern located on the side of the third insulating layer 16 away from the substrate 13. The third conductive layer may include a bottom connecting electrode 20-1, a touch line 30, a first sub-electrode 26-1, and a third sub-electrode 27-3, as shown in Figures 13A, 13B, and 13C. Figure 13B is a schematic cross-sectional view of the portion marked BB in Figure 13A.

[0137] As shown in FIG13A , the main body of the touch line 30 may be in the shape of a line extending along the second direction Y. The orthographic projection of the touch line 30 on the array substrate may at least partially overlap with the orthographic projection of the data line DL on the array substrate. For example, the orthographic projection of the touch line 30 on the array substrate may be located within the orthographic projection of the data line DL on the array substrate, thereby reducing or avoiding the area occupied by the touch line in the pixel opening region, thereby improving the display performance of the array substrate.

[0138] As shown in FIG13A , the touch line 30 may include a connected straight segment 30 - 1 and a bent segment 30 - 2 . The straight segment 30 - 1 may extend along the second direction Y, and the bent segment 30 - 2 may protrude away from the straight segment 30 - 1 along the first direction X. The bent segment 30 - 2 may form a clearance space to avoid the bottom connection electrode 20 - 1 .

[0139] As shown in FIG13A , the orthographic projection of the bottom connection electrode 20-1 on the array substrate can be rectangular. As shown in FIG13B , the bottom connection electrode 20-1 can cover the first via hole K1. The bottom connection electrode 20-1 can be in contact and connected to a portion of the surface of the first region 18-1 away from the substrate 13 through the first via hole K1, and to a portion of the surface of the data line DL away from the substrate 13.

[0140] As shown in FIG13C , the first sub-electrode 26-1 may cover one third via hole K3, and the first sub-electrode 26-1 is in contact and connected with the third region 24-2 and a portion of the surface of the first auxiliary electrode 28 away from the substrate 13 through the third via hole K3. The third sub-electrode 27-3 may cover one third via hole K3, and the third sub-electrode 27-3 is in contact and connected with the fourth region 24-3 and a portion of the surface of the second auxiliary electrode 29 away from the substrate 13 through the third via hole K3.

[0141] (25) Forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include: depositing a fourth conductive film on one side of the substrate 13, and patterning the fourth conductive film through a patterning process to form a fourth conductive layer pattern located on the side of the third conductive layer away from the substrate 13. The fourth conductive layer may include a top connection electrode 20-2, a common electrode 21, a second sub-electrode 26-2, and a fourth sub-electrode 27-4. As shown in Figures 14A, 14B, and 14C. Figure 14B is a schematic cross-sectional view of the portion marked BB in Figure 14A.

[0142] As shown in FIG14B , the orthographic projection of the top connection electrode 20-2 on the array substrate at least partially overlaps with the orthographic projection of the bottom connection electrode 20-1 on the array substrate. For example, the orthographic projection of the top connection electrode 20-2 on the array substrate may include the orthographic projection of the bottom connection electrode 20-1 on the array substrate. The top connection electrode 20-2 and the bottom connection electrode 20-1 together form the data connection electrode 20.

[0143] As shown in FIG14C , the orthographic projection of the second sub-electrode 26-2 on the array substrate at least partially overlaps with the orthographic projection of the first sub-electrode 26-1 on the array substrate. For example, the orthographic projection of the second sub-electrode 26-2 on the array substrate may include the orthographic projection of the first sub-electrode 26-1 on the array substrate. The second sub-electrode 26-2 and the first sub-electrode 26-1 together form the first connecting electrode 26.

[0144] As shown in FIG14C , the orthographic projection of fourth sub-electrode 27-4 on the array substrate at least partially overlaps with the orthographic projection of third sub-electrode 27-3 on the array substrate. For example, the orthographic projection of fourth sub-electrode 27-4 on the array substrate may include the orthographic projection of third sub-electrode 27-3 on the array substrate. Fourth sub-electrode 27-4 and third sub-electrode 27-3 together form second connecting electrode 27.

[0145] FIG15 is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure. As shown in FIG15 , an embodiment of the present disclosure further provides a display device. For example, a display device capable of implementing an Advanced Super Dimension Switch (ADS) mode may include the array substrate described in any of the aforementioned embodiments.

[0146] The display device may further include a counter substrate 1 and a liquid crystal layer 2 disposed between the array substrate and the counter substrate 1. The pixel electrodes and common electrodes included in the array substrate may be configured to generate an electric field that controls the deflection of liquid crystal molecules in the liquid crystal layer 2. As shown in Figure 15 , the pixel electrodes 10 and the common electrodes 21 are both located on the array substrate; no electrodes are provided on the counter substrate 1. As shown in Figure 15 , the liquid crystal molecules in the liquid crystal layer 2 may be horizontally aligned on the array substrate. In the disclosed embodiment, the horizontal direction is parallel to the plane of the array substrate.

[0147] In an exemplary embodiment, as shown in Figure 15 , the counter substrate 1 may include a base substrate, and a black matrix 3 and a color filter layer 4 disposed on the base substrate. However, the present disclosure is not limited thereto.

[0148] The present disclosure also provides a display device. The display device includes the array substrate described in any of the preceding embodiments. The display device can be any product or component with a display function, such as a liquid crystal panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. The present disclosure is not limited thereto.

[0149] Although the embodiments disclosed herein are as described above, the contents described are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. It should be noted that the above embodiments or implementations are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the implementations without departing from the scope of the present disclosure.

Claims

1. An array substrate, comprising a substrate and a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked in sequence on one side of the substrate; the fourth conductive layer comprises a common electrode, the material of the fourth conductive layer is a transparent conductive oxide material, the material of the third conductive layer is a metal conductive material, and at least a portion of the surface of the third conductive layer away from the substrate is in contact with at least a portion of the surface of the fourth conductive layer close to the substrate.

2. The array substrate according to claim 1, wherein: The third conductive layer includes at least one signal line extending along a first direction, or the third conductive layer includes at least one signal line extending along a second direction, and the first direction intersects with the second direction; At least a portion of a surface of the at least one signal line that is away from the substrate is in contact with at least a portion of a surface of the common electrode that is close to the substrate.

3. The array substrate according to claim 2, wherein: The second conductive layer includes a plurality of gate lines, and the plurality of gate lines extend along the first direction and are arranged at intervals along the second direction; the at least one signal line includes at least one common electrode line, and the at least one common electrode line extends along the first direction, and at least a portion of the surface of the at least one common electrode line away from the substrate side contacts at least a portion of the surface of the common electrode close to the substrate side.

4. The array substrate according to claim 3, wherein: The orthographic projection of the common electrode line on the array substrate is located within the orthographic projection of the gate line on the array substrate.

5. The array substrate according to claim 2, wherein: The first conductive layer includes a plurality of data lines, and the plurality of data lines are arranged at intervals along the first direction and extend along the second direction; the at least one signal line includes at least one touch line, and the at least one touch line extends along the second direction, and at least a portion of the surface of the at least one touch line away from the substrate side contacts with at least a portion of the surface of the common electrode close to the substrate side.

6. The array substrate according to claim 5, wherein: The orthographic projection of the touch line on the array substrate and the orthographic projection of the data line on the array substrate at least partially overlap.

7. The array substrate according to claim 6, wherein: The orthographic projection of the touch line on the array substrate is located within the orthographic projection of the data line on the array substrate.

8. The array substrate according to any one of claims 1 to 7, comprising a display area and a frame area located around the display area; the display area comprises at least one first transistor, the first transistor comprises a first active layer and a first gate, the first active layer is located between the first conductive layer and the second conductive layer, the first gate is located in the second conductive layer, and the first conductive layer comprises a plurality of data lines; The first active layer is electrically connected to the data line via a data connection electrode, and at least a portion of the data connection electrode is located in the third conductive layer.

9. The array substrate according to claim 8, wherein: The data connection electrode includes a bottom connection electrode and a top connection electrode which are stacked, and the bottom connection electrode is located in the third conductive layer, the top connection electrode is located in the fourth conductive layer, and at least a portion of a surface of the bottom connection electrode away from the substrate is in contact with at least a portion of a surface of the top connection electrode close to the substrate.

10. The array substrate according to claim 9, wherein: The orthographic projection of the top connecting electrode on the array substrate includes the orthographic projection of the bottom connecting electrode on the array substrate.

11. The array substrate according to any one of claims 1 to 7, comprising a display area and a frame area located around the display area; the frame area comprises at least one second transistor, the second transistor comprises a second active layer and a second gate, the second active layer is located between the first conductive layer and the second conductive layer, and the second gate is located in the second conductive layer; The frame region includes a first connecting electrode, the second active layer is electrically connected to the first connecting electrode, and at least a portion of the first connecting electrode is located in the third conductive layer.

12. The array substrate according to claim 11, wherein: The first connecting electrode includes a first sub-electrode and a second sub-electrode which are stacked, and the first sub-electrode is located in the third conductive layer, the second sub-electrode is located in the fourth conductive layer, and at least a portion of the surface of the first sub-electrode away from the substrate is in contact with at least a portion of the surface of the second sub-electrode close to the substrate.

13. The array substrate according to claim 12, wherein: The orthographic projection of the second sub-electrode on the array substrate includes the orthographic projection of the first sub-electrode on the array substrate.

14. The array substrate according to any one of claims 1 to 7, comprising a display area and a frame area located around the display area; the frame area comprises at least one second transistor, the second transistor comprises a second active layer and a second gate, the second active layer is located between the first conductive layer and the second conductive layer, and the second gate is located in the second conductive layer; The frame area further includes a first auxiliary electrode, which is located in the second conductive layer and is electrically connected to the second active layer via a first connecting electrode, and at least a portion of the first connecting electrode is located in the third conductive layer.

15. The array substrate according to claim 14, wherein: The first connecting electrode includes a first sub-electrode and a second sub-electrode which are stacked, and the first sub-electrode is located in the third conductive layer, the second sub-electrode is located in the fourth conductive layer, and at least a portion of the surface of the first sub-electrode away from the substrate is in contact with at least a portion of the surface of the second sub-electrode close to the substrate.

16. A display device, comprising the array substrate, an opposing substrate and a liquid crystal layer according to any one of claims 1 to 15; the array substrate and the opposing substrate are arranged opposite to each other, and the liquid crystal layer is located between the array substrate and the opposing substrate.

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