Multilayer capacitor

Abstract

The invention relates to a multilayer capacitor, a circuit board including the multilayer capacitor, and an integrated circuit package including the multilayer capacitor. A multilayer capacitor includes a body including a plurality of dielectric layers and a plurality of electrode layers alternating. Each electrode layer includes a first electrode having a base portion, a connection portion, and a central portion; a first connecting edge extends from a first front edge of the base portion to a first edge of the central portion, and a second connecting edge extends from a second front edge of the base portion to a second edge of the central portion. At least a portion of at least one of a first connection edge or a second connection edge of the first electrode in the plurality of electrode layers is not perpendicular to a respective first edge or second edge of a central portion of the first electrode.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 420,726, filed on Oct. 31, 2022, which is incorporated herein by reference in its entirety. Background Art

[0003] Multi-layer capacitors are typically constructed with multiple dielectric layers and multiple internal electrode layers in a stacked arrangement. During manufacture, the stacked dielectric and internal electrode layers are pressed and sintered to obtain a generally monolithic capacitor body. To improve the performance of these capacitors, various configurations and designs have been employed for the dielectric layers and the internal electrode layers.

[0004] However, as the electronics industry undergoes rapid changes and new performance standards are required, these configurations are typically manipulated. Specifically, various application design considerations have led to a need to redefine capacitor parameters and their performance in high-speed environments, especially as integrated circuits become faster and more dense. For example, greater current, higher density circuit boards, and rising costs all converge on the need for better and more efficient capacitors. Additionally, the design of various electronic components has been driven by the overall industry trend towards miniaturization and increased functionality.

[0005] In this regard, there is a need to provide a capacitor with improved operating characteristics. Summary of the Invention

[0006] According to an embodiment of the present invention, a multilayer capacitor is disclosed. The multilayer capacitor has a first end and a second end, and the second end is separated from the first end in the longitudinal direction, which is perpendicular to the transverse direction, and both the transverse direction and the longitudinal direction are perpendicular to the Z direction. The multilayer capacitor includes a body having a top surface and a bottom surface opposite to the top surface along the Z direction. The body includes a plurality of alternating dielectric layers and a plurality of electrode layers, and the plurality of electrode layers include a plurality of first electrode layers and a plurality of second electrode layers. Each electrode layer includes a first electrode having a base portion, a connecting portion, and a central portion; a first connecting edge of the connecting portion extends from a first front edge of the base portion to a first edge of the central portion, and a second connecting edge of the connecting portion extends from a second front edge of the base portion to a second edge of the central portion. The multilayer capacitor further includes a plurality of external terminals, and the plurality of external terminals include a first external terminal and a second external terminal. The first external terminal is disposed on at least one of the top surface or the bottom surface, and the second external terminal is disposed on at least one of the top surface or the bottom surface. The first external terminal is electrically connected to the plurality of first electrode layers along at least one of the first front edge or the second front edge of the first electrode in the plurality of first electrode layers. The second external terminal is electrically connected to the plurality of second electrode layers along at least one of the first front edge or the second front edge of the first electrode in the plurality of second electrode layers. At least a part of at least one of the first connecting edge or the second connecting edge of the first electrode in the plurality of electrode layers is not perpendicular to the corresponding first edge or the second edge of the central portion of the first electrode.

[0007] Other features and aspects of the present invention are set forth in more detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The complete and enabling disclosure of the present invention, including the best mode thereof for those skilled in the art, is set forth more particularly in the remainder of the specification, including reference to the accompanying drawings, in which:

[0009] Figure 1A A generally top and side external perspective view of an embodiment of a capacitor including two external terminals according to the present invention is shown;

[0010] Figure 1B A perspective view of a capacitor according to the present invention mounted on a mounting surface is shown; Figure 1A of the capacitor;

[0011] Figure 1C A side perspective view of an electrode layer of a capacitor according to an embodiment of the present invention is shown; Figure 1A of the capacitor;

[0012] Figure 1D A perspective view of a capacitor according to another embodiment of the present invention is shown; Figure 1ASide perspective view of the electrode layer of the capacitor;

[0013] Figure 1E Perspective view showing an embodiment of the arrangement of multiple electrode layers of the present invention;

[0014] Figure 1F Showing according to another embodiment of the present invention Figure 1A Side perspective view of the electrode layer of the capacitor;

[0015] Figure 1G Showing according to yet another embodiment of the present invention Figure 1A Side perspective view of the electrode layer of the capacitor;

[0016] Figure 2A Top view showing another embodiment of the electrode of the present invention;

[0017] Figure 2B And FIG. 2D shows according to various embodiments of the present invention Figure 2A Side perspective view of the electrode layer of the capacitor;

[0018] Figure 3A Approximate top and side external perspective views showing an embodiment of a 2 by 2 packaged capacitor according to the present invention;

[0019] Figure 3B Approximate top and side external perspective views showing another embodiment of a 2 by 2 packaged capacitor according to the present invention;

[0020] Figure 3C Showing Figure 3A Including Figure 1F Top and side perspective views of a capacitor having multiple sets of alternating dielectric layers and internal electrode layers;

[0021] Figure 4A Approximate top and side external perspective views showing an embodiment of a 2 by 4 packaged capacitor according to the present invention;

[0022] Figure 4B Showing Figure 4A Top and side external perspective views of a capacitor including the multiple sets of alternating dielectric layers and internal electrode layers of FIG. 2D;

[0023] Figure 5A Approximate top and side external perspective views showing an embodiment of a 4 by 4 packaged capacitor according to the present invention;

[0024] Figure 5B Showing Figure 5A Top and side perspective views of a capacitor including the multiple sets of alternating dielectric layers and internal electrode layers of FIG. 2D;

[0025] Figure 6 shows a side view of a printed circuit board and an integrated circuit package incorporating an encapsulated capacitor according to the present invention; and

[0026] FIG. 7 shows a side view of a printed circuit board and an integrated circuit package incorporating a plurality of prior art multilayer ceramic capacitors. DETAILED DESCRIPTION

[0027] Those of ordinary skill in the art will understand that this discussion is only a description of exemplary embodiments and is not intended to limit the broader aspects of the present invention.

[0028] Generally, the present invention relates to a multilayer capacitor. The multilayer capacitor (or simply capacitor) includes at least one set of alternating dielectric layers and electrode layers within a single body, as well as a plurality of external terminals. Additionally, the electrode layers can include electrodes having a specific configuration. More specifically, at least one electrode layer includes an electrode that includes at least one edge that is not perpendicular to an intersecting edge. That is, aspects of the present disclosure relate to controlling the shape of the electrode to improve the operating characteristics of the capacitor, such as increasing the breakdown voltage.

[0029] As used herein, the description of a first edge as "not perpendicular to" a second edge generally means that the first edge and the second edge meet or intersect in a manner such that the intersecting edge does not form a substantially right angle or 90-degree angle. This intersection of edges can also be referred to as non-orthogonal. Additionally, one of the two edges can be referred to as an abnormal edge. Additionally or alternatively, an electrode having a first edge that is not perpendicular to the intersecting second edge can be described in terms of the overall shape of the electrode, which will be understood to include the non-perpendicular intersecting edge.

[0030] Various examples of electrodes including at least a portion of at least one edge that is not perpendicular to an intersecting edge are described and shown herein. For example, the electrode can have a connecting portion and a central portion as defined herein, where an angle greater than 90° and less than 180° is formed between an edge of the central portion and a connecting edge of the connecting portion. Without intending to be limited by theory, this angle can provide the electrode with a generally Y-shaped configuration.

[0031] As another example, the electrode may include at least one curved or rounded connecting edge. The curved or rounded connecting edge may define a rounded corner. The rounded corner may provide an increased breakdown voltage by reducing the electric field / charge concentration. For example, a rectangular electrode typically concentrates the electric field and charge concentration at its corners, such that breakdown of the dielectric is more likely to occur near the corners of the dielectric. In accordance with aspects of the present disclosure, at least a portion of at least one edge that is not perpendicular to an intersecting edge may be curved or rounded, which may reduce the electric field concentration in the dielectric material. For example, although the corners of the electrode and the corners of the charged portion of the dielectric generally do not coincide, they may still be relatively close to each other. Thus, reducing the charge concentration in the corners of the electrode further reduces the charge concentration in the charged portion of the dielectric. Reducing the charge concentration and thus increasing the breakdown voltage as compared to other similar capacitors employing conventional electrodes.

[0032] In addition, in some embodiments, the outer edge of the electrode may not be geometrically discontinuous. As an example, a rounded corner may be continuously incorporated into the adjacent straight edges of the electrode without a geometric discontinuity. Geometric discontinuities are generally described with reference to the order of the corresponding derivative. For example, a shape may typically be defined by a coordinate function (e.g., Cartesian or polar coordinates). If the coordinate function itself has no discontinuities, the shape is geometrically continuous. Similarly, if there are no discontinuities in the coordinate function and its first derivative, the shape is geometrically continuous to the first order. An electrode having an outer edge that is geometrically continuous to at least the first order may further reduce the electric field and charge concentration in the corners and / or along the edges of the electrode adjacent to the corners. This reduction may increase the breakdown voltage of the capacitor as compared to conventional electrode designs.

[0033] Furthermore, the inventors have found that by utilizing these configurations of the capacitor and the electrode layers therein and by utilizing the specific materials of the electrodes and dielectrics described herein, multilayer capacitors (particularly over a wide frequency range) may have a lower equivalent series resistance. Specifically, this lower equivalent series resistance may be achieved at relatively high frequencies and is beneficial.

[0034] In this regard, the equivalent series resistance of the capacitor can be 100 ohms or less, such as 75 ohms or less, such as 50 ohms or less, such as 40 ohms or less, such as 30 ohms or less, such as 25 ohms or less, such as 20 ohms or less, such as 15 ohms or less, such as 10 ohms or less, such as 8 ohms or less, such as 5 ohms or less, such as 3 ohms or less, such as 2 ohms or less, such as 1 ohm or less. The equivalent series resistance can be 0.01 ohms or greater, such as 0.1 ohms or greater, such as 0.2 ohms or greater, such as 0.3 ohms or greater, such as 0.5 ohms or greater, such as 0.8 ohms or greater, such as 1 ohm or greater, such as 2 ohms or greater, such as 3 ohms or greater, such as 5 ohms or greater, such as 8 ohms or greater, such as 10 ohms or greater. Such equivalent series resistance can be achieved when measured in a frequency range from 1 GHz to 10 GHz (such as from 2 GHz to 10 GHz, such as from 3 GHz to 10 GHz, such as from 4 GHz to 9 GHz). General techniques known in the art and described herein can be used to measure the equivalent series resistance.

[0035] In some embodiments, the capacitor can exhibit the aforementioned equivalent series resistance at approximately a single frequency. For example, in one embodiment, the capacitor can exhibit the aforementioned equivalent series resistance at the following frequencies: at approximately 2 GHz, such as at approximately 3 GHz, such as at approximately 4 GHz, such as at approximately 5 GHz, such as at approximately 6 GHz, such as at approximately 7 GHz, such as at approximately 8 GHz, such as at approximately 9 GHz, such as at approximately 10 GHz. In one embodiment, the capacitor can exhibit the aforementioned equivalent series resistance at more than one of the aforementioned frequencies.

[0036] In addition to exhibiting a relatively low equivalent series resistance due to selectively controlling the specific configuration of the electrodes and the capacitor, as well as the materials of the electrodes and the dielectric, the resulting capacitor can also exhibit a low equivalent series inductance. In certain applications, it is desirable to keep the inductance as low as possible (i.e., parasitic inductance). Employing the capacitor of the present invention allows for a significant reduction in inductance. Specifically, minimizing the distance or path to ground can help reduce the inductance. Generally speaking, compared with employing multiple separate multilayer ceramic capacitors as shown in FIG. 7, employing the capacitor of the present invention as Figure 6The capacitor shown can allow the inductance to be reduced by at least one order of magnitude. For example, compared with capacitors of the prior art that exhibit relatively large inductance values, the capacitor of the present invention can produce inductance values in the picohenry or even femtohenry range. Generally, the inductance can be less than 1 nanohenry. Specifically, the inductance can be 900 picohenry or less, such as 750 picohenry or less, such as 500 picohenry or less, such as 400 picohenry or less, such as 250 picohenry or less, such as 100 picohenry or less, such as 50 picohenry or less, such as 25 picohenry or less, such as 15 picohenry or less, such as 10 picohenry or less. The inductance can be 1 femtohenry or greater, such as 25 femtohenry or greater, such as 50 femtohenry or greater, such as 100 femtohenry or greater, such as 250 femtohenry or greater, such as 500 femtohenry or greater, such as 750 femtohenry or greater. Minimizing such inductance can achieve good performance, especially good decoupling performance under high-speed transient conditions. The characteristic of a lower equivalent series inductance value can also be a lower impedance value, which reflects the parasitic inductance.

[0037] The electrode layers within a group can be stacked in the lateral direction such that these electrode layers will be perpendicular to the mounting surface. In this regard, each electrode layer will extend in the longitudinal direction and the Z direction, both the longitudinal direction and the Z direction being perpendicular to the lateral direction. By arranging the dielectric layers and the electrode layers in a stacked or laminated configuration, the capacitor can be referred to as a multilayer capacitor, and especially as a multilayer ceramic capacitor when the dielectric layer includes ceramics, for example.

[0038] In addition, in some embodiments, multiple sets of alternating dielectric layers and electrode layers can be included within a single capacitor body. For example, a multilayer capacitor can include a first set of alternating dielectric layers and electrode layers and a second set of alternating dielectric layers and electrode layers. The capacitor can also include external terminals electrically connected to the electrode layers, where the external terminals are formed on the top surface of the capacitor and on the bottom surface of the capacitor opposite the top surface. In other embodiments, the capacitor can include at least three sets of alternating dielectric layers and electrode layers, such as at least four sets of alternating dielectric layers and electrode layers. However, it should be understood that the present invention can include any number of sets of alternating dielectric layers and electrode layers and is not necessarily limited. Additionally, the multiple sets of alternating dielectric layers and electrode layers can be spaced apart from adjacent sets by a certain distance. For example, the distance is greater than the thickness of an individual dielectric layer within the set. Specifically, the distance can be at least twice the thickness of a dielectric layer within the set, such as at least 3 times, such as at least 5 times, such as at least 10 times.

[0039] Generally, the thicknesses of the dielectric layer and the internal electrode layer are not limited and can be any desired thickness according to the performance characteristics. For example, the thickness of the electrode layer can be, but is not limited to, about 500 nanometers (nm) or greater, such as about 1 micrometer (μm) or greater, such as about 1.5 μm or greater, such as about 2 μm or greater, such as about 3 μm or greater, such as about 4 μm or greater. The thickness of the electrode layer can be about 10 μm or less, such as about 5 μm or less, such as about 4 μm or less, such as about 3 μm or less, such as about 2.5 μm or less, such as about 2 μm or less. For example, the internal electrode layer can have a thickness ranging from about 1 μm to about 2 μm.

[0040] In addition, the present invention need not be limited by the number of internal electrode layers in each set of alternating dielectric layers and internal electrode layers or the number of internal electrode layers in the entire capacitor. For example, each set can include the following number of internal electrode layers: 10 or more, such as 25 or more, such as 50 or more, such as 100 or more, such as 200 or more, such as 300 or more, such as 500 or more, such as 600 or more, such as 750 or more, such as 1000 or more. Each set can include the following number of internal electrode layers: 5000 or less, such as 4000 or less, such as 3000 or less, such as 2000 or less, such as 1500 or less, such as 1000 or less, such as 750 or less, such as 500 or less, such as 400 or less, such as 300 or less, such as 250 or less, such as 200 or less, such as 175 or less, such as 150 or less. In addition, the entire capacitor can include the aforementioned number of electrode layers.

[0041] In addition to the alternating internal electrode layers and dielectric layers, the capacitor further includes a first external terminal and a second external terminal. The first external terminal is electrically connected to the first internal electrode layer and is disposed on the first surface (e.g., the upper surface) of the capacitor. The second external terminal is electrically connected to the first internal electrode layer and is disposed on the second surface (e.g., the lower surface) of the capacitor. Similarly, a third external terminal is electrically connected to the second internal electrode layer and is disposed on the first surface of the capacitor, and a fourth external terminal is electrically connected to the second internal electrode layer and is disposed on the second surface of the capacitor. Generally, the first external terminal and the second external terminal have the same polarity (e.g., positive), while the third external terminal and the fourth external terminal have the same polarity (e.g., negative).

[0042] The capacitor may further include external terminals located on opposite end surfaces. For example, one or more of the plurality of external terminals may extend from the first surface (e.g., the upper surface) and / or the second surface (e.g., the lower surface) to the end surface. When present on the end surface, the external terminal may only partially be present on the end surface such that the external terminal does not cover the entire end surface. In another embodiment, the capacitor may not include any external terminals on the opposite end surfaces. In a particular embodiment, there may be no external terminals on the side surfaces of the capacitor. In any case, the external terminals generally include at least one first-polarity terminal and at least one second opposite-polarity terminal. The capacitor may include the following number of first-polarity terminals and / or second opposite-polarity terminals on the upper surface of the capacitor: at least one, such as at least two, such as at least four, such as at least six, such as at least eight. Additionally, the capacitor may include the above-mentioned number of terminals on the lower surface of the capacitor.

[0043] The capacitor may include an equal number of first-polarity terminals and / or second-polarity terminals on the upper surface and the lower surface of the capacitor. On the upper surface of the capacitor, the number of first-polarity terminals may be equal to the number of second opposite-polarity terminals. On the lower surface of the capacitor, the number of first-polarity terminals may be equal to the number of second opposite-polarity terminals. The total number of terminals present on the upper surface of the capacitor may be equal to the total number of terminals present on the lower surface of the capacitor. The total number of first-polarity terminals present on the upper surface and the lower surface of the capacitor may be equal to the total number of second opposite-polarity terminals present on the upper surface and the lower surface of the capacitor. Generally, the terminals of similar polarity corresponding to a particular set of alternating dielectric layers and internal electrode layers on the lower surface of the capacitor are electrically connected to the terminals of similar polarity on the upper surface of the capacitor. The terminals of similar polarity located on the upper surface and the lower surface of the capacitor may not be staggered. In this regard, the corresponding terminals of similar polarity on the top surface and the lower surface may not be offset in terms of terminal position, but may instead be directly positioned above or below another terminal of similar polarity on the opposite top surface or lower surface. In other words, the corresponding terminals of similar polarity (and in particular the corresponding lead tabs of this set) corresponding to a particular set of alternating dielectric layers and internal electrode layers may be substantially aligned. Substantially aligned means that the offset of one lateral edge of the polarity terminal on the upper surface relative to the lateral edge is within + / - 10%, such as within + / - 5%, such as within + / - 4%, such as within + / - 3%, such as within + / - 2%, such as within + / - 1%, such as within + / - 0.5% of the offset of the corresponding polarity terminal on the lower surface relative to the lateral edge.

[0044] A specific arrangement of capacitor elements (e.g., the orientation of electrode layers in a single capacitor body, the number of groups of alternating layers) can provide several advantages. For example, the capacitors of the present invention can be mounted onto a circuit board as surface mount capacitors and can provide a smaller footprint on the circuit board. This in turn can also allow for a reduction in the size of the circuit board.

[0045] The capacitors of the present invention can be further described according to the various embodiments shown as Figures 1A to 1G , Figures 2A to 2C , Figures 3A to 3C , Figure 4A and Figure 4B , Figure 5A and Figure 5B as well as Figure 6 and are shown in the following embodiments.

[0046] Turning to Figures 1A to 1G , an embodiment of a multilayer capacitor 10 is disclosed. Generally, capacitor 10 includes a body 16 that contains a plurality of alternating dielectric layers and electrode layers 102, 104. A first external terminal 12 and a second external terminal 14 are formed on capacitor body 16.

[0047] For example, capacitor 10 has a 1 by 2 configuration. That is, capacitor 10 includes two external terminals that are arranged in a one-dimensional linear manner on the top and bottom surfaces of the capacitor. In the depicted embodiment, capacitor 10 includes external terminals that are arranged in a linear manner or in a single row along a longitudinal direction L, which may be referred to as a linear terminal arrangement. Additionally, in the depicted embodiment, external terminals 12, 14 are spaced apart from side surfaces 18e, 18f of capacitor body 16 such that only dielectric material is provided between external terminals 12, 14 and side surfaces 18e, 18f.

[0048] Body 16 includes six surfaces. For example, referring to Figure 1A, the body 16 includes a top surface 18a and an opposite bottom surface 18b in the Z-direction 136 or the width direction. The body 16 may further include two end surfaces 18c, 18d extending between the top surface 18a and the bottom surface 18b. The end surfaces 18c, 18d may be opposite to each other in the longitudinal direction 132 or the length direction. The end surfaces 18c, 18d may extend in the transverse direction 134 and the Z-direction 136. The body 16 may further include two side surfaces 18e, 18f, which also extend between the top surface 18a and the bottom surface 18b. The side surfaces 18e, 18f may extend in the longitudinal direction 132 and the Z-direction 136. In one embodiment, the side surfaces 18e, 18f may be parallel to the major face of the electrode. Similarly, in one embodiment, the top surface 18a and the bottom surface 18b may be perpendicular to the major face of the electrode. Thus, in one embodiment, the body 16 includes a total of at least six surfaces (e.g., one top surface, one bottom surface, two side surfaces, and two end surfaces). In this regard, the body 16 may have a parallelepiped shape, such as a rectangular parallelepiped shape.

[0049] In addition, as Figure 1B shown, the capacitor 10 may be mounted to a mounting surface 11, such as a printed circuit board or a substrate. In this regard, the multilayer capacitor may be configured to be mounted to the mounting surface such that the electrode layers are perpendicular to the mounting surface.

[0050] The multilayer capacitor 10 may include a plurality of electrode layers 102, 104 and a plurality of dielectric layers stacked in the transverse direction 134. Some of the dielectric layers may include electrode layers formed thereon. Generally, the thicknesses of the dielectric layers and the electrode layers are not limited and may be any desired thickness according to the performance characteristics of the capacitor. For example, the electrode layer may have a thickness ranging from about 1 μm to about 2 μm, but electrode layers having other thicknesses described herein may also be used. In addition, in one embodiment, the thickness of the dielectric layer may be defined according to the aforementioned thickness of the electrode layer. Furthermore, it should be understood that such a thickness of the dielectric layer may also be applicable to any layer between the electrode layers.

[0051] Figure 1C A side view of an embodiment of an electrode configuration according to aspects of the present disclosure is shown. More specifically, each electrode layer may include a first electrode layer 102 and a second electrode layer 104 arranged alternately, such as as described in the following reference Figure 1E described. Reference Figure 1C, each electrode layer 102, 104 may include a first electrode 106 and a second electrode 108. The first electrode 106 may have a base portion 114. For example, the base portion 114 of the first electrode 106 may extend in the longitudinal direction 132 and have a vertical edge 121 extending in the Z direction 136. The base portion 114 may further include a first front edge 114a and a second front edge 114b opposite the first front edge 114a along the Z direction 136. The first front edge 114a and the second front edge 114b each extend in the longitudinal direction 132 and intersect the vertical edge 121, such that the edges 114a, 114b, 121 define the boundary of the first electrode 106 in the base portion 114.

[0052] The second electrode 108 may have a base portion 114. For example, the base portion 114 of the second electrode 108 may also extend in the longitudinal direction 132 and have a lateral edge extending in the Z direction 136.

[0053] The first electrode 106 may further have a central portion 112. The central portion 112 may extend in the longitudinal direction 132 and have a vertical edge 123 extending in the Z direction 136. The vertical edge 123 of the central portion 112 is opposite to the vertical edge 121 of the base portion 114, such that the vertical edges 121, 123 define the longitudinal boundary of the first electrode 106. In addition, the central portion 112 may include a first edge 112a and a second edge 112b opposite the first edge 112a along the Z direction 136. The first edge 112a and the second edge 112b each extend in the longitudinal direction 132 and intersect the vertical edge 123, such that the edges 112a, 112b, 123 define the boundary of the first electrode 106 in the central portion 112.

[0054] The central portion 112 of the first electrode 106 may have a first width 127 extending, for example, in the Z direction 136. In addition, the base portion 114 of the first electrode 106 may have a second width 129 extending, for example, in the Z direction 136. In this regard, the position of the first width 127 may be offset from the position of the second width 129 in the longitudinal direction 132, such that the position of the second width 129 is closer to the external terminal to which it is electrically connected. This configuration may allow adjustment of the overlapping region between the central portions 112 of adjacent electrodes in the transverse direction 134. In addition, in at least some embodiments, the second width 129 of the base portion 114 may be greater than the first width 127 of the central portion 112.

[0055] In addition, a central end gap distance 133 can be formed in the longitudinal direction 132 between the longitudinal ends of the central portion 112 of the first electrode 106 and the longitudinal ends of the base portion 114 of the second electrode 108. Thus, in one embodiment, the ratio of the central end gap distance 133 to the capacitor length 15( Figure 1A ) can be 0.01 or greater, such as 0.05 or greater, such as 0.1 or greater, such as 0.2 or greater, such as 0.3 or greater, such as 0.4 or greater. The ratio can be, for example, 0.5 or less, such as 0.4 or less, such as 0.3 or less, such as 0.2 or less, such as 0.1 or less.

[0056] Generally, the internal electrode layers 102, 104 include at least one lead tab 1002, 1004 that extends along the Z direction 136 from the top and bottom edges of the central portion 112 of the internal electrode layer. For example, as Figure 1C shown, the first lead tab 1002 extends from the top edge 112a of the central portion 112, and the second lead tab 1004 extends from the bottom edge 112b. Typically, the lead tabs 1002, 1004 of the electrode layers 102, 104 extend to the top and bottom surfaces of the capacitor and assist in forming the external terminals 12, 14. In this regard, the lead tabs 1002, 1004 can be exposed on the top surface 18a and the bottom surface 18b of the capacitor and allow for connection between the central portion 112 of the internal electrode layer and the external terminals 12, 14. For example, the lead tabs 1002, 1004 can be defined by the base portion 114 and include a first front edge 114a and a second front edge 114b that extend to the edge of the dielectric layer and allow for the formation of the external terminals 12, 14 on the top surface 18a and the bottom surface 18b.

[0057] The lengths of the lead connection tabs 1002, 1004 can vary as needed, but are typically from about 0.3 millimeters (mm) to about 1.2 mm, in some embodiments from about 0.4 mm to about 1.1 mm, and in some embodiments from about 0.5 mm to about 1 mm. When there is more than one lead connection tab along an edge, each lead connection tab can have the same length. In another embodiment, each lead connection tab can have a different length. For example, a lead connection tab that is generally aligned with the side edge of the internal electrode layer can have a greater length than a lead connection tab that is offset from the side edge of the internal electrode layer. In this regard, the ratio of the length of a lead connection tab that is aligned with the side edge of the internal electrode layer to the length of a lead connection tab that is offset from the side edge of the internal electrode layer can be from about 0.3 to about 5, in some embodiments from about 0.5 to about 4, and in some embodiments from about 0.7 to about 3. Generally aligned typically means that the offset of a lateral edge of the first lead connection tab and / or the second lead connection tab on the top edge relative to the side edge is within + / - 10% of the offset of the corresponding lateral edge of the first lead connection tab and / or the second lead connection tab on the bottom edge relative to the side edge, such as within + / - 5%, such as within + / - 4%, such as within + / - 3%, such as within + / - 2%, such as within + / - 1%, such as within + / - 0.5%.

[0058] The lead connection tabs 1002, 1004 on the top and bottom edges of the internal electrode layers 102, 104 can be aligned in the vertical direction. That is, a lateral edge (extending in the Z direction 136) of the first lead connection tab 1002 can be aligned with a lateral edge (extending in the Z direction 136) of the second lead connection tab 1004 that is opposite the first lead connection tab 1002. Additionally, such lateral edges of the lead connection tabs 1002, 1004 can be aligned with the side edges 121 of the internal electrode layers 102, 104. However, it should be understood that the lateral edges of the lead connection tabs 1002, 1004 can be aligned with each other but offset from the side edge 121.

[0059] As described, the relationship between the lateral edges of the first lead connection tab on the top edge and the lateral edges of the second lead connection tab on the bottom edge, as mentioned with respect to the internal electrode layer 102, can also apply to the internal electrode layer 104. With this arrangement, a gap can be formed between the first lead connection tab 1002 of the first internal electrode layer 102 and the first lead connection tab 1002 of the second internal electrode layer 104. Similarly, a gap can be formed between the second lead connection tab 1004 of the first internal electrode layer 102 and the second lead connection tab 1004 of the second internal electrode layer 104. The sizes of the respective corresponding gaps can be substantially the same.

[0060] The lead tabs 1002 can be arranged in parallel with the lead tabs 1004, extending from the internal electrode layers 102 and 104 such that the respective lead tabs extending from the alternating electrode layers 102 and 104 can be aligned in corresponding columns. For example, the lead tabs 1002, 1004 of the internal electrode layer 102 can be arranged in a corresponding stacked configuration, and the lead tabs 1002, 1004 of the internal electrode layer 104 can be arranged in a corresponding stacked configuration.

[0061] It will be understood that the lead tabs 1002, 1004 of the electrode layer 102 are connected to the external terminals 12, and the lead tabs 1002, 1004 of the electrode layer 104 are connected to the external terminals 14. Thus, the respective lead tabs 1002, 1004 of the electrode layer 102 will be staggered with the respective lead tabs 1002, 1004 of the electrode layer 104 in a manner similar to the external terminals 12 and 14. The staggered lead tabs can provide multiple adjacent current injection points on the associated main electrode portions.

[0062] The distance between each adjacent exposed lead tab of the internal electrode layer in a given column can be specifically designed to help ensure the guiding and shaping of each terminal. The range of the distance between the exposed lead tabs of the internal electrode layer in a given column can be, for example, from about 0.25 μm to about 10 μm, in some embodiments from about 0.5 μm to about 5 μm, and in some embodiments from about 1 μm to about 4 μm. Additionally, the distance between adjacent columnar stacks of each electrode tab can (but is not limited to) be at least twice as large as the distance between adjacent lead tabs in a given column to ensure that different terminals do not operate together. In some embodiments, the distance between each adjacent columnar stack of the exposed metallization can be about four times (4x) the distance between each adjacent exposed electrode tab in a particular stack. However, this distance can vary depending on the desired capacitance performance and circuit board configuration. For example, as determined based on the central point of each lead tab or based on the distance between adjacent lateral edges of each lead tab, this distance can be from about 0.1 mm to about 1.5 mm, in some embodiments from about 0.2 mm to about 1.3 mm, and in some embodiments from about 0.3 mm to about 1 mm. Additionally, such a distance can correspond to the spacing distance of the balls on a ball grid array.

[0063] Still referring to Figure 1C, the first electrode 106 may also have a connection portion 116. The connection portion 116 may extend from the base portion 114 in the longitudinal direction 132. Specifically, the connection portion 116 may extend between and connect the base portion 114 and the central portion 112. For example, the first connection edge 116a of the connection portion 116 extends from the first front edge 114a of the base portion 114 to the first edge 112a of the central portion 112, and the second connection edge 116b of the connection portion 116 extends from the second front edge 114b of the base portion 114 to the second edge 112b of the central portion 112. Thus, the first connection edge 116a intersects the first front edge 114a and the first edge 112a to connect the base portion 114 to the central portion 112 along one longitudinal side of the first electrode 106, and the second connection edge 116b intersects the second front edge 114b and the second edge 112b to connect the base portion 114 to the central portion 112 along the other opposite longitudinal side of the first electrode 106.

[0064] The connection portion 116 may have, for example, a third width 131 that extends in the Z direction 136. In this regard, the position of the third width 131 may be offset in the longitudinal direction 132 from the position of the first width 127 and the position of the second width 129. In one embodiment, the third width 131 of the connection portion may be less than the second width 129 of the base portion 114. Additionally, the third width 131 of the connection portion may be greater than the first width 127 of the central portion 112. In this regard, the position of the third width 131 may be between the position of the first width 127 and the position of the second width 129.

[0065] Furthermore, the third width 131 may vary within the connection portion 116. For example, the third width 131 may have a first value at one position within the connection portion 116 and a different second value at another position within the connection portion 116, where these two positions within the connection portion 116 are separated from each other in the longitudinal direction 132.

[0066] At least a portion of at least one of the first connecting edge 116a or the second connecting edge 116b is not perpendicular to the edges 112a, 112b where the sum of the central portion and the connecting edges 116a, 116b intersect. For example, in one embodiment, the first connecting edge 116a of the connecting portion 116 may form a first angle 141 with the first edge 112a of the central portion 112. Such an angle 141 may be greater than 90° and less than 180°. For example, such an angle 141 may be greater than 90°, such as 95° or greater, such as 100° or greater, such as 110° or greater, such as 120° or greater, such as 130° or greater, such as 140° or greater. Such an angle 141 may be less than 180°, such as 175° or less, such as 170° or less, such as 160° or less, such as 150° or less, such as 140° or less, such as 130° or less, such as 120° or less, such as 110° or less. Without being bound by theory, such a configuration may provide a generally Y-shaped electrode configuration.

[0067] In addition, in the depicted Figure 1C embodiment, a second angle 147 is formed between the second edge 112b of the central portion 112 and the second connecting edge 116b of the connecting portion 116, and the second angle 147 (as described above for the first angle 141) is greater than 90° and less than 180°. Thus, for Figure 1C the first electrode 106 shown in, at least a portion of the first connecting edge 116a is not perpendicular to the first edge 112a, and at least a portion of the second connecting edge 116b is not perpendicular to the second edge 112b. It should also be understood that for the depicted embodiment, at least a portion of the first connecting edge 116a is not perpendicular to the first front edge 114a, and at least a portion of the second connecting edge 116b is not perpendicular to the second front edge 114b.

[0068] In another embodiment, as Figure 1DAs shown, the connecting portion 116 can also form an angle 143 with the base portion 114. For example, the base portion 114 can have a first lateral edge portion 130a extending in the Z direction 136 and a second lateral edge portion 130b extending in the Z direction 136. The first lateral edge portion 130a and the second lateral edge portion 130b intersect the first connecting edge 116a and the second connecting edge 116b respectively. At least a portion of the second connecting edge 116b may not be perpendicular to the vertical edge 130 of the base portion 114. For example, such a vertical edge 130 can form an angle 143 with the second connecting edge 116b of the connecting portion 116. Similarly, at least a portion of the first connecting edge 116a may not be perpendicular to the vertical edge 130 of the base portion 114, such that an angle 143 is also defined between the first connecting edge 116a and the vertical edge 130. Such an angle 143 can be greater than 90° and less than 180°. For example, such an angle 143 can be greater than 90°, such as 95° or greater, such as 100° or greater, such as 110° or greater, such as 120° or greater, such as 130° or greater, such as 140° or greater. Such an angle 143 can be less than 180°, such as 175° or less, such as 170° or less, such as 160° or less, such as 150° or less, such as 140° or less, such as 130° or less, such as 120° or less, such as 110° or less. Vertical edge 130.

[0069] It will be understood that Figure 1F The embodiments of Figures 1C to 1E are generally similar to Figure 1F However, Figure 1F In the embodiments of the electrode layers 102, 104 of Figure 1C and Figure 1D the second electrode 108 is omitted and only the first electrode 106 is included. In addition, Figure 1D The first electrode shown in

[0070] As shown, the connecting edges 116a, 116b of the connecting portion 116 can extend in the longitudinal direction 132 and the Z direction 136. In one embodiment, such edges can be straight edges, such that the connecting edges 116a, 116b are substantially straight. Such straight edges are inFigure 1C and Figure 1D as shown. In another embodiment, such an edge can be a curved edge having a curved / circular configuration.

[0071] For example, Figure 1G electrode layers 102, 104 are shown having curved or circular connection edges 116a, 116b. That is, Figure 1G electrode layers 102, 104 are shown in which at least one of the first electrode 106 or the second electrode 108 has at least one rounded corner. As used herein, "circular" can refer to an outer edge having an arc of a circle or an ellipse. "Circular" can also refer to any suitable edge that is not precisely circular or elliptical but is otherwise curved / arcuate.

[0072] Furthermore, in some embodiments, the outer edges of the first electrode 106 and / or the second electrode 108 may not be geometrically discontinuous. For example, one or more rounded corners can blend continuously into adjacent straight edges without any geometric discontinuities. In some embodiments, at least one of the first electrode 106 and / or the second electrode 108 can have a geometrically continuous shape. In other words, there can be no discontinuities in the coordinate function that describes the shape (e.g., in Cartesian or polar coordinates). In some embodiments, the shape can be geometrically continuous to the first order. In other words, the first derivative of the coordinate function that describes the shape of the first electrode 106 and / or the second electrode 108 can not contain discontinuities.

[0073] Such a rounded corner configuration can reduce the electric field and charge concentration in the rounded corners and / or along the edges adjacent to the rounded corners of the electrodes 106, 108. Compared to conventional electrode configurations, such a reduction can increase the breakdown voltage of a capacitor incorporating the electrode layers 102, 104.

[0074] As described herein, a corner can be the intersection of two edges of the electrodes 106, 108. In some embodiments, each corner of the first electrode 106 and each corner of the second electrode 108 can be circular. However, in other embodiments, as Figure 1G shown, some of the multiple electrode corners are circular and some are not. For example, in the illustrated embodiment, both the first connection edge 116a and the second connection edge 116b are curved or circular such that at least a portion of each of the respective connection edges 116a, 116b is not perpendicular to the first edge 112a and the second edge 112b, and the first electrode 106 has two rounded corners at the transition from the base portion 114 to the central portion 112. Producing rounded corners can involve additional manufacturing costs compared to non-rounded corners; thus, a mixed corner configuration can provide similar benefits as embodiments having more (e.g., all) rounded corners and reduce manufacturing costs.

[0075] It should be understood that additional configurations regarding rounded corners and non-rounded corners are possible within the scope of the present disclosure. For example, in some embodiments, the second electrode 108 may similarly have two rounded corners and two non-rounded corners. For example, the rounded corners of the second electrode 108 may be adjacent to the first electrode 106, and the non-rounded corners of the second electrode 108 may face away from the first electrode 106. In other embodiments, the first electrode 106 may have only rounded corners, while the second electrode 108 has only non-rounded corners. In still other embodiments, the first electrode 106 may not have any rounded corners, while the second electrode 108 has only rounded corners.

[0076] There may also be other variations and / or combinations within the scope of the present disclosure. For example, the first electrode 106 may have an electrode configuration that is generally Y-shaped and one or more rounded corners. Different numbers and / or configurations of connecting edges that are not perpendicular to the edges of the central portion may be used in the electrodes 106, 108 on the respective electrode layers 102, 104. For example, one or more of the electrode layers 102, 104 may have electrodes 106, 108 with a connecting portion 116 configuration that is different from at least one other electrode layer 102, 104.

[0077] As Figure 1C 、 Figure 1D 、 Figure 1F and Figure 1G As further shown, each of the front edges 114a, 114b of the base portion 114 of the first electrode 106 may also have a certain length 135 that extends in the longitudinal direction 132. Generally, such a length 135 of the base portion may be defined as the distance between the vertical edge 121 and the transition point between the base portion 114 and the connecting portion 116. For example, each of the first front edge 114a and the second front edge 114 may generally have a slope of 0°, and the point at which the slope changes may be considered the aforementioned transition point. In any case, such a length may be 0.05 or greater, such as 0.1 or greater, such as 0.15 or greater, such as 0.2 or greater, such as 0.3 or greater, as defined herein for the capacitor length 15. Such a length 135 may be 0.5 or less, such as 0.4 or less, such as 0.3 or less, such as 0.25 or less, such as 0.2 or less, such as 0.15 or less of the capacitor length 15.

[0078] Still as Figure 1C 、 Figure 1D and Figure 1GAs shown, the base portion 114 of the second electrode 108 may also have a certain length 145 extending in the longitudinal direction 132. Such length may be 0.05 or greater of the capacitor length 15, such as 0.1 or greater, such as 0.15 or greater, such as 0.2 or greater, such as 0.3 or greater. Such length 145 may be 0.5 or less of the capacitor length 15, such as 0.4 or less, such as 0.3 or less, such as 0.25 or less, such as 0.2 or less, such as 0.15 or less.

[0079] In one embodiment, the aforementioned lengths 135 and 145 may be different. In a particular embodiment, the aforementioned lengths 135 and 145 may be substantially the same.

[0080] In addition, the first external terminal 12 may have a first lateral edge 122 ( Figure 1A ). The first lateral edge 122 may extend in the Z direction 136 and / or the transverse direction 134. The first lateral edge 122 may define a terminal width BW of the first external terminal 12; the second external terminal 14 may also have the terminal width BW. The external terminals 12, 14 have a terminal length BL along the top surface 18a, and the terminal length BL extends along the longitudinal direction 132.

[0081] The first lateral edge 122 of the first external terminal 12 may be substantially aligned with the vertical edge 130 of the base portion 114 of the first electrode 106 in the longitudinal direction. Such vertical edge 130 may be located at the position where the base portion 114 ends and the connecting portion 116 begins. For example, the first lateral edge 122 of the first external terminal 12 may be within 5% in the longitudinal direction based on the length of the base portion 114 of the first electrode 106 with respect to the vertical edge 130 of the base portion 114 of the first electrode 106, such as within 4% or less, such as within 3% or less, such as within 2% or less, such as within 1% or less, such as within 0.8% or less, such as within 0.6% or less, such as within 0.5% or less, such as within 0.4% or less, such as within 0.3% or less, such as within 0.2% or less, such as within 0.1% or less.

[0082] Similarly, the second external terminal 14 may have a second lateral edge 124 ( Figure 1A)。The second lateral edge 124 can extend in the Z direction 136 and / or the lateral direction 134. The second lateral edge 124 of the second external terminal 14 can be substantially aligned with the vertical edge 130 of the base portion 114 of the first electrode 106 in the longitudinal direction. Such a vertical edge 130 can be located at the position where the base portion 114 ends and the connecting portion 116 begins. For example, the second lateral edge 124 of the second external terminal 14 can be within 5%, such as within 4%, such as within 3%, such as within 2%, such as within 1%, such as within 0.8%, such as within 0.6%, such as within 0.5%, such as within 0.4%, such as within 0.3%, such as within 0.2%, such as within 0.1% of the vertical edge 130 of the base portion 114 of the first electrode 106 in the longitudinal direction based on the length of the base portion 114 of the first electrode 106.

[0083] In addition, the first lateral edge 122 of the first external terminal 12 can be substantially aligned with the lateral edge 126 of the base portion 114 of the second electrode 108 of the electrode layer 104 in the longitudinal direction ( Figure 1E ). For example, the first lateral edge 122 of the first external terminal 12 can be within 5%, such as within 4%, such as within 3%, such as within 2%, such as within 1%, such as within 0.8%, such as within 0.6%, such as within 0.5%, such as within 0.4%, such as within 0.3%, such as within 0.2%, such as within 0.1% of the lateral edge 126 of the base portion 114 of the second electrode 108 in the longitudinal direction based on the length of the base portion 114 of the second electrode 108.

[0084] Similarly, the second lateral edge 124 of the second external terminal 14 can be substantially aligned with the lateral edge 128 of the base portion 114 of the second electrode 108 of the electrode layer 102 in the longitudinal direction ( Figure 1E ). For example, the second lateral edge 124 of the second external terminal 14 can be within 5%, such as within 4%, such as within 3%, such as within 2%, such as within 1%, such as within 0.8%, such as within 0.6%, such as within 0.5%, such as within 0.4%, such as within 0.3%, such as within 0.2%, such as within 0.1% of the lateral edge 128 of the base portion 114 of the second electrode 108 in the longitudinal direction based on the length of the base portion 114 of the second electrode 108.

[0085] As indicated herein, a dielectric layer and an electrode layer can be stacked to form a set of alternating layers. As described elsewhere herein, one, two, three, four or more sets of stacked, alternating dielectric layers and electrode layers can be disposed within a single capacitor body. Capacitor 10 includes a single set of dielectric layers and electrode layers that form the body 16 of capacitor 10, but the capacitor body can include additional sets of stacked layers, for example, as referenced Figures 3A to 5B as described.

[0086] Referenced Figure 1E , a plurality of first electrode layers 102 and a plurality of second electrode layers 104 can be arranged in an alternating mirror configuration. For example, each electrode layer can be staggered in a relative and spaced-apart relationship, with a dielectric layer between each electrode layer. As shown, the central portions 112 of each electrode layer at least partially overlap. Figure 1E A total of four electrode layers are shown; however, it should be understood that any number of electrode layers can be used to obtain the desired capacitance for a desired application. For example, the capacitor can include 10 or more internal electrode layers, such as 25 or more internal electrode layers, such as 50 or more internal electrode layers, such as 100 or more internal electrode layers, such as 200 or more internal electrode layers, such as 300 or more internal electrode layers, such as 500 or more internal electrode layers, such as 600 or more internal electrode layers, such as 750 or more internal electrode layers, such as 1000 or more internal electrode layers. The capacitor can include 5000 or fewer internal electrode layers, such as 4000 or fewer internal electrode layers, such as 3000 or fewer internal electrode layers, such as 2000 or fewer internal electrode layers, such as 1500 or fewer internal electrode layers, such as 1000 or fewer internal electrode layers, such as 750 or fewer internal electrode layers, such as 500 or fewer internal electrode layers, such as 400 or fewer internal electrode layers, such as 300 or fewer internal electrode layers, such as 250 or fewer internal electrode layers, such as 200 or fewer internal electrode layers, such as 175 or fewer internal electrode layers, such as 150 or fewer internal electrode layers.

[0087] The present invention provides a multilayer capacitor having a unique electrode arrangement and configuration that provides the various benefits and advantages noted herein. In this regard, it should be understood that the materials used in constructing the capacitor can be unrestricted and can be any materials commonly used in the art, and any methods commonly used in the art can be used to form them.

[0088] Generally, a dielectric layer can typically be formed of a specific type of material having a specific dielectric constant. For example, in one embodiment, the dielectric layer can be formed of a material having a relatively high dielectric constant (K). Such a dielectric constant can be greater than 125, for example 200 or greater, for example 500 or greater, for example 1000 or greater up to about 40000 or less, for example about 30000 or less, for example about 20000 or less. In other embodiments, the dielectric layer can be formed of a material having a relatively low dielectric constant (K). For example, the dielectric constant can be 10 or greater, for example 15 or greater, for example 20 or greater, for example 30 or greater, for example 40 or greater, for example 50 or greater, for example 60 or greater, for example 70 or greater, for example 80 or greater, for example 90 or greater. The dielectric constant can be 125 or less, for example 110 or less, for example 100 or less, for example 90 or less, for example 80 or less, for example 70 or less, for example 60 or less, for example 50 or less, for example 40 or less, for example 30 or less, for example 20 or less.

[0089] Generally, these materials can include ceramics. The ceramics can be provided in various forms, for example, (for example pre-fired) wafers or dielectric materials co-fired within the device itself. Specific examples of these types of materials include, for example, NPO (COG), X7R (from about 3000 to about 7000), X7S, Z5U, and / or Y5V materials. It should be recognized that the above materials are described by their industry-accepted definitions, some of which are standard classifications established by the Electronic Industries Alliance (EIA), and should thus be recognized by those of ordinary skill in the art.

[0090] In a particular embodiment, the dielectric layer can include NPO (COG) materials. Generally, these materials are considered EIA Class I ceramic materials. These materials can have a relatively low temperature coefficient. For example, without intending to be limited by theory, these materials can have a minimum capacitance change with temperature. Additionally, as described above, such materials can also have a relatively low dielectric constant. Thus, such materials can have a relatively small capacitance per unit volume.

[0091] For example, these materials can have a capacitance change with temperature as follows: 0 ± 30 ppm / °C, such as 0 ± 25 ppm / °C, such as 0 ± 20 ppm / °C, such as 0 ± 15 ppm / °C, such as 0 ± 10 ppm / °C, such as 0 ± 5 ppm / °C, such as 0 ppm / °C. In other words, these materials can experience a change of ±0.3%, such as ±0.25%, such as ±0.2%, such as ±0.15%, such as ±0.1%, such as ±0.05%, such as 0%, from -55°C to 125°C. For the above cases, the capacitance value at 25°C can be used as a reference point. In this regard, the capacitance can range from 10 pF to 0.01 μF. For example, the capacitance can be 0.5 pF or greater, such as 1 pF or greater, such as 5 pF or greater, such as 10 pF or greater, such as 50 pF or greater, such as 100 pF or greater, such as 200 pF or greater, such as 500 pF or greater, such as 800 pF or greater, such as 1 nF or greater, such as 5 nF or greater. The capacitance can be 10 nF or less, such as 8 nF or less, such as 5 nF or less, such as 3 nF or less, such as 1 nF or less, such as 900 pF or less, such as 700 pF or less, such as 500 pF or less, such as 300 pF or less, such as 200 pF or less, such as 100 pF or less, such as 50 pF or less, such as 20 pF or less. The capacitance mentioned above can refer to the capacitance of a capacitor.

[0092] These ceramic materials including NPO (COG) ceramic materials and the resulting dielectric layers can include perovskites, such as barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconate titanate, barium strontium zirconate titanate, barium calcium zirconate titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconate titanate, lead lanthanum zirconate titanate), sodium bismuth titanate, etc. In a particular embodiment, for example, barium strontium titanate with the chemical formula Ba x Sr 1-x TiO 3 can be used, where x ranges from 0 to 1, in some embodiments x ranges from about 0.15 to about 0.65, and in some embodiments x ranges from about 0.25 to about 0.6. In this regard, in one embodiment, the dielectric layer can include titanate. Other suitable perovskites can include, for example: Ba x Ca 1-x TiO 3 , where x ranges from about 0.2 to about 0.8, in some embodiments, from about 0.4 to about 0.6; Pb x Zr 1-x TiO 3(“PZT”), where x ranges from about 0.05 to about 0.4; lead lanthanum zirconium titanate (“PLZT”), lead titanate (PbTiO 3 ), barium calcium zirconium titanate (BaCaZrTiO 3 ), sodium nitrate (NaNO 3 ), KNbO 3 , LiNbO 3 , LiTaO 3 , PbNb 2 O 6 , PbTa 2 O 6 , KSr(NbO 3 ), and NaBa 2 (NbO 3 ) 5 KHb 2 PO 4 . Additional complex perovskites can include A[B1 1 / 3 B2 2 / 3 O 3 materials, where A is Ba x Sr 1-x (x can be a value from 0 to 1); B1 is Mg y Zn 1-y (y can be a value from 0 to 1); B2 is Ta z Nb 1-z (z can be a value from 0 to 1). In this regard, in one embodiment, the material and the corresponding dielectric layer can include titanates, such as barium titanate.

[0093] In yet another embodiment, these ceramic materials including NPO (COG) ceramic materials and the resulting dielectric layers can include oxides. For example, the oxides can include zinc, zirconium, niobium, magnesium, tantalum, titanium, cobalt, strontium, neodymium, samarium, silicon, etc., or mixtures thereof. In one embodiment, the oxides can include rare earth oxides. In one embodiment, the ceramic material can at least include titanium dioxide. In one embodiment, the ceramic material can include zirconium dioxide. In yet another embodiment, the ceramic material can include silicon dioxide. In one embodiment, the ceramic material can include titanium dioxide, zirconium dioxide, silicon dioxide, or mixtures thereof.

[0094] In yet another embodiment, these ceramic materials including NPO (COG) ceramic materials and the resulting dielectric layer may include a combination of titanates and oxides. Specifically, the ceramic materials and the dielectric layer may include a combination of barium titanate and oxides.

[0095] The electrodes and electrode layers may be formed of any of a variety of different metals known in the art. The electrode layer may be made of a metal such as a conductive metal. The materials may include noble metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, aluminum, zinc, etc.), etc., and various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloys and corresponding sputtered layers of chromium, nickel, and gold may also be suitable. The electrodes may also be made of low-resistance materials (e.g., silver, copper, gold, aluminum, palladium, etc.). In one particular embodiment, the electrode layer may include nickel or an alloy thereof. In another particular embodiment, the electrode layer may include copper or an alloy thereof.

[0096] Each electrode layer 102, 104 may include one or more electrodes, such as described below with reference to Figures 1C to 1G For example, in some embodiments, such as Figures 1C to 1E and Figure 1G shown, each electrode layer 102, 104 may include a first electrode 106 and a second (opposing) electrode 108. In other embodiments, such as Figure 1F shown, each electrode layer 102, 104 may include a single electrode.

[0097] Generally, the capacitors described herein relate to a particular electrode configuration. However, it should be understood that other types of electrodes and / or electrode layers known in the art may also be used within the capacitors. For example, these other electrodes and / or electrode layers may include, but are not limited to, shield electrodes, dummy electrodes, floating electrodes, etc. For example, in one embodiment, the capacitor may include a shield electrode. In another embodiment, the capacitor may include a dummy electrode. In yet another embodiment, the capacitor may include a floating electrode. Additionally, such electrodes may have any shape known in the art. However, in one embodiment, the capacitor may not include a shield electrode, a dummy electrode, and / or a floating electrode. For example, in one embodiment, the capacitor may not include a shield electrode. In another embodiment, the capacitor may not include a dummy electrode. In yet another embodiment, the capacitor may not include a floating electrode.

[0098] As Figure 1AAs shown, in addition to the main body 16 including the dielectric layer and the electrode layers 102, 104, the capacitor 10 may further include a first external terminal 12 and a second external terminal 14. The first external terminal 12 may be connected (e.g., electrically connected) to the first electrode 106 of the first electrode layer 102 and the second (opposite) electrode 108 of the second electrode layer 104. The second external terminal 14 may be connected (e.g., electrically connected) to the first electrode 106 of the second electrode layer 104 and the second (opposite) electrode 108 of the first electrode layer 102.

[0099] For example, the first external terminal 12 may be electrically connected to the first electrode layer 102 along at least one of the first front edge 114a or the second front edge 114b of the base portion 114 of the first electrode 106 of the first electrode layer 102. The second external terminal 14 may be electrically connected to the second electrode layer 104 along at least one of the first front edge 114a or the second front edge 114b of the base portion 114 of the first electrode 106 of the second electrode layer 104. The front edges 114a, 114b may help form the external terminals 12, 14 further described herein.

[0100] The external terminals 12 and 14 may be formed on the corresponding end surfaces 18c and 18d of the main body 16. However, the external terminals 12 and 14 may be present on other surfaces. For example, the external terminals may extend to the top surface 18a, the bottom surface 18b, and the two side surfaces 18e, 18f. Specifically, the external terminal 12 may extend to the top surface 18a, the bottom surface 18b, and the side surfaces 18e, 18f. Similarly, the external terminal 14 may extend to the top surface 18a, the bottom surface 18b, and the side surfaces 18e, 18f. In Figure 1A the embodiment shown, the first external terminal 12 extends to the top surface 18a, the bottom surface 18b, and the end surface 18c, and the second external terminal 14 extends to the top surface 18a, the bottom surface 18b, and the end surface 18d, such that the external terminals 12, 14 are separated from the side surfaces 18c, 18d. In yet another embodiment, the external terminals may be formed only on the top surface, only on the bottom surface, or only on the top surface and the bottom surface, for example, such that the external terminals are separated from one or more of the end surfaces 18c, 18d or the side surfaces 18e, 18f.

[0101] Generally, the average thickness of the external terminal can be about 500 μm or less, such as about 400 μm or less, such as about 250 μm or less, such as about 150 μm or less, such as about 100 μm or less, such as about 50 μm or less, such as about 40 μm or less, such as about 30 μm or less, such as about 25 μm or less, such as about 20 μm or less. The average thickness of the external terminal can be about 5 μm or greater, such as about 10 μm or greater, such as about 15 μm or greater, such as about 25 μm or greater, such as about 50 μm or greater, such as about. For example, the average thickness of the external terminal can be from about 5 μm to about 50 μm, such as from about 10 μm to about 40 μm, such as from about 15 μm to about 30 μm, such as from about 15 μm to about 25 μm. In one embodiment, the aforementioned thickness refers to the average thickness of the entire external terminal (e.g., an external terminal including more than one layer). In another embodiment, the aforementioned thickness refers to the average thickness of a single layer of the external terminal.

[0102] Regarding the embodiments discussed herein, the external terminal can be formed of any of a variety of different metals known in the art. The external terminal can be made of a metal such as a conductive metal. The materials can include noble metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and the like, and various combinations thereof. In a particular embodiment, the external terminal can include copper or its alloy.

[0103] The external terminal can be formed using any method known in the art. The external terminal can be formed using techniques such as sputtering, painting, printing, electroless plating, or fine copper termination (FCT), electroplating, plasma deposition, propellant spray / airbrushing, etc.

[0104] In one embodiment, the external terminal can be formed such that the external terminal is relatively thick. For example, such a terminal can be formed by applying a thick film strip of metal to the exposed portion of the electrode layer (e.g., by dipping the capacitor into a liquid external terminal material). Such metal can be in a glass matrix and can include silver or copper. As an example, such a strip can be printed and fired onto the capacitor. Thereafter, additional metal (e.g., nickel, tin, solder, etc.) plating can be formed on the termination strip such that the capacitor can be soldered to the substrate. Such application of the thick film strip can be performed using any method known in the art (e.g., by a terminator and a printing wheel for transferring a metal-carrying paste onto the exposed electrode layer).

[0105] The average thickness of the thick-plated external terminal can be about 500 μm or less, such as about 300 μm or less, such as about 200 μm or less, such as about 150 μm or less, such as about 100 μm or less, such as about 80 μm or less. The average thickness of the thick-plated external terminal can be about 25 μm or greater, such as about 35 μm or greater, such as about 50 μm or greater, such as about 75 μm or greater. For example, the average thickness of the thick-plated external terminal can be from about 25 μm to about 150 μm, such as from about 35 μm to about 125 μm, such as from about 50 μm to about 100 μm. In one embodiment, the aforementioned thickness refers to the average thickness of the entire external terminal (e.g., an external terminal including more than one layer). In another embodiment, the aforementioned thickness refers to the average thickness of a single layer of the external terminal.

[0106] In another embodiment, the external terminal can be formed such that the external terminal is a thin film coating of metal. Such a thin film coating can be formed by depositing a conductive material such as a conductive metal on the exposed portion of the electrode layer. For example, the front edge of the electrode layer can be exposed so that the front edge can allow the formation of a plated terminal.

[0107] The average thickness of the thin-plated external terminal can be about 50 μm or less, such as about 40 μm or less, such as about 30 μm or less, such as about 25 μm or less. The average thickness of the thin-plated external terminal can be about 5 μm or greater, such as about 10 μm or greater, such as about 15 μm or greater. For example, the average thickness of the external terminal can be from about 5 μm to about 50 μm, such as from about 10 μm to about 40 μm, such as from about 15 μm to about 30 μm, such as from about 15 μm to about 25 μm. In one embodiment, the aforementioned thickness refers to the average thickness of the entire external terminal (e.g., an external terminal including more than one layer). In another embodiment, the aforementioned thickness refers to the average thickness of a single layer of the external terminal.

[0108] Generally, the external terminal can include a plated terminal. For example, the external terminal can include an electroplated terminal, an electroless-plated terminal, or a combination thereof. For example, an electroplated terminal can be formed by electroplating. An electroless-plated terminal can be formed by electroless plating.

[0109] When multiple layers constitute the external terminal, the external terminal can include an electroplated terminal and an electroless-plated terminal. For example, electroless plating can be first used to deposit an initial material layer. Then the plating technique can be switched to an electrochemical plating system, which can allow for faster material deposition.

[0110] When forming a plated terminal by any plating method, the front edge of the electrode layer exposed from the body of the capacitor is subjected to the plating solution. In one embodiment, by being subjected to, the capacitor can be immersed in the plating solution.

[0111] A plating solution containing a conductive material (such as a conductive metal) is used to form the plated terminals. Such a conductive material can be any of the above materials or any material known in the art. For example, the plating solution can be a nickel sulfamate bath solution or other nickel solutions, such that the plated layer and the external terminals include nickel. Alternatively, the plating solution can be a copper acid bath solution or other suitable copper solutions, such that the plated layer and the external terminals include copper.

[0112] In addition, it should be understood that the plating solution can include other additives known in the art. For example, the additives can include other organic additives and media that can assist the plating process. In addition, additives can be used in order to use the plating solution at a desired pH. In one embodiment, additives that reduce resistance can be employed in the solution to assist in complete plating coverage and bonding of the plating material to the exposed leading edges of the capacitor and the electrodes.

[0113] The capacitor can be exposed, immersed, or dipped into the plating solution for a predetermined amount of time. Such exposure time need not be limited, but can be an amount of time sufficient to allow deposition of enough plating material to form the plated terminals. In this regard, the time should be sufficient to allow formation of a continuous connection between the desired exposed, adjacent electrode leading edges.

[0114] Generally speaking, the difference between electroplating and electroless plating is that electroplating (such as by using an external power source) employs an electrical bias. The electroplating solution can typically withstand a high current density range, for example, ten to fifteen amperes per square foot (amp / ft 2 )(with a rated voltage of 9.4 volts). The connection can be formed by connecting the negative pole of the capacitor that needs to form the plated terminals and the positive pole of a solid material (such as copper in a copper plating solution) in the same plating solution. That is, the capacitor is biased to a polarity opposite to that of the plating solution. Using this method, the conductive material of the plating solution is attracted to the metal on the exposed leading edge of the electrode layer.

[0115] Before immersing the capacitor into the plating solution or subjecting the capacitor to the plating solution, various pretreatment steps can be employed. These steps can be carried out for various purposes, including catalyzing, accelerating, and / or improving the adhesion of the plating material to the leading edges of the electrodes.

[0116] In addition, an initial cleaning step may be employed prior to plating or any other pre-treatment step. Such a step may be employed to remove any oxide buildup formed on the exposed edges of the electrode. When the internal electrode or other conductive element is formed of nickel, this cleaning step may be particularly helpful in assisting in removing any buildup of nickel oxide. Parts cleaning may be accomplished by complete immersion in a pre-cleaning bath, such as a bath comprising an acidic detergent. In one embodiment, exposure may be for a predetermined time, such as on the order of about 10 minutes. Cleaning may also alternatively be accomplished by a chemical polishing or harperizing step.

[0117] In addition, the step of activating the exposed metal front edge of the electrode can be performed to promote the deposition of the conductive material. Activation can be achieved by immersion in a palladium salt, (by mask or laser) photopatterning of a palladium organometallic precursor, screen printing or inkjet deposition of a palladium compound, or electrophoretic palladium deposition. It should be appreciated that only palladium-based activation is currently disclosed as an example of an activation scheme, which generally works well with the activation of an exposed tab portion formed of nickel or its alloy. However, it should be understood that other activation schemes may also be used.

[0118] Furthermore, in lieu of or in addition to the aforementioned activation steps, an activating dopant may be introduced into the conductive material when forming the electrode layer of the capacitor. For example, when the electrode layer comprises nickel and the activating dopant comprises palladium, a palladium dopant may be introduced into the nickel ink or composition forming the electrode layer. Doing so may eliminate the palladium activation step. It should also be appreciated that some of the activation methods described above (e.g., organometallic precursors) also facilitate co-deposition of glass formers to increase adhesion to the general ceramic body of the capacitor. When an activation step is taken as described above, trace amounts of activator material may often remain at the exposed conductive portion before and after termination plating.

[0119] In addition, post-treatment steps after plating can also be used. These steps can be performed for a variety of purposes (including enhancing and / or improving the adhesion of the material). For example, a heating (or annealing) step can be used after performing the plating step. This heating can be performed by baking, laser irradiation, ultraviolet exposure, microwave exposure, arc welding, etc.

[0120] As indicated herein, the external terminal may include at least one plating layer. In one embodiment, the external terminal may include only one plating layer. However, it should be understood that the external terminal may include multiple plating layers. For example, the external terminal may include a first plating layer and a second plating layer. In addition, the external terminal may also include a third plating layer. The materials of these plating layers may be any of the materials previously described and known in the art.

[0121] For example, a plating layer (e.g., a first plating layer) may include copper or its alloy. Another plating layer (e.g., a second plating layer) may include nickel or its alloy. Another plating layer (e.g., a third plating layer) may include tin, lead, gold, or a combination (e.g., an alloy). Alternatively, the initial plating layer may include nickel, followed by a plating layer of tin or gold. In another embodiment, an initial plating layer of copper may be formed, followed by a nickel layer.

[0122] In one embodiment, the initial plating layer or the first plating layer may be a conductive metal (e.g., copper). Then, the area may be covered with a second layer containing a resistive polymeric material for sealing. Then, the area may be polished to selectively remove the resistive polymeric material, and then a third layer containing a conductive metal material (e.g., copper) may be plated again.

[0123] The aforementioned second layer above the initial plating layer may correspond to a solder mask layer, such as a nickel solder mask layer. In some embodiments, the aforementioned layer may be formed by electroplating an additional metal (e.g., nickel) layer on top of an initially electrolessly or electrolytically plated layer (e.g., plated copper). Other exemplary layer materials for the aforementioned solder mask layer include nickel-phosphorus, gold, and silver. In some embodiments, the third layer on the aforementioned solder mask layer may correspond to a conductive layer, such as plated nickel (Ni), nickel / chromium (Ni / Cr), silver (Ag), palladium (Pd), tin (Sn), lead / tin (Pb / Sn), or other suitable plated solders.

[0124] In addition, a layer of metal plating may be formed, and then an electroplating step may be performed to provide a resistive alloy or a metal alloy coating with a higher resistance on such metal plating, such as electroless Ni-P alloy. However, it should be understood that any metal coating may be included, as would be understood by one of ordinary skill in the art from the entire disclosure herein.

[0125] It should be recognized that any of the foregoing steps may be performed as a batch processing technique, such as barrel plating, fluidized bed plating, and / or a flow-through plating termination process, all of which are well known in the art. Such batch processing techniques are capable of processing multiple components at one time, thereby providing an efficient and fast termination process. This is a particular advantage over traditional termination methods (e.g., printing of thick film terminals that require individual component processing).

[0126] As described herein, the formation of the external terminals or the external terminals are generally guided by the position of the edges of the internal electrode layer that are exposed. Since the formation of the external plated terminals is determined by the configuration of the exposed conductive metal of the electrode layer at selected peripheral locations on the capacitor, this phenomenon can be referred to as "self-determination". In some embodiments, the capacitor may include "dummy tabs" that are used to provide exposed conductive metal along multiple portions of the body of the capacitor that do not include other electrodes (e.g., active electrodes or shielding electrodes). In some embodiments, for example, one or more "dummy tabs", "dummy electrodes", anchor tabs, and / or anchor electrodes may be added as features for, e.g., nucleation functions that occur during fine copper termination (FCT, electroless plating) processes. During the FCT process, such dummy tabs or electrodes, or anchor tabs or electrodes, may be positioned internally or externally relative to the component body to nucleate the metallization plating material to form the external plated terminals. For example, a first plurality of dummy tabs may be connected to a first external terminal and a second plurality of dummy tabs may be connected to a second external terminal. Generally, the second electrodes 108 of the internal electrode layers 102, 104 may be dummy tabs or electrodes, or anchor tabs or electrodes that assist in forming the first external terminal 12 and the second external terminal 14.

[0127] The second electrode (i.e., the dummy tab or electrode, or anchor tab or electrode) may have any configuration known in the art. For example, in some embodiments, as shown, the second electrode may have a rectangular configuration or shape, while in other embodiments, the second electrode may have a C-shaped configuration or an L-shaped configuration. For example, the second electrode may have a base portion and at least one electrode arm (e.g., two electrode arms) extending from the base portion (particularly from a lateral end of the base portion). Such electrode arms may extend away from one end of the capacitor body in a longitudinal direction. The electrode arms of the second electrode may also be longitudinally aligned. However, it should be recognized that the second electrode may have any shape known in the art.

[0128] Additional aspects of the above-described techniques for forming thin film plated terminals are described in U.S. Patent Nos. 7,177,137 to Ritter et al. and 7,463,474 to Ritter et al., which are incorporated herein by reference for all purposes. It should be recognized that additional techniques for forming capacitor terminals may also be within the scope of the present technology. Exemplary alternatives include, but are not limited to, forming the terminals by: plating; magnetic; masking; electrophoresis / electrostatic; sputtering; vacuum deposition; printing; or other techniques for forming thick film conductive layers or thin film conductive layers.

[0129] Returning to the reference drawings, particularly Figure 1A and Figure 1B, in some embodiments, the first lateral edge 122 of the first external terminal 12 may be offset and deviate from the end surface 18c in the longitudinal direction 132. The second lateral edge 124 of the second external terminal 14 may be offset and deviate from the end surface 18d in the longitudinal direction. Refer to Figure 1B , the second lateral edge 124 may be offset from the first lateral edge 122 by an external terminal gap distance 39 in the longitudinal direction 132. In this regard, the external terminal gap distance 39 may be formed in the longitudinal direction 132.

[0130] The external terminal gap distance 39 may be about 100 μm or greater, such as about 150 μm or greater, such as about 200 μm or greater, such as about 300 μm or greater, such as about 400 μm or greater, such as about 500 μm or greater, such as about 600 μm or greater. The external terminal gap distance 39 may be about 1000 μm or less, such as about 900 μm or less, such as about 800 μm or less, such as about 700 μm or less, such as about 600 μm or less.

[0131] Refer to Figure 1A and Figure 1B , in some embodiments, the multilayer capacitor 10 may have a capacitor length 13 in the longitudinal direction 132 between the two ends of the capacitor (i.e., including the external terminals at ends 18c, 18d). The capacitor length 13 may be about 600 μm or greater, such as about 700 μm or greater, such as about 800 μm or greater, such as about 900 μm or greater, such as about 1000 μm or greater, such as about 1200 μm or greater, such as about 1400 μm or greater. The capacitor length 13 may be about 3000 μm or less, such as about 2500 μm or less, such as about 2200 μm or less, such as about 1800 μm or less, such as about 1600 μm or less, such as about 1500 μm or less, such as about 1400 μm or less, such as about 1300 μm or less, such as about 1200 μm or less, such as about 1100 μm or less. Thus, in one embodiment, the ratio of the external terminal gap distance 39 to the capacitor length 13 may be 0.1 or greater, such as 0.2 or greater, such as 0.3 or greater, such as 0.4 or greater, such as 0.5 or greater, such as 0.6 or greater, such as 0.7 or greater. The ratio may be 0.9 or less, such as 0.8 or less, such as 0.7 or less, such as 0.6 or less, such as 0.5 or less.

[0132] Similarly, in some embodiments, the body 16 of the capacitor 10 may have a body length 15 between the end surfaces 18c, 18d of the capacitor body 16 in the longitudinal direction 132. The body length 15 may be about 600 μm or greater, such as about 700 μm or greater, such as about 800 μm or greater, such as about 900 μm or greater, such as about 1000 μm or greater, such as about 1200 μm or greater, such as about 1400 μm or greater. The body length 15 may be about 3000 μm or less, such as about 2500 μm or less, such as about 2200 μm or less, such as about 1800 μm or less, such as about 1600 μm or less, such as about 1500 μm or less, such as about 1400 μm or less, such as about 1300 μm or less, such as about 1200 μm or less, such as about 1100 μm or less. Thus, in one embodiment, the ratio of the external terminal gap distance 39 to the body length 15 may be 0.1 or greater, such as 0.2 or greater, such as 0.3 or greater, such as 0.4 or greater, such as 0.5 or greater, such as 0.6 or greater, such as 0.7 or greater. The ratio may be 0.9 or less, such as 0.8 or less, such as 0.7 or less, such as 0.6 or less, such as 0.5 or less.

[0133] In one embodiment, the capacitor 10 or a portion thereof may be symmetric about a longitudinal centerline extending in the longitudinal direction 132. In another embodiment, the capacitor 10 or a portion thereof may be symmetric about a transverse centerline extending in the transverse direction 134. In yet another embodiment, the capacitor 10 or a portion thereof may be symmetric about a Z - direction centerline extending in the Z - direction 136.

[0134] As Figure 1A and Figure 1B shown, the capacitor 10 includes two external terminals formed on the top and bottom surfaces. However, as described above, the present invention is not limited to the number of external terminals.

[0135] For example, Figure 2A illustrates a capacitor 20 that includes four external terminals on each of the top and bottom surfaces. In Figures 2A to 2C the same reference numerals as Figures 1A to 1G are used to denote the same or similar features.

[0136] As Figure 2AAs shown, the capacitor 20 has a 1 by 4 configuration. That is, the capacitor 20 includes two external terminals that are arranged linearly in one dimension on the top and bottom surfaces of the capacitor. In the depicted embodiment, the capacitor 20 includes external terminals that are arranged linearly or in a single row along the longitudinal direction L, which may be referred to as a linear terminal arrangement. In this regard, the capacitor 20 includes a body 26 that has a total of four external terminals 22a, 22b, 24a, 24b on the top surface 28a and corresponding four external terminals (not shown) on the bottom surface 28b, where the external terminals 22a, 22b, 24a, 24b on the top surface 28a are electrically connected to the corresponding external terminals 22a, 22b, 24a, 24b on the bottom surface 28b. Additionally, in the depicted embodiment, the external terminals 22a, 22b, 24a, 24b are separated from the side surfaces 28e, 28f of the capacitor body 26 such that only dielectric material is provided between the external terminals 22a, 22b, 24a, 24b and the side surfaces 28e, 28f.

[0137] Furthermore, the external terminals 22a, 24a extend from the top surface 28a along the respective end surfaces 28c, 28d of the body 26 to the bottom surface 28b. For example, the external terminal 22a extends from the top surface 28a around the end surface 28c to the bottom surface 28b, and the external terminal 24a extends from the top surface 28a around the end surface 28d to the bottom surface 28b. The external terminals 22a, 24a may be referred to as end external terminals.

[0138] The first external terminal 22a and the third external terminal 22b may be connected (e.g., electrically connected) to the first electrode 206 of the first electrode layer 202 and the second (opposing) electrode 208 of the second electrode layer 204. The second external terminal 24a and the fourth external terminal 24b may be connected (e.g., electrically connected) to the first electrode 206 of the second electrode layer 204 and the second (opposing) electrode 208 of the first electrode layer 202.

[0139] For example, the first external terminal 22a can be electrically connected to the first electrode layer 202 along at least one of the first front edge 214a or the second front edge 214b of the first base portion 214-1 of the first electrode 206 of the first electrode layer 202. The second external terminal 24a can be electrically connected to the second electrode layer 204 along at least one of the first front edge 214a or the second front edge 214b of the first base portion 214-1 of the first electrode 206 of the second electrode layer 204. The third external terminal 22b can be electrically connected to the first electrode layer 202 along at least one of the third front edge 214c or the fourth front edge 214d of the second base portion 214-2 of the first electrode 206 of the first electrode layer 202. The fourth external terminal 24b can be electrically connected to the second electrode layer 204 along at least one of the third front edge 214c or the fourth front edge 214d of the second base portion 214-2 of the first electrode 206 of the second electrode layer 204. The front edges 214a, 214b, 214c, 214d can help form the external terminals 22a, 22b, 24a, 24b further described herein.

[0140] In addition, Figure 2A the capacitor 20 in [[]] includes at least one first polar terminal and at least one second opposite polar terminal on the top surface. Although not shown, the bottom surface includes at least the first polar terminal and the second opposite terminal. Specifically, as Figure 2A shown, the capacitor 20 includes two positive terminals 22a, 22b and two negative terminals 24a, 24b on the top surface 28a.

[0141] The body 26 of the capacitor 20 has a length 25 extending in the longitudinal direction 232, which can be measured from one end surface 28c to the opposite end surface 28d. In addition, the body 26 of the capacitor 20 has a width 127 extending in the transverse direction 234, which can be measured from one side surface 28e to the opposite side surface 28e. In addition, the body 26 of the capacitor 20 has a height 29 extending in the Z direction 236, which can be measured from the top surface 28a to the opposite bottom surface 28b.

[0142] As Figure 2AAs shown, the external terminals 22a, 22b, 24a, and 24b each have a terminal width BW that extends in the lateral direction 234. The external terminals 22a and 24a also have a terminal length BLA along the top surface 18a, and the terminal length BLA extends in the longitudinal direction 232. Similarly, the external terminals 22b and 24b have a terminal length BLB along the top surface 18a that extends in the longitudinal direction 232. It should be appreciated that one or both of the terminals 22a, 24a or one or both of the terminals 22b, 24b may each have a terminal length BlA or BLB along the bottom surface 18b, and the terminal length BlA or BLB may be the same as or different from the corresponding terminal lengths BLA, BLB along the top surface 18a.

[0143] Although not shown herein, it will be appreciated that the capacitor 20 may be mounted to a mounting surface, such as a printed circuit board or a substrate, such as Figure 1B the mounting surface 11 shown in. In this regard, the multilayer capacitor may be configured for mounting to a mounting surface such that the electrode layers are perpendicular to the mounting surface.

[0144] As shown, the multilayer capacitor 20 may be configured to be generally similar to the multilayer capacitor 10 described with reference to Figure 1A and Figure 1B However, as described further below, the multilayer capacitor 20 has a first electrode layer 202 and a second electrode layer 204, and the first electrode layer 202 and the second electrode layer 204 have a plurality of base portions 214, a plurality of connection portions 216, and a plurality of central portions 212.

[0145] The multilayer capacitor 20 may include a plurality of electrode layers 202, 204 and dielectric layers stacked in the lateral direction 234. Some of the dielectric layers may include electrode layers formed thereon. Generally, the thicknesses of the dielectric layers and the electrode layers are not limited and may be any desired thickness depending on the performance characteristics of the capacitor.

[0146] Figure 2B A side view showing an embodiment of an electrode structure according to aspects of the present disclosure is shown, Figure 2C A side view showing an embodiment of an electrode structure according to aspects of the present disclosure is shown. Figure 2B The electrode structure of may be described as being generally a Y-shaped electrode structure, including a plurality of Y-shapes (similar to Figures 1C to 1F the embodiment of ). Figure 2C The electrode structure of may be described as being generally a multi-tab rounded-edge structure (similar to Figure 1G the embodiment of ). Figure 2B and Figure 2C Each of the electrode structures shown in and has at least a portion of at least one side that is not perpendicular to the side with which it intersects.

[0147] Specifically referring to Figure 2B , each of the electrode layers 202, 204 may include a first electrode 206. Although not shown, it will be appreciated that in some embodiments, the electrode layers 202, 204 may further include a second electrode 208, such as Figure 2C shown, and similar to Figures 1C to 1E the embodiment of. The first electrode 206 may have a first base portion 214-1 and a second base portion 214-2. For example, each of the first base portion 214-1 and the second base portion 214-2 of the first electrode 206 may extend in the longitudinal direction 232 and have vertical edges 221a, 221b extending in the Z direction 236, respectively. The first base portion 214-1 may further include a first front edge 214a and a second front edge 214b opposite to the first front edge 214a in the Z direction 236. The first front edge 214a and the second front edge 214b each extend in the longitudinal direction 232 and intersect with the first vertical edge 221a, such that the edges 214a, 214b, 221a define the boundary of the first electrode 206 in the first base portion 214-1. Similarly, the second base portion 214-2 may further include a third front edge 214c and a fourth front edge 214d opposite to the third front edge 214c in the Z direction 236. The third front edge 214c and the fourth front edge 214c each extend in the longitudinal direction 232 and intersect with the second vertical edge 221b, such that the edges 214c, 214d, 221b define the boundary of the first electrode 206 in the second base portion 214-2.

[0148] The first electrode 206 may also have a first central portion 212-1 and a second central portion 212-2. The first central portion 212-1 may extend in the longitudinal direction 232 to the second vertical edge 221b of the second substrate portion 214-2. The second central portion 212-2 may extend in the longitudinal direction 232 and have a vertical edge 223 extending in the Z direction 236. The vertical edge 223 of the second central portion 212-2 is opposite to the first vertical edge 221a of the first substrate portion 214-1, such that the vertical edges 221a, 223 define the longitudinal boundaries of the first electrode 206. In addition, the first central portion 212-1 may include a first edge 212a and a second edge 212b opposite to the first edge 212a in the Z direction 236. The first edge 212a and the second edge 212b each extend in the longitudinal direction 232 and intersect with the second vertical edge 221b of the second substrate portion 214-2, such that the edges 212a, 212b, 221b define the boundaries of the first electrode 106 in the first central portion 212-1. The second central portion 212-2 may include a third edge 212c and a fourth edge 212d opposite to the third edge 212c in the Z direction 236. The third edge 212c and the fourth edge 212d each extend in the longitudinal direction 232 and intersect with the vertical edge 223 of the second central portion 212-2, such that the edges 212c, 212d, 223 define the boundaries of the first electrode 106 in the second central portion 212-2.

[0149] Each central portion 212-1, 212-2 of the first electrode 206 may have a first width 227 extending, for example, in the Z direction 236. In addition, each substrate portion 214-1, 21402 of the first electrode 206 may have a second width 229 extending, for example, in the Z direction 236. In this regard, the position of the first width 227 may be offset from the position of the second width 229 in the longitudinal direction 232, such that the position of the second width 229 is closer to the external terminal to which the first electrode 206 is electrically connected. This configuration may allow adjustment of the overlapping region between the central portions 212 of adjacent electrodes in the transverse direction 234. In addition, in at least some embodiments, the second width 229 of each substrate portion 214-1, 214-2 may be greater than the first width 227 of each central portion 212-1, 212-2.

[0150] Generally, the internal electrode layers 202, 204 include at least one lead tab 2002a, 2004a extending along the Z direction 236 from the top and bottom edges of the first central portion 212-1 and at least one lead tab 2002b, 2004b extending along the Z direction 236 from the top and bottom edges of the second central portion 212-2. Generally, the lead tabs 2002a, 2004a, 2002b, 2004b of the electrode layers 202, 204 extend to the top and bottom surfaces of the capacitor and help form the external terminals 22a, 22b, 24a, 22b. In this regard, the lead tabs 2002a, 2004a, 2002b, 2004b may be exposed on the top surface 28a and the bottom surface 28b of the capacitor and allow connection between the central portions 212-1, 212-2 of the internal electrode layer and the external terminals 22a-b, 24a-b. For example, the lead tabs 2002a, 2004a of the electrode layers 202, 204 may be defined by the first substrate portion 214-1 and include a first front edge 214a and a second front edge 214b extending to the edge of the dielectric layer and allow the formation of the external terminals 22a, 24a on the top surface 28a and the bottom surface 28b. The lead tabs 2002b, 2004b of the electrode layers 202, 204 may be defined by the second substrate portion 214-2 and include a third front edge 214c and a fourth front edge 214d extending to the edge of the dielectric layer and allow the formation of the external terminals 22b, 24b on the top surface 28a and the bottom surface 28b.

[0151] The lead tabs 2002a, 2004a, 2002b, 2004b can generally be configured as described for the lead tabs 1002, 1004 of the capacitor 10 above. For example, the lengths of the lead tabs 2002a, 2004a, 2002b, 2004b can vary as needed, but are typically from about 0.3 mm to about 1.2 mm, in some embodiments from about 0.4 mm to about 1.1 mm, and in some embodiments from about 0.5 mm to about 1 mm. When there are more than one lead tab along an edge, each lead tab can have the same length. In another embodiment, each lead tab can have a different length. For example, a lead tab that is generally aligned with a side edge of the internal electrode layer can have a greater length than a lead tab that is offset from the side edge of the internal electrode layer. In this regard, the ratio of the length of a lead tab aligned with a side edge of the internal electrode layer to the length of a lead tab offset from the side edge of the internal electrode layer can be from about 0.3 to about 5, in some embodiments from about 0.5 to about 4, and in some embodiments from about 0.7 to about 3. Generally aligned typically means that the offset of a lateral edge of the first lead tab and / or the second lead tab on the top edge relative to the side edge is within + / - 10% of the offset of the corresponding lateral edge of the first lead tab and / or the second lead tab on the bottom edge relative to the side edge, such as within + / - 5%, such as within + / - 4%, such as within + / - 3%, such as within + / - 2%, such as within + / - 1%, such as within + / - 0.5%.

[0152] The lead tabs 2002a, 2004a, 2002b, 2004b on the top and bottom edges of the internal electrode layers 202, 204 can be aligned in the vertical direction. For example, as Figure 2B shown, a lateral edge (extending in the Z direction 136) of the first lead tab 2002a can be aligned with a lateral edge (extending in the Z direction 136) of the second lead tab 2004a that is opposite the first lead tab 2002a. Additionally, such lateral edges of the lead tabs 2002a, 2004a can be aligned with the side edge 221a of the internal electrode layer 202. However, it should be understood that the lateral edges of the lead tabs 2002a, 2004a can be aligned with each other but offset from the side edge 221a. The third lead tab 2002b and the fourth lead tab 2004b can be aligned with each other as described for the first lead tab 2002a and the second lead tab 2004a.

[0153] Regarding the relationship between the lateral edges of the first lead tabs on the top edge and the lateral edges of the second lead tabs on the bottom edge as mentioned for the internal electrode layer 202, the same can also apply to the internal electrode layer 204. With this arrangement, a gap can be formed between the first lead tab 2002a of the first internal electrode layer 202 and the third lead tab 2002b of the second internal electrode layer 204. In addition, a gap can be formed between the third lead tab 2002b of the first internal electrode layer 202 and the third lead tab 2002b of the second internal electrode layer 204, and another gap can be formed between the third lead tab 2002b of the first internal electrode layer 202 and the first lead tab 2002a of the second internal electrode layer 204. Similarly, a first gap can be formed between the second lead tab 2004a of the first internal electrode layer 202 and the fourth lead tab 2004b of the second internal electrode layer 204, a second gap can be formed between the fourth lead tab of the first internal electrode layer 202 and the fourth lead tab 2004b of the second internal electrode layer 204, and a third gap can be formed between the fourth lead tab 2004b of the first internal electrode layer 202 and the second lead tab 2004a of the second internal electrode layer 204. The size of each corresponding gap can be substantially the same, or the size of at least one gap can be different from another gap. For example, the size of the gap between the first lead tab 2002a of the first internal electrode layer 202 and the third lead tab 2002b of the second internal electrode layer 204 can be different from the size of the gap between the third lead tab 2004a of the first internal electrode layer 202 and the third lead tab 2004a of the second internal electrode layer 204.

[0154] For a given electrode layer 202, 204, the lead tab 2002a can be arranged in parallel with the lead tab 2004a, and the lead tab 2002b can be arranged in parallel with the lead tab 2004b, such that the lead tabs extending from the alternating electrode layers 202 and 204 can be aligned in the corresponding columns. For example, the lead tabs 2002a, 2004a of the internal electrode layer 202 can be arranged in a corresponding stacked configuration, while the lead tabs 2002a, 2004a of the internal electrode layer 204 can be arranged in a corresponding stacked configuration. Similarly, the lead tabs 2002b, 2004b of the internal electrode layer 202 can be arranged in a corresponding stacked configuration, while the lead tabs 2002b, 2004b of the internal electrode layer 204 can be arranged in a corresponding stacked configuration. Thus, for Figure 2B the embodiment depicted in, the stacked electrode layers 202, 204 can form corresponding four columns of lead tabs.

[0155] It will be appreciated that the lead tabs 2002a, 2004a of the electrode layer 202 are connected to the external terminals 22a, while the lead tabs 2002a, 2004a of the electrode layer 204 are connected to the external terminals 24a. In addition, the lead tabs 2002b, 2004b of the electrode layer 202 are connected to the external terminals 22b, while the lead tabs 2002b, 2004b of the electrode layer 204 are connected to the external terminals 24b. Thus, the corresponding lead tabs 2002a, 2004a, 2002b, 2004b of the electrode layer 202 will be staggered with the corresponding lead tabs 2002a, 2004a, 2002b, 2004b of the electrode layer 204 in a manner similar to the external terminals 22a, 22b, 24a, 24b. The staggered lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0156] The distance between each adjacent exposed lead tab of the internal electrode layer in a given column can be specifically designed to help ensure the guiding and shaping of each terminal. The range of the distance between the exposed lead tabs of the internal electrode layer in a given column can be, for example, from about 0.25 μm to about 10 μm, in some embodiments from about 0.5 μm to about 5 μm, and in some embodiments from about 1 μm to about 4 μm. Additionally, the distance between adjacent columnar stacks of each electrode tab can (but is not limited to) be at least twice as large as the distance between adjacent lead tabs in a given column to ensure that different terminals do not operate together. In some embodiments, the distance between each adjacent columnar stack of the exposed metallization can be about four times (4x) the distance between each adjacent exposed electrode tab in a particular stack. However, this distance can vary according to the desired capacitance performance and circuit board construction. For example, as determined based on the central point of each lead tab or based on the distance between adjacent lateral edges of the lead tab, this distance can be from about 0.1 mm to about 1.5 mm, in some embodiments from about 0.2 mm to about 1.3 mm, and in some embodiments from about 0.3 mm to about 1 mm. Additionally, such a distance can correspond to the spacing distance of the balls on a ball grid array.

[0157] Still referring to Figure 2B, the first electrode 206 may have a first connection portion 216-1 and a second connection portion 216-2. The first connection portion 216-1 may extend from the first base portion 214-1 in the longitudinal direction 232. Specifically, the first connection portion 216-1 may extend between the first base portion 214-1 and the first central portion 212-1 and connect the first base portion 214-1 and the first central portion 212-1. Similarly, the second connection portion 216-2 may extend from the second base portion 214-2 in the longitudinal direction 232. Specifically, the second connection portion 216-2 may extend between the second base portion 214-2 and the second central portion 212-2 and connect the second base portion 214-2 and the second central portion 212-2.

[0158] As Figure 2B shown in the embodiment of, the first connection edge 216a of the first connection portion 216-1 extends from the first front edge 214a of the first base portion 214-1 to the first edge 212a of the first central portion 212-1, and the second connection edge 216b of the first connection portion 216-1 extends from the second front edge 214b of the first base portion 214-1 to the second edge 212b of the first central portion 212-1. Thus, the first connection edge 216a intersects the first front edge 214a and the first edge 212a to connect the first base portion 214-1 to the first central portion 212-1 along one longitudinal side of the first electrode 206. The second connection edge 216b intersects the second front edge 214b and the second edge 212b to connect the first base portion 214-1 to the first central portion 212-1 along the other opposite longitudinal side of the first electrode 206.

[0159] In addition, the third connection edge 216c of the second connection portion 216-2 extends from the third front edge 214c of the second base portion 214-2 to the third edge 212c of the second central portion 212-2, and the fourth connection edge 216b of the second connection portion 216-2 extends from the fourth front edge 214d of the second base portion 214-2 to the fourth edge 212d of the second central portion 212-2. Thus, the third connection edge 216c intersects the third front edge 214c and the third edge 212c to connect the second base portion 214-2 to the second central portion 212-2 along one longitudinal side of the first electrode 206. The fourth connection edge 216d intersects the fourth front edge 214d and the fourth edge 212d to connect the second base portion 214-2 to the second central portion 212-2 along the other opposite longitudinal side of the first electrode 206.

[0160] Each connecting portion 216-1, 216-2 may have, for example, a third width 231 extending in the Z direction 236. In this regard, the position of the third width 231 may be offset in the longitudinal direction 232 from the position of the corresponding first width 227 and the position of the corresponding second width 229. In one embodiment, the third width 231 of the corresponding connecting portions 216-1, 216-2 may be less than the second width 229 of the corresponding base portions 214-1, 214-2. Additionally, the third width 231 of the corresponding connecting portions 216-1, 216-2 may be greater than the first width 227 of the corresponding central portions 212-1, 212-2. In this regard, for each corresponding Y-shaped portion of the first electrode 206, the position of the third width 231 may be located between the position of the first width 227 and the position of the second width 229.

[0161] Moreover, the third width 231 may vary within the connecting portions 216-1, 216-2. For example, the third width 231 may have a first value at one position within the corresponding connecting portions 216-1, 216-2 and a different second value at another position within the corresponding connecting portions 216-1, 216-2, where the two positions within the corresponding connecting portions 216-1, 216-2 are spaced apart from each other in the longitudinal direction 232.

[0162] At least a portion of at least one of the first connecting edge 216a, the second connecting edge 216b, the third connecting edge 216c, or the fourth connecting edge 216d is not perpendicular to the corresponding edge 212a, 212b, 212c, 212d of the central portion that intersects the corresponding connecting edge 216a, 216b, 216c, 216d. For example, in one embodiment, the first connecting edge 216a of the first connecting portion 216-1 may form a first angle 241 with the first edge 212a of the first central portion 212-1. Similarly, the third edge 212c of the second central portion 212-2 may form a first angle 241 with the third connecting edge 216c of the second connecting portion 216-2. Such an angle 241 may be greater than 90° and less than 180°. For example, such an angle 241 may be within the above range of the angle 141. Without being limited by theory, such a configuration may provide a generally Y-shaped electrode configuration from the first base portion 214-1 to the first central portion 212-1 and from the second base portion 214-4 to the second central portion 212-2, such that the depicted embodiment includes multiple Y-shapes.

[0163] Moreover, in Figure 2BIn the described embodiment, a second angle 247 is formed between the second edge 212b and the second connecting edge 216b, and the second angle 247 is greater than 90° and less than 180°, as described above with respect to the first angle 241. A second angle 247 is also formed between the fourth edge 212d and the fourth connecting edge 216d, and the second angle 247 is greater than 90° and less than 180°, as described above with respect to the first angle 241. Thus, it will be appreciated that Figure 2B the second Y-shape of the first electrode 206 shown in is configured to be similar to the first Y-shape of the first electrode 206. For example, the first base portion 214-1, the first connecting portion 216-1, and the first central portion 212-1 of the first electrode 206 define the first Y-shape, and the second base portion 214-2, the second connecting portion 216-2, and the second central portion 212-2 of the first electrode 206 define the second Y-shape. The first Y-shape and the second Y-shape of the first electrode may be generally similar to each other, or these Y-shapes may be different from each other. For example, the first angle 241 of one Y-shape of the first electrode 206 may have a value different from that of the first angle 241 of the other Y-shape of the first electrode 206.

[0164] In addition, for Figure 2B the first electrode 206 shown in, at least a portion of the first connecting edge 216a is not perpendicular to the first edge 212a, and at least a portion of the second connecting edge 216b is not perpendicular to the second edge 212b. In addition, at least a portion of the third connecting edge 216c is not perpendicular to the third edge 212c, and at least a portion of the fourth connecting edge 216d is not perpendicular to the fourth edge 212d. It will also be appreciated that for the depicted embodiment, at least a portion of the first connecting edge 216a is not perpendicular to the first front edge 214a, at least a portion of the second connecting edge 216b is not perpendicular to the second front edge 214b, at least a portion of the third connecting edge 216c is not perpendicular to the third front edge 214c, and at least a portion of the fourth connecting edge 216d is not perpendicular to the fourth front edge 214d.

[0165] Figure 2C Electrode layers 202, 204 are shown in accordance with aspects of the present disclosure, wherein at least one of the first electrode 206 or the second electrode 208 has at least one edge that is not perpendicular to at least a portion of an intersecting edge. For example, at least one of the first electrode 206 or the second electrode 208 includes a rounded corner, and the circular edge of the rounded corner is not perpendicular to the intersecting edge. As referenced Figure 1G as described, "circular" may refer to an outer edge having an arc or elliptical arc shape, or may refer to any suitable edge that is not precisely circular or elliptical but is otherwise curved or arcuate. In addition, in some embodiments, the outer edge of the first electrode 206 and / or the second electrode 208 may not be geometrically discontinuous. For example, as referenced aboveFigure 1G as described in the embodiments. The rounded corner configuration can reduce the electric field and charge concentration in the corner and / or along the edges of the electrodes 206, 208 adjacent to the corner, which can increase the breakdown voltage of the capacitor incorporating the electrode layers 202, 204 compared to conventional electrode configurations.

[0166] The electrode layers 202, 204 can be configured to be similar to the electrode layers 202, 204 described in the reference Figure 2B but have curved or rounded connection edges 216a, 216b, 216c, 216d of the corresponding connection portions 216-1, 216-2 instead of the linear connection edges 216a, 216b, 216c, 216d as shown in Figure 2B For example, as shown in Figure 2C the first connection edge 216a defines a first rounded corner having a first radius r 1 the second connection edge 216b defines a second rounded corner having a second radius r 2 the third connection edge 216c defines a third rounded corner having a third radius r 3 the fourth connection edge 216d defines a fourth rounded corner having a fourth radius r 4 Accordingly, at least a portion of the connection edges 216a, 216b, 216c, 216d is not perpendicular to the corresponding edges 212a, 212b, 212c, 212d that intersect the corresponding connection edges.

[0167] In addition, in the embodiments of Figure 2C the first electrode 206 defines additional rounded corners and the second electrode 208 also includes rounded corners. For example, the first electrode 206 defines a fifth rounded corner and a sixth rounded corner between the first central portion 212-1 and the second substrate portion 214-2, the rounded corners having radii r 5 and r 6 respectively. The second electrode 208 defines a seventh rounded corner having a radius r 7 and an eighth rounded corner having a radius r 8 where the seventh rounded corner and the eighth rounded corner are defined at the intersection of the edge of the second electrode 208 closest to the first electrode 206.

[0168] It will be appreciated that the radii of the respective rounded corners in the electrode layers 202, 204 can be the same or at least one radius can be different from the other radii. For example, as shown in Figure 2C the seventh radius r 7 and the eighth radius r 8 of the second electrode 208 can be equal to each other but not equal to the first radius r 1 the second radius r 2 the third radius r 3 the fourth radius r4 , the fifth radius r 5 and / or the sixth radius r 6 Any one of them (which may be equal to each other, but different from the seventh radius r 7 and the eighth radius r 8 ).

[0169] As Figure 2C further shown in, a central end gap distance 233 can be formed between the longitudinal ends of the second central portion 212-2 of the first electrode 206 and the longitudinal ends of the base portion 214 of the second electrode 208 in the longitudinal direction 232. Thus, in one embodiment, the ratio of the central end gap distance 233 to the capacitor length 25( Figure 2A ) can be 0.01 or greater, such as 0.05 or greater, such as 0.1 or greater, such as 0.2 or greater, such as 0.3 or greater, such as 0.4 or greater. The ratio can be, for example, 0.5 or less, such as 0.4 or less, such as 0.3 or less, such as 0.2 or less, such as 0.1 or less.

[0170] Within the scope of the present disclosure, other variations and / or combinations are possible. For example, the first electrode 206 can have a generally Y-shaped configuration and one or more curved or circular connecting edges 216a, 216b, 216c, 216d. Different numbers and / or configurations of connecting edges that are not perpendicular to the edges of the corresponding central portion can be used in the electrodes 206, 208 on the respective electrode layers 202, 204, that is, one or more of the electrode layers 202, 204 can have electrodes 206, 208 with a connecting edge configuration different from that of at least one other electrode layer 202, 204.

[0171] As Figure 2B and Figure 2C further shown, each front edge 214a, 214b, 214c, 214d of the base portions 214-1, 214-2 of the first electrode 206 can also have a certain length 235 extending in the longitudinal direction 232. Generally speaking, such a length 235 of the corresponding base portion can be defined as the distance between the vertical edges 221a, 221b and the transition points between the corresponding base portions 214-1, 214-2 and the corresponding connecting portions 216-1, 216-2. For example, the front edges 214a, 214b, 214c, 214d can generally all have a slope of 0°, and the point at which the slope changes can be considered the aforementioned transition point. In any case, such a length 235 can be the capacitor length 25 as defined herein( Figure 2A) 0.05 or greater, such as 0.1 or greater, such as 0.15 or greater, such as 0.2 or greater, such as 0.3 or greater. Such a length 235 can be 0.5 or less of the capacitor length 25, such as 0.4 or less, such as 0.3 or less, such as 0.25 or less, such as 0.2 or less, such as 0.15 or less.

[0172] Also as Figure 2C shown, the base portion 214 of the second electrode 208 can also have a certain length 245 extending in the longitudinal direction 232. Such a length can be 0.05 or greater of the capacitor length 25, such as 0.1 or greater, such as 0.15 or greater, such as 0.2 or greater, such as 0.3 or greater. Such a length 245 can be 0.5 or less of the capacitor length 25, such as 0.4 or less, such as 0.3 or less, such as 0.25 or less, such as 0.2 or less, such as 0.15 or less.

[0173] In one embodiment, the aforementioned lengths 235 and 245 can be different. In a specific embodiment, the aforementioned lengths 235 and 245 can be substantially the same. In addition, the length 235 of the first base portion 214-1 can be the same as or different from the length 235 of the second base portion 214-2.

[0174] In addition, referring to Figure 2A , the first end external terminal 22a can have a first lateral edge 222. The first lateral edge 222 can extend in the Z direction 236 and / or the transverse direction 234. The first lateral edge 222 of the first external terminal 22a can be substantially aligned with the vertical edge 230 of the first base portion 214-1 of the first electrode 206 in the longitudinal direction ( Figure 2B , Figure 2C ). Such a vertical edge 230 can be located at the position where the first base portion 214-1 ends and the first connection portion 216-1 begins. For example, the first lateral edge 222 of the first end external terminal 22a in the longitudinal direction is within 5% based on the length of the first base portion 214-1 of the first electrode 206, such as within 4% based on the length of the first base portion 214-1 of the first electrode 206, such as within 3% based on the length of the first base portion 214-1 of the first electrode 206, such as within 2% based on the length of the first base portion 214-1 of the first electrode 206, such as within 1% based on the length of the first base portion 214-1 of the first electrode 206, such as within 0.8% based on the length of the first base portion 214-1 of the first electrode 206, such as within 0.6% based on the length of the first base portion 214-1 of the first electrode 206, such as within 0.5% based on the length of the first base portion 214-1 of the first electrode 206, such as within 0.4% based on the length of the first base portion 214-1 of the first electrode 206, such as within 0.3% based on the length of the first base portion 214-1 of the first electrode 206, such as within 0.2% based on the length of the first base portion 214-1 of the first electrode 206, such as within 0.1% based on the length of the first base portion 214-1 of the first electrode 206.

[0175] Similarly, the second end external terminal 24a can have a second lateral edge 224 ( Figure 2A)。The second lateral edge 224 can extend in the Z direction 236 and / or the lateral direction 234. The second lateral edge 224 of the second external terminal 24a can be substantially aligned with the vertical edge 230 of the first base portion 214-1 of the first electrode 206 in the longitudinal direction. Such a lateral edge 224 can be located at the position where the first base portion 214-1 ends and the first connection portion 216-1 begins. For example, the second lateral edge 224 of the second end external terminal 24a can be within 5%, such as within 4%, such as within 3%, such as within 2%, such as within 1%, such as within 0.8%, such as within 0.6%, such as within 0.5%, such as within 0.4%, such as within 0.3%, such as within 0.2%, such as within 0.1% of the vertical edge 230 of the first base portion 214-1 of the first electrode 206 in the longitudinal direction based on the length of the first base portion 214-1 of the first electrode 206.

[0176] It will be appreciated that the first lateral edge 222 of the first end external terminal 22a can be aligned with the vertical edge 230 of the first electrode 206 of the electrode layer 202 or the electrode layer 204, while the second lateral edge 224 of the second end external terminal 24a can be aligned with the vertical edge 230 of the first electrode 206 of the other one of the electrode layer 202 or the electrode layer 204.

[0177] In addition, the first lateral edge 222 of the first end external terminal 22a can be substantially aligned with the lateral edge 226 ( Figure 2C ) of the base portion 214 of the second electrode 208 of the electrode layer 202, while the second lateral edge 224 of the second end external terminal 24a can be substantially aligned with the lateral edge (not shown) of the base portion 214 of the second electrode 208 of the electrode layer 204. For example, each of the lateral edges 222, 224 of the corresponding end external terminals 22a, 24a can be within 5%, such as within 4%, such as within 3%, such as within 2%, such as within 1%, such as within 0.8%, such as within 0.6%, such as within 0.5%, such as within 0.4%, such as within 0.3%, such as within 0.2%, such as within 0.1% of the corresponding lateral edge of the base portion 214 of the second electrode 208 in the longitudinal direction based on the length 245 of the base portion 214 of the second electrode 208.

[0178] As indicated herein, the dielectric layer and electrode layer stacks of capacitor 20 can be arranged to form a set of alternating layers. For example, the electrode layers can be staggered in a relative and spaced-apart relationship, with a dielectric layer between each electrode layer, and any number of dielectric layers and electrode layers as described herein can be included in the respective stack. Additionally, as described elsewhere herein, one, two, three, four, or more sets of stacked, alternating dielectric layers and electrode layers can be disposed within a single capacitor body. Capacitor 20 includes a single set of dielectric layers and electrode layers that form the body 26 of capacitor 20, but the capacitor body can include additional sets of stacked layers, such as, for example, as referenced Figures 3A to 5B as described.

[0179] Now referring Figure 3A to FIGS. 6 and 7, for embodiments including multiple stacks of alternating dielectric layers and electrode layers disposed within a single capacitor body, each set of alternating dielectric layers and internal electrode layers defines a capacitive element. Each set of alternating dielectric layers and electrode layers includes dielectric layers alternating with electrode layers. Specifically, each electrode layer includes a first electrode layer and a second electrode layer staggered in a relative and spaced-apart relationship, with a dielectric layer between each electrode layer. In at least some embodiments, the first electrode layer and the second electrode layer can be configured as described above with respect to the first electrode layer 102 and the second electrode layer 104 of capacitor 10 and / or the first electrode layer 202 and the second electrode layer 204 of capacitor 20. For example, each capacitive element within a single capacitor body can include a stack of the first electrode layer 102 and the second electrode layer 104, or the first electrode layer 202 and the second electrode layer 204.

[0180] The particular arrangement of the capacitive elements within a single, one-piece package (i.e., a single body) can provide several advantages. For example, such a capacitor can be mounted as a surface-mount capacitor onto a circuit board and can provide a smaller footprint on the circuit board. This, in turn, can also allow for a reduction in the size of the circuit board.

[0181] One distinct advantage of a capacitor and configuration that uses multiple capacitive elements within a single body compared to using multiple separate multilayer ceramic capacitors is with respect to direct power-to-ground connections. As Figure 6 shown, such a capacitor 608 (having multiple capacitive elements within a single body) can be mounted (e.g., surface-mounted) onto a circuit board 606 that includes a substrate (e.g., an insulating layer) having an upper surface and a lower surface. The circuit board 606 has multiple current paths (not shown) defined therein. The external terminals of capacitor 608 are in electrical communication with predetermined current paths of the circuit board 606, respectively. Additionally, any method known in the art (e.g., general soldering techniques) can be used to physically connect the external terminals of capacitor 608 to the circuit board 606.

[0182] AsFigure 6 As shown, an integrated circuit package 602 can also be provided on the circuit board 606. A ball grid array 604 can be used to connect the integrated circuit package 602 to the circuit board 606. The circuit board can also include a processor 600. A ball grid array 612 can also be used to connect the processor 600 to the integrated circuit package 602.

[0183] Generally, the ball grid array 604 can be configured such that the pitch is 1.5 mm or less (e.g., 1.25 mm or less, e.g., 1 mm or less, e.g., 0.8 mm or less, e.g., 0.6 mm or less), and 0.4 mm or greater (e.g., 0.5 mm or greater, e.g., 0.6 mm or greater).

[0184] In addition, a capacitor 608 as defined herein can also be used to connect the integrated circuit package 602 to the circuit board 606. In this regard, the internal electrode layers of the capacitor 608 can be positioned such that these internal electrode layers are orthogonal to the horizontal planes of the circuit board 606 and the integrated circuit package 602. In other words, the internal electrode layers of the capacitor 608 can be positioned such that these internal electrode layers are not substantially parallel to the circuit board 606. For example, the capacitor 608 can be positioned between the integrated circuit package 602 and the circuit board 606 such that the capacitor 608 is "sandwiched" between the two components. In this regard, the capacitor 608 is directly connected to the integrated circuit package 602 and the circuit board 606. For example, any method known in the art (e.g., general soldering techniques) can be used to connect (e.g., physically connect and / or electrically connect) the capacitor 608 to the circuit board 606 and / or the circuit package 602.

[0185] By employing a capacitor in the above arrangement, the capacitor 608 can allow for the removal of a portion of the original ball grid array 604. However, as Figure 6 shown, the capacitor 608 can still be surrounded by the ball grid array 604.

[0186] Therefore, as Figure 6 shown, the capacitor 608 of the present invention can be directly connected to the integrated circuit package 602 and the circuit board 606, such as a printed circuit board. This direct connection allows current 610 to flow through the capacitor, thereby providing a direct power ground connection.

[0187] Meanwhile, a prior art circuit board 706 is shown in FIG. 7. The circuit board 706 includes a processor 700, an integrated circuit package 702, and ball grid arrays 704 and 712. However, the circuit board 706 of FIG. 7 employs a plurality of individual multi-layer ceramic capacitors 708 instead of a single one-piece capacitor package like the capacitor 608 in Figure 6 .

[0188] Compared with a circuit board that uses multiple separate multilayer ceramic capacitors, the present configuration that uses a single integrated capacitor can bring various advantages and benefits. Compared with using multiple separate multilayer ceramic capacitors, an obvious advantage of the capacitor and configuration of the present invention is regarding the direct power supply ground connection (as Figure 6 shown), where the capacitor of the present invention is directly connected to the integrated circuit package 602 and the circuit board 606. When providing multiple separate capacitors in the prior art as shown in FIG. 7, due to various reasons (including slight differences in height), some multilayer capacitors 708 cannot be directly connected to the circuit board 706 and the integrated circuit package 702. Due to this consistency problem, it may be difficult to make connections using multiple separate multilayer capacitors. Therefore, as shown in FIG. 7, there are two current paths: (1) the current 714 between the processor 700 and each separate capacitor 708; and (2) the current 716 between the processor 700 and the circuit board 716. Using this configuration, a direct power supply ground connection may not be obtained.

[0189] In addition to the above, although not shown herein, in one embodiment, the integrated circuit package itself may include a multilayer capacitor. In this regard, the capacitor can be directly embedded in the package. This combination of capacitors can allow for a reduced size, which may be beneficial for various electronic applications.

[0190] Now referring to Figures 3A to 5B , various embodiments of a capacitor having multiple capacitive elements will be described. Figure 3A and Figure 3B both show a 2-by-2 configuration capacitor 30. That is, the capacitor 30 includes two terminals along each dimension of the top surface 38a and the bottom surface 38b. In this regard, the capacitor 30 includes a total of four external terminals 32, 34 on the top surface and four corresponding external terminals (not shown) on the bottom surface, where the external terminals on the top surface are electrically connected to the corresponding external terminals on the bottom surface. In the embodiment of Figure 3A , the external terminals 32, 34 are separated from the end surfaces 38c, 38d and the side surfaces 38e, 38f of the capacitor 38. In the embodiment of Figure 3B , the external terminals 32, 34 are separated from the side surfaces 38e, 38f of the capacitor 38 and extend along the end surfaces 38c, 38d.

[0191] Figure 3A and Figure 3B the capacitor 30 includes two sets 350 of alternating dielectric layers and internal electrode layers (as Figure 3CAs shown). Each set of 350 alternating dielectric layers and internal electrode layers includes internal electrode layers 102, 104 and dielectric layers (not shown) arranged alternately. These sets 350 of alternating dielectric layers and internal electrode layers are separated from each other by a spacing distance t. For example, a spacing distance t can be defined between a first set 350a of alternating dielectric layers and internal electrode layers and a second set 350b of alternating dielectric layers and internal electrode layers.

[0192] The spacing t between the groups can be from about 0.2 μm to about 10 μm, in some embodiments from about 0.5 μm to about 8 μm, and in some embodiments from about 1 μm to about 5 μm. Additionally, the spacing distance t can be (but is not limited to) at least 2 times greater than the distance between adjacent lead tabs in a given column, in some embodiments at least about 3 times, and in embodiments from about 4 times to about 8 times, to ensure that different terminals do not connect together.

[0193] Generally, the electrode layers 102, 104 are configured as described with reference to Figure 1F However, the electrode layers 102, 104 can also be configured as described for other embodiments of the capacitor 10. For example, in the case where the external terminals 32, 34 extend along the ends 38c, 38d (and the top surface 38a and bottom surface 38b) of the capacitor 30, the internal electrode layers 102, 104 can be similar to Figure 1C , Figure 1D or Figure 1G configured, and these internal electrode layers have a second electrode 108 to assist in forming the external terminals 32, 34 (especially along the end surfaces 38c, 38d). Additionally, it will be appreciated that for an embodiment of the capacitor 30 as shown in, for example, Figure 3A , the base portions 114 of the electrode layers 102, 104 can be separated from the end surfaces 38c, 38d of the capacitor 30. For example, a dielectric material can be provided along the front edge (extending in the Z direction) of the base portions 114 to define the entire end surfaces 38c, 38d of the capacitor 30.

[0194] As Figures 3A to 3C shown, the capacitor 30 includes four external terminals on each surface. However, as described above, the present invention is not limited by the number of external terminals.

[0195] For example, Figure 4AA capacitor 40 having a 2 - by - 4 configuration is shown. That is, the capacitor 40 includes two terminals along one dimension of the top surface 48a and the bottom surface 48b and four terminals along the other dimension. In this regard, the capacitor 40 includes a total of eight external terminals 42a, 42b, 44a, 44b on the top surface 48a and corresponding eight external terminals (not shown) on the bottom surface 48b, where the external terminals on the top surface 48a are electrically connected to the corresponding external terminals 42a, 42b, 44a, 44b on the bottom surface 48b.

[0196] Although not shown in the figure, it will be appreciated that the capacitor 40 can also be configured to have end external terminals 42a, 44b extending along the end surfaces 48c, 48d. That is, like Figure 3B the capacitor 30 shown in, the external terminals 42a, 44b adjacent to the end surfaces 48c, 48d can extend along the end surfaces 48c, 48d as well as the top surface 48a and the bottom surface 48b. In such an embodiment, the front edge (extending in the Z - direction) of the first substrate portion 214 - 1 is disposed at the end surfaces 48c, 48d (instead of being separated from the end surfaces 48c, 48d), such that the first substrate portion 214 - 1 along its front edge can help form the external terminals along the end surfaces 48c, 48d.

[0197] Figure 4A The capacitor 40 of includes two sets 450 of alternating dielectric layers and internal electrode layers (as Figure 4B shown). Each set 450 of alternating dielectric layers and internal electrode layers 110 includes internally electrode layers 202, 204 and dielectric layers (not shown) arranged alternately. These sets 450 of alternating dielectric layers and internal electrode layers are separated from each other by a spacing distance t. For example, a spacing distance t can be defined between the first set 450a of alternating dielectric layers and internal electrode layers and the second set 450b of alternating dielectric layers and internal electrode layers.

[0198] The spacing distance t between the sets can be from about 0.2 μm to about 10 μm, in some embodiments from about 0.5 μm to about 8 μm, and in some embodiments from about 1 μm to about 5 μm. Additionally, the spacing distance t can be (but is not limited to) at least 2 times greater, in some embodiments at least about 3 times greater, and in embodiments from about 4 times to about 8 times greater than the distance between adjacent lead tabs in a given column to ensure that different terminals do not get connected together.

[0199] Generally, the electrode layers 202, 204 are as referenced Figure 2Bconfigured as described. However, the electrode layers 202, 204 may also be configured as described in other embodiments of the capacitor 20. For example, in the case where the external terminals 42a, 44b extend along the ends 48c, 48d (and the top surface 48a and the bottom surface 48b) of the capacitor 40, the internal electrode layers 202, 204 may be similar to Figure 2C configured, and these internal electrode layers have a second electrode 208 to assist in forming the external terminals 42a, 44b (especially along the end surfaces 48c, 48d). In addition, it will be recognized that for an embodiment of the capacitor 40 such as Figure 4A shown in, the first base portions 214-1 of the electrode layers 202, 204 may be separated from the end surfaces 48c, 48d of the capacitor 40. For example, a dielectric material may be provided along the front edge (extending in the Z direction) of the first base portion 214-1 to define the entire end surfaces 48c, 48d of the capacitor 40.

[0200] As another example of a different number of external terminals, Figure 5A a capacitor 50 having a 4 by 4 configuration is shown. That is, the capacitor 50 includes four terminals along one dimension of the top surface 58a and the bottom surface 58b and four terminals along the other dimension. In this regard, the capacitor 50 includes a total of sixteen external terminals 52a, 52b, 54a, 54b on the top surface 58a and corresponding sixteen external terminals (not shown) on the bottom surface 58b, wherein the external terminals on the top surface 58a are electrically connected to the corresponding external terminals 52a, 52b, 54a, 54b on the bottom surface 58b.

[0201] Although not shown in the figures, it will be recognized that the capacitor 50 may also be configured to have end external terminals 52a, 54b extending along the end surfaces 58c, 58d. That is, just like Figure 3B the capacitor 50 shown in, the external terminals 52a, 54b adjacent to the end surfaces 58c, 58d may extend along the end surfaces 58c, 58d and the top surface 58a and the bottom surface 58b. In such an embodiment, the front edge (extending in the Z direction) of the first base portion 214-1 is provided at the end surfaces 58c, 58d (instead of being separated from the end surfaces 58c, 58d), such that the first base portion 214-1 along its front edge may assist in forming the external terminals along the end surfaces 58c, 58d.

[0202] Figure 5A The capacitor 50 of includes four sets 550 of alternating dielectric layers and internal electrode layers (as Figure 5BAs shown). Each set of 550 alternating dielectric layers and internal electrode layers includes internal electrode layers 202, 204 and dielectric layers (not shown) arranged alternately. These sets 550 of alternating dielectric layers and internal electrode layers are separated from each other by a spacing distance t, which may be the same or different between the sets 550. For example, a first spacing distance t may be defined between the first set 550a and the second set 550b 1 , a second spacing distance t may be defined between the second set 550b and the third set 550c 2 , and a third spacing distance t may be defined between the third set 550c and the fourth set 550d 3 . The first spacing distance t 1 may be the same as the second spacing distance t 2 and / or the third spacing distance t 3 . For example, at least one of the first spacing distance t 1 , the second spacing distance t 2 and the third spacing distance t 3 is different from the other spacing distances t 1 , t 2 , t 3 .

[0203] Similar to the embodiments discussed above, the spacing distances "t 1 ", "t 2 " and / or "t 3 " between the sets may be from about 0.2 μm to about 10 μm, in some embodiments from about 0.5 μm to about 8 μm, and in some embodiments from about 1 μm to about 5 μm. Additionally, the spacing distances "t 1 ", "t 2 " and / or "t 3 " may be (but are not limited to) at least 2 times greater, in some embodiments at least about 3 times greater, and in embodiments from about 4 times to about 8 times greater than the distance between adjacent lead tabs in a given column to ensure that different terminals do not become connected together.

[0204] Generally, the electrode layers 202, 204 are configured as described with reference to Figure 2B . However, the electrode layers 202, 204 may also be configured as described in other embodiments regarding the capacitor 20. For example, in the case where the external terminals 52a, 54b extend along the ends 58c, 58d (and the top surface 58a and bottom surface 58b) of the capacitor 50, the internal electrode layers 202, 204 may be configured similarly to Figure 2C , and these internal electrode layers have a second electrode 208 to assist in forming the external terminals 52a, 54b (especially along the end surfaces 58c, 58d). Additionally, it will be appreciated that for example Figure 5AIn the embodiment of the capacitor 50 shown, the first substrate portions 214-1 of the electrode layers 202, 204 may be separated from the end surfaces 58c, 58d of the capacitor 50. For example, a dielectric material may be provided along the front edge (extending in the Z direction) of the first substrate portion 214-1 to define the entire end surfaces 58c, 58d of the capacitor 50.

[0205] Capacitors 30, 40, 50 each include at least one first polar terminal and at least one second opposite polar terminal on the top surface, and at least one first polar terminal and at least one second opposite terminal on the bottom surface. For example, Figure 3A It includes two positive terminals 32 and two negative terminals 34 on the top surface 38a.

[0206] Generally, terminals of similar polarity corresponding to a particular set of alternating dielectric layers and internal electrode layers on the bottom surface of the capacitor are electrically connected to terminals of similar polarity on the top surface of the capacitor. The terminals of similar polarity located on the top and bottom surfaces of the capacitor may not be staggered. In this regard, the corresponding terminals of similar polarity on the top and bottom surfaces may not be offset in terms of terminal position, but may be directly positioned above or below another terminal of similar polarity on the opposite top or bottom surface. In other words, the corresponding similar polarity terminals corresponding to a particular set of alternating dielectric layers and internal electrode layers may be substantially aligned. Substantially aligned means that the offset of a lateral edge of a polar terminal on the top surface relative to the lateral edge is within + / -10%, for example within + / -5%, for example within + / -4%, for example within + / -3%, for example within + / -2%, for example within + / -1%, for example within + / -0.5% of the offset of the corresponding polar terminal on the bottom surface relative to the lateral edge.

[0207] In addition, the pitch of the external terminals (i.e., the nominal distance between each center, also referred to as the center-to-center pitch) can generally be determined by a particular circuit board configuration. The pitch of the external terminals in one direction (i.e., the x direction or the y direction) can be the same as the pitch of adjacent external terminals in the other direction (i.e., the y direction or the x direction respectively). That is, the pitch between any two adjacent external terminals can be substantially the same as the pitch between any other two adjacent external terminals.

[0208] The spacing can be about 0.1 mm or greater, such as about 0.2 mm or greater, such as about 0.3 mm or greater, such as 0.4 mm or greater, such as about 0.5 mm or greater, such as about 0.6 mm or greater, such as about 0.7 mm or greater, such as about 0.8 mm or greater, such as about 0.9 mm or greater, such as about 1.0 mm or greater. The spacing can be about 2.0 mm or less, such as about 1.5 mm or less, such as about 1.4 mm or less, such as about 1.3 mm or less, such as about 1.2 mm or less, such as about 1.1 mm or less, such as about 1.0 mm or less. For example, the spacing can be about 0.2 mm, about 0.4 mm, about 0.6 mm, about 0.8 mm, about 1.0 mm, about 1.2 mm, etc. Specifically, the spacing can be 0.6 mm, 0.8 mm or 1.0 mm. In one embodiment, the spacing can be about 0.6 mm, such as 0.6 mm + / - 10%, such as 0.6 mm + / - 5%, such as 0.6 mm + / - 2%, such as 0.6 mm + / - 1%. In another embodiment, the spacing can be about 0.8 mm, such as 0.8 mm + / - 10%, such as 0.8 mm + / - 5%, such as 0.8 mm + / - 2%, such as 0.8 mm + / - 1%. In yet another embodiment, the spacing can be about 1 mm, such as 1 mm + / - 10%, such as 1 mm + / - 5%, such as 1 mm + / - 2%, such as 1 mm + / - 1%).

[0209] In addition, the external terminals can be positioned in a configuration similar to that of a ball grid array. For example, external terminals can be provided to form the contacts typically employed in a ball grid array (especially around a ball grid array). In this regard, the spacing of each external terminal can be the same as the spacing around the ball grid array. That is, the spacing can be within 10% of the spacing around the ball grid array, such as within 5%, such as within 2%, such as within 1%, such as within 0.5%, such as within 0.1%.

[0210] In addition, like a ball grid array, each external terminal can be provided in multiple rows and multiple columns. That is, each external terminal can be provided such that they are present in at least two rows and at least two columns. For example, each external terminal can be presented in at least two rows, such as in at least three rows, such as in at least four rows. The number of rows can be determined by the number of different alternating dielectric layers and internal electrode layers. In addition, each external terminal can be presented in at least two columns, such as in at least three columns, such as in at least four columns. The number of columns can be determined by the number of different columnar tabs of the internal electrodes.

[0211] Although Figures 3A to 5BThe capacitors therein employ multiple sets of alternating dielectric layers and internal electrode layers 102, 104 or 202, 204, but it should be understood that other configurations may also be employed. For example, in capacitors similar to capacitor 40 and capacitor 50 in Figures 4A to 5B a set of 350 alternating dielectric layers and internal electrode layers 102, 104 (such as any one of those in Figures 1C to 1G can also be employed. In this regard, the capacitor can employ up to eight sets of 350 alternating dielectric layers and internal electrode layers 102, 104 instead of only the two sets of 350 alternating dielectric layers and internal electrode layers within capacitor 30 of Figures 3A to 3C . For example, capacitor 30 can employ two to eight sets of 350 alternating dielectric layers and internal electrode layers.

[0212] In addition, each set of alternating dielectric layers and internal electrode layers in the embodiments in the figures employs only four internal electrode layers. However, it should be understood that each set of the present invention can include any number of internal electrode layers and is not necessarily limited.

[0213] Generally speaking, the present invention provides a capacitor with a unique configuration that provides various benefits and advantages. In this regard, it should be understood that the materials used in constructing the capacitor can be unrestricted and can be any materials commonly used in the art, and any methods commonly used in the art can be used to form it.

[0214] Accordingly, Figures 3A to 5B various exemplary arrangements of multiple capacitive elements within a single one-piece package (i.e., a single body) are provided. For example, each of capacitor 30 and capacitor 40 includes two capacitive elements, while capacitor 50 includes four capacitive elements. However, as described herein, different numbers of capacitive elements (such as two, such as three, such as four, such as five, such as six or more capacitive elements) can be included within a single capacitive body.

[0215] As previously mentioned, the arrangement of multiple capacitive elements within a single one-piece package or a single body as described herein can provide several advantages. For example, such a capacitor can be mounted onto a circuit board as a surface-mount capacitor and can provide a smaller footprint on the circuit board, which can also allow for a reduction in the size of the circuit board. In addition, another advantage of a capacitor and configuration that uses multiple capacitive elements within a single body (such as compared to using multiple separate multilayer ceramic capacitors) is a direct power ground connection, where the capacitor can be directly connected to an integrated circuit package and the circuit board, which allows current to flow through the capacitor and provides a direct power ground connection.

[0216] In the embodiments described herein, the internal electrode layers are generally oriented in a vertical configuration. Of course, this is by no means necessary, and other geometric configurations (e.g., horizontal configurations) are equally suitable.

[0217] The disclosed capacitors can be used in a variety of applications. For example, these applications can include communication-related applications. These applications can include 5G, mobile devices, devices that require high-frequency communication, base stations, V2X (Vehicle to Everything technology), etc. These applications can also include power trains, safety devices, automatic data acquisition systems (ADA), etc.

[0218] Example

[0219] The multi-layer capacitors defined herein are manufactured according to the specifications disclosed herein. Specifically, a 2 by 4 multi-layer capacitor is manufactured, which includes two sets of alternating dielectric layers and internal electrode layers. Each internal electrode layer includes two lead tabs extending from the top edge and two lead tabs extending from the bottom edge. The capacitor includes 8 external terminals on the top surface and 8 external terminals on the bottom surface. Four external terminals on each surface have a first polarity, and the remaining four external terminals on each surface have a second opposite polarity. The capacitor includes approximately 300 active internal electrode layers, and the distance between each layer and the adjacent internal electrode layer within a set is approximately 4 micrometers.

[0220] Sample Inductance (pH) Capacitance (μF) Resistance (mOhm) 1 0.55 5 2 2 0.55 12 7 3 0.55 12 5 4 0.55 12 5

[0221] Test method

[0222] A test assembly can be used to test the performance characteristics of a capacitor according to aspects of the present disclosure, such as equivalent series resistance. For example, the capacitor can be mounted to a test board. Both the input line and the output line can be connected to the test board. The test board can include microstrip lines or test traces that electrically connect the input line and the output line to the corresponding external terminals of the capacitor. The test traces can be spaced apart by approximately 0.432 mm (0.017 inches) or approximately 0.610 mm (0.024 inches).

[0223] An input signal can be applied to the input line using a source signal generator (e.g., a 1806 Keithley 2400 series Source Measure Unit (SMU), e.g., a Keithley 2410-C SMU), and the output signal of the resulting capacitor can be measured at the output line (e.g., using the source signal generator). The equivalent series resistance can be determined in the frequency range from 1 GHz to 10 GHz. This test method can be repeated for multiple capacitors having the same design and nominal dimension.

[0224] Those of ordinary skill in the art can practice these and other modifications and variations of the present invention without departing from the spirit and scope of the present invention. Additionally, it should be understood that aspects of various embodiments may be interchanged in whole or in part. Also, those of ordinary skill in the art will recognize that the foregoing description is by way of example only and is not intended to limit the present invention as further described in these appended claims.

Claims

1. A multilayer capacitor having a first end and a second end, the second end being separated from the first end in a longitudinal direction perpendicular to a transverse direction, both the transverse direction and the longitudinal direction being perpendicular to the Z direction, the multilayer capacitor comprises: a body having a top surface and a bottom surface opposite the top surface in the Z direction, the body including a plurality of alternating dielectric layers and a plurality of electrode layers, the plurality of electrode layers including a first electrode layer and a second electrode layer, each electrode layer including: a first electrode having a base portion, a connecting portion, and a central portion, a first connecting edge of the connecting portion extending from a first front edge of the base portion to a first edge of the central portion, and a second connecting edge of the connecting portion extending from a second front edge of the base portion to a second edge of the central portion; and a plurality of external terminals including a first external terminal and a second external terminal, the first external terminal being disposed on at least one of the top surface or the bottom surface, the second external terminal being disposed on at least one of the top surface or the bottom surface, wherein the first external terminal is electrically connected to the first electrode layer along at least one of the first front edge or the second front edge of the first electrode in the first electrode layer, wherein the second external terminal is electrically connected to the second electrode layer along at least one of the first front edge or the second front edge of the first electrode in the second electrode layer, and wherein at least a portion of at least one of the first connecting edge or the second connecting edge of the first electrode in the plurality of electrode layers is not perpendicular to a corresponding first edge or second edge of the central portion of the first electrode.

2. The multilayer capacitor according to claim 1, wherein, the first connecting edge of the connecting portion forms a first angle greater than 90° and less than 180° with the first edge of the central portion.

3. The multilayer capacitor according to claim 2, wherein, the first angle is from 100° to 160°.

4. The multilayer capacitor according to claim 1, wherein, the first connecting edge of the connecting portion is a straight edge.

5. The multilayer capacitor according to claim 1, wherein, the first connecting edge of the connecting portion is a curved edge.

6. The multilayer capacitor according to claim 1, wherein, the second connecting edge of the connecting portion forms a second angle greater than 90° and less than 180° with the second edge of the central portion.

7. The multilayer capacitor according to claim 6, wherein, the second angle is from 100° to 160°.

8. The multilayer capacitor according to claim 1, wherein, the second connecting edge of the connecting portion is a straight edge.

9. The multilayer capacitor according to claim 1, wherein, the second connecting edge of the connecting portion is a curved edge.

10. The multilayer capacitor according to claim 1, wherein, The base portion of the first electrode has a vertical edge extending in the Z direction and a length extending in the longitudinal direction, wherein the first external terminal has a first lateral edge extending in the lateral direction, and wherein the first lateral edge of the first external terminal is within 5% of the vertical edge of the base portion based on the length of the base portion.

11. The multilayer capacitor according to claim 1, wherein, the base portion includes a first vertical edge, and wherein the first vertical edge of the base portion and the first connection edge of the connection portion form a second angle greater than 90° and less than 180°.

12. The multilayer capacitor according to claim 11, wherein, the second angle is 100° to 160°.

13. The multilayer capacitor according to claim 1, wherein, the base portion includes a second vertical edge, and wherein the first vertical edge of the base portion and the second connection edge of the connection portion form a second angle greater than 90° and less than 180°.

14. The multilayer capacitor according to claim 13, wherein, the second angle is 100° to 160°.

15. The multilayer capacitor according to claim 1, wherein, the body has a body length in the longitudinal direction between the first end and the second end of the multilayer capacitor, and wherein the first external terminal has a first lateral edge, the second external terminal has a second lateral edge, wherein the second lateral edge is offset from the first lateral edge by an external terminal gap distance in the longitudinal direction, and wherein the ratio of the body length to the external terminal gap distance is 0.2 to 0.

8.

16. The multilayer capacitor according to claim 1, wherein, the multilayer capacitor is symmetric about a longitudinal center line in the lateral direction, the longitudinal center line extending in the longitudinal direction.

17. The multilayer capacitor according to claim 1, wherein, the multilayer capacitor is symmetric about a lateral center line in the Z direction, the lateral center line extending in the lateral direction.

18. The multilayer capacitor according to claim 1, wherein, the multilayer capacitor is configured to be mounted to a mounting surface such that the plurality of electrode layers are perpendicular to the mounting surface.

19. The multilayer capacitor according to claim 1, wherein, each electrode layer further includes a second electrode coplanar with the first electrode.

20. The multilayer capacitor according to claim 19, wherein, a central end gap distance is formed between the central portion of the first electrode and the base portion of the second electrode in the longitudinal direction.

21. The multilayer capacitor according to claim 20, wherein, the central end gap distance is 2% to 40% of the length of the body of the capacitor.

22. The multilayer capacitor according to claim 20, wherein, The central end gap distance is 5% to 40% of the length of the central portion of the first electrode.

23. The multilayer capacitor according to claim 19, wherein, the second electrode extends 5% to 50% of the length of the body of the capacitor.

24. The multilayer capacitor according to claim 1, wherein, the central portion of the first electrode extends 40% to less than 100% of the length of the body of the capacitor.

25. The multilayer capacitor according to claim 24, wherein, the central portion extends 50% to less than 100% of the length of the body of the capacitor.

26. The multilayer capacitor according to claim 1, wherein, the first electrode includes copper.

27. The multilayer capacitor according to claim 1, wherein, each electrode layer further includes a second electrode, and wherein the first electrode and the second electrode include copper.

28. The multilayer capacitor according to claim 1, wherein, the plurality of dielectric layers include NPO material.

29. The multilayer capacitor according to claim 1, wherein, the plurality of dielectric layers include titanate.

30. The multilayer capacitor according to claim 29, wherein, the plurality of dielectric layers further include oxide.

31. The multilayer capacitor according to claim 1, wherein, the first connection edge is rounded, and the second connection edge is rounded.

32. The multilayer capacitor according to claim 31, wherein, at least one electrode layer further includes a second electrode, and the second electrode is coplanar with the first electrode.

33. The multilayer capacitor according to claim 32, wherein, the second electrode has at least one rounded corner.

34. The multilayer capacitor according to claim 33, wherein, the second electrode has a substantially rectangular configuration.

35. The multilayer capacitor according to claim 31, wherein, the central portion of the first electrode extends 40% to less than 100% of the length of the body of the capacitor.

36. The multilayer capacitor according to claim 35, wherein, the central portion extends 50% to less than 100% of the length of the body of the capacitor.

37. The multilayer capacitor according to claim 32, wherein, there is a gap between the first electrode and the second electrode.

38. The multilayer capacitor according to claim 37, wherein, the gap is 2% to 40% of the length of the body of the capacitor.

39. The multilayer capacitor according to claim 37, wherein, the gap is 5% to 40% of the length of the body of the first electrode.

40. The multilayer capacitor according to claim 32, wherein, the second electrode extends 5% to 50% of the length of the body of the capacitor.

41. The multilayer capacitor according to claim 1, wherein, the plurality of external terminals include two or more external terminals arranged in a linear manner.

42. The multilayer capacitor according to claim 1, wherein, The plurality of dielectric layers and the plurality of electrode layers include a first set of layers and a second set of layers, wherein the first set of layers includes a first portion of the plurality of dielectric layers that is alternately stacked with a first portion of the plurality of electrode layers, and the second set of layers includes a second portion of the plurality of dielectric layers that is alternately stacked with a second portion of the plurality of electrode layers.

43. The multilayer capacitor according to claim 42, wherein, a spacing distance is defined between the first set of layers and the second set of layers.

44. The capacitor according to claim 1, wherein, the capacitor includes at least three sets of alternating dielectric layers and electrode layers.

45. A circuit board, the circuit board including the capacitor according to claim 1, the capacitor being positioned on the circuit board.

46. The circuit board according to claim 45, wherein, the board further includes an integrated circuit package, and wherein the capacitor is positioned vertically between the circuit board and the integrated circuit package such that the circuit board, the capacitor, and the integrated circuit package are presented in a stacked arrangement.

47. The circuit board according to claim 46, wherein, the capacitor is directly connected to the circuit board and the integrated circuit package.

48. An integrated circuit package, the integrated circuit package including the capacitor according to claim 1.

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