Surface modifiers for enhanced epitaxial nucleation and wetting

Abstract

A method of forming a semiconductor device is provided. In some implementations, the method includes positioning a substrate into a processing chamber, the substrate having an exposed amorphous surface and an exposed crystalline surface. The method further includes heating the processing chamber to a temperature for deposition. The method further includes injecting a pretreatment gas into the processing chamber. The pretreatment gas includes molecules for reducing the interfacial energy between the exposed amorphous surface and the exposed crystalline surface. The method further includes injecting a deposition gas into the processing chamber to selectively grow an n-type doped epitaxial silicon layer on the exposed crystalline surface.

Description

Background Technical Field

[0002] Embodiments of the present disclosure generally relate to a method for forming a semiconductor device. More particularly, the present application relates to an epitaxial deposition method for forming a horizontal gate-all-around (hGAA) device structure.

[0003] Description of Related Art

[0004] The electronics industry is experiencing a growing demand for smaller and faster electronic devices that can simultaneously support more increasingly complex and sophisticated functions. As a result, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). These goals are largely achieved by reducing the size of semiconductor ICs (e.g., minimum feature size) to increase production efficiency and reduce associated costs. However, this miniaturization has introduced greater complexity to semiconductor manufacturing processes. Therefore, achieving continued progress in semiconductor ICs and devices requires similar progress in semiconductor manufacturing processes and technologies.

[0005] Recently, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effect (SCE). One such multi-gate device is the gate-all-around (GAA) transistor. In a GAA device, all side surfaces of the channel region are surrounded by gate electrodes, which allows for more complete depletion in the channel region and results in a smaller short-channel effect due to a steeper subthreshold current swing and a smaller drain-induced barrier lowering (DIBL).

[0006] As transistor sizes shrink to smaller technology nodes, further improvements in the design and manufacturing of GAA are needed. Summary of the Invention

[0007] Embodiments of the present disclosure generally relate to a method for forming a semiconductor device. More particularly, the present application relates to an epitaxial deposition method for forming a horizontal gate-all-around (hGAA) device structure.

[0008] In at least one aspect, a method of forming a semiconductor device is provided. The method includes positioning a substrate in a processing chamber, the substrate having an exposed amorphous surface and an exposed crystalline surface. The method further includes heating the processing chamber to a temperature for deposition. The method further includes injecting a pretreatment gas into the processing chamber. The pretreatment gas includes molecules configured to reduce the interfacial energy between the exposed amorphous surface and the exposed crystalline surface. The method further includes injecting a deposition gas into the processing chamber to selectively grow an n-type doped epitaxial silicon layer on the exposed crystalline surface.

[0009] Embodiments may include one or more of the following. The molecule is a Group V chloride. The molecule is selected from the group consisting of PCl 3 , AsCl 3 , and SbCl 3 . The injection of the pretreatment gas and the injection of the deposition gas at least partially overlap. The injection of the pretreatment gas is completed before the injection of the deposition gas. The injection of the pretreatment gas and the injection of the deposition gas are repeated in sequence multiple times. The method further includes exposing the substrate to a dry etchant to remove contaminants from the substrate surface. The exposed amorphous surface includes silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbide, silicon carbonitride oxide, or a combination of the foregoing. The dry etching includes exposing the substrate to H 2 , NF 3 , NH 3 , and plasma by-products. The plurality of exposed silicon layers have a <110> structure. The deposition temperature is 400 degrees Celsius or higher. The injection of the pretreatment gas is performed at a pressure in the range of about 1 torr to about 760 torr.

[0010] In another aspect, a method of forming a semiconductor device is provided. The method includes positioning a substrate in a processing chamber. The substrate has a multi-material layer formed thereon, the multi-material layer including a plurality of exposed dielectric surfaces and a plurality of exposed silicon layers on a plurality of Si 1-x Ge x layers. The method further includes heating the processing chamber to a temperature for deposition. The method further includes injecting a pretreatment gas into the processing chamber, wherein the pretreatment gas includes molecules configured to reduce the interfacial energy between the plurality of exposed dielectric surfaces and the plurality of exposed silicon layers. The method further includes injecting a deposition gas into the processing chamber to selectively grow an n-type doped epitaxial silicon layer on the exposed silicon layers.

[0011] Embodiments may include one or more of the following. The exposed dielectric surfaces include silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbide, silicon carbonitride oxide, or a combination of the foregoing. The molecule is a Group V chloride. The molecule is selected from the group consisting of PCl 3 , AsCl 3 , and SbCl 3A group formed. The injection of the pretreatment gas and the injection of the deposition gas at least partially overlap.

[0012] In yet another aspect, a method of forming a semiconductor device is provided. The method includes positioning a substrate in a cleaning chamber, forming a multi-material layer on the substrate, the multi-material layer including a plurality of dielectric surfaces and a plurality of silicon layers disposed on the outer surfaces of a plurality of Si 1-x Ge x layers, the plurality of Si 1-x Ge x layers being alternately arranged with the plurality of silicon layers. The method further includes exposing the substrate to a dry etchant to remove contaminants from the substrate surface. The method further includes positioning the substrate in a processing chamber. The method further includes heating the processing chamber to a temperature for deposition. The method further includes injecting a pretreatment gas into the processing chamber, wherein the pretreatment gas includes molecules configured to reduce the interfacial energy between the dielectric surface and the silicon surface. The method further includes injecting a deposition gas into the processing chamber to selectively grow an n-type doped epitaxial silicon layer on the exposed silicon surface.

[0013] Embodiments may include one or more of the following. The molecule is a Group V chloride. The injection of the pretreatment gas and the injection of the deposition gas are repeated sequentially multiple times. The exposed dielectric surfaces include silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxynitride, or a combination of the foregoing.

[0014] In another aspect, a non-transitory computer-readable medium has instructions stored thereon that, when executed by a processor, cause the process to perform the operations of the above-described apparatus and / or method. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to be able to understand in detail the manner in which the above-described features of the present disclosure can be obtained, a more specific description of the present disclosure, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the drawings. It should be noted, however, that the drawings only illustrate typical embodiments of the present disclosure and are not to be considered limiting of its scope, as the present disclosure may admit to other equally effective embodiments.

[0016] Figure 1 A schematic isometric view of a horizontal gate-all-around (hGAA) structure according to an embodiment of the present disclosure is shown.

[0017] Figures 2A to 2C According to an embodiment of the present disclosure, the formation of Figure 1 is shown in schematic cross-sectional views of the various stages of the hGAA structure.

[0018] Figure 3 A flowchart of a method of forming a semiconductor device according to an embodiment of the present disclosure is shown.

[0019] Figure 4 Shows a schematic side cross-sectional view of an exemplary processing chamber in accordance with one embodiment of the present disclosure.

[0020] Figure 5 Shows a schematic top view of a system for processing a substrate in accordance with one embodiment of the present disclosure. Detailed Description

[0021] Embodiments of the present disclosure generally relate to a method for forming semiconductor devices. More particularly, the present application relates to an epitaxial deposition method for forming a horizontal all-around gate (hGAA) device structure.

[0022] As the feature sizes of transistor devices continue to shrink to achieve greater circuit density and higher performance, it is necessary to improve transistor device structures to improve electrostatic coupling and reduce negative impacts such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field effect transistor (FinFET) structures, and horizontal all-around gate (hGAA) structures. The hGAA device structure includes a number of lattice-matched channels that are suspended in a stacked configuration and connected by source / drain regions.

[0023] The epitaxial growth of an epitaxial silicon layer for forming source / drain materials on a nanosheet-type framework typically begins on a (110) sidewall silicon surface and must grow laterally outward and on adjacent silicon spacers. Under certain process conditions, the epitaxial layer resists nucleation on the sidewall silicon surface and overgrowth of the spacers. For example, process conditions containing excessive HCl act as "overly selective" on the spacers, such that continued filling of the source / drain cavity results in pore formation. Current techniques optimize process conditions or select specific silicon precursors to enhance the wetting and lateral overgrowth of the epitaxial material. However, these current techniques alter the epitaxial process to affect the desired results. Altering the process to accommodate nucleation and overgrowth can compromise other variables such as selectivity, throughput, and layer structure.

[0024] In addition, the selective growth of the epitaxial silicon layer introduces challenges associated with the serrated growth morphology of the epitaxial silicon layer and the degree of growth of the epitaxial silicon layer. Accordingly, a method is needed to improve the growth morphology and the degree of growth of the epitaxial silicon layer.

[0025] This document describes a method for forming an epitaxial silicon layer that can be used as, for example, an n-channel metal oxide semiconductor (NMOS) or p-channel metal oxide semiconductor (PMOS) epitaxial silicon layer within a semiconductor device structure such as an hGAA device structure. The epitaxial silicon layer can be grown on the hGAA device structure into a shaped structure, such as a diamond-like top structure, to form source / drain regions and source / drain extension regions according to the requirements of the hGAA semiconductor device on the substrate.

[0026] The described method includes using a surface modifier that enhances epitaxial nucleation and wetting. Pre-adding the surface modifier to the growth surface can assist in the initial stage of epitaxial layer nucleation and the later stages of dielectric wetting and overgrowth. The surface modifier is used to reduce the interfacial energy between the growing semiconductor and the dielectric surface, thereby promoting the later overgrowth of the spacer from the silicon channel region. The surface modifier can include surfactant molecules. The surface modifier can be pre-injected into the processing chamber before introducing the deposition gas. The surface modifier can be pulsed in sequence with the deposition gas. Surface modifiers that can activate the dielectric surface for n-type epitaxial growth include group V chlorides, tri-tert-butylarsine (TBAs), triethylantimony (TESb), triethylarsine (TEAs), plasma ammonia (NH 3 ), plasma hydrogen (H), and plasma deuterium (D). Examples of suitable group V chlorides for n-type epitaxial growth include phosphorus chloride, such as PCl 3 , arsenic chloride, such as AsCl 3 , and antimony chloride, such as SbCl 3 . Surface modifiers that can activate the dielectric surface for p-type epitaxial growth include group V chlorides, triethylgallium (TEGa), triethylindium (TEIn), triethylaluminum (TEAl), plasma ammonia (NH 3 ), plasma hydrogen (H), and plasma deuterium (D). Examples of suitable group V chlorides for p-type epitaxial growth include aluminum chloride, such as AlCl 3 , gallium chloride, such as GaCl 3 , and indium chloride, such as InCl 3 .

[0027] The surface modifier can be supplied as a pretreatment gas. The pretreatment gas can be injected into the processing chamber and adsorbed on the exposed dielectric surface and the exposed silicon surface. Chemically modify the dielectric surface and the silicon surface so that the surface is more reactive to the deposition gas for forming the epitaxial layer.

[0028] The pretreatment gas is used to continuously etch the epitaxial layer during epitaxial layer formation and to improve the overgrowth of the epitaxial layer when the epitaxial layer is deposited onto the superlattice structure. The epitaxial layer is selectively formed only on the crystalline portions of the superlattice structure relative to the oxide or amorphous surface. Under certain process conditions, the epitaxial layer resists nucleation on the crystalline layer and overgrows the spacer. For example, process conditions with an excess of HCl act “overselectively” on the spacer, such that continuous filling of the epitaxial silicon layer cavity results in pore formation. Using the pretreatment gas, the growth morphology of the epitaxial layer is less jagged and the pores are reduced.

[0029] This method of improving the growth morphology of the epitaxial layer does not require changing the epitaxial process. Altering the process to accommodate nucleation and overgrowth can compromise other process variables such as selectivity, throughput, and layer structure. Additionally, a predetermined or sequential quantification allows the growth process parameters to be decoupled from the nucleation and overgrowth issues.

[0030] Figure 1 A schematic isometric view of an hGAA structure 100 according to one embodiment is shown. The hGAA structure 100 includes a multi-material layer 105 having alternating first layer 106 and second layer 108, with spacers 110 formed in the second layer 108 for use in the hGAA structure 100. The hGAA structure 100 utilizes the multi-material layer 105 as a nanowire (e.g., a channel) between a source 114a, a drain 114b, and a gate structure 112. The source / drain 114a, 114b are formed of epitaxial silicon layers 115a, 115b formed according to method 300. As Figure 1 shown in the cross-sectional view of the multi-material layer 105, the spacers 110 formed at the bottom (e.g., or ends) of each second layer 108 help manage the interface between the second layer 108 and the source / drain 114a, 114b, thereby reducing parasitic capacitance and maintaining minimal device leakage.

[0031] The hGAA structure 100 includes the multi-material layer 105 disposed on the top surface 103 of a substrate 102, e.g., on top of an optional material layer 104 disposed on the substrate 102. In embodiments where the optional material layer 104 is absent, the multi-material layer 105 is formed directly on the substrate 102.

[0032] The substrate 102 can be a material such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, germanium, doped or undoped polysilicon, doped or undoped silicon wafers, and patterned or unpatterned silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire. The substrate 102 can have various dimensions, such as 200 mm, 300 mm, 450 mm, or other diameters, and is a rectangular or square panel. Unless otherwise specified, the described examples are performed on substrates having a 200 mm diameter, 300 mm diameter, or 450 mm diameter.

[0033] In one example, the optional material layer 104 is an insulating material. Suitable examples of insulating materials can include silicon oxide materials, silicon nitride materials, silicon oxynitride materials, or any suitable insulating material. Alternatively, the optional material layer 104 can be any suitable material, including conductive or non-conductive materials as needed. The multi-material layer 105 includes at least a pair of layers, each pair including a first layer 106 and a second layer 108. Although Figure 1 the examples described in show four pairs and a first layer 106 cap, each pair includes a first layer 106 and a second layer 108 (alternating pairs, each pair including a first layer 106 and a second layer 108). An additional first layer cap 106 is disposed on top of the multi-material layer 105. The number of pairs can vary based on different process requirements, with additional or no additional first layer 106 or second layer 108. In one embodiment, the thickness of each first layer 106 can be between about and about e.g., about and the thickness of each second layer 108 can be between about and about e.g., about The multi-material layer 105 can have a total thickness between about and about e.g., between about and

[0034] The first layer 106 is a crystalline material layer, such as a single-crystalline silicon layer, a polysilicon layer, or a single-crystalline silicon layer. The first layer 106 is formed using an epitaxial deposition process. Alternatively, the first layer 106 is a doped silicon layer, including a p-type doped silicon layer or an n-type doped layer. Suitable p-type dopants include B dopants, Al dopants, Ga dopants, In dopants, etc. Suitable n-type dopants include N dopants, P dopants, As dopants, Sb dopants, etc. In yet another example, the first layer 106 is a III-V material, such as a GaAs layer.

[0035] The second layer 108 is a non-crystalline material layer. In some embodiments, the second layer 108 is a Ge-containing layer, such as a SiGe layer, a Ge layer, or other suitable layers. Alternatively, the second layer 108 is a doped silicon layer, including a p-type doped silicon layer or an n-type doped layer. In yet another example, the second layer 108 is a III-V material, such as a GaAs layer. In yet another example, the first layer 106 is a silicon layer, and the second layer 108 is a metal material having a high-k material coating on its outer surface. Suitable examples of high-k materials include hafnium dioxide (HfO 2 ), zirconium dioxide (ZrO 2 ), hafnium silicate (HfSiO 4 ), hafnium aluminum oxide (HfAlO), zirconium silicate (ZrSiO 4 ), tantalum dioxide (TaO 2 ), aluminum oxide, aluminum-doped hafnium dioxide, bismuth strontium titanium (BST), or platinum zirconium titanium (PZT), etc. In a particular embodiment, the coating is a hafnium dioxide (HfO 2 ) layer. In some embodiments, the second layer 108 is a material similar to the gate structure 112 to form a surrounding gate around the first layer 106.

[0036] Each of the spacers 110 is formed adjacent to the end of the second layer 108 and can be considered a part of the second layer 108. The spacers 110 are dielectric spacers, air gaps, or a combination of dielectric spacers and air gaps. The spacers 110 can have any known shape. In some embodiments, the spacers can be crescent-shaped, triangular, square, rectangular, irregularly shaped, etc. The spacers 110 can be formed by etching away a portion of each second layer 108 using an etch precursor to form a groove at the end of each second non-crystalline layer. The spacers 110 are formed in the grooves adjacent to each second layer 108. Before depositing the spacers 110, a liner layer (not shown) can be additionally deposited in the grooves. The spacers 110 are formed of a dielectric material and separate each nanowire or nanosheet that will form the first layer 106. In some embodiments, the spacers 110 are selected to be a silicon-containing material, such as a low-k material, that can reduce the parasitic capacitance between the gate and the source / drain 114a, 114b in the hGAA nanowire structure. The silicon-containing material or low-k material can be silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, a doped silicon layer, or other suitable materials, such as the Black material available from Applied Materials.

[0037] In one embodiment, the spacer 110 is a low-k material (e.g., having a dielectric constant less than 4) or a material containing silicon oxide / silicon nitride / silicon carbide. In other embodiments, the spacer 110 is an air gap.

[0038] The gate structure 112 is disposed above and around the multi-material layer 105. According to one embodiment, the gate structure 112 includes a gate electrode layer and may also include a gate dielectric layer, gate spacers, and a mask layer. The gate electrode layer of the gate structure 112 includes a polysilicon layer or a metal layer covered with a polysilicon layer. The gate electrode layer may include metal nitrides (e.g., titanium nitride (TiN), tantalum nitride (TaN), or molybdenum nitride (MoN x )), metal carbides (e.g., tantalum carbide (TaC) or hafnium carbide (HfC)), metal carbonitrides (e.g., TaCN), metal oxides (e.g., molybdenum oxide (MoO x )), metal oxynitrides (e.g., molybdenum oxynitride (MoO x N y )), metal silicides (e.g., nickel silicide) or a combination of the above. The gate electrode layer is disposed on top of and around the multi-material layer 105.

[0039] The gate dielectric layer may optionally be disposed below the gate electrode layer and below the multi-material layer 105. The optional gate dielectric layer may include silicon oxide (SiO 2 ), which may be formed by thermal oxidation of one or more of the first layer 106 and / or the second layer 108 or by any suitable deposition process. Suitable materials for forming the gate dielectric layer include silicon oxide, silicon nitride, oxynitrides, metal oxides such as hafnium oxide (HfO 2 ), hafnium zirconium oxide (HfZrO x ), hafnium silicon oxide (HfSiO 2 ), hafnium titanium oxide (HfTiO x ), hafnium aluminum oxide (HfAlO x ) and combinations of the above and multiple layers thereof. Gate spacers are formed on the sidewalls of the gate electrode layer. Each gate spacer includes a nitride portion and / or an oxide portion. The mask layer is formed on top of the gate electrode layer and may include silicon nitride.

[0040] The composition and formation of the epitaxial silicon layers 115a, 115b for forming source / drain 114a, 114b on the hGAA structure 100 are described.

[0041] Figures 2A to 2C is a cross-sectional view of a portion of the GAA structure corresponding to the various stages of method 300. Figure 3FIG. 0 is a flow chart of a method 300 for processing a substrate. The method 300 can be used to form a nanowire structure and an epitaxial silicon layer on a substrate with a desired material for a horizontal gate-all-around (hGAA) semiconductor device structure. Referring Figures 2A to 2C to FIGS. Figure 3 Figure 3 provides cross-sectional views of the gate-all-around structure at different stages of fabrication to illustrate Figures 2A to 2C the method. Although Figures 2A to 2C described with respect to method 300, it should be understood that Figures 2A to 2C the disclosed structure is not limited to method 300, but can exist independently as a structure separate from method 300. Similarly, although method 300 is described with respect to Figures 2A to 2C the disclosed structure, it should be understood that method 300 is not limited to Figures 2A to 2C the disclosed structure. But can be independent of

[0042] Figures 2A to 2C FIG. Figure 1 Figure 1 shows a schematic cross-sectional view of the formation of the hGAA structure 100 according to an embodiment. The hGAA structure 100 is formed using Figure 3 the method 300. The described hGAA structure 100 is an n-channel metal oxide semiconductor (NMOS) device. Thus, the dopant within the hGAA structure 100 is an n-type dopant such as phosphorus, arsenic, antimony, or any combination of the foregoing. According to an embodiment, the dopant includes phosphorus (P).

[0043] The source / drain 114a, 114b are formed from the epitaxial silicon layers 115a, 115b. The epitaxial silicon layers 115a, 115b can be n-type doped epitaxial silicon layers. The epitaxial silicon layers 115a, 115b can be formed from a silicon-containing material, a doped silicon material, a composite silicon material, or a non-silicon material. For example, the epitaxial silicon layers 115a, 115b can be silicon, phosphorus-doped silicon, silicon-germanium material, germanium, or other similar materials.

[0044] Regarding Figure 2A the multi-material layer 105 and the gate structure 112 described are formed on the substrate 102 and the optional material layer 104. Before starting method 300, the hGAA structure 100 is similar to Figure 2A the structure in FIGS.

[0045] The gate structure 112 is formed around the multi-material layer 105. In some embodiments, the gate electrode layer of the gate structure 112 is a material similar to the material of each second layer 108 within the multi-material layer 105. The gate structure 112 and the second layer 108 form a surrounding gate around each layer in the first layer 106. The first layer 106 serves as a nanowire or nanosheet disposed within the surrounding gate. After the epitaxial silicon layers 115a, 115b for forming the source / drain 114a, 114b are formed, the first layer 106 serves as a channel between the epitaxial silicon layers.

[0046] After forming the film stack, the epitaxial silicon layers 115a, 115b for forming the source / drain 114a, 114b are formed during method 300 as shown Figure 3 in the method 300.

[0047] In one embodiment, method 300 includes operation 310. Operation 310 includes exposing the substrate to a remote plasma dry etching process. In one embodiment, operation 310 can be a remote plasma-assisted dry etching process, which involves simultaneously exposing the substrate to H 2 , NF 3 and NH 3 plasma by-products. Remote plasma excitation of hydrogen and fluorine species allows substrate processing without plasma damage. The etching is largely conformal and selective to the silicon oxide layer, but silicon is not easily etched regardless of whether it is amorphous, crystalline, or polycrystalline. In one example, the remote plasma dry etching process of operation 310 is an etching process, which can be performed in a SiCoNi chamber available from Applied Materials, Inc. of Santa Clara, California. Operation 310 can be performed in a pre-cleaning chamber, e.g., in the cleaning chamber 516 as shown Figure 5 in the figure.

[0048] In operation 320, method 300 includes loading the substrate into a processing chamber. The processing chamber can be an epitaxial deposition chamber, e.g., the processing chamber 400 as shown Figure 4 in the figure. The processing chamber 400 can be positioned on a cluster tool, e.g., the cluster tool 501, as a processing chamber, e.g., at least one of the plurality of processing chambers 502, 503, 516, 518 as shown Figure 5 in the figure.

[0049] At operation 330, method 300 includes bringing the processing chamber to a deposition temperature. In one embodiment, the deposition temperature can be in the range of 200 °C to 800 °C. In another embodiment, the deposition temperature can be in the range of 400 °C to 800 °C. In yet another embodiment, the deposition temperature can be in the range of 600 °C to 700 °C. In yet another embodiment, the deposition temperature is 400 degrees Celsius or higher. The pressure in the processing chamber can be adjusted such that the reaction zone pressure is in the range of about 1 Torr to about 760 Torr, or in the range of about 1 Torr to about 600 Torr, or in the range of about 100 Torr to about 500 Torr, or in the range of about 200 Torr to about 400 Torr.

[0050] At operation 340, method 300 further includes injecting a pretreatment gas into the processing chamber and adsorbing it on the exposed dielectric surface (e.g., amorphous surface) and the exposed Si surface (e.g., crystalline surface). In another embodiment, operation 340 includes injecting a pretreatment gas into the processing chamber and adsorbing it on the exposed amorphous surface and the exposed crystalline surface. The pretreatment gas can be used for n-type epitaxial growth or p-type epitaxial growth. The pretreatment gas includes a molecule or a surface modifier that is configured to reduce the interfacial energy between the exposed dielectric surface and the exposed silicon surface, thereby promoting overgrowth of the dielectric surface from the silicon surface during operation 350. The molecule or the surface modifier can also act as an etchant on the exposed surface. In some embodiments, for n-type epitaxial growth, the molecule can be a Group V chloride, tri-tert-butylarsine (TBAs), triethylantimony (TESb), triethylarsine (TEAs), plasma ammonia (NH 3 ), plasma hydrogen (H), and / or plasma deuterium (D). Suitable Group V chlorides for n-type epitaxial growth include phosphorus chloride, arsenic chloride, and antimony chloride. In some embodiments with n-type epitaxial growth, the molecule is PCl 3 , AsCl 3 , or SbCl 3 . In some embodiments, for p-type epitaxial growth, the molecule can be a Group V chloride, triethylgallium (TEGa), triethylindium (TEIn), triethylaluminum (TEAl), plasma ammonia (NH 3 ), plasma hydrogen (H), and / or plasma deuterium (D). Suitable Group V chlorides for p-type epitaxial growth include gallium chloride, aluminum chloride, and indium chloride. In some embodiments with p-type epitaxial growth, the molecule is GaCl 3 , AlCl 3 , or InCl 3 .

[0051] In some embodiments, the pretreatment gas is accompanied by a carrier gas. Any suitable carrier gas can be used. The carrier gas can be an inert gas. The carrier gas can be selected from H2 , N 2 , argon, helium, or a combination of the foregoing.

[0052] In some embodiments, the exposed non-crystalline surface (e.g., dielectric surface) comprises silicon oxide (SiO), silicon dioxide (SiO 2 ), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or a combination of the foregoing.

[0053] In one or more embodiments, the silicon carbonitride film has the formula SiC y N z , where both y and z are greater than zero. In one or more embodiments, the silicon oxycarbide film has the formula SiO x C y , where both x and y are greater than zero. In one or more embodiments, the silicon oxycarbonitride has the formula SiO x C y N z , where x, y, and z are all greater than zero. In one or more embodiments, the silicon oxide film has the formula SiO x , where x is greater than zero, such as SiO or SiO 2 . In one or more embodiments, the silicon nitride film has the formula Si v N z , where v and z are greater than zero, such as Si 3 N 4 .

[0054] In some embodiments, operation 340 is performed for a time range of about 10 seconds to about 120 seconds, or a time range of about 10 seconds to about 60 seconds. In other embodiments, operation 340 is performed for a time range from about 20 seconds to about 40 seconds. Operation 340 can be operated within a pressure range of 200 Torr to 400 Torr. The flow rate of the pretreatment gas in operation 340 can be in the range of 1 sccm to about 1000 sccm. In other embodiments, the flow rate of the pretreatment gas in operation 340 can be in the range of 10 sccm to 100 sccm. The flow rate of the carrier gas during operation 340 can be in the range of about 5 slm to about 30 slm.

[0055] During operation 350, a deposition gas mixture is introduced into the processing chamber to grow epitaxial silicon layers 115a, 115b that form source / drain 114a, 114b. In at least one implementation, the deposition gas mixture includes a silicon source gas and an n-type dopant. Any suitable silicon source gas can be used. Examples of suitable silicon source gases include silane and chlorosilane, such as disilane (Si 2 H 6 ), tetrasilane (Si 4 H10 ) Trichlorosilane (Cl 3 SiH), Hexachlorodisilane (Si 2 Cl 6 ), Tetrachlorosilane (SiCl 4 ), Pentachlorodisilane (Cl 5 Si 2 H), Octachlorotrisilane (Cl 8 Si 3 ), or a combination of the above. Any suitable n-type dopant can be used. In at least one implementation, the n-type dopant precursor is a phosphorus-containing precursor, an antimony precursor, or a combination of the above. Examples of suitable antimony precursors include one or a combination of antimony, antimony trichloride, antimony tetrachloride, antimony pentachloride, triphenylantimony, antimony trihydride, antimony trioxide, antimony pentoxide, antimony trifluoride, antimony tribromide, antimony triiodide, antimony tribromide, antimony triiodide, antimony pentafluoride, triethylantimony, and trimethylantimony. Examples of suitable phosphorus-containing precursors include phosphine, trimethylphosphine, dimethylphosphine, triethylphosphine, diethylphosphine, tert-butylphosphine, or a combination of the above. Any suitable p-type dopant can be used. For example, GeH 4 , B 2 H 6 , BCl 3 , or a combination of the above.

[0056] In some embodiments for n-type deposition, the deposition gas mixture includes DCS / PH 3 , TCS / PH 3 , DCS / AsH 3 , Si 2 H 6 / PH 3 , Si 2 H 6 / PH 3 , Si 4 H 10 / PH 3 , or a combination of the above.

[0057] In some embodiments for p-type deposition, the deposition gas mixture includes DCS / GeH 4 / B 2 H 6 , SiH4 / GeH 4 / B 2 H 6 , SiH 4 / GeH 4 / BCl 3 , Si 2 H 6 / GeH 4 / B 2 H 6A combination of the above items or more.

[0058] The epitaxial deposition process performed at operation 350 can grow epitaxial silicon layers 115a, 115b from the first layer 106 of the multi-material layer 105, as Figure 2B shown. Since the first layer 106 in this example is made of a crystalline material such as silicon, the epitaxial deposition process of operation 350 can grow from the sidewalls 206 of the first layer 106 rather than from the spacers 110 (e.g., silicon dielectric layers).

[0059] Then, the epitaxial silicon layers 115a, 115b can be continuously grown to form a shaped structure, such as a diamond-like top structure, to form the source / drain regions and source / drain extension regions required for a horizontal gate-all-around (hGAA) semiconductor device on the substrate 102. Since the epitaxial growth process performed at operation 350 can provide a selective deposition process to form the epitaxial silicon layers 115a, 115b mainly on the top of the sidewalls 206 of the first layer 106, which is a silicon material, and on the substrate 102, which is also a silicon material (when the optional material layer 104 is absent), a gap (e.g., a pore, a space, or an air gap) can be formed near the sidewalls 210 of the spacers 110. The silicon material is inert to the dielectric material formed by the spacers 110. Therefore, during the epitaxial deposition process, a selective deposition process is achieved to mainly deposit the epitaxial silicon layers 115a, 115b on the top of the sidewalls 206 of the first layer 106 because the silicon material is mostly inert to the dielectric material formed by the spacers 110. If present, the gap formed on the top of the sidewalls 210 of the spacers 110 can then be used to form part of a nanowire spacer (together with the spacers 110) for the nanowire structure of a horizontal gate-all-around (hGAA) semiconductor device on the substrate.

[0060] The epitaxial silicon layers 115a, 115b that form the source / drains 114a, 114b can grow from each first layer 106 deposited on the substrate 102, and each first layer 106 is located within the multi-material layer 205, as Figure 2BAs shown. The epitaxial silicon layers 115a, 115b may have a thickness range from about 1 nanometer to about 10 nanometers. In the illustrated embodiment, the epitaxial silicon layers 115a, 115b are deposited on the first layer 106 made of a crystalline material such as Si and the exposed portion of the substrate 102, and the epitaxial silicon layers 115a, 115b are not deposited on the gate structure 112 or the spacer 110 made of a dielectric material. The pressure in the processing chamber can be adjusted such that the reaction zone pressure is in the range of about 1 to about 760 Torr, or in the range of about 1 Torr to about 600 Torr, or in the range of about 100 Torr to about 300 Torr, or in the range of about 200 Torr to about 300 Torr. In some embodiments, a carrier gas (such as nitrogen) may flow into the processing chamber at a flow rate of about 1 to 40 SLM (standard liters per minute).

[0061] The deposition gas mixture used in operation 350 includes a silicon-containing precursor, such as a chlorosilane precursor. Suitable chlorosilane precursors include dichlorosilane (DCS), trichlorosilane (TCS), or a combination of the above. The silicon-containing precursor may be co-flowed with a doping gas, such as an n-type doping gas or a p-type doping gas.

[0062] The deposition gas mixture used in operation 350 may further include a dopant gas, such as an n-type dopant or a p-type dopant. In some embodiments, the n-type dopant may be phosphorus (P), arsenic (As), antimony (Sb), and in gallium arsenide (GaAs) may be: sulfur (S), selenium (Se), tin (Sn), silicon (Si), and carbon (C). The p-type dopant includes but is not limited to boron (B). Exemplary dopant gases may include boron-containing gases such as BH 3 or phosphorus- or arsenic-containing gases such as PH 3 or AsH 3 where the concentration of impurities in the gas phase determines their concentration in the epitaxial silicon layers 115a, 115b. According to an exemplary embodiment, the epitaxial silicon layers 115a, 115b are formed of in-situ doped (i.e., during growth) epitaxial materials, such as in-situ doped epitaxial Si, carbon-doped silicon (Si:C), and / or SiGe. Using an in-situ doping process in operation 350 is merely an example. For example, a non-in-situ process may be used to introduce dopants into the epitaxial silicon layers 115a, 115b. Other doping techniques may also be utilized to incorporate dopants into the epitaxial silicon layers 115a, 115b. Doping techniques include but are not limited to ion implantation, gas-phase doping, plasma doping, plasma immersion ion implantation, cluster doping, immersion doping, liquid-phase doping, solid-phase doping, in-situ epitaxial growth, or any suitable combination of these techniques.

[0063] The deposition gas mixture may also include a carrier gas. Any suitable carrier gas may be used. The carrier gas may be an inert gas. For example, the deposition gas may further comprise H 2 , N 2 , argon, helium, or a combination of the foregoing.

[0064] In some embodiments, operation 340 and operation 350 completely overlap. In other embodiments, operation 340 and operation 350 partially overlap. In other embodiments, operation 340 and operation 350 do not overlap.

[0065] In some embodiments, operation 340 and operation 350 are performed only once. In other embodiments, operation 350 is performed only once, and operation 340 is performed twice - the first time before operation 350 and the second time after operation 350. In other embodiments, operation 340 and operation 350 are performed multiple times.

[0066] The overgrowth amount and uniformity in the epitaxial silicon layers 115a, 115b can be controlled by changing the processing conditions, such as the partial pressure of the pretreatment gas, the molecular ratio in the pretreatment gas, the processing temperature, the number of repetitions of operation 340 and operation 350, and / or the layer thickness.

[0067] In some embodiments, via operation 340, the pretreatment of the epitaxial silicon layers 115a, 115b is performed in a first processing chamber, and via operation 350, the gas deposition on the epitaxial silicon layers 115a, 115b is performed in a second processing chamber. In other embodiments, the pretreatment of the epitaxial silicon layers 115a, 115b and the deposition of the epitaxial silicon layers 115a, 115b are carried out in one chamber.

[0068] Figure 4FIG. 0 is a schematic side cross-sectional view of an exemplary processing chamber 400 that can be used to implement various embodiments of the deposition processes discussed in the present disclosure. Chamber 400 can be used to perform chemical vapor deposition, such as an epitaxial deposition process, although chamber 400 can be used for etching or other processes. Chamber 400 includes an outer shell structure 402 made of a process-resistant material, such as aluminum or stainless steel. The outer shell structure 402 encloses various functional elements of the processing chamber 400, such as a quartz chamber 404 that includes an upper chamber 406 and a lower chamber 408 that contain a processing space 410. A substrate support 412 made of a ceramic material or a graphite material coated with a silicon material, such as silicon carbide, is used to receive a substrate 414 within the quartz chamber 404. The substrate support 412 includes a lift mechanism 472 and a rotation mechanism 474 coupled to a substrate support assembly 464. The lift mechanism 472 can be used to move the substrate support 412 along a central axis "A". The rotation mechanism 474 can be used to rotate the substrate support 412 about the central axis "A". Reactive species from a precursor reactant material are applied to a processing surface 416 of the substrate 414, and by-products can then be removed from the processing surface 416.

[0069] Heating of the substrate 414 and / or the processing space 410 is provided by an energy source that can be a radiation source or a heat source. The radiation source can include UV, IR, and visible light frequency lamps, lasers, and light emitting diodes, or any combination thereof. The heat source can be a laser, a light emitting diode, and an incandescent lamp, or a combination thereof. In Figure 4 one embodiment shown, the energy source is a radiation source using lamps, such as an upper lamp module 418A and / or a lower lamp module 418B. In one embodiment, as Figure 4 shown, the lamp modules 418A, 418B are mounted horizontally. In one example, the upper lamp module 418A and the lower lamp module 418B are infrared lamps. Radiation from the lamp modules 418A and 418B travels through an upper quartz window 420 of the upper chamber 406 and through a lower quartz window 422 of the lower chamber 408. If desired, cooling gas for the upper chamber 406 enters via an inlet 424 and exits via an outlet 426.

[0070] Reactive species are provided to the quartz chamber 404 through the gas distribution assembly 428, and process by-products are removed from the processing space 410 through the exhaust assembly 430, which is typically in communication with a vacuum source (not shown). Precursors reactant materials as well as diluent, purge, and exhaust gases for the chamber 400 can enter via the gas distribution assembly 428 and exit via the exhaust assembly 430. The processing chamber 400 includes a plurality of gaskets 432A through 432G. The gaskets 432A through 432G shield the processing space 410 from isolation from the metal wall 434 surrounding the processing space 410. In one embodiment, the gaskets 432A through 432G include a process kit that covers all metal components that can communicate with or otherwise be exposed to the processing volume 410.

[0071] The lower gasket 432A is disposed in the lower chamber 408. The upper gasket 432B is at least partially disposed in the lower chamber 408 and is adjacent to the lower gasket 432A. The exhaust insert gasket assembly 432C is disposed near the upper gasket 432B. In Figure 4 it, the exhaust insert gasket 432D is disposed adjacent to the exhaust insert gasket assembly 432C and can replace a portion of the upper gasket 432B to facilitate installation. The injector gasket 432E is shown on the side of the processing space 410 opposite to the exhaust insert gasket assembly 432C and the exhaust gasket 432D. The injector gasket 432E is configured as a manifold to provide one or more fluids, such as gases or plasmas of gases, to the processing space 410. One or more fluids are provided to the injector gasket 432E through the injection insert gasket assembly 432F. The baffle gasket 432G is coupled to the injection insert gasket assembly 432F. The baffle gasket 432G is coupled to the first gas source 435A and the second gas source 435B and provides gases to the injection insert gasket assembly 432F and the gas outlets 436A and 436B formed in the injector gasket 432E.

[0072] In one embodiment, one or more gases are provided from the first gas source 435A, the second gas source 435B, and the third gas source 435C to the processing space 410 via the baffle gasket 432G, the injection insert gasket assembly 432F, and via one or more gas outlets 436A and 436B formed in the injector gasket 432E. One or more gas outlets 436A and 436B formed in the injector gasket 432E are coupled to outlets configured as angled / layered flow paths 433A or 433B. As will be discussed in more detail below, one or more gas outlets 436A are at different angles relative to an axis "A" parallel to the substrate surface to adjust film uniformity on the substrate. The gas outlets 436A and 436B are configured to provide single or multiple gas flows with different parameters, such as velocity, density, or composition.

[0073] In one embodiment employing multiple gas outlets 436A and 436B, the gas outlets 436A and 436B may be distributed along a portion of the circumference of the gas distribution assembly 428 (e.g., injector liner 432E) in a substantially linear arrangement to provide an airflow wide enough to substantially cover the diameter of the substrate. For example, each of the gas outlets 436A and 436B may be arranged in at least one linear group as much as possible to provide an airflow generally corresponding to the diameter of the substrate. The gas exiting the gas outlet 436A flows along the flow path 433B, which is generally at an angle with respect to the axis A' (substantially perpendicular to the longitudinal axis A of the chamber 400) and mixes with the gas exiting the gas outlet 436B. The gas or gas mixture flows over the entire surface of the substrate along the flow paths 433A, 433B and enters the gas chamber 437 in the exhaust liner 432D along the exhaust flow path 433C. The gas chamber 437 is coupled to an exhaust pump or a vacuum pump (not shown). In one embodiment, the gas chamber 437 is coupled to a manifold 439 that guides the exhaust flow path 433C in a direction substantially parallel to the longitudinal axis A'. At least the injection insert liner assembly 432F may be disposed through the injection cover 429 and is partially supported by the injection cover 429.

[0074] Figure 5 is a schematic diagram of a system 500 for processing a substrate according to one embodiment. The system 500 can be used to perform Figure 3 the operations of the method 300 shown. The system 500 includes a cluster tool 501. The cluster tool 501 of the system 500 includes one or more processing chambers 502, 503, 516, 518 (a plurality of processing chambers 502, 503, 516, 518 are shown) coupled to one or more transfer chambers 504 and 510.

[0075] The first transfer chamber 504 is coupled to one or more epitaxial chambers 502. The first transfer chamber 504 has a transfer robot 515 disposed at the center for transferring substrates between the epitaxial chamber 502, the etching chamber 503, and a plurality of transfer stations 506. The first transfer chamber 504 is coupled to the second transfer chamber 510 via the transfer station 506, and the second transfer chamber 510 is coupled to a cleaning chamber 516 for cleaning substrates and an annealing chamber 518. The second transfer chamber 510 has a transfer robot 514 disposed at the center for transferring substrates between a set of load lock chambers 512 and the cleaning chamber 516. The factory interface 520 is connected to the second transfer chamber 510 through the load lock chamber 512. The factory interface 520 is coupled to one or more cassettes 530 on the opposite side of the load lock chamber 512. The cassettes 530 are typically front opening unified pods (FOUPs) that can be accessed from the cleaning chamber where the cluster tool 501 is disposed.

[0076] In one embodiment of the operation, the substrate can first be transferred to the cleaning chamber 516 for pre-cleaning the substrate. Then the substrate is transferred to one or more etching chambers 503, where the substrate is exposed to atomic hydrogen radicals to etch the substrate and remove nodules from the substrate, as described in operation 310. Then the substrate is transferred to one or more processing chambers 502 to selectively grow an epitaxial layer on the substrate, as described in operations 340 and 350. Then, the substrate can be transferred to the annealing chamber 518, where the epitaxial layer formed on the substrate is annealed to the annealing temperature.

[0077] The first transfer chamber 504 and the second transfer chamber 510 are maintained under vacuum during operation, such that the transfer robots 514 and 515 transfer the substrate under vacuum between all the processing chambers, the load lock chamber 512, and the transfer station 506. Transferring the substrate under vacuum helps to reduce the chance of contamination, improve the quality of the deposited epitaxial film, and provide an optional pre-cleaning process before repeating the operations of injecting the pretreatment gas and introducing the deposition gas, operations 140 and 150. The present disclosure contemplates that one or more of the chambers shown in system 500 may not be clustered into the cluster tool 501. For example, one or both of the etching chamber 503 and / or the annealing chamber 518 in system 500 may be separated (not clustered) from the cluster tool 501 having the cleaning chamber 516 and the epitaxial chamber 502. When bringing back the substrate (from a separate etching chamber and a separate annealing chamber) to repeat the epitaxial operation, the use of the cleaning chamber 516 is present, unless the cluster tool 501 is capable of receiving a purified FOUP or a portable vacuum station to minimize contamination when the substrate is transferred out and into the cluster tool 501.

[0078] In Figure 5 the illustrated embodiment, the cleaning chamber 516, the epitaxial chamber 502, the etching chamber 503, and the annealing chamber 518 are different from each other. In one embodiment that can be combined with other embodiments, each of the processing chambers 502 and 503 is a single processing chamber, where each of operations 310, 320, 330, 340, 350, the repeating operation 340, and the repeating operation 350 is performed.

[0079] System 500 includes a non-transitory computer-readable medium 550 configured to control the operation of cluster tool 501. The non-transitory computer-readable medium 550 is coupled to pod 530, factory interface 520, load lock chamber 512, second transfer chamber 510, transfer robot 514, cleaning chamber 516, epitaxial chamber 502, first transfer chamber 504, transfer robot 515, etch chamber 503, and anneal chamber 518 to control their operation. The non-transitory computer-readable medium 550 includes instructions that, when executed, cause cleaning chamber 516, epitaxial chamber 502, etch chamber 503, and anneal chamber 518 to perform the operations of method 300. In one embodiment, which may be combined with other embodiments, the non-transitory computer-readable medium 550 is a controller that includes instructions.

[0080] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from its basic scope, and its scope is determined by the claims that follow.

Claims

1. A method of forming a semiconductor device, the method comprises: positioning a substrate in a processing chamber, the substrate having an exposed amorphous surface and an exposed crystalline surface; heating the processing chamber to a deposition temperature; injecting a pretreatment gas into the processing chamber, wherein the pretreatment gas comprises molecules configured to reduce the interfacial energy between the exposed amorphous surface and the exposed crystalline surface; and injecting a deposition gas into the processing chamber to selectively grow an n-type doped epitaxial silicon layer on the exposed crystalline surface.

2. The method of claim 1, wherein the molecules are group V chlorides.

3. The method according to claim 2, wherein the molecule is selected from the group consisting of PCl 3 , AsCl 3 and SbCl 3 .

4. The method of claim 1, wherein the injecting of the pretreatment gas and the injecting of the deposition gas at least partially overlap.

5. The method of claim 1, wherein the injecting of the pretreatment gas is completed before the injecting of the deposition gas.

6. The method of claim 1, wherein the injecting of the pretreatment gas and the injecting of the deposition gas are repeated sequentially multiple times.

7. The method of claim 1, the method further comprises: exposing the substrate to a dry etchant to remove contaminants from the surface of the substrate.

8. The method of claim 1, wherein the exposed amorphous surface comprises silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbide, silicon carbonitride, or a combination of the foregoing.

9. The dry etching of claim 1 comprises: Expose the substrate to H 2 , NF 3 , NH 3 and plasma by-products.

10. The method of claim 1, wherein the plurality of exposed silicon layers have a <110> structure.

11. The method of claim 1, wherein the temperature for deposition is 400 degrees Celsius or higher.

12. The method of claim 1, wherein the injecting of the pretreatment gas is performed at a pressure in the range of about 1 torr to about 760 torr.

13. A method of forming a semiconductor device, the method comprises: Position a substrate in a processing chamber, the substrate having a multi-material layer formed thereon, the multi-material layer including a plurality of Si 1-x Ge x layers with a plurality of exposed dielectric surfaces and a plurality of exposed silicon layers thereon; heating the processing chamber to a deposition temperature; injecting a pretreatment gas into the processing chamber, wherein the pretreatment gas comprises molecules configured to reduce the interfacial energy between the plurality of exposed dielectric surfaces and the plurality of exposed silicon layers; and injecting a deposition gas into the processing chamber to selectively grow an n-type doped epitaxial silicon layer on the exposed silicon layers.

14. The method according to claim 13, wherein the exposed dielectric surface comprises SiC y N z , where y is greater than or equal to zero and z is greater than zero.

15. The method of claim 13, wherein the molecules are group V chlorides.

16. The method according to claim 15, wherein the molecule is selected from the group consisting of PCl 3 , AsCl 3 and SbCl 3 .

17. A method of forming a semiconductor device, the method comprises: Position a substrate in a cleaning chamber, the substrate having a multi-material layer formed thereon, the multi-material layer including a plurality of dielectric surfaces and a plurality of silicon layers disposed on an outer surface of a plurality of Si 1-x Ge x layers, the plurality of Si 1-x Ge x layers being arranged in an alternating pattern with the plurality of silicon layers; exposing the substrate to a dry etchant to remove contaminants from the surface of the substrate; positioning the substrate in a processing chamber; heating the processing chamber to a deposition temperature; injecting a pretreatment gas into the processing chamber, wherein the pretreatment gas comprises molecules configured to reduce the interfacial energy between the dielectric surface and the silicon surface; and injecting a deposition gas into the processing chamber to selectively grow an n-type doped epitaxial silicon layer on the exposed silicon surface.

18. The method of claim 17, wherein the molecules are group V chlorides.

19. The method according to claim 17, wherein said injecting of the pretreatment gas and said injecting of the deposition gas are repeated multiple times in sequence.

20. The method according to claim 17, wherein said exposed dielectric surface comprises silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxynitride, or a combination of the foregoing.

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