Low area flip-flop architecture with improved hold time
By using the input multiplexer of the diode-connect transistor in the scan flip-flop, the hold time requirement in the scan mode is reduced, the problem of high hold time requirements in the prior art is solved, and a smaller circuit area and lower power usage is achieved.
Patent Information
- Application Number
- CN202380073879.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-17
- Publication Date
- 2025-05-30
AI Technical Summary
Existing scan flip-flops have high holding time requirements in scan mode, resulting in significant increase in chip design area, circuit area, wiring complexity and power use.
An input multiplexer including a diode-connection transistor is used to reduce the hold time requirement in the scanning mode by reducing the effective voltage of the transistor.
Reduces the hold time requirements of the scan flip-flop, reduces the circuit area, wiring complexity and power usage of the chip, while reducing the number of hold buffers.
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Figure CN120077570A_ABST
Abstract
Description
BACKGROUND OF THE INVENTION
[0001] A scan flip-flop is a storage device having separate scan and data inputs and scan and data outputs. A D flip-flop can be implemented for the scan flip-flop, where a 2x1 multiplexer is added at the data (D) input. The scan enable input of the scan flip-flop receives a control signal (e.g., an enable signal) that indicates the multiplexer to select between the D input (data or functional mode) or the scan (SD) input (scan mode). The selected input passes through the multiplexer. The flip-flop also has a setup time and a hold time. The setup time is the amount of time required for the input of the flip-flop to stabilize before the clock edge so that the input is correctly captured on the clock edge. The hold time is the minimum amount of time required for the input of the flip-flop to stabilize after the clock edge so that the input is correctly captured on the clock edge. SUMMARY OF THE INVENTION
[0002] According to at least one example of the present specification, a system includes a scan flip-flop that includes a data input, a clock input, a scan data input, a scan enable input, and an output. The scan flip-flop also includes a first transistor and a second transistor coupled to the data input. The scan flip-flop includes a third transistor coupled to the clock input and a fourth transistor coupled to an anti-clock input. The scan flip-flop also includes a fifth transistor coupled to the scan enable input and the first transistor. The scan flip-flop includes a sixth transistor coupled to an anti-scan enable input and the second transistor. The scan flip-flop also includes an input multiplexer that includes the first transistor, the second transistor, the fifth transistor, and the sixth transistor, and also includes a seventh transistor coupled to the scan data input, an eighth transistor coupled to the scan data input, a ninth transistor coupled to the scan enable input, and a tenth transistor coupled to the anti-scan enable input. The input multiplexer also includes a first diode-connected transistor coupled between a first voltage rail and the seventh transistor. The input multiplexer also includes a second diode-connected transistor coupled between a second voltage rail and the eighth transistor.
[0003] According to at least one example of the present specification, a system includes a scan flip-flop, the scan flip-flop including a functional data input, a clock input, a scan data input, a scan enable input, and an output. The scan flip-flop further includes a first transistor and a second transistor coupled to the functional data input, wherein the functional data input is configured to receive a data signal. The scan flip-flop includes a third transistor coupled to the clock input and a fourth transistor coupled to an anti-clock input, wherein the clock input is configured to receive a clock signal, and the anti-clock input is configured to receive the inverse of the clock signal. The scan flip-flop includes a fifth transistor coupled to the scan enable input and the first transistor. The scan flip-flop further includes a sixth transistor coupled to an anti-scan enable input and the second transistor. The scan flip-flop includes an input multiplexer, the input multiplexer including the first transistor, the second transistor, the fifth transistor, and the sixth transistor, and further including a seventh transistor coupled to the scan data input, an eighth transistor coupled to the scan data input, a ninth transistor coupled to the scan enable input, and a tenth transistor coupled to the anti-scan enable input, wherein the input multiplexer is configured to select between the functional data input and the scan data input. The input multiplexer further includes a first diode-connected transistor coupled between a first voltage rail and the seventh transistor, wherein the first diode-connected transistor is configured to provide a first voltage to a source terminal of the seventh transistor, wherein the first voltage is less than a first supply voltage. The input multiplexer includes a second diode-connected transistor coupled between a second voltage rail and the eighth transistor, wherein the second diode-connected transistor is configured to provide a second voltage to a source terminal of the eighth transistor, wherein the second voltage is greater than a second supply voltage. Description of the Drawings
[0004] Figure 1 A circuit diagram of a part of a scan flip-flop with improved hold time according to various examples.
[0005] Figure 2 A block diagram of a part of a scan chain according to various examples.
[0006] Figure 3 A circuit diagram of a system including a scan flip-flop with improved hold time according to various examples.
[0007] The same reference numerals or other reference indicators are used in the drawings to denote (functionally and / or structurally) identical or similar features. Detailed Description
[0008] The hold time of a flip - flop is an important parameter for circuit design. The hold time is the minimum amount of time required for the inputs of a flip - flop to stabilize after a clock edge, thus correctly capturing the inputs at the clock edge. A higher hold time can impose design constraints on the circuit. For example, if a flip - flop has high hold - time requirements, hold buffers can be added to meet the hold constraints. Specifically, multiple scan flip - flops are often connected back - to - back in a scan chain to test for manufacturing faults in a chip. If several flip - flop - to - flip - flop transfer paths in the scan chain have multiple hold buffers to meet the hold constraints, the design area, circuit area, wiring complexity, and power consumption of the chip can increase significantly.
[0009] This document describes a scan flip - flop architecture that reduces the hold - time requirements of scan flip - flops in scan mode (e.g., when the scan - enable input is enabled). The scan flip - flop architecture includes an input multiplexer that selects between a D input (functional data mode) or an SD input (scan data mode). In one example, the input multiplexer includes two diode - connected transistors. Each diode - connected transistor is placed between a voltage rail and other components in the input multiplexer (e.g., one coupled to the positive voltage rail and one coupled to the negative voltage rail). The diode - connected transistors have their gate terminals and drain terminals shorted together, so they each operate in saturation. Compared to previous architectures, the diode - connected transistors reduce the effective voltage across the other transistors that make up the input multiplexer. Reducing the effective voltage across the transistors of the input multiplexer reduces the speed of those transistors. The lower voltage across the transistors increases the time for the transistors to charge or discharge any capacitive load coupled to the transistors, which reduces the switching speed of the transistors. Reducing the switching speed of the transistors in the input multiplexer reduces the hold - time requirements of the scan flip - flops in scan mode. At the reduced hold time, the number of hold buffers in the scan chain of the scan flip - flops can be reduced while still achieving the required performance of the circuit. By reducing the number of hold buffers, the circuit area, wiring complexity, and power consumption of the chip can be reduced.
[0010] Figure 1 FIG. 100 is a circuit diagram of an input multiplexer (e.g., input multiplexer 100) with a tri - state clock inverter having an improved hold time according to various examples of the present document. The input multiplexer 100 is part of a scan flip - flop according to various examples of the present document. The input multiplexer 100 includes a first voltage rail 102 that provides a voltage V DD to the input multiplexer 100. The input multiplexer 100 also includes a second voltage rail 104 that provides a voltage V SS to the input multiplexer 100. V DD and V SSIt may have any suitable value. In one example, the second voltage rail 104 may be coupled to a ground terminal.
[0011] The input multiplexer 100 includes a data (D) input 106, a scan data (SD) input 108, and a clock (CLK) input 110. In this example architecture, an anti-clock input CLKZ 112 is also provided. The input multiplexer 100 also includes a scan enable (SCAN) input 114 and an anti-scan enable (SCANZ) input 116. If the SCAN input 114 receives an input signal 1, the SD input 108 is enabled (e.g., scan mode). If the SCAN input 114 receives an input signal 0, the D input 106 is enabled (e.g., data mode or functional mode).
[0012] The input multiplexer 100 includes three "columns" of transistors, shown as columns 118, 120, and 122. In this example, the first column 118 includes the D input and has four transistors. In this example, the second column 120 is an SD stack (e.g., a stack of transistors including the SD input), and includes six transistors. In some examples, columns 118 and 120 may form a scan multiplexer 123 (e.g., the scan multiplexer 123). In some examples, the input multiplexer 100 may also be referred to as a scan multiplexer. The third column 122 is a tri-state clock inverter (e.g., clock tri-state), and includes the CLK input 110 and the CLKZ input 112. Details of these three columns of transistors are provided below.
[0013] Column 118 includes the D input 106, the SCAN input 114, and the SCANZ input 116. These three inputs are coupled to four transistors as shown. Transistor 124 may be referred to herein as the first transistor, and transistor 126 may be referred to herein as the second transistor. The D input 106 is coupled to the gates of transistor 124 and transistor 126. In this example, transistor 124 is a p-type transistor (e.g., a p-type device), such as a p-channel metal oxide semiconductor (PMOS) transistor. Transistor 126 is an n-type transistor (e.g., an n-type device), such as an n-channel metal oxide semiconductor (NMOS) transistor. The transistors described herein may be field effect transistors (FETs) in some examples, or other types of transistors in other examples. Transistor 124 includes a drain coupled to the drain of transistor 126. In the examples herein, the gate terminal may be referred to as the gate, the source terminal may be referred to as the source, and the drain terminal may be referred to as the drain.
[0014] Column 118 includes a SCAN input 114 coupled to the gate of transistor 128. Transistor 128 includes a source coupled to the first voltage rail 102 and a drain coupled to the source of transistor 124. In the examples herein, transistor 128 may be referred to as the fifth transistor (transistors described herein as the third and fourth transistors are described below). In this example, transistor 128 may be a p-type transistor.
[0015] Column 118 includes a SCANZ input 116 coupled to the gate of transistor 130. Transistor 130 includes a source coupled to the second voltage rail 104 and a drain coupled to the source of transistor 126. In the examples herein, transistor 130 may be referred to as the sixth transistor. In this example, transistor 130 may be an n-type transistor.
[0016] Column 122 includes a CLK input 110 coupled to the gate of transistor 132. The CLK input 110 is coupled to the gate of transistor 132. Transistor 132 includes a drain coupled to transistor 134 and a source coupled to transistor 136. In the examples herein, transistor 132 may be referred to as the third transistor. In this example, transistor 132 may be a p-type transistor. The drain of transistor 132 and the drain of transistor 134 are coupled at node 158. Additional circuitry described below with respect to Figure 3 may be coupled to node 158.
[0017] Column 122 includes a CLKZ input 112 coupled to the gate of transistor 134. The CLKZ input 112 is coupled to the gate of transistor 134. Transistor 134 includes a drain coupled to the drain of transistor 132 and a source coupled to the drain of transistor 138. In the examples herein, transistor 134 may be referred to as the fourth transistor. In this example, transistor 134 may be an n-type transistor.
[0018] Column 122 also includes transistor 136. Transistor 136 includes a gate coupled to the SDI (scan data input) node 140. Transistor 136 includes a source coupled to the first voltage rail 102 and a drain coupled to the source of transistor 132. In one example, transistor 136 may be a p-type transistor.
[0019] Column 122 also includes transistor 138. Transistor 138 includes a gate coupled to the SDI node 140. Transistor 138 includes a source coupled to the second voltage rail 104 and a drain coupled to the source of transistor 134. In one example, transistor 138 may be an n-type transistor.
[0020] Column 120 is an SD stack. The SDI node 140 is coupled to the drains of transistor 124 and transistor 126. Column 120 includes a transistor 142 having a gate coupled to the SD input 108. Transistor 142 includes a source coupled to the VDD_INT node 144 and a drain coupled to transistor 146. In the examples herein, transistor 142 may be referred to as the seventh transistor. In this example, transistor 142 may be a p-type transistor.
[0021] Column 120 includes a transistor 148 having a gate coupled to the SD input 108. Transistor 148 includes a source coupled to the VSS_INT node 150 and a drain coupled to transistor 152. In the examples herein, transistor 148 may be referred to as the eighth transistor. In this example, transistor 148 may be an n-type transistor.
[0022] Column 120 includes a transistor 146 having a gate coupled to the SCANZ input 116. Transistor 146 includes a source coupled to the source of transistor 142 and a drain coupled to the SDI node 140. In the examples herein, transistor 146 may be referred to as the tenth transistor. In this example, transistor 146 may be a p-type transistor.
[0023] Column 120 further includes a transistor 152 having a gate coupled to the SCAN input 114. Transistor 152 includes a source coupled to the source of transistor 148 and a drain coupled to the SDI node 140. In the examples herein, transistor 152 may be referred to as the ninth transistor. In this example, transistor 152 may be an n-type transistor.
[0024] Column 120 further includes two diode-connected transistors 154 and 156. Transistor 154 includes a gate coupled to the drain. The gate-drain connection is also referred to as the VDD_INT node 144. The source of transistor 154 is coupled to the first voltage rail 102 (e.g., a voltage source). In one example, transistor 154 may be referred to as the first diode-connected transistor. In this example, transistor 154 may be a p-type transistor.
[0025] Transistor 156 includes a gate coupled to the drain. The gate-drain connection is also referred to as the VSS_INT node 150. The source of transistor 156 is coupled to the second voltage rail 104. In one example, transistor 156 may be referred to as the second diode-connected transistor. In this example, transistor 156 may be an n-type transistor.
[0026] The scan multiplexer 123 (e.g., columns 118 and 120) selects between the data signal at the D input 106 and the data signal at the SD input 108. Depending on the value of the SCAN input 114, the selected input is passed through the scan multiplexer 123 to the SDI node 140. In operation, the diode-connected transistors 154 and 156 slow down the other transistors (142, 146, 148, and 152) in column 120. The diode-connected transistors 154 and 156 each have a gate terminal coupled to the drain terminal and thus operate similar to a diode. If the diode-connected transistors 154 and 156 were not present in column 120, the effective voltage difference across column 120 would be V DD -V SS , or the difference between the first voltage rail 102 and the second voltage rail 104. The voltage difference V DD -V SS would cause the transistors in column 120 to operate at a first speed, which would result in a first hold time for the scan flip-flop. The transistors would operate at a faster speed at the voltage difference of V DD -V SS , which increases the hold time requirement for the scan flip-flop in the scan mode.
[0027] By adding the diode-connected transistors 154 and 156, the voltage difference across column 120 (transistors 142, 146, 148, and 152, but not including transistors 154 and 156) is no longer V DD -V SS ; rather, the voltage difference across transistors 142, 146, 148, and 152 is VDD_INT - VSS_INT. The gate and drain of the diode-connected transistor 154 are shorted together, and the gate and drain of the diode-connected transistor 156 are shorted together. Thus, for the diode-connected transistors 154 and 156, the gate-to-source voltage is the same as the drain-to-source voltage (V GS = V DS ). The two diode-connected transistors 154 and 156 always operate in saturation. Because there is a voltage drop across each transistor, the voltage VDD_INT at the VDD_INT node 144 is smaller than V DD by an amount V DS . Similarly, the voltage VSS_INT at the VSS_INT node 150 is higher than V SS by an amount V DS .
[0028] In the absence of the diode-connected transistors 154 and 156, the effective voltage across column 120 would be V DD -V SS, but the voltage difference is reduced by two voltage drops caused by the diode-connected transistors 154 and 156 in the architecture shown in the input multiplexer 100. Through the diode-connected transistors 154 and 156, the voltage difference across column 120 (e.g., the SD stack) is VDD_INT - VSS_INT. Due to this reduced supply voltage across column 120, the speed of transistors 142, 146, 148, and 152 is reduced while charging or discharging, which reduces the hold time requirement of the input multiplexer 100 in the scan mode. In the input multiplexer 100, the transistors in column 120 operate at a second speed in the scan mode, which is slower than the first speed described above. The input multiplexer 100 has a second hold time, which is less than the first hold time in the absence of the diode-connected transistors 154 and 156.
[0029] The addition of the diode-connected transistors 154 and 156 reduces the hold time requirement of the input multiplexer 100 in the scan mode, and the increase in layout area is minimal. The addition of the diode-connected transistors 154 and 156 also does not affect other timing parameters, such as the setup time or hold time of the D input in the functional mode when the SCAN input 114 is 0. Reducing the speed of the transistors in column 120 increases the delay in column 120 (e.g., the delay of the scan data input path), which means that the hold time of the scan signal at the input (SD) of the input multiplexer 100 does not have to be as long as the hold time of the signal to be captured when the clock changes in the scan mode.
[0030] In other examples, only one diode-connected transistor may be used in column 120. For example, the diode-connected transistor 154 may be absent, which results in a voltage drop of V DD - VSS_INT across column 120. In another example, the diode-connected transistor 156 may be absent, which results in a voltage drop of VDD_INT - V SS across column 120. In some examples, one voltage drop caused by having either the diode-connected transistor 154 or the diode-connected transistor 156 may produce a desirable result regarding reducing the hold time requirement of the flip-flop.
[0031] In other examples, different circuit components may be used to provide the voltage drop instead of diode-connected transistors. For example, diodes, transistors, or other components may be used to provide the VDD_INT voltage and the VSS_INT voltage in column 120.
[0032] Figure 2A block diagram of a portion of scan chain 200 according to various examples of the present disclosure. Scan chain 200 includes scan flip - flops 202 and 204. Scan chain 200 also includes hold buffer 206 and clock buffer 208. Scan flip - flop 202 is referred to as the launch flip - flop, and scan flip - flop 204 is referred to as the capture flip - flop. Scan chain 200 also includes a CLK (clock) signal 210 and scan data 212.
[0033] A scan chain can be used to test a circuit for manufacturing faults. In a scan chain, a series of scan flip - flops are connected to the output Q of a first flip - flop, and the output Q is coupled to the SD input of the next flip - flop. A clock signal is provided to each flip - flop in the scan chain. The flip - flops are connected in a chain that effectively acts as a shift register.
[0034] Scan flip - flop 202 has a scan data input 214, a CLK input 216, and a Q output 218. Scan flip - flop 204 has a scan data input 220, a CLK input 222, and a Q output 224. In operation, scan data 212 is provided to scan flip - flop 202 via scan data input 214. When the first positive edge of the CLK signal 210 (launch CLK) arrives at the CLK input 216 after passing through at least some of the clock buffers 208, the data in scan flip - flop 202 is provided from the Q output 218 to scan flip - flop 204. The data passes through the hold buffer 206 before reaching the scan data input 220 of scan flip - flop 204. The number of hold buffers 206 determines the delay of the data before it reaches scan flip - flop 204. The hold buffer 206 delays the data to prevent a hold violation. A hold violation occurs if scan flip - flop 204 captures data at the wrong clock signal. For example, in this scan chain 200, scan flip - flop 204 should capture the data from scan flip - flop 202 on the next positive edge of CLK 210 after the positive edge that launches the data from scan flip - flop 202. Scan flip - flop 202 receives the first positive edge of CLK 210 to launch the data, and scan flip - flop 204 receives the second positive edge of CLK 210 (capture CLK) to capture the data. The hold buffer 206 and clock buffer 208 are provided to produce the proper timing of the clock and data that reaches each flip - flop in scan chain 200. In other examples, the systems described herein can be extended to negative - edge - triggered flip - flops to reduce the SD hold requirements.
[0035] In an example scan chain 200 in which the flip-flops use the input multiplexer 100 described herein, the hold time of each of the flip-flops in the scan chain is reduced. By reducing the hold time of each flip-flop in the scan chain 200, the number of hold buffers 206 in the scan chain 200 can be reduced. The string of hold buffers 206 involves a significant amount of wiring, area usage, and timing considerations to be implemented accurately. The use of the input multiplexer 100 in the flip-flops 202 and 204 in the scan chain 200 can reduce the number of hold buffers 206, which improves area usage and simplifies the wiring and timing of the circuit.
[0036] In the examples described herein, the hold time requirements for the SD inputs of the scan flip-flops can be reduced. The hold time requirements can be reduced for flip-flops with various temperature and supply voltage values. The hold time requirements for the flip-flops in the scan chain can also be reduced. A scan chain using the input multiplexer 100 as described herein can also result in a larger reduction in the number of hold buffers, which reduces the area, timing complexity, and wiring complexity of the circuit.
[0037] Figure 3 A scan flip-flop 300 according to various examples includes an input multiplexer having an improved hold time. Figure 3 Includes the input multiplexer 100 as described above with respect to Figure 1 and includes additional circuitry coupled to the input multiplexer 100 that may be present in the scan flip-flop in one example. Like reference numerals refer to like components. In the scan flip-flop 300, some transistors are shown as p-type transistors and some transistors are shown as n-type transistors, but different types of transistors may be used in other examples. The scan flip-flop 300 includes clock circuitry and a Q output 224, as well as additional circuitry.
[0038] The scan flip-flop 300 includes transistors 302 and 304. The gates of the transistors 302 are coupled to the gates of the transistors 304, and those gates are coupled to node 158 of the scan multiplexer 123. The transistor 302 may be a p-type transistor having a source coupled to the first voltage rail 102. The transistor 304 may be an n-type transistor having a source coupled to the second voltage rail 104.
[0039] The scan flip-flop 300 includes transistors 306, 308, 310, and 312 as shown. Transistors 306 and 308 can be p-type transistors, and transistors 310 and 312 can be n-type transistors. Transistor 306 has a source coupled to the first voltage rail 102 and a drain coupled to the source of transistor 308. The gate of transistor 306 is coupled to node 314. Transistor 308 has a drain coupled to the drain of transistor 310 and a gate coupled to the CLKZ input 112. Transistor 310 has a source coupled to the drain of transistor 312 and a gate coupled to the CLK input 110. Transistor 312 has a source coupled to the second voltage rail 104 and a gate coupled to node 314. In one example as described above, transistors 306, 308, 310, and 312 can form the third column 122 (e.g., clock tri-state). In one example, the scan multiplexer 123 and transistors 306, 308, 310, and 312 can form the input multiplexer 100.
[0040] The scan flip-flop 300 further includes transistors 316 and 318. Transistor 316 can be a p-type transistor, and transistor 318 can be an n-type transistor. Transistor 316 includes a drain coupled to node 314, a source coupled to node 320, and a gate coupled to the CLKZ input 112. Transistor 318 includes a drain coupled to node 314, a source coupled to node 320, and a gate coupled to the CLK input 110.
[0041] The scan flip-flop 300 includes transistors 322 and 324. Transistor 322 can be a p-type transistor, and transistor 324 can be an n-type transistor. Transistor 322 includes a source coupled to the first voltage rail 102, a gate coupled to node 320, and a drain coupled to the Q output 224. Transistor 324 includes a drain coupled to the second voltage rail 104, a gate coupled to node 320, and a source coupled to the Q output 224.
[0042] The scan flip-flop 300 includes transistors 326 and 328. Transistor 326 can be a p-type transistor, and transistor 328 can be an n-type transistor. Transistor 326 includes a source coupled to the first voltage rail 102, a gate coupled to node 320, and a drain coupled to node 330. Transistor 328 includes a drain coupled to the second voltage rail 104, a gate coupled to node 320, and a source coupled to node 330.
[0043] The scan flip-flop 300 also includes transistors 332, 334, 336, and 338. Transistors 332 and 334 may be p-type transistors, and transistors 336 and 338 may be n-type transistors. Transistor 332 has a drain coupled to the first voltage rail 102 and a source coupled to the drain of transistor 334. The gate of transistor 332 is coupled to node 330. Transistor 334 has a source coupled to the source of transistor 336 and a gate coupled to the CLKZ input 112. Transistor 336 has a drain coupled to the source of transistor 338 and a gate coupled to the CLK input 110. Transistor 338 has a drain coupled to the second voltage rail 104 and a gate coupled to node 330.
[0044] The scan flip-flop 300 is a scan flip-flop that includes the input multiplexer 100 as described above. The scan flip-flop 300 includes circuitry external to the input multiplexer 100 that can be used to manage the operation of the scan flip-flop. The scan flip-flop 300 receives inputs such as D input, SD input, SCAN input, SCANZ input, CLK input, etc. at the input multiplexer 100 as described above. The scan flip-flop 300 produces an output Q at the Q output 224 at an appropriate clock edge based on the inputs listed above. The scan flip-flop 300 is thus an example circuit that shows how the input multiplexer 100 can be implemented within a scan flip-flop.
[0045] In the examples herein, the effective voltage of some of the transistors in the input multiplexer of the scan flip-flop is reduced, which slows down the transistors in the input multiplexer (specifically, the transistors in column 120). This results in an improvement in the hold time requirement for the flip-flop during the scan mode. Significant improvements can be achieved for lower voltage devices. The reduction in the hold time requirement results in a smaller number of hold buffers for the flip-flop circuit, which reduces area usage and routing congestion. Also, the examples described herein do not affect other timing parameters such as setup time or clock-to-Q delay. In other examples, the systems described herein can be used for other flip-flop variants, such as those with asynchronous clear or preset inputs. The asynchronous inputs of the flip-flop control the output regardless of the clock input state.
[0046] The term "coupled" is used throughout this specification. The term can encompass connections, communications, or signal paths that achieve a functional relationship consistent with the description. For example, if device A generates a signal to control device B to perform an action, then: in a first example, device A is coupled to device B; or in a second example, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not substantially change the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A.
[0047] A device “configured to” perform a task or function can be configured (e.g., programmed and / or hardwired) at the time of manufacture by the manufacturer to perform the function, and / or can be configured (or reconfigured) by the user after manufacture to perform the function and / or other additional or alternative functions. The configuration can be performed by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.
[0048] A circuit or device described herein as including specific components can be physically coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) can actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and can be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, e.g., by an end user and / or a third party.
[0049] Although certain components may be described herein as belonging to a particular process technology, those components can be interchanged with components of other process technologies. The circuits described herein can be reconfigured to include replacement components to provide at least partially similar functionality to that available prior to component replacement. Unless otherwise stated, a component shown as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component can alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.
[0050] The use of the phrase “ground” in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this description. In this specification, unless otherwise indicated, “about,” “substantially,” or “essentially” before a parameter means within + / - 10% of the stated parameter. Modifications can be made in the described examples, and other examples are possible within the scope of the claims.
Claims
1. A system, which comprises: A scan flip-flop, which includes a data input, a clock input, a scan data input, a scan enable input, and an output, and wherein the scan flip-flop further includes: A first transistor and a second transistor, the first transistor and the second transistor being coupled to the data input; A third transistor and a fourth transistor, the third transistor being coupled to the clock input, and the fourth transistor being coupled to an anti-clock input; A fifth transistor, which is coupled to the scan enable input and the first transistor; A sixth transistor, which is coupled to an anti-scan enable input and the second transistor; And An input multiplexer, which includes the first transistor, the second transistor, the fifth transistor, and the sixth transistor, and further includes a seventh transistor coupled to the scan data input, an eighth transistor coupled to the scan data input, a ninth transistor coupled to the scan enable input, and a tenth transistor coupled to the anti-scan enable input, and wherein the input multiplexer further includes: A first diode-connected transistor, which is coupled between a first voltage rail and the seventh transistor; and A second diode-connected transistor, which is coupled between a second voltage rail and the eighth transistor.
2. The system according to claim 1, wherein the seventh transistor is coupled to the tenth transistor, and the eighth transistor is coupled to the ninth transistor.
3. The system according to claim 1, wherein the first transistor and the second transistor are coupled to the eighth transistor and the ninth transistor.
4. The system according to claim 1, wherein the first diode-connected transistor is a p-type device having a gate terminal coupled to a drain terminal.
5. The system according to claim 1, wherein the second diode-connected transistor is an n-type device having a gate terminal coupled to a drain terminal.
6. The system according to claim 1, wherein the seventh transistor and the tenth transistor are p-type devices, and the eighth transistor and the ninth transistor are n-type devices.
7. The system according to claim 1, wherein the first voltage rail is coupled to a voltage source, and the second voltage rail is coupled to ground.
8. The system according to claim 1, wherein the first transistor is a p-type device, and the second transistor is an n-type device.
9. The system according to claim 1, wherein the third transistor is a p-type device, and the fourth transistor is an n-type device.
10. The system according to claim 1, wherein the fifth transistor is coupled to the first voltage rail, and the sixth transistor is coupled to the second voltage rail.
11. A system, which comprises: A scan flip-flop, which includes a functional data input, a clock input, a scan data input, a scan enable input, and an output, and wherein the scan flip-flop further includes: A first transistor and a second transistor, the first transistor and the second transistor being coupled to the functional data input, wherein the functional data input is configured to receive a data signal; A third transistor and a fourth transistor, the third transistor being coupled to the clock input and the fourth transistor being coupled to an anti-clock input, wherein the clock input is configured to receive a clock signal and the anti-clock input is configured to receive the inverse of the clock signal; A fifth transistor, which is coupled to the scan enable input and the first transistor; A sixth transistor, which is coupled to the anti-scan enable input and the second transistor; And An input multiplexer, which includes the first transistor, the second transistor, the fifth transistor, and the sixth transistor, and further includes a seventh transistor coupled to the scan data input, an eighth transistor coupled to the scan data input, a ninth transistor coupled to the scan enable input, and a tenth transistor coupled to the anti-scan enable input, wherein the input multiplexer is configured to select between the functional data input and the scan data input, and wherein the input multiplexer further includes: A first diode-connected transistor, which is coupled between a first voltage rail and the seventh transistor, wherein the first diode-connected transistor is configured to provide a first voltage to the source terminal of the seventh transistor, wherein the first voltage is less than a first supply voltage; And A second diode-connected transistor, which is coupled between a second voltage rail and the eighth transistor, wherein the second diode-connected transistor is configured to provide a second voltage to the source terminal of the eighth transistor, wherein the second voltage is greater than a second supply voltage.
12. The system according to claim 11, wherein the second supply voltage is ground.
13. The system according to claim 11, wherein providing the first voltage to the source terminal of the seventh transistor and providing the second voltage to the source terminal of the eighth transistor reduces the hold time requirement of the scan data input relative to the clock input.
14. The system according to claim 11, wherein the input multiplexer is configured to select between the functional data input and the scan data input based on a signal at the scan enable input.
15. The system according to claim 11, wherein the seventh transistor is coupled to the tenth transistor, and the eighth transistor is coupled to the ninth transistor.
16. The system according to claim 11, wherein the first diode-connected transistor is a p-type device having a gate terminal coupled to the drain terminal.
17. The system according to claim 11, wherein the second diode-connected transistor is an n-type device having a gate terminal coupled to the drain terminal.
18. The system according to claim 11, wherein the scan flip-flop is a negative edge-triggered flip-flop.
19. The system according to claim 11, wherein the scan flip-flop includes an asynchronous input.
20. The system according to claim 11, wherein supplying the first voltage to the source terminal of the seventh transistor and supplying the second voltage to the source terminal of the eighth transistor do not affect the hold time or setup requirements of the functional data input relative to the clock input.