Optimization of vertical transfer field effect transistor integration

Abstract

A vertical transfer field effect transistor (VTFET) includes: a plurality of FET structures on a substrate; the plurality of FET structures includes: a first n-type FET structure oriented in a first planar direction relative to the substrate; and a first p-type FET structure oriented in a second planar direction relative to the substrate; wherein the first n-type FET structure and the first p-type FET structure each include a FIN having a FIN height H, where H defines the FIN height orthogonal to a surface of the substrate, each FIN being configured to transport charge carriers along the FIN height orthogonal to the surface of the substrate.

Description

BACKGROUND OF THE INVENTION

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Patent Application No. 18 / 047,954, filed on October 19, 2022, entitled "OPTIMIZATION OF VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR INTEGRATION", which is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] The present invention relates to vertical transport field effect transistors (VTFETs). Specifically, the present invention relates to improvements in the performance and integration of VTFETs.

[0004] Related Art

[0005] For many years, semiconductor design and manufacturing have revolved around the use and integration of lateral field effect transistors (FETs). Briefly, lateral FETs are so described because charge carriers "laterally" travel through the device parallel to the surface of the device substrate. The maximum feature size in a lateral FET is limited by the connected gate pitch (CGP), which is a measure of the minimum distance between one transistor gate and another transistor gate. For example, Jagannathan et al. (Vertical Transport Nanosheet Technology for CMOS Scaling Beyond Lateral Transport Devices, IEDM 2021) noted that the gate length of a lateral FET is limited to about 0.3×CGP, the spacer width is limited to about 0.1×CGP, and the contact length is limited to about 0.3×CGP. Advancements in manufacturing technology mean that lateral FETs are reaching these fundamental scaling limits. However, adopting vertical transport field effect transistors VTFETs (i.e., where charge carriers move "vertically" perpendicular to the substrate surface) has the effect of removing the gate, spacer, and contact from the CGP, and thus provides continued scaling of device features.

[0006] Although VTFETs provide an advancement in device scaling compared to lateral FETs, there is still room for improving the performance and integration of VTFETs. SUMMARY OF THE INVENTION

[0007] A vertical transmission field-effect transistor (VTFET) includes: a plurality of FET structures located on a substrate; the plurality of FET structures including a first n-type FET structure oriented in a first planar direction with respect to the substrate; a first p-type FET structure oriented in a second planar direction with respect to the substrate; and the first n-type FET structure and the first p-type FET structure each include a channel that includes a FIN having a FIN height H, where H defines the FIN height orthogonal to the surface of the substrate, and each FIN is configured to transport charge carriers orthogonally to the surface of the substrate along the FIN height. A vertical transmission field-effect transistor VTFET (where the FIN is configured to transport charge carriers orthogonally to the surface of the substrate along the FIN height) provides scaling advantages not available in other FET structures (e.g., such as lateral FETs or FINFETs). Additionally, a first n-type structure oriented in a first planar direction with respect to the substrate and a first p-type structure oriented in a second planar direction with respect to the substrate are provided such that an optimal orientation of charge carrier mobility is achieved in both the p-type and n-type structures. This plane describes the crystal plane of the material (typically Si) for fabricating the n-type and p-type structures. In the case where both the n-type and p-type structures are oriented in the same direction, optimal mobility cannot be achieved in at least one of the structures.

[0008] The first planar direction can be oriented at 45 degrees with respect to the second planar direction. This orientation provides optimized charge carrier mobility in both the p-type and n-type devices.

[0009] The first n-type FET structure can include an NMOS transistor; and the first p-type FET structure can include a PMOS transistor. This provides enhanced charge carrier mobility in both the PMOS and NMOS structures and also provides integration with existing PMOS and NMOS technologies.

[0010] The substrate of the VTFET can be a (100) silicon substrate. The FIN of the PMOS transistor can be oriented in the <110> planar direction, while the FIN of the NMOS transistor can be oriented in the <100> planar direction. This orientation configuration between the silicon substrate and the PMOS and NMOS transistors provides optimized charge carrier mobility in the channels of the PMOS and NMOS transistors.

[0011] The NMOS transistor and the PMOS transistor of the VTFET can be arranged in a vertical stacked configuration with respect to the surface of the substrate to form a vertical transmission complementary FET (VTCFET). The integration of the NMOS and PMOS in this stacked manner provides an efficient use of circuit area and also provides an enhanced CMOS structure with optimized mobility in both the P-channel and N-channel.

[0012] The stacked structure can be customized to meet the requirements and constraints of a given circuit requirement.

[0013] The n-type FET structure and p-type FET structure of the VTFET can include: a FIN width W and a FIN length L, where the FIN length is adjustable to provide a predefined effective channel width W for the channel eff Adjusting the FIN length in this way allows for the achievement of the desired W eff W eff = 2L + 2W, thus, where a specific W is required eff to meet the circuit specification or constraint, the adjustable L enables the achievement of the derived W eff This provides a great degree of flexibility in circuit design and manufacturing, as L can be adjusted in an "analog" manner to achieve a given effective channel width W eff where W eff is a key metric of device performance.

[0014] Each of the n-type FET structure and p-type FET structure of the VTFET can also include a gate structure that surrounds the channel. This structure provides a gate-all-around GAA structure that maximizes the amount of gate surface available for charge carrier transport in the device.

[0015] A method of manufacturing a vertical transmission field effect transistor (VTFET) includes forming a plurality of FET structures on a substrate; the plurality of FET structures including: a first n-type FET structure oriented in a first planar direction relative to the substrate; and a first p-type FET structure oriented in a second planar direction relative to the substrate; wherein the first n-type FET structure and the first p-type FET structure each include a channel that includes a FIN having a FIN height H, where H defines the FIN height orthogonal to the surface of the substrate, and each FIN is configured to transport charge carriers orthogonally to the surface of the substrate along the FIN height. Manufacturing the VTFET in this way provides enhanced performance in the resulting device.

[0016] In this method, the first planar direction can be oriented at 45 degrees relative to the second planar direction. This orientation provides optimized charge carrier mobility in the p-type and n-type devices.

[0017] The first n-type FET structure can include an NMOS transistor; and the first p-type FET structure can include a PMOS transistor. This provides enhanced charge carrier mobility in the PMOS and NMOS structures and also provides integration with existing PMOS and NMOS technologies.

[0018] The substrate can be a (100) silicon substrate. The fins of the PMOS transistors can be oriented in the <110> plane direction. The fins of the NMOS transistors can be oriented in the <100> plane direction. This orientation configuration between the silicon substrate and the PMOS and NMOS transistors provides optimized charge carrier mobility in the channels of the PMOS and NMOS transistors.

[0019] The NMOS transistors and PMOS transistors can be arranged in a vertical stacked configuration relative to the surface of the substrate to form a vertical transmission complementary FET (VTCFET). Fabricating the NMOS and PMOS in this stacked manner provides an efficient use of circuit area and also provides an enhanced CMOS structure with optimized mobility in both the P-channel and N-channel.

[0020] Thus, a degree of tunability is provided in the method such that the structures can be arranged in the most suitable manner to meet the given circuit requirements.

[0021] The method can also include defining a fin width W and a fin length L, where the fin length is adjustable to provide a predefined effective channel width W for the channel. eff Adjusting the fin length in this way allows the desired W to be achieved. eff As noted, where a specific W is required eff to meet circuit specifications or constraints, L can be adjusted such that the derived W is obtained. eff This provides a high degree of flexibility in circuit design and fabrication as L can be adjusted in an "analog" manner to achieve a given W. eff

[0022] The method can also include forming a gate structure that surrounds the channel. Such an arrangement provides a GAA structure.

[0023] W eff is defined by the formula W eff = 2L + 2W. The present disclosure provides an arrangement where W eff can be adjusted or tuned by changing the fin length L.

[0024] The effective length L of the gate structure is defined based on the fin height. eff Since the fin height and the gate length are in the vertical direction orthogonal to the surface of the substrate, this provides a greater degree of control over L eff as the fin height can be defined by epitaxial growth during fabrication. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a representation of a FINFET structure according to the prior art. ​

[0026] Figure 2 is a representation of a VTFET structure according to the prior art.

[0027] Figure 3A is a representation of the orientation of an N-type structure on the substrate surface.

[0028] Figure 3B is a representation of the orientation of a P-type structure on the substrate surface.

[0029] Figure 4A is a top-down representation of a VTFET structure having a FIN length L1.

[0030] Figure 4B is a top-down representation of a VTFET structure having a FIN length L2.

[0031] Figure 4C is a top-down representation of a VTFET structure having a FIN length L3.

[0032] Figure 5A , Figure 5B and Figure 5C are representations of alternative VTFET structures according to the present invention.

[0033] Figure 6A , Figure 6B and Figure 6C are representations of alternative VTFET structures according to the present invention.

[0034] Figure 7A , Figure 7B and Figure 7C is Figure 4A , Figure 4B and Figure 4C a cross-sectional representation of the VTFET structure of.

[0035] Figure 8 shows the result of FIN patterning used in the fabrication of a VTFET structure according to the present invention.

[0036] Figure 9 shows the well patterning step used in the fabrication of a VTFET structure according to the present invention.

[0037] Figure 10 shows the oxide layer deposition and chemical mechanical polishing steps used in the fabrication of a VTFET structure according to the present invention.

[0038] Figure 11 shows the etching step used in the fabrication of a VTFET structure according to the present invention.

[0039] Figure 12Shows the patterning steps used in the fabrication of the VTFET structure according to the present invention.

[0040] Figure 13 Shows the gate formation steps used in the fabrication of the VTFET structure according to the present invention.

[0041] Figure 14 Shows the well formation steps used in the fabrication of the VTFET structure according to the present invention.

[0042] Figure 15 Shows the oxide layer deposition and chemical mechanical polishing steps used in the fabrication of the VTFET structure according to the present invention.

[0043] Figure 16 Shows the epitaxial layer deposition and contact formation steps used in the fabrication of the VTFET structure according to the present invention.

[0044] Figure 17 Is a representation of a vertical transfer complementary FET (VTCFET) structure according to the present invention.

[0045] Figure 18 Is a representation of a vertical transfer complementary FET (VTCFET) structure according to the present invention. Detailed Description

[0046] The present invention will now be described with reference to the accompanying drawings. Figure 1 Is a representation of a FINFET structure 100 according to the prior art. Structure 100 includes a silicon substrate 101 on which an oxide layer 102 is formed. A 3D FIN structure 103 forms a transfer channel 104 and transports charge carriers from a source 105 to a drain 106 through a gate structure 107. Note that the direction of travel of the charge carriers is parallel to the substrate surface. The FINFET transistor including a 3D structure such as Figure 1 shown in can provide improved charge carrier transport on a planar device and further provide an opportunity to increase the amount of effective width (W eff ) available in a given device area. W effEffectively increases the channel region of the device available for transporting electrons or holes and is thus a key metric of device performance. Thus, while offering improvements over previous planar structures, the FINFET itself presents some drawbacks. As has been pointed out, such structures are reaching their scaling limits. To maintain reliable functionality, the FIN elements of the FINFET structure must maintain a digital width W rather than an analog width for device driveability matching. Additionally, the FIN height H in a FINFET is fixed because an increase in H in such structures results in a higher device aspect ratio and a smaller process margin. Moreover, H in the FIN structure is fixed for all FINFETs. Thus, the individual FINFET H cannot be adjusted to adjust W eff 。

[0047] Thus, to increase W in such devices eff ,several additional FINs can be added. For such FINFET devices, W eff = N*(W eff Fin), where N is the number of FINs and W eff Fin is the effective width of a FIN. Thus, the FINFET W eff is "quantized" and can only be increased by a set factor, i.e., x2, x3, etc., depending only on the number of FINs. Additionally, increasing the number of FINs inevitably increases the size of the entire device.

[0048] Figure 2 is a representation of a vertical transport FET (VTFET) structure 200 according to the prior art. Refer to Figure 2, 201 and 202 are metal 0 layers. These can be made of, for example, copper. 203 is a drain contact and can be made of, for example, tungsten or cobalt. 204 is an epitaxial layer for forming the drain, which can be made of, for example, Si for NMOS devices or SiGe for PMOS devices. 205 and 206 are top spacers. These top spacers are used to isolate the gate and the contact, and can be made of, for example, silicon nitride SiN. 215 is a bottom spacer. Similarly, this is used to isolate the gate and the contact. 207 and 208 are capping layers for the gate. These capping layers can be formed of an oxide layer or of SiN. 217 is an oxide layer. 209 and 210 form a metal gate structure, while 216 is a high-k dielectric layer. 211 is a channel structure including a FIN, which functionally corresponds to the FIN of a FINFET structure. The VTFET includes a FIN having a height H, where H defines the FIN height orthogonal to the surface of the substrate, and the FIN is configured to transport charge carriers (electrons or holes) orthogonally to the surface of the substrate along the FIN height. Note that in this vertical structure, the FIN height H and the distance bridged by the FIN between the source and drain epitaxial regions are defined by the material height. This distance defines the effective gate length gateL eff . Therefore, an epitaxial process can be used to define the height and thus the effective gate length as layer-by-layer heights. This is more precise than the lithography process used to define the effective gate length in a FINFET structure. 212 is a substrate material. 213 is a well, which will be a P-well for NMOS devices and an N-well for PMOS devices. 214 is a bottom-side epitaxial layer for forming the source. This epitaxial layer can further provide stress and strain into the channel region to increase the mobility in the channel. The stress and strain can be provided by a slight mismatch between the atomic lattice structure of the epitaxial layer and the lattice structure of the channel. In NMOS devices, tensile stress is introduced into the channel, while for PMOS, compressive stress is introduced into the channel.

[0049] Figure 3A is a representation of the orientation of the N-type structure 300 on the substrate surface 301, while Figure 3B is a representation of the orientation of the P-type structure 302 on the substrate surface 301. In Figure 3A and Figure 3B , the structure is viewed from top to bottom on the substrate surface 301. Figure 3A and Figure 3B The gate structures 303, 304 and the channel structures 305, 306 of Figure 2 can correspond to these structures. The substrate 301 is a (100) silicon substrate. (100) used in this context is an indication of the crystal plane of the Si surface using Miller indices. These indices are used to indicate the orientation of the Si crystal structure. This orientation is generated by the growth direction of the silicon ingot from which the Si wafer is cut.

[0050] Thus, in the example provided, the Si wafer has been fabricated to present a (100) oriented surface on which additional structures can be fabricated. The n-type devices are fabricated in the <100> plane direction, while the p-type devices are fabricated at 45 degrees relative to the <100> Si plane direction in the <110> plane direction. The channel plane direction relative to the Si wafer can be changed by rotating the wafer plane or notch 45 degrees during fabrication.

[0051] Figure 3A The n-type device 300 of is shown as a NMOS gate-all-around (GAA) VTFET. In this GAA structure, it can be seen that the gate 303 surrounds the channel on four sides, i.e., "all-around". This is different from Figure 1 the FINFET structure of, where the gate only covers three sides of the channel and is interrupted by the substrate on the fourth channel side. The channel of the n-type structure 300 shown can be the channel of a NMOS transistor. Referring to Figure 3A , it can be seen that the channel 305 of the NMOS transistor can be oriented in the (100) surface plane relative to the substrate surface.

[0052] Figure 3B The p-type device 302 of is shown as a PMOS gate-all-around (GAA) VTFET. Similarly, it can be seen that the gate 304 surrounds the channel 306 on four sides. The channel of the p-type structure 302 can thus be the channel of a PMOS transistor. Referring to Figure 3B , it can be seen that the channel 306 of the PMOS transistor is oriented in the (110) surface plane relative to the substrate surface. Thus, this has the effect that the channels 305, 306 of the NMOS and PMOS structures are oriented at 45 degrees relative to each other. It should be noted that the orientation of the NMOS and PMOS structures in this configuration provides optimization of electron mobility in the NMOS structure and optimization of hole mobility in the PMOS structure. Specifically, it should be noted that providing the PMOS structure in the (110) surface plane orientation results in a significant enhancement of charge carrier mobility.

[0053] Thus, a vertical transmission field effect transistor (VTFET) can be provided that includes a plurality of FET structures, such as the GAA VTFET structures described on a substrate. The plurality of FET structures can include a first n-type structure oriented in a first plane direction relative to the substrate and a first p-type structure oriented in a second plane direction relative to the substrate.

[0054] The n-type and p-type structures of the VTFET can include FIN pattern regions having a FIN width W and a FIN length L, and the FIN length is adjustable to provide a predefined effective channel width W for the channel eff . Figure 4A ,Figure 4B and Figure 4C Examples of VTFET structures with different FIN lengths are shown in FIG. Figure 4A is a top-down representation of the VTFET structure 400A with a FIN length L1. Figure 4B is a top-down representation of a VTFET structure 400B having a FIN length L2. Figure 4C is a top-down representation of a VTFET structure 400C having a FIN length L3.

[0055] Figure 4A , Figure 4B and Figure 4C Each of the structures is shown as being fabricated on a bottom silicon layer 401A, 401B, 401C. Channels 402A, 402B, 402C including FIN structures 403A, 403B, 403C are shown. The drain contact is located on top of the channel 402A, 402B, 402C. Gate oxides 406A, 406B, 406C are shown surrounding the channel region. Two gate contacts 404A, 404B and 404C and a single source contact 407A, 407B, 407C are shown on each structure. Gate structures 408A, 408B, 408C are shown as GAA type gate structures. Note that the channel is also surrounded by the gate so that all four channel sides are exposed to the gate. The W of the channel eff According to the formula W eff =2L+2W definition. Therefore, Figure 4A W of the channel eff It is W eff =2L1+2W, Figure 4B W of the channel eff It is W eff =2L2+2W, Figure 4C W of the channel eff It is W eff =2L3+2W. Therefore, a great degree of flexibility is provided in the design and manufacturing stage to adjust the FIN length L according to the desired specifications. In this way, the FIN L can be adjusted until the desired W is met. eff Guidelines to provide W eff FINFET solutions do not offer this type of tunable adjustment, and W eff It may only increment or decrement a set or quantized amount depending on the number of FINs being used.

[0056] Figure 5A , Figure 5B and Figure 5C yes Figure 4A , Figure 4B and Figure 4CRepresentation of an alternative VTFET structure of the VTFET structure. Figure 5A Is a top-down representation of the VTFET structure 500A with a FIN length L1. Figure 5B Is a top-down representation of the VTFET structure 500B with a FIN length L2. Figure 5C Is a top-down representation of the VTFET structure 500C with a FIN length L3. Figure 5A 、 Figure 5B and Figure 5C Each of the structures in is shown as fabricated on bottom silicon layers 501A, 501B, 501C. Channels 502A, 502B, 502C that make up the FIN structures 503A, 503B, 503C are shown. Gate oxides 506A, 506B, 506C are shown surrounding the channel regions. In this alternative, compared with Figure 4A 、 Figure 4B and Figure 4C two gate contacts and a single source contact 507A, 507B, 507C, a single gate contact 504A, 504B, 504C is provided. 509A, 509B, and 509C are drain contacts. Gate structures 508A, 508B, 508C are shown. Note that the channels are also surrounded by gates such that all four channel sides are exposed to the gates. Also, the W of the channels eff is defined by the formula W eff = 2L + 2W. Thus, Figure 5A the W of the channel in eff is W eff = 2L1 + 2W, Figure 5B the W of the channel in eff is W eff = 2L2 + 2W, Figure 5C the W of the channel in eff is W eff = 2L3 + 2W.

[0057] Figure 6A 、 Figure 6B and Figure 6C are Figure 4A 、 Figure 4B and Figure 4C representation of an alternative VTFET structure of the VTFET structure. Figure 6A Is a top-down representation of the VTFET structure with a FIN length L1. Figure 6B Is a top-down representation of the VTFET structure with a FIN length L2. Figure 6C Is a top-down representation of the VTFET structure with a FIN length L3. Figure 6A 、 Figure 6B and Figure 6CEach of the structures is shown as fabricated on bottom silicon layers 601A, 601B, 601C. The channels that make up FIN structures 603A, 603B, 603C are shown. Gate oxides 606A, 606B, 606C are shown surrounding the channel regions. In this alternative, two source contacts 607A, 607B, 607C are provided as compared to a single source contact for Figure 4A , Figure 4B and Figure 4C . In this alternative, a single gate contact 604A, 604B, 604C is provided. 609A, 609B, and 609C are drain contacts. Gate structures 608A, 608B, 608C are shown. Note that the channels are also surrounded by the gate such that all four channel sides are exposed to the gate. Also, the W of the channel eff is defined by the formula W eff = 2L + 2W. Thus, Figure 6A the W of the channel in eff is W eff = 2L1 + 2W, Figure 6B the W of the channel in eff is W eff = 2L2 + 2W, Figure 6C the W of the channel in eff is W eff = 2L3 + 2W.

[0058] Figure 7A , Figure 7B and Figure 7C provide cross-sectional representations of the VTFET structures 700A, 700B, 700C of Figure 4A , Figure 4B and Figure 4C . 703A, 703B, and 703C are drain contacts. 704A, 704B, 704C are the epitaxial layers of the drain. 705A, 705B, and 705C, 706A, 706B, and 706C are top spacers. 715A, 715B, and 715C are bottom spacers. 707A, 707B, and 707C and 708A, 708B, and 708C are capping layers for the gate. 717A, 717B, and 717C are oxide layers. 709A, 709B, 709C, 710A, 710B, and 710C form the gate structures. 711A, 711B, and 711C are channels. 712A, 712B, and 712C are substrate materials. 713A, 713B, and 713C are wells which will be P-wells for NMOS devices and N-wells for PMOS devices. 714A, 714B, and 714C are bottom-side epitaxial layers for forming the source.

[0059] Now will be described as Figures 4A to 4C and Figures 7A to 7CFabrication of the structure shown. Figure 8 The result of FIN patterning used in the fabrication of a VTFET structure according to the present invention is shown. A well 801 is formed on a substrate 800 by introducing dopants into the substrate. The substrate can be a (100) silicon substrate. A P-well can be formed for NFET devices, while an N-well can be formed for PFET devices. Channel material can be etched or deposited from the substrate to provide a channel FIN structure to a specified W, L, and H. Gate oxides 802, 803, 804 are also provided. The FIN has a height H, where H defines the FIN height orthogonal to the surface of the substrate, and the FIN is configured to transport charge carriers orthogonally to the surface of the substrate along the FIN height. Note that, as described above, the channel of the PMOS transistor can be oriented in the <110> plane direction with respect to the substrate. The channel of the NMOS transistor can be oriented in the <100> plane direction with respect to the substrate.

[0060] Then oxide layers or silicon nitride SiN layers 805, 806, 807, and 808 are deposited and then etched to remove the oxide or SiN from the FIN sidewalls. Then well patterning can be performed as Figure 9 shown. This provides bottom wells 901, 902, 903 and bottom spacers 904, 905, 906. Patterning is performed by etching away regions of the well layer to provide a defined well structure 901, 902, 903. Figure 10 The deposition of an oxide layer 1000 is shown. Then chemical mechanical polishing (CMP) is performed.

[0061] Etching is performed to provide an oxide recess 1100 as Figure 11 shown. Then a SiN layer is deposited. This layer is patterned and then etched back to form Figure 12 the top spacers 1200, 1201, 1202 as in Figure 13 Next, in Figure 13 oxide is recessed to form a shallow trench isolation layer STI, and metal gates 1301, 1302, and 1303 are formed. Then the metal gates are patterned. The gate structure is formed to surround the channel sidewalls around the FIN width and FIN length to form a GAA structure as described above. A SiN film is deposited and etched back to form spacers 1304, 1305, 1306. In Figure 14 patterning and recessing are performed to provide bottom wells 1400, 1401, 1402 for the epitaxial layers 1403, 1404, 1405. The epitaxial layers form the source. The epitaxial layers are deposited and strain is provided to the channel due to the lattice mismatch between the epitaxial layer and the channel. In Figure 15 an oxide layer 1500 is deposited and chemical mechanical polishing is performed. This forms an interlayer dielectric ILD 1501. Subsequently, channel recesses 1502, 1503, 1504 are formed. In Figure 16In it, the epitaxial top layers 1600, 1601, 1602 are grown or deposited to form the drain. Further oxide deposition and chemical mechanical polishing are performed to form the second interlayer dielectric ILD 1603. In this way, a source structure is formed by depositing a first epitaxial layer at the first end of the FIN close to the substrate surface; and a drain structure is formed by depositing a second epitaxial layer at the second end of the FIN far from the substrate surface. Then, contacts 1604, 1605, 1606 and 1607, 1608, 1609 for the drain and source are formed. A voltage can be applied across the contacts to operate the device. The device shown can be placed or "stacked" above another such device to form a vertical transmission complementary FET as described herein. Figure 17 and Figure 18 shows such a vertical transmission complementary FET structure.

[0062] Figure 17 is a representation of a vertical transmission complementary FET structure. This structure arranges the NMOS transistor and the PMOS transistor in a vertical stacked configuration with respect to the substrate surface to form a vertical transmission complementary FET (VTCFET).

[0063] In the stacked configuration, the NMOS transistor of the VTFET can be arranged below the PMOS transistor. In the stacked configuration, the NMOS transistor of the VTFET can be arranged above the PMOS transistor. For example, in Figure 17 representation, the structures 1701, 1711, and 1721 can be configured (i.e., doped or the work function adjusted accordingly to provide n-type functionality) as NMOS transistors, while the structures 1731, 1741, and 1751 can be configured (i.e., doped or the work function adjusted accordingly to provide p-type functionality) as PMOS transistors. The opposite situation can also be provided, where the structures 1701, 1711, 1721 are configured as PMOS transistors and the structures 1731, 1741, 1751 are configured as NMOS transistors. Stacking and integrating PMOS and NMOS transistors thus provides a VTCFET structure. Therefore, the performance benefits of the vertical structure described herein can be provided in CMOS devices to utilize the existing benefits of CMOS over NMOS / PMOS, such as reduced power consumption and enhanced functionality. Figure 17 The arrangement of shows six FET structures 1701, 1711, 1721, 1731, 1741, and 1751 sharing a common substrate. Each FET includes with respect to Figures 4A to 4C and Figures 7A to 7CThe described features. Therefore, these features will not be further described herein. However, attention is drawn to the contact structure of the FETs. FET 1701 includes a drain contact 1702 and a source contact 1703. FET 1711 includes a drain contact 1712 and a source contact 1713. FET 1721 includes a drain contact 1722 and a source contact 1723. FET 1731 includes a drain contact 1732 and a source contact 1733. FET 1741 includes a drain contact 1742 and a source contact 1743. FET 1751 includes a drain contact 1752 and a source contact 1753. Each contact includes a metal layer surface contact (M0), resulting in a total of 12 metal contacts. This arrangement provides an effective stacking of the FET structures. However, an alternative arrangement may provide a reduced number of metal layer surface contacts.

[0064] Figure 18 is Figure 17 an alternative arrangement of the vertical transfer complementary FET structure of. Figure 18 The arrangement of shows six FET structures 1801, 1811, 1821, 1831, 1841, and 1851 sharing a common substrate. Again, each FET includes features with respect to Figures 4A to 4C and Figures 7A to 7C described. Therefore, these features will not be further described herein. However, attention is drawn to the contact structure of the FETs. FET 1801 includes a drain contact 1802 and a source contact (not visible in the cross-section of Figure 18 ). FET 1811 includes a drain contact 1812 and a source contact (not visible in the cross-section of Figure 18 ). FET 1821 includes a drain contact 1822 and a source contact (not visible in the cross-section of Figure 18 ). FET 1831 includes a drain contact 1832 and a source contact 1833. FET 1841 includes a drain contact 1842 and a source contact 1843. FET 1851 includes a drain contact 1852 and a source contact 1853. Note that the inversion of 1801, 1811, and 1821 with respect to 1831, 1841, and 1851 (and compared to 1701, 1711, and 1721) allows the drain contacts of 1801 and 1831 to be connected to a shared metal contact M0. Additionally, the drain contacts of 1811 and 1841 are connected to a shared metal contact, and the drain contacts of 1821 and 1851 are connected to a shared metal contact. This sharing of metal contacts for the drain structure, as shown in Figure 18 , provides nine metal layer surface contacts (M0), including three shared drain contacts and six source contacts (where three source contacts are not visible in Figure 18 ). This is in contrast to the 12 metal layer surface contacts of Figure 17 .

[0065] Although specific combinations of features are recited in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of each aspect. In fact, many of these features may be combined in ways not specifically recited in the claims and / or not disclosed in the specification. Although each dependent claim listed below may directly depend on only one claim, the disclosure of each aspect includes each dependent claim in combination with every other claim in the claim set. A phrase referring to "at least one" of a list of items refers to any combination of those items, including a single member. As an example, "at least one of a, b, or c" is intended to cover a, b, c, a - b, a - c, b - c, and a - b - c, as well as any combination having multiple of the same element (e.g., a - a, a - a - a, a - a - b, a - a - c, a - b - b, a - c - c, b - b, b - b - b, b - b - c, c - c, and c - c - c, or any other ordering of a, b, and c).

[0066] Any element, act, or instruction used herein should not be construed as critical or essential unless explicitly stated as such. Additionally, as used herein, the articles "a" and "an" are intended to include one or more items and may be used interchangeably with "one or more." Additionally, as used herein, the terms "set" and "group" are intended to include one or more items (e.g., related items, unrelated items, combinations of related and unrelated items, etc.) and may be used interchangeably with "one or more." If only intending to refer to a single item, the phrase "only one" or similar language will be used. Additionally, as used herein, the term "having" and the like are intended to be open - ended terms. Additionally, the phrase "based on" is intended to mean "at least partially based on" unless otherwise explicitly stated.

Claims

1. A vertical transmission field effect transistor (VTFET), comprising: a plurality of field effect transistor (FET) structures located on a substrate; the plurality of FET structures comprising: a first n-type FET structure oriented in a first planar direction with respect to the substrate; and a first p-type FET structure oriented in a second planar direction with respect to the substrate; wherein the first n-type FET structure and the first p-type FET structure each include a channel that includes a FIN having a FIN height H, where H defines the FIN height orthogonal to the surface of the substrate, and each FIN is configured to transport charge carriers orthogonally to the surface of the substrate along the FIN height.

2. The VTFET according to claim 1, wherein the first planar direction is oriented at 45 degrees with respect to the second planar direction.

3. The VTFET according to claim 1, wherein: the first n-type FET structure includes an NMOS transistor; and the first p-type FET structure includes a PMOS transistor.

4. The VTFET according to claim 3, wherein the substrate of the VTFET is a (100) silicon substrate.

5. The VTFET according to claim 4, wherein the FIN of the PMOS transistor is oriented in a planar direction with respect to the surface of the substrate.

6. The VTFET according to claim 4, wherein the FIN of the NMOS transistor is oriented in a planar direction with respect to the surface of the substrate.

7. The VTFET according to claim 3, wherein the NMOS transistor and the PMOS transistor of the VTFET are arranged in a vertical stacked configuration with respect to the surface of the substrate to form a vertical transmission complementary FET (VTCFET).

8. The VTFET according to claim 1, wherein each of the first n-type FET structure and the first p-type FET structure further comprises: FIN width W and FIN length L, where the FIN length is adjustable to provide a predefined effective channel width W for the channel eff .

9. The VTFET according to claim 1, wherein each of the first n-type FET structure and the first p-type FET structure further includes a gate structure that surrounds the channel.

10. A method of manufacturing a vertical transmission field effect transistor (VTFET), the method comprising: forming a plurality of FET structures on a substrate; the plurality of FET structures comprising: a first n-type FET structure oriented in a first planar direction with respect to the substrate; and a first p-type FET structure oriented in a second planar direction with respect to the substrate; wherein the first n-type FET structure and the first p-type FET structure each include a channel that includes a FIN having a FIN height H, where H defines the FIN height orthogonal to the surface of the substrate, and each FIN is configured to transport charge carriers orthogonally to the surface of the substrate along the FIN height.

11. The method according to claim 10, wherein the first planar direction is oriented at 45 degrees with respect to the second planar direction.

12. The method according to claim 11, wherein the first n-type FET structure includes an NMOS transistor; and the first p-type FET structure includes a PMOS transistor.

13. The method according to claim 12, wherein the substrate is a (100) silicon substrate.

14. The method according to claim 13, wherein the FIN of the PMOS transistor is oriented in a planar direction with respect to the substrate surface.

15. The method according to claim 13, wherein the FIN of the NMOS transistor is oriented in a planar direction with respect to the substrate surface.

16. The method according to claim 12, wherein the NMOS transistor and the PMOS transistor are arranged in a vertical stacked configuration with respect to the surface of the substrate to form a vertical transmission complementary FET (VTCFET).

17. The method according to claim 10, the method further comprises: Define the FIN width W and the FIN length L, where the FIN length is adjustable to provide a predefined effective channel width W for the channel eff .

18. The method according to claim 10, the method further comprises: forming a gate structure that surrounds the channel.

19. The method according to claim 17, wherein W eff is defined by the formula W eff = 2L + 2W 20. The method according to claim 18, wherein an effective length L of the gate structure eff is defined based on the FIN height.

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