Optoelectronic semiconductor body and optoelectronic semiconductor chip

Abstract

Optoelectronic semiconductor body (1) comprising a sequence of semiconductor layers (2) with an active region (20) intended for generating radiation, a first barrier region (21) and a second barrier region (22), wherein - the active area (20) is located between the first barrier area (21) and the second barrier area (22); - in the first barrier area (21) at least one load carrier barrier layer (3) is arranged which is tension-stressed; - the active area on a material system Al x In y Ga 1-x-y P is based on 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and x + y ≤ 1; - the charge carrier barrier layer has an Al content x of 0.52 ≤ x ≤ 0.7; - the first barrier area (21) has at least one further load carrier barrier layer (35) which is tension-stressed; - the first charge carrier barrier layer (3) and the further charge carrier barrier layer (35) are spaced apart by 50 nm and 200 nm inclusive, respectively, wherein the entire semiconductor material between the charge carrier barrier layer (3) and the further charge carrier barrier layer (35) is either unstressed or compressively strained; and - the further charge carrier barrier layer (35) is further away from the active area (20) than the charge carrier barrier layer (3) and has a higher Al content than the charge carrier barrier layer (3).

Description

[0001] The present application relates to an optoelectronic semiconductor body and an optoelectronic semiconductor chip.

[0002] Leakage currents can represent a significant loss mechanism in radiation-emitting devices such as LEDs, limiting their efficiency. For InGaAlP-based LEDs, this loss mechanism has been shown to be more pronounced at short wavelengths and to increase considerably with rising operating temperature.

[0003] The publication DE 200 19 477 U1 relates to a semiconductor chip for optoelectronics in which a photon-emitting zone is attached to a substrate.

[0004] In the publication JP H07- 235 733 A, a p-type barrier sheathing layer with tensile stress is described.

[0005] One task is to achieve improved efficiency in radiation emission.

[0006] This problem is solved by an optoelectronic semiconductor body with the features of claim 1 and by a semiconductor chip with the features of claim 10. Further embodiments and developments are the subject of the dependent claims.

[0007] According to one embodiment, an optoelectronic semiconductor body comprises a sequence of semiconductor layers with an active region for generating electromagnetic radiation, a first barrier region, and a second barrier region. The active region is located between the first and second barrier regions. Advantageously, the first and second barrier regions are different in terms of their conductor type. For example, the first barrier region can be p-type and the second barrier region n-type, or vice versa. At least one charge carrier barrier layer is arranged in the first barrier region and is subject to tensile stress.

[0008] It has been shown that leakage currents during the operation of the optoelectronic semiconductor body can be efficiently reduced by means of a tensile-stressed charge carrier barrier layer. This increases the efficiency of the optoelectronic semiconductor body.

[0009] In a tensile-stressed layer, a lattice constant of the layer along a principal plane of the layer is greater than the intrinsic lattice constant of the layer material. Analogously, semiconductor layers whose lattice constant is smaller than their intrinsic lattice constant are described as compression-stressed.

[0010] In a preferred embodiment, the relative lattice mismatch of the charge carrier barrier layer is between 0.2% and 1%, particularly preferably between 0.3% and 0.7%. The relative lattice mismatch is the ratio of the difference between the lattice constant g of the layer and the intrinsic lattice constant g0 to the intrinsic lattice constant, i.e., (g-g0) / g0.

[0011] It has been found that such a relative lattice mismatch is particularly suitable for designing a charge carrier barrier layer in such a way that it efficiently reduces leakage currents and at the same time exhibits high crystal quality, in particular free from strain-reducing relaxations.

[0012] The charge carrier barrier layer can be configured as an electron barrier in a p-type first barrier region. Alternatively or additionally, the charge carrier barrier can also be configured as a hole barrier in an n-type first or second barrier region.

[0013] In a preferred embodiment, the active area is based on the compound semiconductor material system Al x In y Ga 1-x-y P with 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and x + y ≤ 1. This material system, which is also referred to below as a phosphide semiconductor material, is particularly suitable for the generation of radiation in the yellow to red spectral range.

[0014] However, the active region can be based on a different semiconductor material, in particular a different III-V compound semiconductor material. For example, nitride semiconductor material (Al) is suitable for generating radiation in the ultraviolet, blue, and green spectral ranges. x In y Ga 1-x-y N) and for the red to infrared spectral range, arsenide compound semiconductor material (Al x In y Ga 1-x-y As) . Here, 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and x + y ≤ 1 hold true in each case.

[0015] In a preferred embodiment, the charge carrier barrier layer has a higher aluminium content than the material adjacent to at least one side of the charge carrier barrier layer, and particularly preferably than the material adjacent to both sides of the charge carrier barrier layer.

[0016] Furthermore, the material adjacent to the charge carrier barrier layer is preferably lattice-matched or substantially lattice-matched with respect to gallium arsenide. In this context, substantially lattice-matched means that the relative lattice mismatch is at most 0.15%.

[0017] In a further embodiment, the charge carrier barrier layer has an aluminum content x between 0.52 and 0.7 inclusive. In phosphide semiconductor material deposited on gallium arsenide, the charge carrier barrier layer is therefore under tension relative to the gallium arsenide.

[0018] In a further embodiment, the charge carrier barrier layer has a thickness between 1 nm and 25 nm, particularly preferably between 3 nm and 20 nm.

[0019] A charge carrier barrier layer of this thickness, particularly in conjunction with the aforementioned relative lattice mismatch, can form a barrier that efficiently reduces leakage currents and whose thickness is below the critical layer thickness. The critical layer thickness for a semiconductor layer is a material-specific upper limit for the growth of a strained semiconductor layer. Above the critical layer thickness, strain reduction in the form of dislocations, which impairs crystal quality, is typical. The smaller the relative lattice mismatch, the greater the critical layer thickness typically is.

[0020] In a further development, the first barrier region has at least one additional charge carrier barrier layer. This charge carrier barrier layer and the additional charge carrier barrier layer represent a barrier for the same type of charge, for example, for electrons in a p-type first barrier region.

[0021] The first charge carrier barrier layer and the second charge carrier barrier layer are preferably spaced apart by 3 nm and 200 nm, inclusive. In particular, the first charge carrier barrier layer and the second charge carrier barrier layer can be spaced apart by 50 nm and 200 nm, inclusive.

[0022] Advantageously, the additional charge carrier barrier layer is also tension-stressed. In particular, the additional charge carrier barrier layer can have at least one or more of the features mentioned above in connection with the charge carrier barrier layer.

[0023] The semiconductor material between the charge carrier barrier layer and the subsequent charge carrier barrier layer can be strain-free. Alternatively, an intermediate layer can be arranged between the charge carrier barrier layer and the subsequent charge carrier barrier layer, which is compression-stressed.

[0024] The stress on the charge carrier barrier layer can be at least partially compensated by means of the pressure-stressed intermediate layer. Such stress compensation prevents the total stress on the semiconductor material from leading to the formation of dislocations.

[0025] In a preferred further development, the secondary charge carrier barrier layer is located further from the active area than the primary charge carrier barrier layer and has a higher aluminum content. The secondary charge carrier barrier layer is therefore under greater tensile stress than the primary charge carrier barrier layer and thus represents a larger charge carrier barrier. Due to the greater stress, the risk of relaxation and a resulting reduction in barrier effectiveness is increased. However, in the event of such relaxation, the upstream charge carrier barrier layer with its lower aluminum content still ensures a barrier effect for the charge carriers.

[0026] The active region preferably exhibits a quantum structure with at least one quantum layer. The term quantum structure here does not imply any restriction regarding the dimensionality of the quantization and includes, in particular, quantum wells, quantum rods, and quantum dots.

[0027] The charge carrier barrier layer is preferably located between 10 nm and 900 nm, and particularly preferably between 100 nm and 600 nm, away from the quantum layer of the quantum structure nearest to the charge carrier barrier layer.

[0028] A particularly efficient barrier effect can be achieved by using a charge carrier barrier layer at this distance from the quantum layer.

[0029] An optoelectronic semiconductor chip preferably comprises a semiconductor body with the features described above and a support, wherein the semiconductor body is arranged on the support.

[0030] The support can, for example, be a growth substrate for the semiconductor layer sequence of the semiconductor body. For example, gallium arsenide is suitable as a growth substrate for phosphide compound semiconductor material.

[0031] Alternatively, the support can be different from a growth substrate for the semiconductor layer sequence. In this case, the support is connected to the semiconductor body by means of a metallurgical bond. In a metallurgical bond, the bonding partners, preferably prefabricated, are held together by atomic and / or molecular forces. A metallurgical bond can be achieved, for example, by means of a bonding agent, such as an adhesive or solder. As a rule, separation of the bond is accompanied by the destruction of the bonding agent and / or at least one of the bonding partners.

[0032] The support serves primarily to mechanically stabilize the semiconductor layer sequence. The growth substrate is no longer required for this purpose and can therefore be removed.

[0033] A semiconductor chip in which the substrate for the semiconductor layer sequence has been removed is also called a thin-film semiconductor chip. Preferably, a reflective layer, particularly a metallic one, is arranged between the semiconductor body and the substrate. Radiation generated in the active region and emitted towards the substrate can be reflected by the reflective layer and exit at a radiation emission surface of the semiconductor chip opposite the substrate.

[0034] The semiconductor chip can be characterized in particular by at least one of the following aspects, which are numbered and referenced for the sake of simplicity.

[0035] 1. Optoelectronic semiconductor body comprising a sequence of semiconductor layers with an active region intended for generating radiation, a first barrier region and a second barrier region, wherein - the active area is located between the first barrier area and the second barrier area; and - in the first barrier area at least one load carrier barrier layer is arranged which is tension-stressed.

[0036] 2. Optoelectronic semiconductor body according to aspect 1, wherein a relative lattice mismatch of the charge carrier barrier layer is between inclusive 0.2% and inclusive 1%.

[0037] 3. Optoelectronic semiconductor body according to aspect 1 or 2, wherein the active region is located on the material system Al x In y Ga 1-x-y P is based on 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and x + y ≤ 1.

[0038] 4. Optoelectronic semiconductor body according to one of the preceding aspects, wherein the charge carrier barrier layer has a higher Al content than the material adjacent to both sides of the charge carrier barrier layer.

[0039] 5. Optoelectronic semiconductor body according to one of the preceding aspects, where the charge carrier barrier layer has an Al content x of 0.52 ≤ x ≤ 0.7.

[0040] 6. Optoelectronic semiconductor body according to one of the preceding aspects, wherein the charge carrier barrier layer has a thickness between 1 nm inclusive and 25 nm inclusive.

[0041] 7. Optoelectronic semiconductor body according to one of the preceding aspects, wherein the first barrier area has at least one further tension-stressed load carrier barrier layer.

[0042] 8. Optoelectronic semiconductor body according to aspect 7, wherein the first charge carrier barrier layer and the further charge carrier barrier layer are spaced apart by between inclusive 3 nm and inclusive 200 nm.

[0043] 9. Optoelectronic semiconductor body according to aspect 7, wherein the first charge carrier barrier layer and the further charge carrier barrier layer are spaced apart by between 50 nm inclusive and 200 nm inclusive.

[0044] 10. Optoelectronic semiconductor body according to aspect 7, wherein the first charge carrier barrier layer and the further charge carrier barrier layer are spaced apart by between inclusive 3 nm and inclusive 100 nm.

[0045] 11. Optoelectronic semiconductor body according to one of aspects 7 to 10, wherein the additional charge carrier barrier layer is located further away from the active area than the charge carrier barrier layer and has a higher Al content than the charge carrier barrier layer.

[0046] 12. Optoelectronic semiconductor body according to one of aspects 7 to 11, wherein an intermediate layer is arranged between the charge carrier barrier layer and the further charge carrier barrier layer, which is pressure-stressed.

[0047] 13. Optoelectronic semiconductor body according to one of the preceding aspects, wherein the active region has a quantum structure with at least one quantum layer and the charge carrier barrier layer is located between 10 nm and 900 nm inclusive from the quantum layer of the quantum structure nearest to the charge carrier barrier layer.

[0048] 14. Optoelectronic semiconductor chip comprising a semiconductor body according to one of the preceding aspects, wherein the semiconductor body is arranged on a support.

[0049] 15. Optoelectronic semiconductor chip according to aspect 14, wherein a metallic mirror layer is arranged between the semiconductor body and the substrate.

[0050] Further features, designs and advantages will become apparent from the following description of the exemplary embodiments in conjunction with the figures.

[0051] They show: Fig. 1 and Fig. 2 each an embodiment of a semiconductor chip with a semiconductor body in schematic sectional view; Fig. 3 a schematic course of the band gap E G along a separation direction z according to an exemplary embodiment; Fig. 4A to 4C each show a section of the conductor band edge path E C for various embodiments; Fig. 5 Measurements of the emitted radiant power for various semiconductor chips emitting with an emission wavelength λ, with and without a charge carrier barrier layer; Fig. 6A to 6D each simulate a current density profile j along the deposition direction z for semiconductor bodies with charge carrier barrier layer ( Fig. 6B and Fig. 6D) and without a charge carrier barrier layer ( Fig. 6A and Fig. 6C) at various operating temperatures.

[0052] Identical, similar, or similarly effective elements in the figures are provided with the same reference symbols.

[0053] The figures and the relative sizes of the elements depicted within them are not to be considered to scale. Rather, individual elements, and in particular layer thicknesses, may be exaggerated for clarity and / or better understanding.

[0054] A first embodiment of a semiconductor chip 10 with a semiconductor body 1 is shown in Fig. Figure 1 is shown schematically. The following description is based on an example of a luminescent diode, for instance, a light-emitting diode with an active region for radiation generation based on phosphide compound semiconductor material. However, other III-V compound semiconductor materials can also be used, such as nitride compound semiconductor material or arsenide compound semiconductor material.

[0055] The semiconductor chip 10 comprises a semiconductor body 1 arranged on a support 5. In this embodiment, the support serves as the growth substrate for the preferably epitaxial deposition of the semiconductor layer sequence 2 of the semiconductor body 1, for example by MOCVD or MBE. Gallium arsenide is particularly suitable as a growth substrate.

[0056] The semiconductor layer sequence 2 extends in a vertical direction, i.e. in a direction perpendicular to a principal extension plane of the semiconductor layers of the semiconductor layer sequence 2, between a first principal surface 23 and a second principal surface 24 and forms the semiconductor body 1.

[0057] The semiconductor layer sequence 2 includes an active region 20 designed for generating radiation. The active region 20 has a quantum structure with a plurality of quantum layers 201, with a quantum barrier 202 arranged between adjacent quantum layers. For the sake of simplicity, only three quantum layers are shown. However, the number of quantum layers can be varied within wide limits. In particular, the active region can have between inclusive one and inclusive 200 quantum layers.

[0058] The semiconductor layer sequence 2 further comprises a first barrier region 21 and a second barrier region 22. The active region 20 is located between the first and second barrier regions. In the following description, the first barrier region 21 is p-type and the second barrier region 22 is n-type. The first barrier region 21 extends between the active region and the first main surface 23, and the second barrier region 22 extends between the active region and the second main surface 24. However, the semiconductor body 1 can also be configured with an inverted conductor type.

[0059] The semiconductor chip 10 further comprises a first contact 61 and a second contact 62. By applying an electrical voltage between the contacts, charge carriers can be injected from opposite sides into the active area 20 and recombine there by emitting radiation.

[0060] The first barrier region 21 has a charge carrier barrier layer 3. The charge carrier barrier layer 3 is tensile-stressed. In contrast, the material of the first barrier region adjacent to both sides of the charge carrier barrier layer is unstrained. For example, phosphide compound semiconductor material is suitable for a gallium arsenide growth substrate, in particular phosphide compound semiconductor material with an aluminum content between 48% and 51% and a corresponding indium content between 52% and 49%.

[0061] In particular, the material adjacent to the charge carrier barrier layer 3 can be free of gallium or substantially free of gallium, i.e., with a gallium content of at most 5%.

[0062] In the illustrated embodiment, the first barrier region 21 has a main region 212 and a contact region 211. The contact region 211 forms the first main surface 23. The charge carrier barrier layer 3 is arranged within the main region 212.

[0063] The contact area 211 can be based on arsenide compound semiconductor material. The contact area 211 can also be multilayered. In particular, the material directly adjacent to the main surface 23 can consist of p-doped gallium arsenide.

[0064] An ohmic contact to the first contact 61 can thus be achieved more easily. Alternatively, such a contact area made of arsenide compound semiconductor material can also be omitted.

[0065] The vertical extent of the main area 212 is preferably at least twice as large as the vertical extent of the contact area 211.

[0066] The relative lattice mismatch of the tension-stressed charge carrier barrier layer 3 is preferably between 0.2% and 1%, and in particular between 0.3% and 0.7%.

[0067] The thickness of the charge carrier barrier layer is preferably between 1 nm and 5 nm, and particularly preferably between 3 nm and 20 nm.

[0068] Preferably, the relative lattice mismatch of the charge carrier barrier layer 3 and the thickness of the charge carrier barrier layer are matched such that the charge carrier barrier layer does not exceed the critical layer thickness. Thus, the smaller the relative lattice mismatch, the greater the thickness of the charge carrier barrier layer can be, and vice versa.

[0069] A distance d between the quantum layer 201 of the active region 20 nearest to the barrier region 21 and the charge carrier barrier layer 3 is preferably between 10 nm and 900 nm, and particularly preferably between 100 nm and 600 nm.

[0070] The semiconductor material of the first barrier region 21 does not necessarily have to be deposited with continuous p-type doping. For example, a subregion, in particular the charge carrier barrier layer 3, may be nominally undoped. Doping of the nominally undoped layer can occur through back-diffusion of the subsequently deposited semiconductor material.

[0071] The p-doping of the first barrier region 21 can be achieved, for example, using magnesium and / or carbon. In particular, the main region 212 can be doped with magnesium and the contact region 211 with carbon. Tellurium or silicon, for example, are suitable for n-doping.

[0072] The charge carrier barrier layer 3 preferably has a higher aluminum content than the material adjacent to both sides of the charge carrier barrier layer. In particular, the aluminum content can be between 0.52 and 0.7 inclusive. The higher the aluminum content, the larger the band gap E typically is. G of the material.

[0073] In a p-type first barrier region 21, the charge carrier barrier layer 3 is designed as an electron barrier. The electron barrier reduces the proportion of electrons that pass through the active region 20 without radiative recombination and reach the first contact 61.

[0074] It has been shown that an efficient electron barrier can be formed by the described tensile-stressed charge carrier barrier layer, even though the tensile stress can slightly counteract the barrier effect.

[0075] Furthermore, it has been shown that positioning the charge carrier barrier layer 3 in a highly doped area, for example with a doping of at least 1*10 18 cm -3This represents a comparatively large barrier for minority charge carriers, i.e., for electrons in a p-type region, and simultaneously a comparatively small barrier for majority charge carriers, i.e., holes in the p-type region. The band discontinuities at the interface between the charge carrier barrier layer and the adjacent material of the first barrier region 21 therefore occur predominantly in the conduction band.

[0076] Furthermore, a comparatively strong doping in the material of the first barrier region 21 adjacent to the charge carrier barrier layer 3 causes the depletion zone in the area of ​​the band discontinuities to be small and the Fermi level to be located close to the band edge.

[0077] In a deviation from the described configuration, the first barrier region 21 can also be n-type. In this case, the charge carrier barrier layer 3 formed in the first barrier region is a hole barrier. Furthermore, in addition to the charge carrier barrier layer in the first barrier region 21, a charge carrier barrier layer can also be formed in the second barrier region 22. In this case, the semiconductor body can have both an electron barrier and a hole barrier.

[0078] The in Fig. The second embodiment shown in section 2 essentially corresponds to the one described in connection with Fig. The embodiment described in Figure 1 differs from the carrier 5, which is a growth substrate for the semiconductor layer sequence 2. The carrier 5 serves primarily to mechanically stabilize the semiconductor layer sequence 2, thus eliminating the need for the growth substrate, which can be removed. The semiconductor chip 10 is therefore designed as a thin-film semiconductor chip.

[0079] The semiconductor layer sequence 2 is materially bonded to the support 5 by means of a bonding layer 71, for example by means of a solder layer or an electrically conductive adhesive layer.

[0080] A mirror layer 72 is arranged on the first main surface 23 of the semiconductor layer sequence 2, which reflects radiation generated in the active region 20 and emitted in the direction of the support 5. The emission from the semiconductor chip occurs predominantly, preferably to at least 70%, through the second main surface 24 of the semiconductor body 1, which faces away from the support 5.

[0081] Furthermore, in contrast to the first embodiment, the second barrier region 22 has a contact region 221 that adjoins the second main surface 24. The contact region 221 can be based on arsenide compound semiconductor material. However, such a contact region can also be omitted.

[0082] A schematic representation of the band gap E G along the separation direction z, i.e. along the vertical direction, is in Fig. Figure 3 is shown schematically. In the embodiment shown, the active region 20 has a plurality of quantum layers, for example one hundred quantum layers, so that the individual quantum layers cannot be resolved individually in the figure.

[0083] The charge carrier barrier layer 3 has a higher aluminum content and therefore a higher band gap than the semiconductor material adjacent to the charge carrier barrier layer 3 on both sides.

[0084] The semiconductor material of the first barrier region 21, which borders the charge carrier barrier layer 3 on both sides, has a higher aluminum content and thus a larger band gap than the quantum barriers 202 of the active region 20.

[0085] The first barrier region 21 itself already constitutes a charge carrier barrier, and the barrier effect is further enhanced by the tensile-stressed charge carrier barrier layer 3. Due to the design of the charge carrier barrier layer 3 below the critical layer thickness, the barrier effect for electrons in the p-type first barrier region 21 can be improved without reducing the material quality due to relaxation.

[0086] In the Fig. 4A to 4C each schematically represent the band edge profile E C of the conduction band shown in a section in which part of the active region 20 and the charge carrier barrier layer 3 can be seen.

[0087] At the in Fig. In the embodiment shown in Figure 4A, the first barrier region 21 has, in addition to the charge carrier barrier layer 3, two further charge carrier barrier layers 35. The distance between the charge carrier barrier layers is preferably between 3 nm and 200 nm, and particularly preferably between 50 nm and 200 nm.

[0088] In this embodiment, the charge carrier barrier layer 3 and the further charge carrier barrier layers 35 are each identical, particularly with regard to their aluminum content and their tension. The barrier effect is improved by increasing the number of charge carrier barrier layers.

[0089] In contrast to the similar design, the charge carrier barrier layers in the one in Fig. In the embodiment shown in 4B, increasing distance from the active area 20 results in a higher aluminium content and thus a higher degree of tensile stress.

[0090] The higher the aluminum content, the more effectively the charge carrier barrier layer 3, and subsequently the other charge carrier barrier layers 35, can function as an electron barrier. However, this also increases the risk of exceeding the critical layer thickness during manufacturing, thereby reducing the strain through relaxation. Preferably, the charge carrier barrier layer 3 with the lowest aluminum content is designed such that the critical layer thickness is not exceeded, even under process fluctuations. If the charge carrier barrier layers 35 with higher aluminum content, located further away from the active region, relax, a charge carrier barrier effect is ensured at least by the charge carrier barrier layer 3 closest to the active region.

[0091] At the in Fig. In the embodiment shown in Figure 4C, an intermediate layer 31 is arranged between adjacent charge carrier barrier layers 3, 35, wherein the intermediate layers are each compression-stressed. These intermediate layers are designed to compensate for the tension of the tension-stressed charge carrier barrier layers 3, 35, so that the sum of the layer thicknesses of the charge carrier barrier layers 3, 35 can also be above the critical layer thickness. The thickness of the intermediate layers 31, and thus the distance between adjacent charge carrier barrier layers, is preferably between 1 nm and 100 nm, and particularly preferably between 3 nm and 40 nm. With an intermediate layer 31 thickness of at most 10 nm, quantum effects can also be utilized.

[0092] Measurement results of the radiant power P for various semiconductor chips are in Fig. Figure 5 shows that the measured values ​​80 refer to semiconductor bodies with a charge carrier barrier layer and the measured values ​​90 to semiconductor bodies without a charge carrier barrier layer. The thickness of the charge carrier barrier layer is 15 nm in each case.

[0093] The measurements were performed at a temperature of 100 °C. Since the radiant power P also depends on the emission wavelength λ, wavelength-dependent straight lines are plotted as upper bounds 82 and 92, lower bounds 83 and 93, and mean values ​​81 and 91 for the measured values. Comparing the mean values, represented by arrow 95, reveals an increase in radiant power of 23%. Comparing the upper bounds, represented by arrow 96, shows an increase of 14%. Even comparing the mean value of the four semiconductor bodies with charge carrier barriers with the upper bound 92 for semiconductor bodies without charge carrier barriers still yields an increase of 10%. The measurements thus demonstrate that the charge carrier barrier layer 3 can significantly increase the efficiency of the semiconductor chips.

[0094] In the Fig. Figures 6A to 6D show simulation results for the current density j along the deposition direction z. The simulations were based on a semiconductor layer sequence with an active region containing 20 quantum wells and an emission wavelength of 600 nm. The simulations are each based on a current density j of 200 A / cm². 2 at a temperature of 100 °C ( Fig. 6A and Fig. 6B) and Fig. 20 °C ( Fig. 6C and Fig. 6D).

[0095] The Fig. 6A and Fig. 6C each relate to a comparison structure without a charge carrier barrier and the Fig. 6B and Fig. 6D a structure with a tensile-stressed 10 nm thick charge carrier barrier layer as an electron barrier with a band gap that is 40 meV larger than the band gap of the adjacent material of the first barrier region.

[0096] Curves 97 and 98 show the current density for holes and electrons, respectively. The value of curve 98 for z = 0 divided by the assumed current density of 200 A / cm² 2This represents the proportion of electrons that traverse the active region without recombination and therefore contribute no to radiation emission. Comparing these values, the charge carrier barrier layer 3 reduces this proportion from 23.3% to 20.9% at a temperature of 100 °C and from 3.8% to 3.2% at a temperature of 20 °C. Assuming a direct proportionality between the efficiency increase and the reduced leakage current, this would result in an increase of approximately 3% at 100 °C. However, the so-called photon recycling factor must also be considered for the actual expected increase in emitted radiation power. This factor indicates how many times a photon is absorbed and re-emitted before it leaves the semiconductor material.With a reduction in losses from 23.3% to 20.9% and a typical photon recycling factor of about 5, simulations suggest an increase in efficiency by a factor of ((1-0.209) / 1-0.233))^5 = 1.17, i.e. by about 17%.

[0097] The simulations thus demonstrate, in accordance with the findings in Fig. The measurements shown in Figure 5 demonstrate that the efficiency of radiation generation can be significantly improved by incorporating a tensile-stressed charge carrier barrier layer. Furthermore, this improvement can be achieved without making any substantial changes to the rest of the semiconductor chip manufacturing process.

Claims

[1] Optoelectronic semiconductor body (1) comprising a sequence of semiconductor layers (2) with an active region (20) intended for generating radiation, a first barrier region (21) and a second barrier region (22), wherein - the active area (20) is located between the first barrier area (21) and the second barrier area (22); - in the first barrier area (21) at least one load carrier barrier layer (3) is arranged which is tension-stressed; - the active area on a material system Al x In y Ga 1-x-y P is based on 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and x + y ≤ 1; - the charge carrier barrier layer has an Al content x of 0.52 ≤ x ≤ 0.7; - the first barrier area (21) has at least one further load carrier barrier layer (35) which is tension-stressed; - the first charge carrier barrier layer (3) and the further charge carrier barrier layer (35) are spaced apart by 50 nm and 200 nm inclusive, respectively, wherein the entire semiconductor material between the charge carrier barrier layer (3) and the further charge carrier barrier layer (35) is either unstressed or compressively strained; and - the further charge carrier barrier layer (35) is further away from the active area (20) than the charge carrier barrier layer (3) and has a higher Al content than the charge carrier barrier layer (3). [2] Optoelectronic semiconductor body according to claim 1, wherein a relative lattice mismatch of the charge carrier barrier layer (3) is between inclusive 0.2% and inclusive 1%. [3] Optoelectronic semiconductor body according to any of the preceding claims, wherein the material adjacent to the charge carrier barrier layer (3) is free of gallium or has a gallium content of at most 5%. [4] Optoelectronic semiconductor body according to one of the preceding claims, wherein the charge carrier barrier layer (3) has a higher Al content than the material adjacent on both sides of the charge carrier barrier layer (3). [5] Optoelectronic semiconductor body according to any of the preceding claims, wherein the charge carrier barrier layer (3) has a thickness between 1 nm inclusive and 25 nm inclusive. [6] Optoelectronic semiconductor body according to any of the preceding claims, wherein the charge carrier barrier layer (3) has a thickness between 3 nm inclusive and 20 nm inclusive. [7] Optoelectronic semiconductor body according to one of the preceding claims, wherein the first charge carrier barrier layer (3) and the further charge carrier barrier layer (35) are spaced apart from each other by between inclusive 50 nm and inclusive 100 nm. [8] Optoelectronic semiconductor body according to one of the preceding claims, wherein an intermediate layer (31) is arranged between the charge carrier barrier layer (3) and the further charge carrier barrier layer (35), which is pressure-stressed. [9] Optoelectronic semiconductor body according to one of the preceding claims, wherein the active region (20) has a quantum structure with at least one quantum layer (201) and the charge carrier barrier layer (3) is located between 10 nm and 900 nm away from the quantum layer (201) of the quantum structure that is closest to the charge carrier barrier layer (3). [10] Optoelectronic semiconductor chip with a semiconductor body (1) according to one of the preceding claims, wherein the semiconductor body is arranged on a support (5). [11] Optoelectronic semiconductor chip according to claim 10, wherein a metallic mirror layer (72) is arranged between the semiconductor body (1) and the support (5).

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