Mask, layout optimization method thereof and metal layer manufacturing method

Abstract

The application provides a mask layout optimization method and a metal layer manufacturing method, and belongs to the field of semiconductors. The mask layout optimization method comprises the following steps: obtaining an initial layout and design parameters of all patterns in the initial layout; in a first direction, adding a virtual pattern to sparse patterns located at edge positions in each sparse pattern area, the virtual pattern being distributed along a second direction; and widening the width of the virtual pattern to the area where the sparse area is located to obtain a target layout. By adding a virtual pattern to the side of the sparse pattern close to the sparse area, the sparse pattern is converted into a dense pattern, so that the original design parameters of the sparse pattern used for metal layer interconnection are maintained during photolithography, and the original sparse pattern does not need to be widened, thereby ensuring that the electrical properties of the device are not affected.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a photomask and its layout optimization method, and a method for fabricating a metal layer. Background Technology

[0002] With the rapid development of very large-scale integrated circuits (VLSI), integrated circuit manufacturing processes have become increasingly complex and sophisticated. Photolithography is a driving force behind this development and is one of the most complex technologies. Photolithography is a crucial method for transferring the design pattern of an integrated circuit from a photomask onto a silicon wafer using a photolithography machine. The photolithography process typically includes steps such as coating photoresist, exposure, development, and etching. Specifically, it involves: first, coating a layer of photoresist onto the substrate; then, transferring the pattern from the photomask to the photoresist through exposure; dissolving the exposed or unexposed areas of the photoresist through development; and finally, transferring the pattern onto the substrate through etching.

[0003] In the back-end metal interconnect process, the metal layer pattern on the photomask needs to be transferred to the metal layer. The layout of the metal layer pattern includes densely patterned regions and sparsely patterned regions. Densely patterned regions contain dense patterns, while sparsely patterned regions contain sparse patterns. Regarding exposure focusing, the process window for densely patterned metal layers is larger than that for sparsely patterned metal layers. When comparing the sparse pattern with the anchor point pattern, the sparse pattern exhibits a focus center offset. The anchor point pattern serves as an alignment reference for subsequent photolithography layers. A clear anchor point pattern can improve the overlay accuracy of multi-layer patterns. Therefore, sparse patterns present a technical challenge due to their smaller process window.

[0004] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a photomask and its layout optimization method, as well as a metal layer fabrication method, to solve the problem of small process windows in sparse patterns.

[0006] To solve the above technical problems, the present invention provides a method for optimizing a mask layout, comprising:

[0007] Obtain an initial layout and design parameters for all graphics in the initial layout. The initial layout includes several sparse graphic regions and empty regions. The empty regions are located outside the sparse graphic regions. Each sparse graphic region is provided with several sparse graphics. The several sparse graphics are distributed along a first direction.

[0008] Based on the design parameters of the graphics in the initial layout, the sparse regions of the graphics are selected.

[0009] Along the first direction, in each of the sparse regions of the graphic, a virtual graphic is added to the side of the sparse graphic located at the edge position that is close to the empty region, and the length of the virtual graphic is distributed along the second direction;

[0010] The width of the virtual graphic is widened to the area where the empty area is located to obtain the target map.

[0011] Preferably, the design parameters of the graphic include the line width, length, and spacing between the graphics.

[0012] Preferably, the design parameters of the virtual graphic are 1-2 times the minimum value of the design rules.

[0013] Preferably, the virtual graphics design parameters are equal to the sparse graphics design parameters.

[0014] Preferably, the value by which the width of the virtual graphic is widened towards the area containing the open space satisfies the design rules.

[0015] Preferably, the sparse shape is rectangular, the first direction is the width direction of the sparse shape, and the second direction is the length direction of the sparse shape.

[0016] Preferably, the virtual graphic is rectangular, and the ends of the virtual graphic are flush with those of the sparse graphic.

[0017] Based on the same inventive concept, the present invention also provides a photomask, comprising:

[0018] The mask is fabricated using the mask layout optimization method described above.

[0019] Based on the same inventive concept, the present invention also provides a method for fabricating a metal layer, comprising:

[0020] A metal layer pattern is formed on the metal layer using a mask prepared as described above, the metal layer pattern including several sparse patterns and virtual patterns;

[0021] Metal is filled into the sparse pattern to achieve metal interconnection between different metal layers.

[0022] Preferably, the design parameters of the virtual graphic are 1-2 times the minimum value of the design rules.

[0023] Compared with the prior art, the mask layout optimization method of the present invention has the following advantages:

[0024] This invention transforms a sparse pattern into a dense pattern by adding a virtual pattern to the side of a sparse pattern near the empty area. This allows the sparse pattern, originally used for metal layer interconnects, to maintain its original design parameters during photolithography, eliminating the need to widen the existing sparse pattern and ensuring that the electrical properties of the device remain unaffected. By widening the virtual pattern towards the empty area, the process window for the sparse pattern is increased. Therefore, using the target layout disclosed in this embodiment for photolithography can improve the process window for the sparse pattern while avoiding any impact on the electrical properties of the device, thereby reducing production costs and shortening development time.

[0025] The mask and metal layer fabrication method provided by this invention and the mask layout optimization method provided by this invention belong to the same inventive concept. Therefore, the mask and metal layer fabrication method provided by this invention has at least all the advantages of the mask layout optimization method provided by this invention. It can improve the sparse pattern process window while avoiding the impact on the electrical properties of the device, so as to reduce production costs and shorten the research and development time. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of an optimized sparse graph in one embodiment;

[0027] Figure 2 This is a schematic diagram of the three sparse graphs after optimization in another embodiment;

[0028] Figure 3 This is a schematic diagram of the optimized five sparse graphs in another embodiment;

[0029] Figure 4 This is a flowchart of a mask layout optimization method according to one embodiment of the present invention;

[0030] Figure 5 This is a schematic diagram of the structure of a sparse pattern in one embodiment of the present invention;

[0031] Figure 6 This is a schematic diagram of the sparse pattern structure in another embodiment of the present invention;

[0032] Figure 7 yes Figure 6 A schematic diagram of the structure after adding virtual graphics to sparse graphics;

[0033] Figure 8 yes Figure 7 A schematic diagram of the structure after the virtual graphic is widened to the area where the empty area is located;

[0034] In the picture,

[0035] 100 - Sparse graph; 110 - First-optimal graph;

[0036] 200 - Virtual graphics; 210 - Second optimized graphics;

[0037] 300 - Sparse region of the graphic. Detailed Implementation

[0038] To make the objectives, advantages, and features of the present invention clearer, the following detailed description of the photomask and its layout optimization method, and the metal layer fabrication method proposed in this invention, in conjunction with the accompanying drawings and specific embodiments, is provided. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, used only to facilitate and clearly illustrate the objectives of the embodiments of the present invention. It should be understood that the accompanying drawings do not necessarily show the specific structure of the present invention to scale, and the illustrative features used to illustrate certain principles of the present invention in the accompanying drawings are also drawn in a slightly simplified manner. Specific design features of the present invention disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and usage environment. Furthermore, in the embodiments described below, the same reference numerals are sometimes used across different drawings to denote the same parts or parts having the same function, omitting repeated descriptions. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0039] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0040] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0041] It should be noted that, in the following embodiments, the term "first direction" refers to a direction parallel to the width of the sparse pattern 100 (i.e., Figure 7the direction in which the arrow X is located). The term "second direction" refers to the direction parallel to the length of the sparse pattern 100 (i.e., Figure 7 the direction in which the arrow Y is located).

[0042] Referring Figures 1 to 3 As shown, in order to improve the process window of the sparse pattern 100, during the layout design, the sparse pattern 100 is thickened along its width direction, that is, the line width of the sparse pattern 100 is increased to ensure that during lithography, the process parameters of the sparse pattern 100 can meet the process requirements. For example, as Figure 1 shown in the layout design of a sparse pattern 100, when transferring the sparse pattern 100 to the mask, it is thickened. For those, such as Figure 2 and as Figure 3 shown in the layout design of the sparse pattern 100, only the sparse pattern 100 at the edge position is thickened to form the first optimized pattern 110, while the sparse pattern 100 in the middle part still retains the original design. After the above layout design optimization, then, the layout design is transferred to the mask, and the pattern on the mask is transferred to the metal layer to achieve metal interconnection in the metal layer. However, due to the thickening of the sparse pattern 100, after the sparse pattern 100 is filled with metal, the line width of the metal changes, resulting in a change in the resistance of the metal. During the electrical measurement of the semiconductor device, there is an error, causing the function of the device to be not as expected, and the layout design needs to be modified, and finally, the mask needs to be remade. The above optimization method increases the production cost and the R & D time.

[0043] The core idea of the present invention is to provide a mask layout optimization method, which can improve the process window of the sparse pattern 100 while avoiding affecting the electrical properties of the device, so as to achieve the purpose of reducing the production cost and shortening the R & D time.

[0044] To achieve the above idea, the present invention provides a mask layout optimization method, referring to Figures 4 to 8 a specific implementation manner of a mask layout optimization method disclosed. The mask layout optimization method includes the following steps S1 to step S4.

[0045] Step S1: Obtain the initial layout and the design parameters of all patterns in the initial layout. The initial layout includes a pattern sparse area 300 and an empty area (not shown in the figure). The empty area is located outside the pattern sparse area 300. A number of sparse patterns 100 are arranged in the pattern sparse area 300, and the number of the sparse patterns 100 is distributed along the first direction.

[0046] Specifically, referring to Figures 4 to 6As shown, the initial layout is obtained. The initial layout is the initial design pattern. By obtaining the initial layout, the design parameters of all the patterns in it can be obtained. This initial layout has not yet transferred the metal layer pattern onto the mask. The initial layout includes a sparse pattern region 300, a dense pattern region, and an empty region. The sparse pattern region 300 is designed with sparse patterns 100. The dense pattern region is designed with dense patterns. The dense patterns and sparse patterns 100 refer only to the density of the pattern distribution, and there are no special requirements for the process parameters of the pattern design. As long as the sparse patterns 100 and the dense patterns meet the layout design rules, it is acceptable. The empty region is located around the sparse pattern region 300. Furthermore, the empty region is located between the sparse pattern region 300 and the dense pattern region. The empty region is the area where no metal layer pattern is set.

[0047] Within each sparse region 300 of a graphic, several sparse graphics 100 can be set; for example, one can be set, or multiple sparse graphics can be set. Figure 5 The three in the text can also be like Figure 6 The five elements can be set, but two, four, etc., are also possible; specific requirements are not specified here. The sparse shape 100 can be a rectangle, a square, a combination of squares and rectangles, or other shapes. The following example... Figure 7 The explanation will be based on five sparse graphs of size 100. (Reference) Figure 6 As shown, in the original map, the sparse graphics 100 are all rectangles. The five sparse graphics 100 are evenly distributed along their width direction.

[0048] Step S2: Based on the design parameters of the graphics in the initial layout, filter out the sparse region 300 of the graphics in the initial layout.

[0049] Specifically, refer to Figures 4 to 6 As shown, the design parameters of the graphics in the initial layout include, but are not limited to, the line width, length, and spacing between adjacent graphics. Based on these design parameters, sparse regions 300 are selected. Each sparse region 300 contains several sparse graphics 100. The periphery of each sparse region 300 is an empty area.

[0050] Step S3: Along the first direction, in each of the sparse regions 300 of the graphic, add a virtual graphic 200 to the side of the sparse graphic 100 located at the edge position that is close to the open area, and the length of the virtual graphic 200 is distributed along the second direction.

[0051] Specifically, refer to Figure 4 and Figure 7As shown, virtual graphics 200 are set in each sparse region 300 of the sparse graphics 100 along the width direction. The virtual graphics 200 are located on the side of the sparse graphics 100 near the open area at the edge. The length of the virtual graphics 200 is distributed along a second direction. That is, the length direction of the virtual graphics 200 is consistent with the length direction of the sparse graphics 100. The process parameters of the virtual graphics 200 are 1-2 times the minimum value of the design rules. The line width d1 of the virtual graphics 200 and the distance d2 between the virtual graphics 200 and the sparse graphics 100 are 1-2 times the minimum value of the design rules. Preferably, the design parameters of the virtual graphics 200 are the same as the design parameters of the sparse graphics 100. That is, the line width d1 of the virtual graphics 200 is equal to the line width d3 of the sparse graphics 100. The distance and length of the virtual graphics 200 are also equal.

[0052] Step S4: Widen the width of the virtual graphic 200 to the area where the empty area is located to obtain the target map.

[0053] Specifically, refer to Figure 4 and Figure 8 As shown, the virtual graphic 200 is widened, that is, its line width is increased. The width of the virtual graphic 200 is widened towards the area containing the empty space to obtain the second optimized graphic 210. The parameters for widening the virtual graphic 200 satisfy the layout design rules. The line width of the widened virtual graphic 200 is d5, where d5 is greater than d1. The spacing between the virtual graphic 200 and the sparse graphic 100 remains unchanged.

[0054] It should be noted that in this embodiment, by adding a virtual pattern 200 to the side of the sparse pattern 100 located near an empty area at the edge, the density of the sparse pattern 100 can be increased, transforming the sparse pattern 100 into a dense pattern. When the optimized layout design is used to photolithographically lithographically form a metal layer pattern, a metal layer pattern is formed on the metal layer. The metal layer pattern formed by the sparse pattern 100 fills the metal to achieve metal interconnection between different metal layers. The metal layer pattern formed by the virtual pattern 200, however, is not used for filling the metal and is not used in the metal interconnection process.

[0055] Simulation tools were used to obtain the depth-of-focus (DOF) data of the original and target lithography patterns. The DDF is used to characterize the process window of the lithography process; a larger DDF value indicates a greater process tolerance, i.e., a larger process window.

[0056] Table 1 shows a comparison of the depth of field between the original and target maps obtained for a sparse graphic.

[0057] Graphic type iDOF (depth of focus) Anchor point graphics 343 A sparse graph 81 Adding virtual graphics to sparse graphics 138

[0058] Table 2 shows the depth-of-focus contrast images of the original and target maps obtained from three sparse graphics.

[0059] Graphic type iDOF (depth of focus) Anchor point graphics 343 Three sparse graphs 119 Adding virtual graphics to sparse graphics 193

[0060] As shown in Tables 1 and 2, regardless of whether there is one or three sparse graphs 100, the iDOF increases after adding a virtual graph 200 to the sparse graph 100, as verified by simulation tools. When there is only one sparse graph 100, the iDOF increases from 81 to 138 after adding the virtual graph 200. When there are three sparse graphs 100, the iDOF increases from 119 to 193 after adding the virtual graph 200. The iDOF is closer to the depth of focus value of the anchor point graph.

[0061] In this embodiment, by adding a virtual pattern 200 to the side of the sparse pattern 100 near the empty area, the sparse pattern 100 is transformed into a dense pattern. This allows the exposure focus to be closer to the focal center during photolithography, and the iDOF of the target pattern to be closer to the depth of focus of the anchor point pattern. The sparse pattern 100 originally used for metal layer interconnection retains its original design parameters, eliminating the need to widen the original sparse pattern 100, thus ensuring that the electrical properties of the device are not affected. By widening the virtual pattern 200 towards the empty area, the process window of the sparse pattern 100 can be increased. Therefore, using the target layout disclosed in this embodiment for photolithography can improve the process window of the sparse pattern 100 while avoiding any impact on the electrical properties of the device, thereby reducing production costs and shortening development time.

[0062] To achieve the above idea, this embodiment also discloses a mask, which is made using the mask layout optimization method described above.

[0063] To achieve the above-mentioned idea, this embodiment also discloses a method for fabricating a metal layer, including:

[0064] A metal layer pattern is formed on a metal layer using a mask as described above, the metal layer pattern including a plurality of sparse patterns 100 and virtual patterns 200;

[0065] Metal is filled into the sparse pattern to achieve metal interconnection between different metal layers.

[0066] The design parameters for virtual graphics 200 are 1-2 times the minimum value of the design rules.

[0067] The mask and metal layer fabrication method provided in this embodiment belongs to the same inventive concept as the mask layout optimization method provided in this embodiment. Therefore, the mask and metal layer fabrication method provided in this embodiment has at least all the advantages of the mask layout optimization method provided in this embodiment. It can improve the sparse pattern process window while avoiding the impact on the electrical properties of the device, so as to reduce production costs and shorten the research and development time.

[0068] In summary, the above embodiments have provided detailed descriptions of different configurations of photomasks and their layout optimization methods, as well as metal layer fabrication methods. Of course, the above descriptions are only descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention in any way. The present invention includes, but is not limited to, the configurations listed in the above embodiments. Those skilled in the art can draw inferences from the above embodiments. Any changes or modifications made by those skilled in the art based on the above disclosure are within the scope of protection of the claims.

Claims

1. A method for optimizing a mask layout, characterized in that, The method comprises the following steps: acquiring an initial mask layout and design parameters of all patterns in the initial mask layout, the initial mask layout comprising a plurality of sparse pattern areas and a blank area located at the periphery of the sparse pattern areas, each of the sparse pattern areas being provided with a plurality of sparse patterns, and the sparse patterns being distributed along a first direction; selecting the sparse pattern areas based on the design parameters of the patterns in the initial mask layout; adding a virtual pattern to a sparse pattern located at an edge position in each of the sparse pattern areas and close to one side of the blank area along a second direction; widening the width of the virtual pattern to the area where the blank area is located to obtain a target mask layout.

2. The method of claim 1, wherein, The design parameters of the patterns comprise line width, length, and spacing between patterns.

3. The method of claim 1, wherein, The design parameters of the virtual pattern are 1-2 times the minimum value of the design rules.

4. The method of claim 3, wherein, The design parameters of the virtual pattern are equal to the design parameters of the sparse patterns.

5. The method of claim 3, wherein, The value of the width of the virtual pattern widened to the area where the blank area is located satisfies the design rules.

6. The method of claim 1, wherein, The sparse patterns are rectangular, the first direction is the width direction of the sparse patterns, and the second direction is the length direction of the sparse patterns.

7. The method of claim 6, wherein, The virtual pattern is rectangular, and the virtual pattern is flush with the end of the sparse pattern.

8. A mask, characterized in that The method comprises the following steps: manufacturing a mask plate by using the mask layout optimization method according to any one of claims 1-7.

9. A method of fabricating a metal layer, the method comprising: The method comprises the following steps: forming a metal layer pattern on a metal layer by using the mask plate according to claim 8, the metal layer pattern comprising a plurality of sparse patterns and virtual patterns; filling the sparse patterns with metal to realize metal interconnection between different metal layers.

10. The method of claim 9, wherein the metal layer is formed by sputtering. The design parameters of the virtual pattern are 1-2 times the minimum value of the design rules.

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