Method, system and device for preventing hanging of IPMB based on domestic MCU and medium

Abstract

The invention relates to the technical field of software, and discloses an IPMB (Intelligent Power Management Bus) hanging prevention method, system and equipment based on a domestic MCU (Microprogrammed Control Unit) and a medium. The method comprises the following steps: sending a message to an IPMB bus through slave equipment, and detecting whether the IPMB bus is in a busy state or not through an external buffer connected with the slave equipment; in response to the fact that the IPMB is detected to be in the busy state, the external buffer disconnects physical connection between the slave equipment and the IPMB through the built-in switch; and in response to detecting that the IPMB is in a non-busy state and monitoring that response corresponding to the message waits for timeout and the number of times of waiting for timeout is greater than a preset number of times, the slave equipment sends a communication stop signal to the IPMB and triggers an equipment re-mounting mechanism. According to the scheme of the invention, the problem that multiple hosts seize a bus to cause busy in an IPMB application scene is effectively solved through a dual hanging-up prevention mechanism, and the situation that the whole link is hung up is avoided.

Description

Technical Field

[0001] The present invention relates to the field of software technology, and in particular, to a method, system, device and medium for preventing IPMB bus from hanging based on domestic MCU. Background Art

[0002] With the continuous progress of server technology, blade servers have occupied an important position in special application industries and high-density computing environments due to their high-density deployment and high-availability characteristics. These special scenarios often pose strict requirements on the power consumption of blade servers, requiring that while ensuring the basic health information collection function of the server, the device complexity be reduced as much as possible to reduce the overall power consumption. The operating environment of blade servers is complex and changeable, including different physical conditions, electromagnetic interference, etc., which poses a severe challenge to the communication between modules. To ensure the correctness and stability of data transmission, reliable communication protocols and hardware designs must be adopted. IPMB (Intelligent Platform Management Bus) as a "request-response" mechanism protocol based on the IIC bus shows unique advantages in such applications. Traditionally, the implementation of the IPMB protocol relies on the BMC (Baseboard Management Controller) system, and the implementation of BMC functions usually requires an additional independent processor as a hardware carrier. Although this design ensures the stability of communication and the correctness of information, it also increases the complexity and power consumption of the system.

[0003] Therefore, the present invention proposes a method, system, device and medium for preventing IPMB bus from hanging based on domestic MCU. Summary of the Invention

[0004] In view of this, the present invention proposes a method, system, device and medium for preventing IPMB bus from hanging based on domestic MCU, which effectively solves the problem of bus congestion caused by multiple hosts competing for the bus in the IPMB application scenario, and avoids the situation where the entire link hangs due to long-term bus occupation caused by interference or other reasons during the communication process.

[0005] Based on the above purpose, on the one hand, an embodiment of the present invention provides a method for preventing IPMB bus from hanging based on domestic MCU, which specifically includes the following steps: Sending a message to the IPMB bus through a slave device and detecting whether the IPMB bus is busy through an external buffer connected to the slave device; In response to detecting that the IPMB bus is busy, the external buffer disconnects the physical connection between the slave device and the IPMB bus through a built-in switch; In response to detecting that the IPMB bus is in an idle state, monitoring that the response waiting time for the message has timed out, and the number of times of timeout is greater than a preset number, the slave device sends a stop communication signal to the IPMB bus and triggers a device remount mechanism.

[0006] In some embodiments, the step of detecting whether the IPMB bus is busy through an external buffer connected to the slave device includes: Detecting the occupancy time of the IPMB bus through a built-in timer of the external buffer; Determining whether the occupancy time exceeds a preset threshold; In response to the occupancy time exceeding the preset threshold, determining that the IPMB bus is in a busy state; In response to the occupancy time not exceeding the preset threshold, determining that the IPMB bus is in an idle state.

[0007] In some embodiments, after the step of disconnecting the physical connection between the slave device and the IPMB bus through a built-in switch of the external buffer, the method further includes: Sending a release signal to the IPMB bus through the external buffer to release the occupancy of the IPMB bus by the slave device.

[0008] In some embodiments, before the step of detecting whether the IPMB bus is in a busy state through an external buffer connected to the slave device, the method further includes: In response to the start of IPMB bus communication, initializing all the slave devices connected to the IPMB bus.

[0009] In some embodiments, the IPMB bus anti-hang method based on a domestic MCU further includes: In response to monitoring a timeout, performing an error reporting process on the data status register corresponding to the slave device, and waiting for the slave device to perform the initialization operation again to update the data status register.

[0010] In some embodiments, the IPMB bus anti-hang method based on a domestic MCU further includes: In response to monitoring a timeout and the number of timeouts being less than a preset number, performing the initialization operation on the slave device again, and returning to the step of detecting whether the IPMB bus is busy through the external buffer connected to the slave device.

[0011] In some embodiments, the IPMB bus anti-hang method based on a domestic MCU further includes: In response to detecting a disconnection of the physical connection between the slave device and the IPMB bus, detect whether the IPMB bus is updated to an idle state through the external buffer; In response to detecting that the IPMB bus is updated to an idle state, control the built-in switch to restore the physical connection between the slave device and the IPMB bus; Perform an initialization operation on the slave device and trigger a device remount mechanism.

[0012] On the other hand, an embodiment of the present invention further provides an IPMB bus anti-hang system based on a domestic MCU, including: A bus detection unit configured to send a message to the IPMB bus through a slave device and detect whether the IPMB bus is in a busy state through an external buffer connected to the slave device; A hardware-level anti-hang unit configured to, in response to detecting that the IPMB bus is in a busy state, disconnect the physical connection between the slave device and the IPMB bus through the built-in switch by the external buffer; A software-level anti-hang unit configured to, in response to detecting that the IPMB bus is in an idle state, and monitoring that the response waiting time for the message times out and the number of timeout times is greater than a preset number, the slave device sends a stop communication signal to the IPMB bus and triggers a device remount mechanism.

[0013] In yet another aspect, an embodiment of the present invention further provides a computer device, including: at least one processor; and a memory storing a computer program executable on the processor, and when the computer program is executed by the processor, the steps of the above method are implemented.

[0014] In still another aspect, an embodiment of the present invention further provides a computer-readable storage medium storing a computer program that implements the steps of the above method when executed by a processor.

[0015] The present invention has at least the following beneficial technical effects: The IPMB bus anti-hang method based on domestic MCU of the present invention proposes a dual anti-hang mechanism based on domestic MCU and external IC. At the hardware level, the external IC is used to monitor the bus status, and when the bus is found to be busy, it can disconnect the connection with the slave device through the built-in switch, avoiding the device from occupying the bus for a long time, so as to ensure that other slave devices can access the bus normally; at the software level, under the control of the MCU, a timeout judgment mechanism, a device re-mounting mechanism, and an error handling for the data status register in the IIC link layer are added to ensure that the bus will not be hung up due to device failures or timeouts; using domestic MCU to replace BMC to implement IPMB protocol communication management, and designing a dual anti-hang mechanism for hardware and software to avoid IPMB bus communication problems such as multi-host bus preemption, long-term bus occupation, and communication failures, realizing the stable operation of the IPMB protocol on domestic MCU, while ensuring the correctness of information and the stability of communication, making the server device not limited to the BMC management method, greatly saving costs and reducing device power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other embodiments based on these drawings without creative efforts.

[0017] Figure 1 It is a block diagram of an embodiment of the IPMB bus anti-hang method based on domestic MCU provided by the present invention; Figure 2 It is a flowchart of an embodiment of the anti-hang processing process at the software level provided by the present invention; Figure 3 It is a schematic diagram of an embodiment of the IPMB bus anti-hang system based on domestic MCU provided by the present invention; Figure 4 It is a schematic diagram of an embodiment of the computer device provided by the present invention; Figure 5 It is a schematic diagram of an embodiment of the computer-readable storage medium provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] To make the objectives, technical solutions, and advantages of the present invention clearer and more understandable, the following will further elaborate on the embodiments of the present invention in detail with reference to specific embodiments and the accompanying drawings.

[0019] It should be noted that in the embodiments of the present invention, all expressions using "first" and "second" are for distinguishing two entities or parameters with the same name but different identities. It can be seen that "first" and "second" are only for the convenience of expression and should not be construed as a limitation on the embodiments of the present invention. This will not be elaborated in the subsequent embodiments one by one.

[0020] Based on the above objectives, in the first aspect of the embodiments of the present invention, an embodiment of a method for preventing IPMB bus from hanging is proposed based on a domestic MCU. As Figure 1 shown, it includes the following steps: Step S100, the slave device sends a message to the IPMB bus and detects whether the IPMB bus is in a busy state through an external buffer connected to the slave device; Step S200, in response to detecting that the IPMB bus is in a busy state, the external buffer disconnects the physical connection between the slave device and the IPMB bus through an internal switch; Step S300, in response to detecting that the IPMB bus is not in a busy state, and monitoring that the response waiting time for the message times out and the number of timeout times is greater than a preset number, the slave device sends a stop communication signal to the IPMB bus and triggers the device re-mounting mechanism.

[0021] In the shown embodiment, in order to meet the power consumption requirements of special scenarios while ensuring the stability and information correctness of the communication link, a domestic MCU (Microcontroller Unit) is used to replace the BMC function. The domestic MCU has the advantages of high flexibility and low power consumption in implementing the IPMB protocol. The domestic MCU can achieve functions similar to those of the BMC on the premise of ensuring communication stability and information correctness, so as to meet the requirements of reducing the power consumption and cost of the server. The method for preventing the IPMB bus link from hanging both in software and hardware designed by the present invention is conducive to the stable operation of the IPMB protocol on the domestic MCU, while ensuring the information correctness and communication stability. Using the domestic MCU as the hardware carrier for IPMB implementation, the function of uploading the device health information of the blade structure in the server industry is realized, so that the server device is not limited to the BMC management method, greatly saving costs and reducing the device power consumption.

[0022] In the illustrated embodiment, the hardware-level anti-freeze mechanism is the first line of defense. The slave device includes an IIC device, and the load receives and responds to requests issued by the host device. The external buffer is an external IC (integrated circuit), which generally refers to connecting an IC chip to an external circuit or system in a certain way to achieve specific functions or enhance the performance of the original circuit. The external IC is used to implement data buffering and automatic disconnection functions. The external IC is connected between the slave device and the IPMB bus, and the external IC has a built-in hardware timer and switch control logic. When it is detected that the occupancy time of the IPMB bus exceeds a preset threshold (e.g., 500 ms), the built-in switch of the buffer automatically disconnects the physical connection between the current slave device and the IPMB bus, and sends a release signal to the IPMB bus. The release signal can be a low-level pulse lasting for 100 ms. The hardware-level anti-freeze mechanism physically isolates the faulty device, avoiding the paralysis of the entire link caused by a single device crashing. By automatically releasing the signal through hardware, it forces the IPMB bus to return to the idle state without the intervention of the MCU, reducing software overhead. Among them, the preset threshold is configurable, and the timeout threshold of the buffer is configured to meet the requirements of different scenarios.

[0023] In the illustrated embodiment, the software-level anti-freeze mechanism is the second line of defense. An overtime judgment and re-mounting mechanism are added at the driver layer. As Figure 2 shown, when the MCU starts the IPMB protocol stack and the IPMB communication starts, the slave device and the external buffer are initialized. Continuously monitor the bus status and detect whether the bus is busy. If the bus is busy or the overtime count of the message waiting for a response does not exceed the preset count, attempt to send the message for communication again and judge again whether the response times out. If the bus is not busy but the overtime count of the message waiting for a response exceeds the preset count, such as twice (configurable), immediately send a stop signal to end the current communication process and record the error log, triggering the device re-mounting mechanism. The device re-mounting resets the IIC controller and clears the buffer error status. Through the timeout threshold and the retry mechanism, communication failures caused by short-term interference are avoided. The error type is recorded in the register for easy fault diagnosis. The method for preventing IPMB bus deadlock based on domestic MCU of the present invention proposes a dual deadlock prevention mechanism based on domestic MCU and external IC. At the hardware level, the external IC is used to monitor the bus status, and when it detects that the bus is busy, it can disconnect the connection with the slave device through the built-in switch to avoid the device occupying the bus for a long time, thus ensuring that other slave devices can access the bus normally; at the software level, under the control of the MCU, a timeout judgment mechanism, a device re-mounting mechanism, and an error handling for the data status register in the IIC link layer are added to ensure that the bus will not be deadlocked due to device failures or timeouts; a domestic MCU is used to replace the BMC to implement IPMB protocol communication management, and a dual deadlock prevention mechanism for hardware and software is designed to avoid IPMB bus communication problems such as multi-host bus preemption, long-term bus occupation, and communication failures, realize the stable operation of the IPMB protocol on the domestic MCU, and at the same time ensure the correctness of information and the stability of communication, so that the server device is not limited to the BMC management method, greatly saving costs and reducing device power consumption.

[0024] In some embodiments, the step of detecting whether the IPMB bus is busy through an external buffer connected to the slave device includes: detecting the occupation time of the IPMB bus through a timer built in the external buffer; judging whether the occupation time exceeds a preset threshold; in response to the occupation time exceeding the preset threshold, determining that the IPMB bus is in a busy state; in response to the occupation time not exceeding the preset threshold, determining that the IPMB bus is in an idle state.

[0025] In the illustrated embodiment, the external IC monitors each link in the communication process. Once a communication timeout occurs (such as the link not responding for a long time), the IC will actively disconnect the slave from the bus. At the same time, the IC will send a release signal to the bus to release the occupation of the bus by the device.

[0026] The method for preventing IPMB bus deadlock based on domestic MCU of the present invention releases the bus resources for other devices by timely disconnecting unresponsive devices, avoiding link deadlocks caused by device failures, enhancing system stability, and the hardware automatic deadlock prevention mechanism can reduce human intervention.

[0027] In some embodiments, after the step of disconnecting the physical connection between the slave device and the IPMB bus through the built-in switch of the external buffer, it further includes: sending a release signal to the IPMB bus through the external buffer to release the occupation of the IPMB bus by the slave device.

[0028] In some embodiments, before the step of detecting whether the IPMB bus is in a busy state through an external buffer connected to the slave device, it further includes: in response to the start of IPMB bus communication, initializing all slave devices connected to the IPMB bus.

[0029] In the illustrated embodiment, when the IPMB communication starts, the software layer first performs an initialization operation to ensure that the communication link is ready for data transmission.

[0030] In some embodiments, the method for preventing IPMB bus deadlock based on domestic MCU of the present invention further includes: in response to detecting a wait timeout, performing an error reporting process on the data status register corresponding to the slave device, and waiting for the slave device to perform an initialization operation again to update the data status register.

[0031] In the illustrated embodiment, for the error reporting process of the data status register, the status register at the IIC link layer is monitored in real time. When a response timeout and device remounting occur, an error reporting process on the data status register is simultaneously performed on the IIC link layer to prevent the situation where the entire hardware link is deadlocked due to a device failure on the bus link.

[0032] In some embodiments, the method for preventing IPMB bus deadlock based on domestic MCU of the present invention further includes: in response to detecting a wait timeout and the number of wait timeouts being less than a preset number, performing an initialization operation on the slave device again, and returning to the step of detecting whether the IPMB bus is busy through an external buffer connected to the slave device.

[0033] In the illustrated embodiment, different timeout thresholds and preset numbers of retries are set for specific application scenarios to improve the flexibility and adaptability of the system. For example, for critical devices, the timeout threshold can be set to a shorter time to ensure a quick response, while for less critical devices, a longer timeout threshold can be set to reduce misjudgment.

[0034] In some embodiments, the method for preventing IPMB bus deadlock based on domestic MCU of the present invention further includes: in response to detecting a physical connection disconnection between the slave device and the IPMB bus, detecting whether the IPMB bus is updated to an idle state through an external buffer; in response to detecting that the IPMB bus is updated to an idle state, controlling an internal switch to restore the physical connection between the slave device and the IPMB bus; performing an initialization operation on the slave device and triggering a device remounting mechanism.

[0035] The method for preventing IPMB bus deadlock based on domestic MCU of the present invention combines two layers of deadlock prevention mechanisms, namely hardware and software. Through the automatic disconnection of the external IC and the timeout judgment and device reconnection mechanism of the software, it effectively prevents the link deadlock problem caused by device failures or communication interference. This method not only improves the fault tolerance and stability of the system, but also reduces the system maintenance cost caused by human intervention, enabling the system to operate more efficiently in a high-density computing environment.

[0036] Based on the same inventive concept, according to another aspect of the present invention, asFigure 3 As shown in the figure, an embodiment of the present invention further provides an IPMB bus anti-hang system based on a domestic MCU, including: A bus detection unit configured to send a message to the IPMB bus through a slave device and detect whether the IPMB bus is in a busy state through an external buffer connected to the slave device; An anti-hang unit at the hardware level configured to, in response to detecting that the IPMB bus is in a busy state, disconnect the physical connection between the slave device and the IPMB bus through an internal switch of the external buffer; An anti-hang unit at the software level configured to, in response to detecting that the IPMB bus is not in a busy state, monitoring that the response waiting for the message times out and the number of timeout times is greater than a preset number, the slave device sends a stop communication signal to the IPMB bus and triggers a device re-mounting mechanism.

[0037] The IPMB bus anti-hang system based on a domestic MCU of the present invention proposes a dual anti-hang mechanism based on a domestic MCU and an external IC. At the hardware level, the external IC is used to monitor the bus status, and when it is found that the bus is busy, the connection with the slave device can be disconnected through an internal switch to avoid the device occupying the bus for a long time, thereby ensuring that other slave devices can access the bus normally; at the software level, under the control of the MCU, a timeout judgment mechanism, a device re-mounting mechanism, and an error handling of the data status register in the IIC link layer are added to ensure that the bus will not be hung up due to device failures or timeouts; a domestic MCU is used to replace the BMC to implement IPMB protocol communication management, and a dual anti-hang mechanism of hardware and software is designed to avoid IPMB bus communication problems such as multi-host bus preemption, long-term bus occupation, and communication failures, realize the stable operation of the IPMB protocol on the domestic MCU, and at the same time ensure the correctness of information and the stability of communication, so that the server device is not limited to the BMC management method, greatly saving costs and reducing device power consumption.

[0038] Based on the same inventive concept, according to another aspect of the present invention, as Figure 4 shown, an embodiment of the present invention further provides a computer device 30, which includes a processor 310 and a memory 320 in the computer device 30. The memory 320 stores a computer program 321 that can run on the processor. When the processor 310 executes the program, it executes the steps of the above method.

[0039] Based on the same inventive concept, according to another aspect of the present invention, as Figure 5 shown, an embodiment of the present invention further provides a computer-readable storage medium 40. The computer-readable storage medium 40 stores a computer program 410 that, when executed by a processor, executes the above method.

[0040] Finally, it should be noted that a person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium of the program can be a disk, an optical disk, a read-only storage memory (ROM) or a random access memory (RAM), etc. The above-mentioned computer program embodiments can achieve the same or similar effects as the corresponding above-mentioned any method embodiments.

[0041] It will also be appreciated by those skilled in the art that various exemplary logic blocks, modules, circuits and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, a general description has been given to the functions of various schematic components, blocks, modules, circuits and steps. Whether this function is implemented as software or hardware depends on specific applications and the design constraints imposed on the entire system. Those skilled in the art can implement the function in various ways for each specific application, but this implementation decision should not be interpreted as causing a departure from the disclosed scope of the embodiments of the present invention.

[0042] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope of the embodiments disclosed in the present invention as defined in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. The serial numbers of the embodiments disclosed in the above embodiments of the present invention are for description only and do not represent the advantages and disadvantages of the embodiments. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless explicitly limited to the singular.

[0043] It should be understood that, as used herein, the singular forms "a", "an" are intended to include the plural forms as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations including one or more of the associated listed items.

[0044] Those of ordinary skill in the art should understand that: The discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope (including the claims) of the disclosure of the embodiments of the present invention is limited to these examples; Under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other variations in different aspects of the embodiments of the present invention as above, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present invention shall be included within the protection scope of the embodiments of the present invention.

Claims

1. A method for preventing IPMB bus from hanging based on domestic MCU, characterized in that: include: Sending a message to the IPMB bus through the slave device and detecting whether the IPMB bus is in a busy state through an external buffer connected to the slave device; In response to detecting that the IPMB bus is in a busy state, the external buffer disconnects the physical connection between the slave device and the IPMB bus through a built-in switch; In response to detecting that the IPMB bus is not busy and monitoring that the response wait corresponding to the message has timed out and the number of timeouts is greater than a preset number, the slave device sends a stop communication signal to the IPMB bus and triggers a device remounting mechanism.

2. The method for preventing IPMB bus from hanging up based on domestic MCU according to claim 1 is characterized in that: The step of detecting whether the IPMB bus is busy through an external buffer connected to a slave device comprises: Detecting the occupancy time of the IPMB bus by means of a built-in timer of the external buffer; Determining whether the occupancy time exceeds a preset threshold; In response to the occupancy time exceeding a preset threshold, determining that the IPMB bus is in a busy state; In response to the occupation time not exceeding a preset threshold, it is determined that the IPMB bus is in a non-busy state.

3. The method for preventing IPMB bus from hanging up based on domestic MCU according to claim 1 is characterized in that: After the step of disconnecting the physical connection between the slave device and the IPMB bus through the built-in switch, the method further includes: A release signal is sent to the IPMB bus through an external buffer to release the slave device from occupying the IPMB bus.

4. The method for preventing IPMB bus from hanging up based on domestic MCU according to claim 1 is characterized in that: Before the step of detecting whether the IPMB bus is in a busy state by an external buffer connected to the slave device, the method further includes: In response to the IPMB bus communication starting, all the slave devices connected to the IPMB bus are initialized.

5. The method for preventing IPMB bus from hanging up based on domestic MCU according to claim 4 is characterized in that: Also includes: In response to monitoring the waiting timeout, an error processing is performed on the data status register corresponding to the slave device, and the slave device is waited to perform the initialization operation again to update the data status register.

6. The method for preventing IPMB bus from hanging up based on domestic MCU according to claim 4 is characterized in that: Also includes: In response to monitoring a wait timeout and the number of wait timeouts being less than a preset number, the initialization operation is performed again on the slave device, and the process returns to the step of detecting whether the IPMB bus is busy through the external buffer connected to the slave device.

7. The method for preventing IPMB bus from hanging up based on domestic MCU according to claim 1 is characterized in that: Also includes: In response to detecting that the physical connection between the slave device and the IPMB bus is disconnected, detecting, by the external buffer, whether the IPMB bus is updated to a non-busy state; In response to detecting that the IPMB bus is updated to a non-busy state, controlling the built-in switch to restore the physical connection between the slave device and the IPMB bus; Initialize the slave device and trigger the device remount mechanism.

8. An IPMB bus anti-hanging system based on domestic MCU, characterized in that: include: A bus detection unit configured to send a message to the IPMB bus through a slave device and detect whether the IPMB bus is in a busy state through an external buffer connected to the slave device; A hardware-level anti-hanging unit configured to disconnect the physical connection between the slave device and the IPMB bus via a built-in switch in response to detecting that the IPMB bus is in a busy state; The software-level anti-hanging unit is configured to respond to detecting that the IPMB bus is not busy and monitoring that the response wait corresponding to the message has timed out and the number of waiting timeouts is greater than a preset number, the slave device sends a stop communication signal to the IPMB bus and triggers a device re-mounting mechanism.

9. A computer device comprising: at least one processor; as well as A memory storing a computer program executable on the processor, wherein the processor executes the steps of the method according to any one of claims 1 to 7 when executing the program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are performed.

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