Clock control method, system on chip and computer equipment

Abstract

The invention provides a clock control method, a system-on-chip and computer equipment, the method is applied to the system-on-chip, the system-on-chip comprises a synchronization unit, a control and state register and a clock control component, the control and state register establishes communication connection with other function modules through the synchronization unit, the clock control assembly is connected with an APB interface of the control and state register; the method comprises the following steps: a clock control component controls a clock signal of a synchronization unit to be started under the condition that a control and state register needs to perform data communication with other functional modules according to a received APB interface signal, and controls the clock signal of the synchronization unit to be started under the condition that the control and state register completes the data communication with other functional modules; controlling the clock signal of the synchronization unit to be closed; wherein the APB interface signal comprises a signal sent to the APB interface and / or a signal sent from the APB interface. According to the method, the clock power consumption of the synchronization unit in the system-on-chip can be reduced, so that the power consumption of the system-on-chip can be reduced.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a clock control method, a system-on-chip, and a computer device. Background Art

[0002] Inside an SOC (System on Chip) or an ASIC (Application Specific Integrated Circuit), multiple functional modules are usually provided, including a CSR (Control and Status Register) module. The system-on-chip can access this module through an APB (Advanced Peripheral Bus) interface. Other modules will give some status signals that need to be monitored or observed to the CSR module, or the CSR module outputs some control signals to achieve the control of other modules. Since different modules usually do not belong to the same clock domain, before the output signals of some modules are given to the CSR module, clock synchronization processing needs to be performed through a synchronization unit. Also, when the control signals of the CSR module are output to other modules, the control signals in the CSR clock domain need to be synchronized to other clock domains through the synchronization unit.

[0003] The above synchronization unit realizes the clock domain synchronization between different functional modules in the system-on-chip, but also increases the power consumption of the system-on-chip, making it difficult to meet the industry's demand for reducing the power consumption of the system-on-chip. Summary of the Invention

[0004] Based on the above technical status quo, this application proposes a clock control method, a system-on-chip, and a computer device, which can reduce the clock power consumption of the synchronization unit in the system-on-chip, and thus can reduce the power consumption of the system-on-chip.

[0005] A first aspect of this application proposes a clock control method applied to a system-on-chip. The system-on-chip includes a synchronization unit, a control and status register, and a clock control component. The control and status register establishes a communication connection with other functional modules of the system-on-chip through the synchronization unit, and the clock control component is connected to the APB interface of the control and status register;

[0006] The method includes:

[0007] When the clock control component confirms that the control and status register needs to communicate data with other functional modules according to the received APB interface signal, it controls the clock signal of the synchronization unit to turn on, and when it confirms that the control and status register has completed data communication with other functional modules, it controls the clock signal of the synchronization unit to turn off;

[0008] Among them, the APB interface signal includes a signal sent to the APB interface and / or a signal sent from the APB interface.

[0009] In some implementation manners, the synchronization unit includes a first synchronization unit and a second synchronization unit. The input end of the control and status register establishes a communication connection with other functional modules of the system-on-chip through the first synchronization unit, and the output end of the control and status register establishes a communication connection with other functional modules of the system-on-chip through the second synchronization unit.

[0010] In some implementation manners, when the clock control component confirms that the control and status register needs to communicate data with other functional modules according to the received APB interface signal, it controls the clock signal of the synchronization unit to turn on, and when it confirms that the control and status register has completed data communication with other functional modules, it controls the clock signal of the synchronization unit to turn off, including:

[0011] When the clock control component receives a read operation instruction sent to the APB interface, it controls the clock signal of the first synchronization unit to turn on, and when it confirms that the data corresponding to the read operation instruction is sent to the control and status register through the first synchronization unit, it controls the clock signal of the first synchronization unit to turn off;

[0012] and / or,

[0013] When the clock control component receives feedback information indicating that a write operation instruction sent from the APB interface has been executed, it controls the clock signal of the second synchronization unit to turn on, and when it confirms that the control and status register outputs data corresponding to the write operation instruction through the second synchronization unit, it controls the clock signal of the second synchronization unit to turn off.

[0014] In some implementation manners, the first synchronization unit includes an N-stage synchronization unit, and the N-stage synchronization unit shares the same clock signal with the control and status register;

[0015] When the clock control component confirms that the data corresponding to the read operation instruction is sent to the control and status register through the first synchronization unit, it controls the clock signal of the first synchronization unit to turn off, including:

[0016] When the clock control component confirms that the first synchronization unit has received at least N cycles of clock signals, it controls the clock signal of the first synchronization unit to be turned off;

[0017] wherein, N is a positive integer.

[0018] In some implementation manners, the second synchronization unit includes an M-stage synchronization unit, and the M-stage synchronization unit shares the same clock signal with the control and status register;

[0019] When the clock control component confirms that the control and status register outputs data corresponding to the write operation instruction through the second synchronization unit, controlling the clock signal of the second synchronization unit to be turned off includes:

[0020] When the clock control component confirms that the second synchronization unit has received at least M cycles of clock signals, it controls the clock signal of the second synchronization unit to be turned off;

[0021] wherein, M is a positive integer.

[0022] In some implementation manners, the second synchronization unit includes a P-stage synchronization unit, and the clock signal of the P-stage synchronization unit has the same frequency as the clock signal of the control and status register and comes from different signal sources; P is a positive integer;

[0023] The clock control component includes a J-stage clock control signal synchronization unit, where J is a positive integer; the J-stage clock control signal synchronization unit is used to switch the clock domain of the clock control signal sent by the clock control component to the clock domain of the P-stage synchronization unit;

[0024] When the clock control component confirms that the control and status register outputs data corresponding to the write operation instruction through the second synchronization unit, controlling the clock signal of the second synchronization unit to be turned off includes:

[0025] When the clock control component confirms that the second synchronization unit has received at least P×J cycles of clock signals, it controls the clock signal of the second synchronization unit to be turned off.

[0026] In some implementation manners, the second synchronization unit includes a Q-stage synchronization unit, where Q is a positive integer; the clock signals of the Q-stage synchronization unit and the control and status register have different frequencies and come from different signal sources;

[0027] The clock control component includes a T-level clock control signal synchronization unit, where T is a positive integer; the T-level clock control signal synchronization unit is used to switch the clock domain of the clock control signal sent by the clock control component to the clock domain of the P-level synchronization unit;

[0028] When the clock control component confirms that the control and status register outputs data corresponding to the write operation instruction through the second synchronization unit, it controls the clock signal of the second synchronization unit to be turned off, including:

[0029] When the clock control component confirms that the second synchronization unit has received at least X clock signals for X cycles; X is a positive integer calculated based on Q, T, the clock signal frequency of the Q-level synchronization unit, and the clock signal frequency of the control and status register.

[0030] In some implementation manners, the second synchronization unit includes multiple groups of Q-level synchronization units; the clock signal frequencies of the multiple groups of Q-level synchronization units and the control and status register are different and come from different signal sources;

[0031] X is a positive integer calculated based on Q, T, the clock signal frequencies of the multiple groups of Q-level synchronization units, and the clock signal frequency of the control and status register.

[0032] In some implementation manners, the calculation process of X includes:

[0033] By comparing the clock signal frequencies of the multiple groups of Q-level synchronization units, the minimum clock signal frequency is selected, and the minimum clock period of the minimum clock signal frequency is determined;

[0034] Calculate the product of the minimum clock period and an integer not less than Q×T to obtain a target clock period;

[0035] Calculate the ratio of the target clock period to the clock period corresponding to the clock signal frequency of the control and status register to obtain the value of the number of clock signal cycles X. When the ratio is a non-integer, the value of the number of clock signal cycles X is the value obtained by rounding up the ratio.

[0036] In some implementation manners, the clock control component includes a clock control module, a control signal synchronization module, and a clock gating unit;

[0037] The clock control module is connected to the APB interface of the control and status register and is used to monitor the signals sent to the APB interface and the signals sent by the APB interface;

[0038] The control signal synchronization module is disposed on the link between the clock signal source of the synchronization unit and the clock gating unit, and is configured to switch the clock domain of the clock control signal sent by the clock control module to the clock domain of the synchronization unit;

[0039] The clock gating unit is disposed on the clock signal input link of the synchronization unit, and is configured to control the on / off of the clock signal of the synchronization unit based on an instruction of the clock control module.

[0040] A second aspect of the present application provides a system on chip, including a synchronization unit, a control and status register, and a clock control component. The control and status register establishes a communication connection with other functional modules of the system on chip through the synchronization unit, and the clock control component is connected to the APB interface of the control and status register;

[0041] The system on chip is configured to implement the above-mentioned clock control method.

[0042] A third aspect of the present application provides a computer device, including the above-mentioned system on chip.

[0043] The clock control method provided by the present application adds a clock control component in the system on chip. The clock control component is connected to the APB interface of the control and status register in the system on chip, so that it can receive the APB interface signal sent to the APB interface and the signal sent from the APB interface. The control and status register of the system on chip establishes a communication connection with other functional modules of the system on chip through the synchronization unit. When the clock control component confirms that the control and status register needs to perform data communication with other functional modules according to the received APB interface signal, it controls the clock of the synchronization unit to be turned on, and when it confirms that the control and status register has completed data communication with other functional modules, it controls the clock of the synchronization unit to be turned off. The above-mentioned clock control method adds a clock control component for controlling the clock of the synchronization unit in the system on chip. The component determines whether the control and status register needs to perform data communication with other functional modules by monitoring the APB interface signal of the control and status register. When data communication is required, it controls the clock signal of the synchronization unit to be turned on, and turns off the clock signal of the synchronization unit after the data communication is completed, so that the timely on / off of the clock signal of the synchronization unit can be realized, and the increase of system power consumption caused by the clock signal of the synchronization unit during no data transmission can be avoided, so the system power consumption can be reduced. Description of the Drawings

[0044] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on the provided drawings.

[0045] Figure 1 It is a schematic structural diagram of a system-on-chip provided by an embodiment of the present application.

[0046] Figure 2 It is a schematic structural diagram of another system-on-chip provided by an embodiment of the present application.

[0047] Figure 3 It is a schematic flowchart of a clock control method provided by an embodiment of the present application.

[0048] Figures 4 - 9 It is a schematic structural diagram of several other system-on-chips provided by an embodiment of the present application. Detailed implementation manners

[0049] The technical solutions of the embodiments of the present application are applicable to the application scenario where the control and status registers inside the system-on-chip interact with other functional modules. By adopting the technical solutions of the embodiments of the present application, the power consumption of the synchronization unit between the control and status registers and other functional modules can be reduced.

[0050] Inside a SOC (System on Chip) or an ASIC (Application Specific Integrated Circuit), multiple functional modules are usually set up, including a CSR (Control and Status Register) module. The system-on-chip can access this module through an APB (Advanced Peripheral Bus) interface. Other modules will give some status signals that need to be monitored or observed to the CSR module, or the CSR module outputs some control signals to achieve the control of other modules. Since different modules are usually not in the same clock domain, before the output signals of some modules are given to the CSR module, they need to be clock-synchronized through a synchronization unit. Also, when the control signals of the CSR module are output to other modules, the control signals in the CSR clock domain need to be synchronized to other clock domains through the synchronization unit.

[0051] Among them, the above-mentioned synchronization unit can specifically adopt a flip-flop. The synchronization unit can be a first-level synchronization unit or a multi-level cascaded synchronization unit. The specific number of synchronization unit levels can be flexibly set according to the number of synchronization unit levels required for clock synchronization between different modules.

[0052] Take Figure 1 as an example. Inside the chip, there are module A, module B, CSR module, module D, and module E.

[0053] Among them, module A is in clock domain A and uses the clock clk_a. Module B is in clock domain B and uses the clock clk_b. The CSR module is in clock domain C and uses the clock clk_c. The output signal a_sts of module A needs to be given to the CSR module, and the signal is synchronized by a synchronization unit in the middle. The signal b_sts output by module B needs to be given to the CSR module, and the signal is synchronized by a synchronization unit in the middle. The CSR module has a group of APB interfaces that support the system to read and write access to the CSR module. Usually, the clocks of these synchronization units directly use clk_c and are always on and will not be turned off. If the APB interface does not read the registers related to a_sts or b_sts, at this time, the clock of the synchronization unit module is enabled. Even if a_sts or b_sts changes and the new value is synchronized to the CSR module, it doesn't make much sense. Because the APB interface doesn't initiate a read request, the outside world doesn't know that a_sts or b_sts has changed. At this time, the clocks of the two-level synchronization units being always on also increase power consumption.

[0054] Module D is in clock domain D and uses the clock clk_d. Module E is in clock domain E and uses the clock clk_e. The control signal d_ctrl output by the CSR module needs to be synchronized to clock domain D through a synchronization unit before being given to module D. The control signal e_ctrl output by the CSR module needs to be synchronized to clock domain E through a synchronization unit, and then the signal is given to module E for use. In the usual design, the synchronization units used for the d_ctrl and e_ctrl signals are not dynamically turned off. They are either always on or always off. They will not be dynamically turned off according to APB access. Only when the e_ctrl or d_ctrl signal is configured by the APB interface and the value changes, is it necessary to synchronize the new value to module E and module D through the synchronization unit. If the APB interface does not configure (write) the e_ctrl or d_ctrl signal, the values of these signals will not change. Keeping the clocks of the synchronization units on will waste electricity and increase power consumption.

[0055] It can be seen that the above-mentioned synchronization unit realizes the clock domain synchronization between different functional modules within the system-on-chip. However, the clock of the synchronization unit also increases the power consumption of the system-on-chip, making it difficult to meet the industry's demand for reducing the power consumption of the system-on-chip.

[0056] In view of the above technical problems, the embodiments of the present application propose a clock control method, which can dynamically turn off the clock signal of the above-mentioned synchronization unit, turn on the synchronization unit clock when signal clock synchronization is required, and turn off the synchronization unit clock when signal clock synchronization is not required, thereby reducing the clock power consumption of the synchronization unit and further facilitating the reduction of system power consumption.

[0057] Next, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0058] The embodiments of the present application first optimize and improve the connection manner between the control and status register CSR inside the chip and other functional modules, thereby proposing a new system-on-chip. Refer to Figure 2 As shown, the system-on-chip includes a synchronization unit, a control and status register. Similar to Figure 1 the internal structure of the chip shown, Figure 2 in the system-on-chip shown, the control and status register establishes a communication connection with other functional modules inside the system-on-chip through the synchronization unit. For example, Figure 2 as shown, the input port of the control and status register establishes a communication connection with other functional module A through the synchronization unit, so that data input by functional module A can be received through the synchronization unit. The output port of the control and status register establishes a communication connection with other functional module B through the synchronization unit, so that a control signal or data can be sent to functional module B through the synchronization unit.

[0059] The above-mentioned other functional modules can be modules with any function, and the number thereof can be one or more. For example, the number of the above-mentioned functional module A can be one or more, and each functional module A can be a module with the same function or different functions; similarly, the number of the above-mentioned functional module B can be one or more, and each functional module B can be a module with the same function or different functions.

[0060] In some embodiments, different functional modules can be connected to the CSR through the same synchronization unit, or different functional modules can be respectively connected to the CSR through dedicated synchronization units.

[0061] Continue to refer toFigure 2 As shown, an embodiment of the present application further provides a clock control component in the system on a chip. The clock control component is disposed on the input link of the clock signal of the above-mentioned synchronization unit and is used to control the on / off of the clock signal input to the synchronization unit. At the same time, the clock control component is also connected to the APB interface of the control and status register CSR, and is used to receive the signal sent to the APB interface and forward it to the APB interface of the CSR, or receive the signal sent from the APB interface of the CSR.

[0062] Based on Figure 2 the system on a chip shown above, an embodiment of the present application provides a clock control method, which is executed by the clock control component in the above-mentioned system on a chip.

[0063] Referring to Figure 3 as shown, the clock control method provided by an embodiment of the present application includes:

[0064] S101. When the clock control component confirms that the control and status register needs to perform data communication with other functional modules according to the received APB interface signal, it controls the clock signal of the synchronization unit to be turned on, and when it confirms that the control and status register has completed data communication with other functional modules, it controls the clock signal of the synchronization unit to be turned off.

[0065] Among them, the above-mentioned APB interface signal includes the signal sent to the APB interface and / or the signal sent from the APB interface.

[0066] The above-mentioned signal sent to the APB interface can be a read operation request signal or a write operation request signal. Among them, the read operation request signal is a signal triggered by the upper-layer application of the system on a chip to read the data sent by other functional modules to the CSR from the CSR. For example, reading Figure 2 the data sent by functional module A in the CSR to the CSR. The write operation request signal is a signal triggered by the upper-layer application of the system on a chip to perform a write operation on the control signal or data sent to other functional modules through the CSR. For example, performing a write operation on the data or control signal sent to Figure 2 functional module B in the CSR.

[0067] The above-mentioned signal sent from the APB interface includes the signal fed back by the CSR through the APB interface after receiving the control signal and performing corresponding processing. The fed-back signal may include the processing result of the CSR in response to the control signal received from the APB interface. For example, after the CSR receives the write operation request signal through the APB interface, it performs a write operation process, and then outputs the write operation process result through the APB interface. The write operation process result may include information such as a write operation completion identification information, the status of the control signal or data after the write operation, etc.

[0068] It can be understood that when the CSR reads data from other functional modules or sends data to other functional modules, it is controlled by the on-chip system sending control signals to the CSR through the APB interface. Therefore, whether the on-chip system calls the CSR to communicate with other functional modules can be identified through the signals sent to and from the APB interface. For example, when a read operation request signal sent to the APB interface is received, it can be determined that the CSR needs to receive data from other functional modules, or when the CSR outputs the processing result of a write operation through the APB interface, it can be determined that the CSR needs to send the processed data of the write operation to other functional modules.

[0069] Based on the uses of the above APB interface signals, in the embodiments of the present application, the APB interface signals of the CSR are connected to a clock control component, and the clock control component monitors the APB interface signals. When the clock control component receives a signal sent to the APB interface and / or a signal sent from the APB interface, it parses the received signal to determine whether the CSR needs to communicate with other functional modules when the CSR receives the signal sent to the APB interface or the CSR sends the signal from the APB interface.

[0070] For example, when the signal sent to the APB interface of the CSR received by the clock control component is a read operation request signal, it can be determined that the CSR needs to receive data sent by other functional modules, that is, it is determined that the CSR needs to communicate with other functional modules connected to the input port of the CSR; when the signal sent to the APB interface of the CSR received by the clock control component is a write operation request signal, and after sending the write operation request signal to the CSR, the CSR returns a signal indicating the completion of the write operation through the APB interface, it can be determined that at this time the CSR needs to send data to other functional modules, that is, it is determined that the CSR needs to communicate with other functional modules connected to the output port of the CSR.

[0071] When it is confirmed that the CSR needs to communicate with other functional modules, the clock control component controls the clock signal of the synchronization unit between the CSR and other functional modules that will communicate with the CSR to be turned on. At this time, the communication link between the CSR and other functional modules that communicate with the CSR is conducted through the synchronization unit, and clock synchronization of signals can be achieved through the synchronization unit.

[0072] In addition, the clock control component also monitors the progress of data communication between the CSR and other functional modules. When it is confirmed that the CSR has completed data communication with other functional modules, it controls the clock signal of the synchronization unit between the CSR and other functional modules to be turned off.

[0073] For example, CSR can output data transfer record information through the APB interface, such as data transfer progress, data transfer completion information, etc. When the clock control component receives a signal indicating data transfer completion through the APB interface, it can determine that CSR has completed data communication with other functional modules.

[0074] Alternatively, the number of clock cycles required for the data sent by other functional modules to reach CSR through the synchronization unit can be pre - counted, and the number of clock cycles required for the data sent by the CSR module to reach other functional modules through the synchronization unit can be counted. When the clock control component controls the clock signal of the synchronization unit to be turned on and the duration of the turn - on is greater than the above - mentioned number of clock cycles, it can be considered that CSR has completed data communication with other functional modules.

[0075] As can be seen from the above introduction, the clock control method proposed in the embodiment of the present application sets a clock control component inside the on - chip system to control the clock of the synchronization unit between the control and status register and other functional modules. The clock control component receives the APB interface signal of the control and status register and determines whether the control and status register needs to perform data communication with other functional modules based on the received APB interface signal. In the case of confirming that the control and status register needs to perform data communication with other functional modules, the clock signal of the synchronization unit between the control and status register and other functional modules is turned on, and in the case of confirming that the control and status register has completed data communication with other functional modules, the clock signal of the synchronization unit between the control and status register and other functional modules is turned off. The above - mentioned clock control method realizes the dynamic shutdown of the clock signal of the synchronization unit, thereby avoiding power consumption waste caused by the long - term on - state of the synchronization unit clock and being beneficial to reducing system power consumption.

[0076] In another embodiment, the synchronization unit at the input end and the output end of CSR are distinguished. Refer to Figure 4 As shown, the input end of SCR establishes a communication connection with other functional modules of the on - chip system through the first synchronization unit. For example, it establishes a communication connection with functional module A through the first synchronization unit. The output end of SCR establishes a communication connection with other functional modules of the on - chip system through the second synchronization unit. For example, it establishes a communication connection with functional module B through the second synchronization unit.

[0077] As Figure 4 shown, the clock control component controls the input of the clock signals of the first synchronization unit and the second synchronization unit respectively.

[0078] Among them, Figure 4The number of functional module A shown in [description] can be one or more. Each functional module A can be a module with the same function or modules with different functions. When the number of functional module A is more than one, different functional modules can be connected to the input terminal of CSR through the same synchronization unit, or different functional modules can be respectively connected to the input terminal of CSR through dedicated synchronization units.

[0079] Similarly, the number of the above-mentioned functional module B can be one or more. Each functional module B can be a module with the same function or modules with different functions. When the number of functional module B is more than one, different functional modules can be connected to the output terminal of CSR through the same synchronization unit, or different functional modules can be respectively connected to the input terminal of CSR through dedicated synchronization units.

[0080] Figure 4 The first synchronization unit and the second synchronization unit described in [description] can respectively be a single-level synchronization unit structure or a multi-level synchronization unit structure.

[0081] In Figure 4 In the system architecture shown in [description], the clock control of the synchronization unit by the clock control component is specifically the clock control of the first synchronization unit and the second synchronization unit by the clock control component.

[0082] For example, in some embodiments, it is disclosed that when the clock control component receives a read operation instruction sent to the APB interface, it controls the clock signal of the first synchronization unit to turn on, and when it is confirmed that the data corresponding to the read operation instruction is sent to the control and status register through the first synchronization unit, it controls the clock signal of the first synchronization unit to turn off.

[0083] And / or,

[0084] When the clock control component receives the feedback information indicating that the write operation instruction sent from the APB interface has been executed, it controls the clock signal of the second synchronization unit to turn on, and when it is confirmed that the control and status register outputs the data corresponding to the write operation instruction through the second synchronization unit, it controls the clock signal of the second synchronization unit to turn off.

[0085] Specifically, when the clock control component receives a read operation instruction sent to the APB interface, it first retains the read operation instruction. At the same time, the clock control component controls the clock signal of the first synchronization unit to turn on. At this time, other functional modules connected to the first synchronization unit can send data to the CSR through the first synchronization unit, that is, the data corresponding to the read operation instruction can be sent to the CSR through the first synchronization unit. For example, assume that the read operation instruction sent by the system-on-chip is an instruction to read the data sent by functional module A. When the clock control component receives this read operation instruction, it turns on the clock signal of the first synchronization unit. At this time, the data sent by functional module A is sent to the CSR through the first synchronization unit.

[0086] When the clock control component confirms that the data corresponding to the above read operation instruction is sent to the CSR through the first synchronization unit, it can determine that the current data communication between other functional modules and the CSR is completed. At this time, the clock control component controls the clock signal of the first synchronization unit to turn off, and forwards the read operation instruction to the CSR. At this time, the CSR can feedback the data corresponding to the read operation instruction to the system-on-chip according to the read operation instruction.

[0087] The specific implementation method for the clock control component to confirm that the data corresponding to the above read operation instruction is sent to the CSR, that is, the specific implementation method for the clock control component to determine whether the current data communication between other functional modules and the CSR is completed, can be implemented according to the implementation methods described in other embodiments.

[0088] When the clock control component receives a write operation instruction sent to the APB interface, it sends the write operation instruction to the CSR, and the CSR performs the processing corresponding to the write operation instruction and gives a response. When the clock control component receives the feedback information sent by the CSR from the APB interface indicating that the write operation instruction has been executed, it controls the clock signal of the second synchronization unit to turn on, and when it confirms that the CSR outputs the data corresponding to the write operation instruction through the second synchronization unit, it controls the clock signal of the second synchronization unit to turn off. Then the clock control component feeds back the write operation response information to the system-on-chip.

[0089] Among them, the implementation method for the clock control component to confirm whether the control and status register outputs the data corresponding to the write operation instruction through the second synchronization unit, that is, to determine whether the current data communication between the CSR and other functional modules is completed, can be implemented according to the implementation methods described in other embodiments.

[0090] In some embodiments, the synchronization unit connected to the input or output end of the CSR can be a multi-stage synchronization unit structure. For example, in Figure 4In the shown system-on-chip architecture, the first synchronization unit for connecting other functional module A to the input end of the CSR may include N-level synchronization units, and the N-level synchronization units share the same clock signal with the CSR, where N is a positive integer.

[0091] Taking N equal to 2 as an example, as Figure 5 shown, functional module A is connected to the input end of the CSR through two-level synchronization units, and both two-level synchronization units use the same clock signal clk_c as the CSR.

[0092] Based on Figure 5 the shown system-on-chip architecture, when the clock control component receives a read operation instruction sent to the APB interface, it first retains the read operation instruction. At the same time, the clock control component controls the clock signal of the two-level synchronization units to be turned on. At this time, functional module A connected to the two-level synchronization units can send data to the CSR through the two-level synchronization units, that is, the data corresponding to the read operation instruction can be sent to the CSR through the two-level synchronization units.

[0093] When the clock control component confirms that the data corresponding to the above read operation instruction is sent to the CSR through the first synchronization unit, it can determine that the current data communication between other functional modules and the CSR is completed. At this time, the clock control component controls the clock signal of the first synchronization unit to be turned off, and forwards the read operation instruction to the CSR. At this time, the clock control component can feedback the data corresponding to the read operation instruction to the system-on-chip according to the read operation instruction.

[0094] In Figure 5 the shown system architecture, after the clock control component turns on the clock signal of the two-level synchronization units, it counts the period of the clock signal of the two-level synchronization units. When it is confirmed that the two-level synchronization units receive at least 2 cycles of synchronization signals, that is, when it is confirmed that the clock of the two-level synchronization units is turned on for at least 2 beats, it can be confirmed that the data sent by functional module A has entered the CSR through the two-level synchronization units at this time. At this time, the clock signal of the two-level synchronization units can be controlled to be turned off.

[0095] In this embodiment, when the CSR needs to receive data, the clock control component controls the clock signal of the first synchronization unit to be turned on, thereby avoiding waste of clock power. At the same time, the clock control component controls the clock opening period of the first synchronization unit to be not less than the number of synchronization unit levels included in the first synchronization unit, so as to ensure that during the process of turning on the clock of the first synchronization unit, the data sent by other functional modules can smoothly enter the CSR through the first synchronization unit.

[0096] In some other embodiments, the synchronization unit connected to the output end of the CSR may be a multi-level synchronization unit structure. For example, in Figure 4In the shown system-on-chip architecture, the second synchronization unit for connecting the output terminal of the CSR to other functional module B may include an M-level synchronization unit, and the M-level synchronization unit shares the same clock signal with the CSR, where M is a positive integer.

[0097] Taking M equal to 2 as an example, as Figure 6 shown, the output terminal of the CSR is connected to functional module B through two-level synchronization units, and both two-level synchronization units use the same clock signal clk_c as the CSR.

[0098] Based on Figure 6 the shown system-on-chip architecture, when the clock control component receives a write operation instruction sent to the APB interface (the write operation instruction is used to indicate a write operation on the control signal sent to functional module B), it sends the write operation instruction to the CSR, and the CSR executes the processing corresponding to the write operation instruction and gives a response. When the clock control component receives the feedback information indicating that the write operation instruction executed by the CSR from the APB interface, it controls the clock signal of the two-level synchronization units to turn on, and when it is confirmed that the CSR outputs the data corresponding to the write operation instruction through the two-level synchronization units, it controls the clock signal of the two-level synchronization units to turn off. Then the clock control component feeds back a write operation response message to the system-on-chip.

[0099] In Figure 6 the shown system architecture, after the clock control component turns on the clock signal of the two-level synchronization units, it counts the cycle of the clock signal of the two-level synchronization units. When it is confirmed that the two-level synchronization units receive at least 2 cycles of synchronization signals, that is, when it is confirmed that the clock signal of the two-level synchronization units is turned on for at least 2 beats, it can be confirmed that the data sent by the CSR has entered functional module B through the two-level synchronization units at this time, and at this time, it can control the clock signal of the two-level synchronization units to turn off.

[0100] In this embodiment, when the CSR needs to send data, the clock control component controls the clock signal of the two-level synchronization units included in the second synchronization unit to turn on, so as to avoid waste of clock power consumption. At the same time, the clock control component controls the clock on period of the two-level synchronization units included in the second synchronization unit to be not less than the number of synchronization unit levels included in the second synchronization unit, so as to ensure that during the process of turning on the clock of the two-level synchronization units included in the second synchronization unit, the data sent by the CSR can smoothly enter other functional modules through the two-level synchronization units included in the second synchronization unit.

[0101] In other embodiments, the synchronization unit connected to the output terminal of the CSR may be a multi-level synchronization unit structure, for example, in Figure 4In the shown system-on-chip architecture, the second synchronization unit for connecting the output end of the CSR to other functional module B may include a P-level synchronization unit, where P is a positive integer. The clock signals of the second synchronization unit connected to the output end of the CSR and the clock signal of the CSR may be clock signals from different signal sources, and the frequencies of the clock signals of the second synchronization unit connected to the output end of the CSR and the clock signal of the CSR may be the same or different.

[0102] Taking P equal to 2 as an example, as Figure 7 shown, the output end of the CSR is connected to the functional module B through a 2-level synchronization unit, and the clock signal of the 2-level synchronization unit is clk_b, the clock signal of the CSR is clk_c, the frequencies of clk_b and clk_c are the same, but they are clock signals from different signal sources.

[0103] In Figure 7 the shown architecture, the clock control component includes a clock control signal synchronization unit for performing clock synchronization processing on the clock control signal issued by the clock control component. Among them, the clock control signal synchronization unit may be a single-level synchronization unit structure or a structure with multiple-level synchronization units connected in series. The number of levels of the clock control signal synchronization unit can be selected according to the difference between the clock of the clock control component and the clock of the controlled clock signal. When the difference between the clock of the clock control component and the clock of the controlled clock signal is larger, the number of levels of the clock control signal synchronization unit required is more; when the difference between the clock of the clock control component and the clock of the controlled clock signal is smaller, the number of levels of the clock control signal synchronization unit required is less.

[0104] In the embodiments of the present application, for the convenience of introduction, it is set that the clock control signal synchronization unit in the clock control component includes a J-level clock control signal synchronization unit, where J is a positive integer. In Figure 7 the shown architecture, the clock of the clock control component is the same as the clock of the APB interface of the CSR, that is to say, the clock of the clock control component is the same as the clock of the CSR. This makes the clock signals of the clock control component and the P-level synchronization unit be clock signals from different signal sources. Therefore, the clock signals of the two cannot be strictly synchronized. The clock control signal output by the clock control component is in the clk_c clock domain, while the P-level synchronization unit is in the clk_b clock domain. Therefore, the clock domain of the clock control signal output by the clock control component is switched to the clk_b clock domain through the J-level clock control signal synchronization unit, so as to realize the cross-clock processing of the clock control signal output by the clock control component.

[0105] In some embodiments, the above-mentioned J is equal to the above-mentioned P, that is, the number of levels of the J-level clock control signal synchronization unit is the same as the number of levels of the P-level synchronization unit. For example, the output end of the CSR is connected to a 2-level synchronization unit, and the clock control component includes a 2-level clock control signal synchronization unit.

[0106] Based on Figure 7 In the system architecture shown, when the write operation instruction received by the clock control component is to write the control signal sent to functional module B, the clock control component sends the write operation instruction to the CSR, and the CSR writes the control signal sent to functional module B. When the CSR outputs a feedback signal indicating the completion of the write operation through the APB interface, the clock control component controls the clock signal of the P-level synchronization unit at the output end of the CSR to turn on. At this time, the CSR sends the processed control signal of the write operation to functional module B through the P-level synchronization unit.

[0107] After the clock control component turns on the clock signal of the P-level synchronization unit, it counts the period of the clock signal of the P-level synchronization unit. When it is confirmed that the two-level synchronization unit has received at least P×J (2×2) cycles of synchronization signals, that is, it is confirmed that the clock signals of the two-level synchronization unit have been turned on for at least 4 beats, it can be confirmed that the data sent by the CSR has entered functional module B through the P-level synchronization unit at this time. At this time, the clock signal of the P-level synchronization unit can be controlled to turn off.

[0108] In this embodiment, when the CSR needs to send data, the clock control component controls the clock signals of the two-level synchronization units included in the second synchronization unit to turn on, thereby avoiding waste of clock power consumption. At the same time, the clock control component controls the clock on period of the two-level synchronization units included in the second synchronization unit to be not less than the minimum number of clock cycles required for the clock control signal sent by the clock control component to reach the two-level synchronization units included in the second synchronization unit and for the data output by the CSR to reach other functional modules through the two-level synchronization units included in the second synchronization unit, so as to ensure that the data sent by the CSR can smoothly enter other functional modules through the two-level synchronization units included in the second synchronization unit during the clock on process of the two-level synchronization units included in the second synchronization unit.

[0109] In some other embodiments, the synchronization unit connected to the output end of the CSR can be a multi-level synchronization unit structure. For example, in Figure 4 In the on-chip system architecture shown, the second synchronization unit used to connect the output end of the CSR to other functional module B can include a Q-level synchronization unit, where Q is a positive integer. The clock signal of the second synchronization unit connected to the output end of the CSR and the clock signal of the CSR are clock signals from different signal sources, and the frequencies of the clock signal of the second synchronization unit connected to the output end of the CSR and the clock signal of the CSR are different.

[0110] The clock control component includes a clock control signal synchronization unit for performing clock synchronization processing on the clock control signal issued by the clock control component. Among them, the clock control signal synchronization unit can be a first-level synchronization unit structure or a structure in which multiple-level synchronization units are connected in series. The number of levels of the clock control signal synchronization unit can be selected according to the difference between the clock of the clock control component and the clock of the controlled clock signal. When the difference between the clock of the clock control component and the clock of the controlled clock signal is larger, the more levels of the clock control signal synchronization unit are required. When the difference between the clock of the clock control component and the clock of the controlled clock signal is smaller, the fewer levels of the clock control signal synchronization unit are required.

[0111] In the embodiment of the present application, for the convenience of introduction, it is set that the clock control signal synchronization unit in the clock control component includes a T-level clock control signal synchronization unit, and T is a positive integer. In the above system architecture, the clock of the clock control component is the same as the clock of the APB interface of the CSR, that is to say, the clock of the clock control component is the same as the clock of the CSR. This makes the clock signals of the clock control component and the Q-level synchronization unit be clock signals from different signal sources and different frequencies. Therefore, the two clock signals are not synchronized. Therefore, the clock domain of the clock control signal output by the clock control component is switched to the clock domain of the Q-level synchronization unit through the T-level clock control signal synchronization unit, so as to solve the problem of cross-clock domain of the clock control signal.

[0112] The system hardware architecture at this time can be seen Figure 7 in the shown architecture. The difference is that in this embodiment, the frequencies of clk_b and clk_c are different.

[0113] In some embodiments, the above Q is equal to the above T, that is, the number of levels of the T-level clock control signal synchronization unit is the same as the number of levels of the Q-level synchronization unit. For example, both T and Q are equal to 2.

[0114] In this case, when the clock control component turns on the clock signal of the Q-level synchronization unit, it counts the period of the clock signal of the Q-level synchronization unit. When it is confirmed that the synchronization unit has received at least X periods of synchronization signals, that is, when it is confirmed that the clock signal of the synchronization unit has been turned on for at least X beats, it can be confirmed that the data sent by the CSR has entered the functional module B through the Q-level synchronization unit at this time. At this time, the clock signal of the Q-level synchronization unit can be controlled to be turned off.

[0115] Among them, since the clock frequencies of the clock control component and the Q-level synchronization unit are different, the above X should be calculated and determined according to the number of levels Q of the synchronization unit, the number of levels T of the clock control signal synchronization unit, the frequency of the clock signal clk_b of the Q-level synchronization unit, and the frequency of the clock signal clk_c of the CSR.

[0116] Exemplarily, first, select the clock cycle corresponding to the minimum frequency from the frequencies of the clock signal clk_b of the Q-level synchronization unit and the clock signal clk_c of the CSR. Then, multiply the minimum clock cycle by an integer greater than Q×T. For example, when both Q and T are equal to 2, multiply the minimum clock cycle by 5, and then divide by the cycle of the clock signal clk_c of the CSR to obtain the value of X.

[0117] For example: when both Q and T are equal to 2, assume that the clock frequency of the clock signal clk_c of the CSR is 50 MHz and the clock cycle is 20 ns; the clock frequency of the clock signal clk_b of the Q-level synchronization unit is 10 MHz and the clock cycle is 100 ns. Among clk_c and clk_b, the one with the minimum frequency is clk_b. Calculate 100 ns * 5 / 20 ns = 25, that is, X is 25. In the above calculation process, if it cannot be divided evenly, round up by 1. That is, if the cycle of clk_c is 30 ns, then calculate 100 ns * 5 / 30 = 17.

[0118] In this embodiment, when the CSR needs to send data, the clock control component controls the clock signals of the two-level synchronization units included in the second synchronization unit to be turned on, thereby avoiding waste of clock power consumption. At the same time, in this embodiment, the clock control component controls the on-time of the clock signals of the two-level synchronization units included in the second synchronization unit to be long enough for the data output by the CSR to enter other functional modules through the two-level synchronization units included in the second synchronization unit.

[0119] In other embodiments, there may be multiple other functional modules connected to the output end of the CSR. At this time, each other functional module is respectively connected to the output end of the CSR through a Q-level synchronization unit. At this time, the second synchronization unit includes multiple groups of Q-level synchronization units, and the frequencies of the multiple groups of Q-level synchronization units and the clock signal of the CSR are all different and come from different signal sources.

[0120] As Figure 8 shown, functional module D is connected to the output end of the CSR through a two-level synchronization unit, and its clock signal is clk_d. Functional module E is also connected to the output end of the CSR through a two-level synchronization unit, and its clock signal is clk_e. The clock signal of the CSR is clk_c. Among them, clk_c, clk_d, and clk_e are clock signals from different signal sources and different frequencies.

[0121] In the clock control component, a clock control signal synchronization unit is also set to implement the clock domain switching of the clock control signals sent by the clock control component to each functional module.

[0122] In this system architecture, after the clock control component turns on the clock signals of multiple groups of Q-level synchronization units simultaneously, it counts the periods of the clock signals of the multiple groups of Q-level synchronization units. When it is confirmed that the synchronization unit has received at least X periods of synchronization signals, that is, when it is confirmed that the clock signal of the synchronization unit has been turned on for at least X beats, it can be confirmed that the data sent by the CSR has entered the functional module D and the functional module E through the multiple groups of Q-level synchronization units. At this time, the clock signals of the multiple groups of Q-level synchronization units can be controlled to be turned off.

[0123] Among them, since the clocks of the clock control component and the multiple groups of Q-level synchronization units are completely different, the above-mentioned X should be calculated and determined according to the number of levels Q of the synchronization unit, the number of levels T of the clock control signal synchronization unit, the frequency of the clock signals of the multiple groups of Q-level synchronization units, and the frequency of the clock signal of the CSR.

[0124] In some embodiments, when calculating the above-mentioned X according to the number of levels Q of the synchronization unit, the number of levels T of the clock control signal synchronization unit, the frequency of the clock signals of the multiple groups of Q-level synchronization units, and the frequency of the clock signal of the CSR, first compare the clock signal frequencies of the multiple groups of Q-level synchronization units, select the minimum clock signal frequency, and determine the minimum clock period of the minimum clock signal frequency; then, calculate the product of the minimum clock period and an integer not less than Q×T to obtain the target clock period. In some embodiments, the target clock period can be an integer greater than the product of the minimum clock period and Q×T, or when calculating the target clock period, calculate the product of the minimum clock period and an integer not less than Q×T as the target clock period.

[0125] Finally, calculate the ratio of the target clock period to the clock period corresponding to the clock signal frequency of the CSR to obtain the value of the clock signal period number X. Among them, when the ratio is a non-integer, the value of the clock signal period number X is the value obtained by rounding up the ratio.

[0126] For example: when both Q and T are equal to 2, assume that the clock frequency of the clock signal clk_c of the CSR is 50 MHz and the clock period is 20 ns; the clock frequency of the clock signal clk_d of the 2-level synchronization unit connected to the functional module D is 100 MHz and the clock period is 10 ns, and the clock frequency of the clock signal clk_d of the 2-level synchronization unit connected to the functional module E is 10 MHz and the clock period is 100 ns.

[0127] Among clk_d and clk_e, the one with the minimum frequency is clk_e, and its clock period is 100 ns. Since both Q and T are equal to 2, then Q×T = 4. Calculate 100 ns * 5 to get the target clock period of 500 ns. Finally, calculate 500 ns / 20 ns = 25, that is, X is 25. In the above calculation process, if it cannot be divided evenly, round up by 1. That is, if the period of clk_c is 30 ns, then calculate 100 ns * 5 / 30 = 17.

[0128] In this embodiment, when the CSR needs to send data, the clock control component controls the clock signal of the second synchronization unit to turn on, thereby avoiding waste of clock power consumption. At the same time, in this embodiment, the clock control component controls the clock turn-on duration of the second synchronization unit to be long enough for the data output by the CSR to enter each other functional module through the second synchronization unit.

[0129] In some other embodiments, the specific composition structure of the above-mentioned clock control component is also disclosed. Refer to Figure 9 As shown, the above-mentioned clock control component includes a clock control module, a control signal synchronization module, and a clock gating unit CG.

[0130] Among them, the clock control module is connected to the APB interface of the CSR, and is used to monitor the signals sent to the APB interface and the signals sent out by the APB interface;

[0131] The control signal synchronization module is arranged on the link between the clock signal source of the synchronization unit and the clock gating unit, and is used to switch the clock domain of the clock control signal sent by the clock control module to the clock domain of the synchronization unit;

[0132] The clock gating unit CG is arranged on the clock signal input link of the synchronization unit, and is used to control the on / off of the clock signal of the synchronization unit based on the instruction of the clock control module.

[0133] The above-mentioned control signal synchronization module and the above-mentioned clock gating unit CG are combined to form the clock control signal synchronization unit in the above-mentioned embodiment, which is used to realize the clock synchronization of the clock control signal output by the clock control module, and to realize the on / off control of the clock signal of the synchronization unit through the clock gating unit CG.

[0134] The above-mentioned clock gating unit CG can be implemented by a simple AND gate and a latch, or a more complex integrated gated clock unit can be used.

[0135] It can be understood that in the above-mentioned embodiments of the present application, in addition to proposing some clock control methods, some on-chip systems with the same or different structures are also proposed, and these on-chip systems are configured to implement the clock control methods introduced in the above-mentioned embodiments.

[0136] Based on the system-on-chip proposed in the above embodiments, another embodiment of the present application further proposes a computer device, which includes the above system-on-chip.

[0137] Exemplarily, the above computer device may be a computer, a server, a handheld terminal, a wearable device, etc.

[0138] For the foregoing method embodiments, for simplicity of description, they are all expressed as a series of action combinations. However, those skilled in the art should be aware that the present application is not limited by the described action sequence, because according to the present application, certain steps may be performed in other sequences or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the present application.

[0139] It should be noted that the embodiments in this specification are all described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. For device embodiments, since they are basically similar to the method embodiments, they are described relatively simply, and the relevant parts can refer to the partial description of the method embodiments.

[0140] The steps in the method embodiments of the present application can be adjusted, combined, and deleted according to actual needs. The technical features recorded in each embodiment can be replaced or combined.

[0141] The modules and sub-modules in the devices and terminals in the embodiments of the present application can be combined, divided, and deleted according to actual needs.

[0142] In several embodiments provided by the present application, it should be understood that the disclosed terminals, devices, and methods can be implemented in other ways. For example, the terminal embodiments described above are merely illustrative. For example, the division of modules or sub-modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple sub-modules or modules can be combined or integrated into another module, or some features can be ignored or not executed. Another point, the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of devices or modules can be in electrical, mechanical, or other forms.

[0143] A module or sub-module described as a separation component may or may not be physically separated. A component as a module or sub-module may or may not be a physical module or sub-module, that is, it may be located in one place, or may be distributed to multiple network modules or sub-modules. Some or all of the modules or sub-modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0144] In addition, each functional module or sub-module in various embodiments of the present application can be integrated in a processing module, or each module or sub-module can exist physically alone, or two or more modules or sub-modules can be integrated in one module. The above-mentioned integrated modules or sub-modules can be implemented in the form of hardware, or in the form of software functional modules or sub-modules.

[0145] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of this application.

[0146] The steps of the method or algorithm described in combination with the embodiments disclosed in this article can be directly implemented by hardware, a software unit executed by a processor, or a combination of both. The software unit can be placed in a random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.

[0147] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of another identical element in the process, method, article or device including the said element.

[0148] The foregoing description of the disclosed embodiments enables those skilled in the art to practice or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A clock control method, characterized in that: Applied to a system on chip, the system on chip includes a synchronization unit, a control and status register, and a clock control component, the control and status register establishes a communication connection with other functional modules of the system on chip through the synchronization unit, and the clock control component is connected to the APB interface of the control and status register; The method comprises: The clock control component controls the clock signal of the synchronization unit to be turned on when confirming that the control and status register needs to communicate data with other functional modules according to the received APB interface signal, and controls the clock signal of the synchronization unit to be turned off when confirming that the control and status register completes data communication with other functional modules; The APB interface signal includes a signal sent to the APB interface and / or a signal sent from the APB interface.

2. The method according to claim 1, characterized in that The synchronization unit includes a first synchronization unit and a second synchronization unit. The input end of the control and status register establishes a communication connection with other functional modules of the system on chip through the first synchronization unit, and the output end of the control and status register establishes a communication connection with other functional modules of the system on chip through the second synchronization unit.

3. The method according to claim 2, characterized in that The clock control component controls the clock signal of the synchronization unit to be turned on when confirming that the control and status register needs to communicate data with other functional modules according to the received APB interface signal, and controls the clock signal of the synchronization unit to be turned off when confirming that the control and status register completes data communication with other functional modules, including: The clock control component controls the clock signal of the first synchronization unit to be turned on when receiving a read operation instruction sent to the APB interface, and controls the clock signal of the first synchronization unit to be turned off when confirming that data corresponding to the read operation instruction is sent to the control and status register through the first synchronization unit; and / or, When the clock control component receives feedback information indicating that the write operation instruction has been executed from the APB interface, it controls the clock signal of the second synchronization unit to be turned on, and when it is confirmed that the control and status register outputs data corresponding to the write operation instruction through the second synchronization unit, it controls the clock signal of the second synchronization unit to be turned off.

4. The method according to claim 3, characterized in that The first synchronization unit includes N-level synchronization units, and the N-level synchronization units share the same clock signal with the control and status registers; The clock control component controls the clock signal of the first synchronization unit to be turned off when confirming that the data corresponding to the read operation instruction is sent to the control and status register through the first synchronization unit, including: The clock control component controls the clock signal of the first synchronization unit to be turned off when confirming that the first synchronization unit has received at least N cycles of the clock signal; Wherein, N is a positive integer.

5. The method according to claim 3, characterized in that: The second synchronization unit includes an M-level synchronization unit, and the M-level synchronization unit shares the same clock signal with the control and status register; The clock control component controls the clock signal of the second synchronization unit to be turned off when confirming that the control and status register outputs the data corresponding to the write operation instruction through the second synchronization unit, including: The clock control component controls the clock signal of the second synchronization unit to be turned off when confirming that the second synchronization unit has received at least M cycles of the clock signal; Wherein, M is a positive integer.

6. The method according to claim 3, characterized in that The second synchronization unit includes a P-level synchronization unit, the clock signal of the P-level synchronization unit has the same frequency as the clock signal of the control and status register and comes from a different signal source; P is a positive integer; The clock control component includes a J-level clock control signal synchronization unit, where J is a positive integer; the J-level clock control signal synchronization unit is used to switch the clock domain of the clock control signal issued by the clock control component to the clock domain of the P-level synchronization unit; The clock control component controls the clock signal of the second synchronization unit to be turned off when confirming that the control and status register outputs the data corresponding to the write operation instruction through the second synchronization unit, including: The clock control component controls the clock signal of the second synchronization unit to be turned off when confirming that the second synchronization unit has received at least P×J cycles of the clock signal.

7. The method according to claim 3, characterized in that The second synchronization unit includes a Q-level synchronization unit, where Q is a positive integer; the frequencies of the clock signals of the Q-level synchronization unit and the control and status register are different and come from different signal sources; The clock control component includes a T-level clock control signal synchronization unit, where T is a positive integer; the T-level clock control signal synchronization unit is used to switch the clock domain of the clock control signal issued by the clock control component to the clock domain of the P-level synchronization unit; The clock control component controls the clock signal of the second synchronization unit to be turned off when confirming that the control and status register outputs the data corresponding to the write operation instruction through the second synchronization unit, including: The clock control component controls the clock signal of the second synchronization unit to be turned off when confirming that the second synchronization unit has received at least X cycles of the clock signal; X is a positive integer calculated and determined based on the clock signal frequencies of the Q, T, and Q-level synchronization units and the clock signal frequencies of the control and status registers.

8. The method according to claim 7, characterized in that The second synchronization unit includes a plurality of groups of Q-level synchronization units; the frequencies of the clock signals of the plurality of groups of Q-level synchronization units and the control and status registers are different and come from different signal sources; The X is a positive integer calculated and determined according to the Q, the T, the clock signal frequencies of the multiple groups of Q-level synchronization units, and the clock signal frequencies of the control and status registers.

9. The method according to claim 8, characterized in that The calculation process of X includes: By comparing the clock signal frequencies of the multiple groups of Q-level synchronization units, a minimum clock signal frequency is selected, and a minimum clock period of the minimum clock signal frequency is determined; Calculate the product of the minimum clock cycle and an integer not less than Q×T to obtain a target clock cycle; The ratio of the target clock cycle to the clock cycle corresponding to the clock signal frequency of the control and status register is calculated to obtain the value of the clock signal cycle number X, wherein when the ratio is a non-integer, the value of the clock signal cycle number X is the value of the ratio rounded up.

10. The method according to any one of claims 1 to 9, characterized in that The clock control component includes a clock control module, a control signal synchronization module and a clock gating unit; The clock control module is connected to the APB interface of the control and status register, and is used to monitor the signals sent to the APB interface and the signals sent from the APB interface; The control signal synchronization module is arranged on a link between the clock signal source of the synchronization unit and the clock gating unit, and is used to switch the clock domain of the clock control signal sent by the clock control module to the clock domain of the synchronization unit; The clock gating unit is arranged on the clock signal input link of the synchronization unit, and is used to control the switch of the clock signal of the synchronization unit based on the instruction of the clock control module.

11. A system on chip, characterized in that: It includes a synchronization unit, a control and status register, and a clock control component. The control and status register establishes a communication connection with other functional modules of the system on chip through the synchronization unit, and the clock control component is connected to the APB interface of the control and status register; The system on chip is configured to implement the clock control method according to any one of claims 1 to 10.

12. A computer device, characterized in that: Comprising the system on chip as claimed in claim 11.

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