Phase detection simulation circuit, method and device

Abstract

The present disclosure relates to a phase detection simulation circuit, method, and device, the circuit comprising: a random signal generation module for generating a random signal; a signal selection module for receiving a first simulation delay signal, a second simulation delay signal, and a random signal, and selecting the second simulation delay signal or the random signal as a selection output signal based on a comparison result of a phase difference between the first simulation delay signal and the second simulation delay signal and a preset threshold range; a sampling simulation register for outputting a sampling simulation result signal based on the first simulation delay signal and the selection output signal; wherein the preset threshold range is used to characterize the setup and hold time of the sampling register simulated by the sampling simulation register. The present disclosure implements simulation of a sampling register containing a metastable state, which helps to improve the integrity and reliability of the simulation results, and helps to improve the reliability of the prediction results of whether the simulated phase detection circuit meets the requirements of the design objectives.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit design, and in particular to a phase detection simulation circuit, method, and device. Background Art

[0002] Phase detection circuit plays an important role in integrated circuits. It is related to signal synchronization and demodulation and has a significant impact on the stability and reliability of integrated circuit performance.

[0003] In phase detection circuits, the sampling registers used for signal comparisons are metastable, causing their outputs to rapidly fluctuate between high and low levels. This is difficult to achieve during the pre-simulation phase of circuit design, making it difficult to realistically verify the functionality of phase detection circuits through equivalent simulation. Summary of the Invention

[0004] In view of this, the present disclosure provides a phase detection simulation circuit, method, and apparatus to enable the phase detection simulation circuit to simulate metastable states, thereby helping to improve the reliability of pre-simulation results of integrated circuits.

[0005] The technical solution of the present disclosure is achieved as follows:

[0006] According to one aspect of an embodiment of the present disclosure, a phase detection simulation circuit is provided, including:

[0007] A random signal generating module, wherein the random signal generating module is used to generate a random signal;

[0008] a signal selection module, the signal selection module being configured to receive a first simulated delay signal, a second simulated delay signal, and the random signal, and select one of the second simulated delay signal and the random signal as a selected output signal based on a comparison result of a phase difference between the first simulated delay signal and the second simulated delay signal and a preset threshold range;

[0009] a sampling simulation register, wherein a clock signal terminal of the sampling simulation register is used to receive the first simulation delay signal, an input terminal of the sampling simulation register is used to receive the selection output signal, and the sampling simulation register outputs a sampling simulation result signal at its output terminal according to the first simulation delay signal and the selection output signal, wherein the sampling simulation result signal is used to represent the phase relationship between the first simulation delay signal and the second simulation delay signal;

[0010] The preset threshold range is used to represent the setup and hold time of the sampling register simulated by the sampling simulation register.

[0011] In one possible implementation, the signal selection module includes:

[0012] a phase counting unit, configured to receive the first simulated delay signal and the second simulated delay signal, obtain a first count value at a transition edge instant of the first simulated delay signal, and obtain a second count value at a transition edge instant of the second simulated delay signal, wherein the first count value is used to represent the transition edge instant of the first simulated delay signal, and the second count value is used to represent the transition edge instant of the second simulated delay signal;

[0013] a phase difference comparison unit, configured to obtain the comparison result according to the first count value, the second count value and the preset threshold range;

[0014] A signal selection unit is configured to select one of the second simulated delayed signal and the random signal as the selected output signal according to the comparison result.

[0015] In one possible implementation, the phase counting unit includes:

[0016] a counting unit, the counting unit being configured to perform counting associated with time;

[0017] A capture unit, wherein the capture unit is used to receive the first simulation delay signal and the second simulation delay signal, and capture the first count value generated by the counting unit at the transition edge of the first simulation delay signal, and capture the second count value generated by the counting unit at the transition edge of the second simulation delay signal.

[0018] In one possible implementation, the phase difference comparison unit includes:

[0019] a phase difference calculation unit, configured to obtain the phase difference according to the first count value and the second count value;

[0020] A comparison unit is used to compare the phase difference with the preset threshold range to obtain the comparison result.

[0021] In one possible implementation, the phase detection simulation circuit further includes:

[0022] A first signal simulation delay circuit is configured to receive a first simulation signal and perform simulation delay on the first simulation signal to obtain the first simulation delayed signal;

[0023] The second signal simulation delay circuit is used to receive a second simulation signal and perform simulation delay on the second simulation signal to obtain the second simulation delayed signal.

[0024] In one possible implementation, the first signal emulation delay circuit includes:

[0025] a first simulation delay unit, configured to receive the first simulation signal and perform simulation delay on the first simulation signal to obtain at least one first delayed selected signal;

[0026] a first emulation multiplexer selection unit, configured to receive the at least one first delayed candidate signal and a first selection signal, and select one of the at least one first delayed candidate signal as the first emulation delayed signal according to the first selection signal;

[0027] The second signal simulation delay circuit includes:

[0028] a second simulation delay unit, configured to receive the second simulation signal and perform simulation delay on the second simulation signal to obtain at least one second delayed selected signal;

[0029] The second simulation multi-path selection unit is used to receive the at least one second delayed selected signal and a second selection signal, and select one of the at least one second delayed selected signal as the second simulation delayed signal according to the second selection signal.

[0030] In one possible implementation, the first emulation delay unit includes:

[0031] At least one first emulation delay register cascaded on a path for delaying the first emulation signal, wherein an input end of the first emulation delay register receives a signal to be delayed, and an output end of the first emulation delay register generates a delayed signal, and when there are at least two first emulation delay registers, the first emulation signal is delayed by beats of at least two first emulation delay registers to obtain at least two first delayed selected signals with different delays;

[0032] The second emulation delay unit comprises:

[0033] At least one second simulation delay register is cascaded on a path for delaying the second simulation signal, wherein the input end of the second simulation delay register receives the signal to be delayed, and the output end of the second simulation delay register generates a delayed signal. When the number of the second simulation delay registers is at least two, the second simulation signal is delayed by the beats of at least two of the second simulation delay registers to obtain at least two second delayed selected signals with different delays.

[0034] According to another aspect of an embodiment of the present disclosure, a phase detection simulation method is provided, including:

[0035] Acquire a first simulation delay signal, a second simulation delay signal, and a random signal;

[0036] selecting one of the second simulated delay signal and the random signal as a selected output signal according to a comparison result of a phase difference between the first simulated delay signal and the second simulated delay signal and a preset threshold range;

[0037] Utilizing a clock signal terminal of a sampling simulation register to receive the first simulation delay signal, utilizing an input terminal of the sampling simulation register to receive the selection output signal, and obtaining a sampling simulation result signal at an output terminal of the sampling simulation register, wherein the sampling simulation result signal is used to characterize a phase relationship between the first simulation delay signal and the second simulation delay signal;

[0038] The preset threshold range is used to represent the setup and hold time of the sampling register simulated by the sampling simulation register.

[0039] In one possible implementation, selecting one of the second simulated delay signal and the random signal as the selected output signal based on a comparison result of the phase difference between the first simulated delay signal and the second simulated delay signal with a preset threshold range includes:

[0040] When the comparison result shows that the phase difference is outside the preset threshold range, using the second simulated delay signal as a selection output signal;

[0041] When the comparison result shows that the phase difference is within the preset threshold range, the random signal is used as a selection output signal.

[0042] In one possible implementation, the phase detection simulation method further includes:

[0043] Acquire a first simulation signal and a second simulation signal;

[0044] Performing simulation delay on the first simulation signal to obtain the first simulation delayed signal;

[0045] Performing simulation delay on the second simulation signal to obtain the second simulation delayed signal.

[0046] According to another aspect of an embodiment of the present disclosure, a phase detection simulation device is provided, comprising:

[0047] A signal receiving module is configured to receive a first simulated delayed signal, a second simulated delayed signal and a random signal;

[0048] a selection module configured to select one of the second simulated delay signal and the random signal as a selection output signal according to a comparison result between a phase difference between the first simulated delay signal and the second simulated delay signal and a preset threshold range;

[0049] a phase relationship determination module, configured to receive the first simulation delay signal using a clock signal terminal of a sampling simulation register, receive the selection output signal using an input terminal of the sampling simulation register, and obtain a sampling simulation result signal at an output terminal of the sampling simulation register, wherein the sampling simulation result signal is used to represent the phase relationship between the first simulation delay signal and the second simulation delay signal;

[0050] The preset threshold range is used to represent the setup and hold time of the sampling register simulated by the sampling simulation register.

[0051] According to another aspect of the present disclosure, an electronic device is provided, including:

[0052] processor;

[0053] a memory for storing executable instructions for the processor;

[0054] The processor is configured to execute the executable instructions to implement the phase detection simulation method as described in any one of the above items.

[0055] According to another aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided. When at least one instruction in the computer-readable storage medium is executed by a processor of an electronic device, the electronic device can implement the phase detection simulation method as described in any one of the above items.

[0056] It can be seen from the above scheme that the phase detection simulation circuit, method and device disclosed in the present invention use the comparison between the phase difference between the first simulation delay signal and the second simulation delay signal and the preset threshold range to determine whether the jump edge of the second simulation delay signal falls within the "setup and hold time" of the sampling simulation register, and based on the determination result of whether the jump edge of the second simulation delay signal falls within the "setup and hold time" of the sampling simulation register, select the second simulation delay signal or the random signal to the sampling simulation register, and then the sampling simulation register outputs the sampling simulation result signal at its output end according to the first simulation delay signal received at its clock signal end and the selected output signal (second simulation delay signal or random signal) received at its input end. Among them, a random number is used to replace the input signal of the sampling simulation register within the "setup and hold time" of the sampling simulation register, wherein the value of the random number may be the same as or different from the second simulation delay signal. In this way, the input signal within the setup and hold time of the sampling simulation register may be correct or incorrect, and thus the output signal of the sampling simulation register may be correct or incorrect, thereby simulating the uncertainty of the output signal result of the sampling register after the metastable state ends due to the existence of the metastable state, thereby realizing the simulation of the sampling register containing the metastable state, equivalent to the sampling situation of the sampling register, solving the simulation problem of the phase detection circuit in the digital circuit, helping to improve the integrity and reliability of the simulation results of the phase detection simulation circuit, and helping to improve the reliability of the prediction results of whether the phase detection circuit simulated by the phase detection simulation circuit meets the requirements of the design target. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 This is a structural diagram of a phase detection circuit in the related art;

[0058] Figure 2 It is a structural diagram of a phase detection simulation circuit in the related art;

[0059] Figure 3 is a structural diagram of a phase detection simulation circuit according to an exemplary embodiment;

[0060] Figure 4 is a structural diagram of a second phase detection simulation circuit according to an exemplary embodiment;

[0061] Figure 5 is a flow chart illustrating a phase detection simulation method according to an exemplary embodiment;

[0062] Figure 6 is a schematic diagram illustrating a process of obtaining a simulated delay signal according to an exemplary embodiment;

[0063] Figure 7is a schematic diagram of a phase detection simulation system according to an exemplary embodiment;

[0064] Figure 8 is a structural diagram of a phase detection simulation device according to an exemplary embodiment;

[0065] Figure 9 It is a structural diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0066] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below with reference to the accompanying drawings and examples.

[0067] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0068] Figure 1 This is a structural diagram of a phase detection circuit in related technology, such as Figure 1 As shown, the phase detection circuit includes a first delay circuit 10, a second delay circuit 20, and a sampling register 30. When the phase detection circuit is used to perform phase detection on a first signal s1 and a second signal s2, the first signal s1 and the second signal s2 are input to the first delay circuit 10 and the second delay circuit 20, respectively. Under the control of a first delay control signal cs1 and a second delay control signal cs2, the first delay circuit 10 and the second delay circuit 20 respectively delay the first signal s1 and the second signal s2 to obtain a first delayed signal s11 and a second delayed signal s21. The output of the first delay circuit 10 and the output of the second delay circuit 20 are respectively coupled to the clock signal terminal clk and the input terminal D of the sampling register 30. A sampling result signal s_out is generated at the output terminal Q of the sampling register 30, so that the phase relationship between the first signal s1 and the second signal s2 can be determined based on the sampling result signal s_out. The sampling register 30 can be a D flip-flop.

[0069] Figure 2 It is a structural diagram of a phase detection simulation circuit in related technology. Figure 2 The structure shown is Figure 1 The simulation circuit of the phase detection circuit in the design stage is shown. Figure 2 The structure shown is a virtual circuit implemented by computer program code, which is used to verify the correctness of the phase detection circuit. Figure 2As shown, the phase detection simulation circuit includes a first signal simulation delay circuit 11, a second signal simulation delay circuit 21 and a sampling simulation register 31. The first signal simulation delay circuit 11 receives a first simulation signal ss1, delays the first simulation signal ss1 through the beat buffer of the simulation register therein, and obtains a first simulation delay signal ss11 under the control of a first simulation delay control signal scs1. The second signal simulation delay circuit 21 receives a second simulation signal ss2, delays the second simulation signal ss2 through the beat buffer of the simulation register therein, and obtains a second simulation delay signal ss21 under the control of a second simulation delay control signal scs2. The output end of the first signal simulation delay circuit 11 and the output end of the second signal simulation delay circuit 21 are respectively coupled to the clock signal end clk and the input end D of the sampling simulation register 31. The sampling simulation result signal ss_out is generated at the output end Q of the sampling simulation register 31. The phase relationship between the first simulation signal ss1 and the second simulation signal ss2 can be determined based on the sampling simulation result signal ss_out.

[0070] Among them, the first signal simulation delay circuit 11 is a simulation circuit for simulating the first delay circuit 10, the second signal simulation delay circuit 21 is a simulation circuit for simulating the second delay circuit 20, the sampling simulation register 31 is a simulation circuit for simulating the sampling register 30, the first simulation signal ss1 is a simulation signal for simulating the first signal s1, the second simulation signal ss2 is a simulation signal for simulating the second signal s2, the first simulation delay control signal scs1 is a simulation signal for simulating the first delay control signal cs1, the second simulation delay control signal scs2 is a simulation signal for simulating the second delay control signal cs2, the first simulation delay signal ss11 is a simulation signal for simulating the first delay signal s11, the second simulation delay signal ss21 is a simulation signal for simulating the second delay signal s21, and the sampling simulation result signal ss_out is a simulation signal for simulating the sampling result signal s_out.

[0071] Although the phase detection simulation circuit can simulate the phase detection circuit before manufacturing to predict the accuracy of the phase detection circuit, that is, to predict whether the designed phase detection circuit meets the design requirements, it is difficult to fully predict the entire behavior of the phase detection circuit due to the objective behavior of the semiconductor devices themselves within the integrated circuit under physical conditions. For example, the impact of the metastable state of the sampling register on the signal is difficult to simulate and predict using the phase detection simulation circuit.

[0072] Because integrated circuit technology uses the Complementary Metal-Oxide-Semiconductor (CMOS) process for device fabrication, registers are composed of multiple semiconductor devices. The charging and discharging processes of these semiconductor devices require time, and signal transmission within the register is also subject to time constraints. Consequently, registers can experience metastable states. Metastable states occur when a register cannot reach a recognizable state within a specified timeframe. When a register is in a metastable state, its output oscillates for an extended period of time. This oscillating output level propagates through the signal path, impacting circuit functionality.

[0073] Failure to meet the register setup and hold times during timing will result in metastable states. Therefore, timing design must meet the register setup and hold time requirements. The setup time (Tsu) refers to the time it takes for the input signal level to remain stable before the rising edge of the register's clock signal. If the setup time is insufficient, the input signal level will not be stably programmed into the register on the rising edge of the clock signal. The hold time (Td) refers to the time it takes for the input signal level to remain stable after the rising edge of the register's clock signal. If the hold time is insufficient, the input signal level will not be stably programmed into the register.

[0074] Due to the presence of register metastable states, phase detection simulation circuits in related technologies cannot simulate situations where the sampling register is within the setup and hold time during digital circuit simulation and field-programmable gate array (FPGA) verification. This means that the phase difference between the detected signals (e.g., the first delayed signal s11 and the second delayed signal s21) is within the setup and hold time of the sampling register. This, in turn, prevents the phase detection circuit's functionality from being truly verified using an equivalent simulation circuit. In the disclosed embodiments, the setup and hold time refers to the period between the start of the setup time and the end of the hold time.

[0075] In view of this, the embodiments of the present disclosure provide a phase detection simulation circuit, method and device to realize the simulation of the metastable behavior of the sampling register, thereby helping to improve the integrity and reliability of the simulation results of the phase detection simulation circuit, and helping to improve the reliability of the prediction results of whether the phase detection circuit simulated by the phase detection simulation circuit meets the requirements of the design objectives.

[0076] Figure 3 FIG. 1 is a structural diagram of a phase detection simulation circuit according to an exemplary embodiment. Figure 3As shown, the phase detection simulation circuit mainly includes a random signal generation module 41, a signal selection module 42 and a sampling simulation register 31. Among them, the random signal generation module 41 is used to generate a random signal rs. The signal selection module 42 is logically coupled to the random signal generation module 41. The signal selection module 42 is used to receive a first simulated delay signal ss11, a second simulated delay signal ss21 and the random signal rs, and select one of the second simulated delay signal ss21 and the random signal rs as the selected output signal sos based on the comparison result cr between the phase difference pd between the first simulated delay signal ss11 and the second simulated delay signal ss21 and a preset threshold range. The input terminal D of the sampling simulation register 31 is logically coupled to the signal selection module 42. The clock signal terminal clk of the sampling simulation register 31 is used to receive the first simulation delay signal ss11. The input terminal D of the sampling simulation register 31 is used to receive the selection output signal sos. The sampling simulation register 31 outputs a sampling simulation result signal ss_out at its output terminal Q based on the first simulation delay signal ss11 and the selection output signal sos. The sampling simulation result signal ss_out is used to represent the phase relationship between the first simulation delay signal ss11 and the second simulation delay signal ss21. The preset threshold range is used to represent the setup and hold time of the sampling register simulated by the sampling simulation register 31.

[0077] In the phase detection simulation circuit of the disclosed embodiment, the comparison result cr of the phase difference pd between the first simulated delay signal ss11 and the second simulated delay signal ss21 with a preset threshold range indicates whether the simulated phase difference between the first delay signal s11 and the second delay signal s21 falls within the setup and hold time of the sampling register. Although the sampling simulation register 31 itself does not exist in a metastable state, based on the truth table relationship between the input signal and the output signal of the register, the randomness of the input terminal D signal of the sampling simulation register 31 will directly lead to the randomness of the sampling simulation result signal ss_out output by the sampling simulation register 31. Therefore, in the phase detection simulation circuit of the embodiment of the present disclosure, the signal selection module 42 uses the comparison between the phase difference pd between the first simulation delay signal ss11 and the second simulation delay signal ss21 and the preset threshold range to determine whether (the transition edge of) the second simulation delay signal ss21 falls within the "setup and hold time" of the sampling simulation register 31, and based on the determination result of whether (the transition edge of) the second simulation delay signal ss21 falls within the "setup and hold time" of the sampling simulation register 31, the second simulation delay signal ss21 or the random signal rs is selected to be given to the sampling simulation register 31, and then the sampling simulation register 31 outputs the sampling simulation result signal ss_out at its output terminal Q according to the first simulation delay signal ss11 received at its clock signal terminal clk and the selected output signal sos (the second simulation delay signal ss21 or the random signal rs) received at its input terminal D, thereby realizing the simulation of the random output result of the sampling register 30 after the end of the metastable state. Because the output signal of the sampling register 30 after the metastable state ends is random and uncertain, even if there may be a difference between the sampling simulation result signal ss_out obtained by the sampling simulation register 31 according to the random signal rs each time and the random output result of the sampling register 30 after each metastable state ends in the embodiment of the present disclosure, from a statistical point of view, such a difference does not affect the reliability of the simulation statistical results corresponding to the statistical results of the random outputs of the sampling register 30 after multiple metastable states end.

[0078] In an exemplary embodiment, the sampling simulation register 31 may be implemented using a simulated D flip-flop.

[0079] Continue to see Figure 3As shown, in the exemplary embodiment, the signal selection module 42 may include a phase counting unit 421 , a phase difference comparing unit 422 and a signal selecting unit 423 . Among them, the phase counting unit 421 is used to receive the first simulation delay signal ss11 and the second simulation delay signal ss21, obtain a first count value cv1 at the transition edge moment of the first simulation delay signal ss11, and obtain a second count value cv2 at the transition edge moment of the second simulation delay signal ss21, wherein the first count value cv1 is used to represent the transition edge moment of the first simulation delay signal ss11, and the second count value cv2 is used to represent the transition edge moment of the second simulation delay signal ss21; the phase difference comparison unit 422 is logically coupled to the phase counting unit 421, and is used to obtain a comparison result cr based on the first count value cv1, the second count value cv2 and the preset threshold range; the signal selection unit 423 is logically coupled to the phase difference comparison unit 422, the random signal generation module 41 and the sampling simulation register 31, and the signal selection unit 423 is used to select one of the second simulation delay signal ss21 and the random signal rs as the selected output signal sos according to the comparison result cr.

[0080] In an exemplary embodiment, the signal selection unit 423 may be a multiplexer, wherein the second simulated delayed signal ss21 and the random signal rs are two input signals of the multiplexer, the comparison result cr is a gating control signal of the multiplexer, and the selected output signal sos is an output signal of the multiplexer. The multiplexer is an emulated device.

[0081] Continue to see Figure 3 As shown, in order to obtain a first count value cv1 at the transition moment of the first simulated delay signal ss11 and a second count value cv2 at the transition moment of the second simulated delay signal ss21, in an exemplary embodiment, the phase counting unit 421 includes a counting unit 4211 and a capture unit 4212. The counting unit 4211 is configured to perform time-related counting. For example, as time passes, the count value of the counting unit 4211 continuously increases. In an exemplary embodiment, a higher-frequency clock signal can be used as a control signal to perform counting in the counting unit 4211. The capture unit 4212 is logically coupled to the counting unit 4211 and is configured to receive the first simulated delay signal ss11 and the second simulated delay signal ss21, and to capture the first count value cv1 generated by the counting unit 4211 at the transition moment of the first simulated delay signal ss11, and to capture the second count value cv2 generated by the counting unit 4211 at the transition moment of the second simulated delay signal ss21.

[0082] Continue to see Figure 3As shown, in order to obtain a comparison result cr, in the exemplary embodiment, the phase difference comparison unit 422 may include a phase difference calculation unit 4221 and a comparison unit 4222. The phase difference calculation unit 4221 is logically coupled to the phase counting unit 421. Furthermore, the phase difference calculation unit 4221 is logically coupled to the capture unit 4212. The phase difference calculation unit 4221 is configured to obtain a phase difference pd based on the first count value cv1 and the second count value cv2. The comparison unit 4222 is logically coupled to the phase difference calculation unit 4221 and the signal selection unit 423. The comparison unit 4222 is configured to compare the phase difference pd with a preset threshold range to obtain a comparison result cr.

[0083] In an illustrative embodiment, the preset threshold range may include a range within a first threshold and a second threshold, wherein the first threshold is a negative value, the second threshold is a positive value, the phase difference pd is the difference between the first count value cv1 and the second count value cv2, the phase difference pd is greater than or equal to the first threshold and less than or equal to the second threshold (that is, the phase difference pd is within the preset threshold range), indicating that the transition edge of the second simulation delay signal ss21 falls within the "setup and hold time" of the sampling simulation register 31, and the phase difference pd is less than the first threshold or greater than the second threshold (that is, the phase difference pd is outside the preset threshold range), indicating that the transition edge of the second simulation delay signal ss21 is outside the "setup and hold time" of the sampling simulation register 31.

[0084] In an exemplary embodiment, when the comparison result cr is that the phase difference pd is outside the preset threshold range, the second simulated delay signal ss21 is used as the selected output signal sos; when the comparison result cr is that the phase difference pd is within the preset threshold range, the random signal rs is used as the selected output signal sos.

[0085] In an exemplary embodiment, if the phase difference pd is outside the preset threshold range, the value of the comparison result cr can be 1; if the phase difference pd is within the preset threshold range, the value of the comparison result cr can be 0; or, if the phase difference pd is outside the preset threshold range, the value of the comparison result cr can be 0; if the phase difference pd is within the preset threshold range, the value of the comparison result cr can be 1.

[0086] In an exemplary embodiment, the random signal generating module 41 can be implemented using various simulation circuits that can generate a random signal rs of 0 or 1. For example, a simulation model of a linear feedback shift register can be used as the random signal generating module 41 to generate the random signal rs.

[0087] In an exemplary embodiment, which can be combined with a phase detection simulation circuit in related art, the first simulation delay signal ss11 and the second simulation delay signal ss21 can be obtained by delaying the first simulation signal ss1 and the second simulation signal ss2. Figure 4 FIG. 1 is a structural diagram of a second phase detection simulation circuit according to an exemplary embodiment. Figure 4 As shown, in Figure 3 Based on the structure of the phase detection simulation circuit embodiment shown, the phase detection simulation circuit further includes a first signal simulation delay circuit 11 and a second signal simulation delay circuit 21. The first signal simulation delay circuit 11 is logically coupled to the signal selection module 42. The first signal simulation delay circuit 11 is also logically coupled to the clock signal terminal clk of the sampling simulation register 31. The first signal simulation delay circuit 11 is used to receive a first simulation signal ss1 and simulate delay the first simulation signal ss1 to obtain a first simulation delay signal ss11. The second signal simulation delay circuit 21 is logically coupled to the signal selection module 42. The second signal simulation delay circuit 21 is used to receive a second simulation signal ss2 and simulate delay the second simulation signal ss2 to obtain a second simulation delay signal ss21.

[0088] It should be noted that Figure 4 In the embodiment of the phase detection simulation circuit shown in FIG. 1 , the structure and function of the signal selection module 42 are similar to those of FIG. Figure 3 The signal selection modules 42 shown have the same structure and function.

[0089] Continue to see Figure 4 As shown, in the exemplary embodiment, the first signal simulation delay circuit 11 includes a first simulation delay unit 111 and a first simulation multiplexing unit 112. The first simulation delay unit 111 is used to receive the first simulation signal ss1, simulate and delay the first simulation signal ss1 to obtain at least one first delayed selected signal, such as Figure 4 As shown, the at least one first delayed selected signal includes a first delayed selected signal dss1_1, a first delayed selected signal dss1_2, ..., a first delayed selected signal dss1_N. The first simulation multiplexer 112 is logically coupled to the first simulation delay unit 111, the signal selection module 42, and the sampling simulation register 31. The first simulation multiplexer 112 is configured to receive the at least one first delayed selected signal and a first selection signal s_s1, and select one of the at least one first delayed selected signal as the first simulation delayed signal ss11 according to the first selection signal s_s1, for example. Figure 4 As shown, the first emulation multiplexing unit 112 selects one of the first delayed selected signals dss1_1 to the first delayed selected signals dss1_N as the first emulation delayed signal ss11 .

[0090] In the exemplary embodiment, the second signal simulation delay circuit 21 includes a second simulation delay unit 211 and a second simulation multiplexing unit 212. The second simulation delay unit 211 is used to receive the second simulation signal ss2, simulate and delay the second simulation signal ss2 to obtain at least one second delayed selected signal, such as Figure 4 As shown, the at least one second delayed selected signal includes a second delayed selected signal dss2_1, a second delayed selected signal dss2_2, ..., a second delayed selected signal dss2_M. The second simulation multiplexer selection unit 212 is logically coupled to the second simulation delay unit 211 and the signal selection module 42. The second simulation multiplexer selection unit 212 is configured to receive the at least one second delayed selected signal and a second selection signal s_s2, and select one of the at least one second delayed selected signal as the second simulation delayed signal ss21 according to the second selection signal s_s2, for example. Figure 4 As shown, the second emulation multiplexing unit 212 selects one of the second delayed selected signals dss2_1 to the second delayed selected signals dss2_M as the second emulation delayed signal ss21 .

[0091] In an exemplary embodiment, the first emulation delay unit 111 may include at least one first emulation delay register logically cascaded on a path for delaying the first emulation signal ss1, wherein the input terminal D of each first emulation delay register receives the signal to be delayed, and the output terminal Q of each first emulation delay register generates a delayed signal. When there are at least two first emulation delay registers, the first emulation signal ss1 is delayed by the beats of the at least two first emulation delay registers to obtain at least two first delayed selected signals with different delays. For example Figure 4 As shown, the first simulation delay unit 111 includes N first simulation delay registers logically cascaded on the path of delaying the first simulation signal ss1, for example, N≥3, including the first simulation delay register SDR1_1, the first simulation delay register SDR1_2,..., the first simulation delay register SDR1_N, wherein the input end D of the first simulation delay register SDR1_1 to the first simulation delay register SDR1_N receives the signal to be delayed, and the first simulation delay register SDR1_1 to the first simulation delay register SDR1_N generate a delayed signal, and the first simulation signal ss1 obtains the first delayed selected signal dss1_1 to the first delayed selected signal dss1_N after different delays through the beat delay of the first simulation delay register SDR1_1 to the first simulation delay register SDR1_N.

[0092] In an exemplary embodiment, the second emulation delay unit 211 may include at least one second emulation delay register logically cascaded on a path for delaying the second emulation signal ss2, wherein the input terminal D of each second emulation delay register receives the signal to be delayed, and the output terminal Q of each second emulation delay register generates a delayed signal. When the number of the second emulation delay registers is at least two, the second emulation signal ss2 is delayed by the beats of the at least two second emulation delay registers to obtain at least two second delayed selected signals with different delays. For example Figure 4 As shown, the second simulation delay unit 211 includes M first simulation delay registers logically cascaded on the path of delaying the second simulation signal ss2, for example, M≥3 (M can be equal to N or not equal to N), including a second simulation delay register SDR2_1, a second simulation delay register SDR2_2,..., a second simulation delay register SDR2_M, wherein the input end D of the second simulation delay register SDR2_1 to the second simulation delay register SDR2_M receives the signal to be delayed, and the second simulation delay register SDR2_1 to the second simulation delay register SDR2_M generate a delayed signal, and the second simulation signal ss2 obtains the second delayed selected signal dss2_1 to the second delayed selected signal dss2_M after different delays through the beat delay of the second simulation delay register SDR2_1 to the second simulation delay register SDR2_M.

[0093] In an exemplary embodiment, the first emulated delay register and the second emulated delay register may be implemented using emulated D flip-flops.

[0094] In an illustrative embodiment, in the phase detection simulation circuit of the embodiment of the present disclosure, the random signal generation module 41, the signal selection module 42, the first signal simulation delay circuit 11 and the second signal simulation delay circuit 21 can all use a clock signal ck having a frequency higher than the frequency of the first simulation delay signal ss11 and the frequency of the second simulation delay signal ss21 for timing control, thereby ensuring that the registers in the phase detection simulation circuit of the embodiment of the present disclosure can correctly capture the signal state of their input terminals in each clock cycle, wherein the clock signal ck is connected to the clock signal terminal clk of each first simulation delay register and the second simulation delay register, for example Figure 4 As shown, the clock signal ck is connected to the clock signal terminal clk of the first emulation delay register SDR1_1 to the first emulation delay register SDR1_N and the second emulation delay register SDR2_1 to the second emulation delay register SDR2_M. In the first signal emulation delay circuit 11 and the second signal emulation delay circuit 21, the signal period of the clock signal ck is the minimum delay time of the emulation signal received by each first emulation delay register and each second emulation delay register, for example Figure 4 As shown, the signal period of the clock signal ck is the minimum delay time of each of the first emulation delay registers SDR1_1 to SDR1_N and the second emulation delay registers SDR2_1 to SDR2_M for the received emulation signal.

[0095] In digital circuit systems, if the setup and hold time requirements of a trigger are not met during data transmission, a metastable state may occur. This occurs when the trigger's output signal remains in an uncertain state for a long period after the active clock edge. During this period, the trigger's output signal oscillates between 0 and 1, rather than being equal to the trigger's input signal. This period is called the resolve time. After the resolve time, the trigger's output signal will stabilize to either 0 or 1, but this stabilization is random and has no necessary relationship to the input signal. This means that the trigger's stable output signal may be an erroneous signal. The idea of the phase detection simulation circuit of the embodiment of the present disclosure is to use a random number (random signal rs) to replace the input signal of the sampling simulation register 31 (the second simulation delay signal ss21) within the setup and hold time of the sampling simulation register 31, wherein the random number may be 0 or 1, that is, the value of the random signal rs may be the same as or different from the value of the second simulation delay signal ss21. In this way, the input signal within the setup and hold time of the sampling simulation register 31 may be correct or incorrect, and thus the output signal of the sampling simulation register 31 may also be correct or incorrect, thereby simulating the uncertainty of the output signal result of the sampling register 30 after the metastable state ends due to the existence of the metastable state. In this way, by counting the accuracy or error rate of the output signal of the sampling simulation register 31 within a period of time, the statistical law of the phase detection simulation circuit can be obtained based on the accuracy rate or error rate, thereby performing relevant verification on the corresponding phase detection circuit.

[0096] Based on this, in an illustrative embodiment, the present disclosure further provides a phase detection simulation statistics system, which may include a statistics module and the phase detection simulation circuit of any of the above-mentioned embodiments. The statistics module is logically coupled to the output terminal Q of the sampling simulation register 31, and is configured to receive the sampling simulation result signal ss_out and to calculate the accuracy or error rate of the sampling simulation result signal ss_out within a preset time period.

[0097] Figure 5 FIG. 1 is a flow chart of a phase detection simulation method according to an exemplary embodiment. Figure 5 As shown, the phase detection simulation method mainly includes the following steps 501 to 503.

[0098] Step 501: Acquire a first simulation delay signal, a second simulation delay signal, and a random signal;

[0099] Step 502: selecting one of the second simulated delay signal and the random signal as a selected output signal based on a comparison result of a phase difference between the first simulated delay signal and the second simulated delay signal and a preset threshold range;

[0100] Step 503: Receive the first simulation delay signal using the clock signal end of the sampling simulation register, and receive the selection output signal using the input end of the sampling simulation register, and obtain a sampling simulation result signal at the output end of the sampling simulation register, wherein the sampling simulation result signal is used to characterize the phase relationship between the first simulation delay signal and the second simulation delay signal.

[0101] The preset threshold range is used to represent the setup and hold time of the sampling register simulated by the sampling simulation register.

[0102] In an exemplary embodiment, step 502 may specifically include: when the comparison result shows that the phase difference is outside the preset threshold range, using the second simulated delay signal as the selected output signal; when the comparison result shows that the phase difference is within the preset threshold range, using the random signal as the selected output signal.

[0103] Figure 6 FIG. 1 is a flow chart showing a process of obtaining a simulated delay signal according to an exemplary embodiment. Figure 6 As shown, the phase detection simulation method implemented in the present disclosure may further include the following steps 601 to 603.

[0104] Step 601: Acquire a first simulation signal and a second simulation signal;

[0105] Step 602: Perform simulation delay on the first simulation signal to obtain a first simulation delayed signal;

[0106] Step 603: Perform simulation delay on the second simulation signal to obtain a second simulation delayed signal.

[0107] In an exemplary embodiment, the phase detection simulation method of the embodiment of the present disclosure may further include: calculating the accuracy or error rate of the sampling simulation result signal within a preset time period.

[0108] The implementation of each step in the phase detection simulation method implemented in the present disclosure can refer to the relevant description in the above-mentioned phase detection simulation circuit embodiment, and will not be elaborated here.

[0109] The embodiment of the present disclosure also provides a phase detection simulation system 700, such as Figure 7As shown, the phase detection simulation system 700 includes a first processor 710 and a storage device 720. The storage device 720 is coupled to the first processor 710. In an exemplary embodiment, the system may be, for example, a server system, and the storage device 720 and the first processor 710 are coupled via a bus system in the server system. In the exemplary embodiment, the storage device 720 is used to store programs, scripts, files, data, etc. associated with the phase detection simulation method. In the exemplary embodiment, the first processor 710 can execute programs and scripts to implement and execute the phase detection simulation circuit and method. The files and data may include files and data related to the phase detection simulation method.

[0110] In this exemplary embodiment, the first processor 710 may obtain corresponding results by accessing content (at least one of a program, script, file, and data) stored in the storage device 720 and executing corresponding processing. For example, the first processor 710 may establish a model of the phase detection simulation circuit by accessing relevant parameters of the phase detection simulation circuit stored in the storage device 720, and obtain desired results by executing the phase detection simulation circuit model. All intermediate data, files, final results, and data involved may be stored in the storage device 720.

[0111] In an exemplary embodiment, the first processor 710 may be a central processing unit (CPU), other programmable general-purpose or special-purpose microprocessor, a digital signal processor (DSP), a programmable controller, an application-specific integrated circuit (ASIC), a programmable logic device (PLD), other similar processing devices, or a combination of these devices. In an exemplary embodiment, the storage device 720 may be a computer-readable storage medium having computer-readable instructions stored thereon. When the computer-readable instructions are executed by the first processor 710, the steps of the phase detection simulation method of the embodiment of the present disclosure may be performed. In an exemplary embodiment, the computer-readable storage medium may be, for example, a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM) used as an external cache. By way of example and not limitation, various forms of RAM may be used, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), direct memory bus random access memory (DR RAM), etc. The storage device 720 may store data, scripts, programs, software, algorithms, etc. required to implement the various steps of the phase detection simulation method according to the embodiment of the present disclosure, and provide the data for execution by the first processor 710.

[0112] Figure 8 FIG. 1 is a structural diagram of a phase detection simulation device according to an exemplary embodiment. Figure 8As shown, the phase detection simulation device mainly includes a signal receiving module 801, a selection module 802 and a phase relationship determination module 803. The signal receiving module 801 is configured to receive a first simulation delay signal, a second simulation delay signal and a random signal. The selection module 802 is configured to select one of the second simulation delay signal and the random signal as a selection output signal based on a comparison result of the phase difference between the first simulation delay signal and the second simulation delay signal and a preset threshold range. The phase relationship determination module is configured to receive the first simulation delay signal using the clock signal end of the sampling simulation register, and receive the selection output signal using the input end of the sampling simulation register, and obtain a sampling simulation result signal at the output end of the sampling simulation register, wherein the sampling simulation result signal is used to characterize the phase relationship between the first simulation delay signal and the second simulation delay signal. The preset threshold range is used to characterize the setup and hold time of the sampling register simulated by the sampling simulation register.

[0113] In an exemplary embodiment, the selection module 802 is further configured to execute: when the comparison result is that the phase difference is outside the preset threshold range, the second simulated delay signal is used as the selected output signal; when the comparison result is that the phase difference is within the preset threshold range, the random signal is used as the selected output signal.

[0114] In an exemplary embodiment, the phase detection simulation device further includes:

[0115] A simulation signal acquisition module is configured to acquire a first simulation signal and a second simulation signal;

[0116] A first delay module is configured to perform simulation delay on the first simulation signal to obtain a first simulation delayed signal;

[0117] The second delay module is configured to perform simulation delay on the second simulation signal to obtain a second simulation delayed signal.

[0118] In an exemplary embodiment, the phase detection simulation apparatus further includes:

[0119] The phase relationship statistics module is configured to perform statistics on the accuracy or error rate of the sampling simulation result signal within a preset time period.

[0120] Regarding the phase detection simulation device in the above embodiment, the specific manner in which each unit performs operations has been described in detail in the embodiments of the phase detection simulation method and the phase detection simulation circuit, and will not be elaborated here.

[0121] It should be noted that the above embodiments are only illustrative of the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0122] Figure 9 It is a structural diagram of an electronic device provided by an embodiment of the present disclosure. In some embodiments, the electronic device is a server. The electronic device 900 may have relatively large differences due to different configurations or performances, and may include one or more processors (Central Processing Units, CPU) 901 and one or more memories 902, wherein the memory 902 stores at least one program code, and the at least one program code is loaded and executed by the processor 901 to implement the phase detection simulation method provided by each of the above embodiments. Of course, the electronic device 900 may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output. The electronic device 900 may also include other components for realizing the functions of the device, which will not be described here.

[0123] In an exemplary embodiment, a computer-readable storage medium including at least one instruction is also provided, such as a memory including at least one instruction. The at least one instruction can be executed by a processor in a computer device to complete the phase detection simulation method in the above embodiment.

[0124] Optionally, the above-mentioned computer-readable storage medium may be a non-temporary computer-readable storage medium, for example, the non-temporary computer-readable storage medium may include ROM (Read-Only Memory), RAM (Random-Access Memory), CD-ROM (Compact Disc Read-Only Memory), magnetic tape, floppy disk and optical data storage device, etc.

[0125] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A phase detection simulation circuit, characterized in that: include: A random signal generating module, wherein the random signal generating module is used to generate a random signal; a signal selection module, the signal selection module being configured to receive a first simulated delay signal, a second simulated delay signal, and the random signal, and select one of the second simulated delay signal and the random signal as a selected output signal based on a comparison result of a phase difference between the first simulated delay signal and the second simulated delay signal and a preset threshold range; a sampling simulation register, wherein a clock signal terminal of the sampling simulation register is used to receive the first simulation delay signal, an input terminal of the sampling simulation register is used to receive the selection output signal, and the sampling simulation register outputs a sampling simulation result signal at its output terminal according to the first simulation delay signal and the selection output signal, wherein the sampling simulation result signal is used to represent the phase relationship between the first simulation delay signal and the second simulation delay signal; The preset threshold range is used to represent the setup and hold time of the sampling register simulated by the sampling simulation register.

2. The phase detection simulation circuit according to claim 1, wherein: The signal selection module includes: a phase counting unit, configured to receive the first simulated delay signal and the second simulated delay signal, obtain a first count value at a transition edge instant of the first simulated delay signal, and obtain a second count value at a transition edge instant of the second simulated delay signal, wherein the first count value is used to represent the transition edge instant of the first simulated delay signal, and the second count value is used to represent the transition edge instant of the second simulated delay signal; a phase difference comparison unit, configured to obtain the comparison result according to the first count value, the second count value and the preset threshold range; A signal selection unit is configured to select one of the second simulated delayed signal and the random signal as the selected output signal according to the comparison result.

3. The phase detection simulation circuit according to claim 2, wherein: The phase counting unit includes: a counting unit, the counting unit being configured to perform counting associated with time; A capture unit, wherein the capture unit is used to receive the first simulation delay signal and the second simulation delay signal, and capture the first count value generated by the counting unit at the transition edge of the first simulation delay signal, and capture the second count value generated by the counting unit at the transition edge of the second simulation delay signal.

4. The phase detection simulation circuit according to claim 2, wherein: The phase difference comparison unit includes: a phase difference calculation unit, configured to obtain the phase difference according to the first count value and the second count value; A comparison unit is used to compare the phase difference with the preset threshold range to obtain the comparison result.

5. The phase detection simulation circuit according to claim 1, wherein: The phase detection simulation circuit also includes: A first signal simulation delay circuit is configured to receive a first simulation signal and perform simulation delay on the first simulation signal to obtain the first simulation delayed signal; The second signal simulation delay circuit is used to receive a second simulation signal and perform simulation delay on the second simulation signal to obtain the second simulation delayed signal.

6. The phase detection simulation circuit according to claim 5, wherein: The first signal simulation delay circuit includes: a first simulation delay unit, configured to receive the first simulation signal and perform simulation delay on the first simulation signal to obtain at least one first delayed selected signal; a first emulation multiplexer selection unit, configured to receive the at least one first delayed candidate signal and a first selection signal, and select one of the at least one first delayed candidate signal as the first emulation delayed signal according to the first selection signal; The second signal simulation delay circuit includes: a second simulation delay unit, configured to receive the second simulation signal and perform simulation delay on the second simulation signal to obtain at least one second delayed selected signal; The second simulation multi-path selection unit is used to receive the at least one second delayed selected signal and a second selection signal, and select one of the at least one second delayed selected signal as the second simulation delayed signal according to the second selection signal.

7. The phase detection simulation circuit according to claim 6, characterized in that: The first emulation delay unit comprises: At least one first emulation delay register cascaded on a path for delaying the first emulation signal, wherein an input end of the first emulation delay register receives a signal to be delayed, and an output end of the first emulation delay register generates a delayed signal, and when there are at least two first emulation delay registers, the first emulation signal is delayed by beats of at least two first emulation delay registers to obtain at least two first delayed selected signals with different delays; The second emulation delay unit comprises: At least one second simulation delay register is cascaded on a path for delaying the second simulation signal, wherein the input end of the second simulation delay register receives the signal to be delayed, and the output end of the second simulation delay register generates a delayed signal. When the number of the second simulation delay registers is at least two, the second simulation signal is delayed by the beats of at least two of the second simulation delay registers to obtain at least two second delayed selected signals with different delays.

8. A phase detection simulation method, comprising: Acquire a first simulation delay signal, a second simulation delay signal, and a random signal; selecting one of the second simulated delay signal and the random signal as a selected output signal according to a comparison result of a phase difference between the first simulated delay signal and the second simulated delay signal and a preset threshold range; Utilizing a clock signal terminal of a sampling simulation register to receive the first simulation delay signal, utilizing an input terminal of the sampling simulation register to receive the selection output signal, and obtaining a sampling simulation result signal at an output terminal of the sampling simulation register, wherein the sampling simulation result signal is used to characterize a phase relationship between the first simulation delay signal and the second simulation delay signal; The preset threshold range is used to represent the setup and hold time of the sampling register simulated by the sampling simulation register.

9. The phase detection simulation method according to claim 8, characterized in that: The selecting one of the second simulated delay signal and the random signal as the selected output signal according to a comparison result of the phase difference between the first simulated delay signal and the second simulated delay signal and a preset threshold range includes: When the comparison result shows that the phase difference is outside the preset threshold range, using the second simulated delay signal as a selection output signal; When the comparison result shows that the phase difference is within the preset threshold range, the random signal is used as a selection output signal.

10. The phase detection simulation method according to claim 8, characterized in that: The phase detection simulation method further includes: Acquire a first simulation signal and a second simulation signal; Performing simulation delay on the first simulation signal to obtain the first simulation delayed signal; Performing simulation delay on the second simulation signal to obtain the second simulation delayed signal.

11. A phase detection simulation device, characterized in that: include: A signal receiving module is configured to receive a first simulated delayed signal, a second simulated delayed signal and a random signal; a selection module configured to select one of the second simulated delay signal and the random signal as a selection output signal according to a comparison result of a phase difference between the first simulated delay signal and the second simulated delay signal and a preset threshold range; a phase relationship determination module, configured to receive the first simulation delay signal using a clock signal terminal of a sampling simulation register, receive the selection output signal using an input terminal of the sampling simulation register, and obtain a sampling simulation result signal at an output terminal of the sampling simulation register, wherein the sampling simulation result signal is used to represent the phase relationship between the first simulation delay signal and the second simulation delay signal; The preset threshold range is used to represent the setup and hold time of the sampling register simulated by the sampling simulation register.

12. An electronic device, characterized in that: include: processor; a memory for storing executable instructions for the processor; The processor is configured to execute the executable instructions to implement the phase detection simulation method according to any one of claims 8 to 10.

13. A computer-readable storage medium, characterized in that When at least one instruction in the computer-readable storage medium is executed by a processor of an electronic device, the electronic device is enabled to implement the phase detection simulation method according to any one of claims 8 to 10.

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