Method for rapidly planning simultaneous escape wiring sequence

Abstract

A method for rapidly planning a simultaneous escape wiring sequence comprises the following steps: respectively determining initial escape track positions of two interconnected core particles according to bonding pad positions of to-be-wired wire nets of the two interconnected core particles and regional wiring candidate track positions; acquiring a simultaneous escape orbit position according to the initial escape orbit position; and according to the simultaneous escape track position, sorting the to-be-wired wire net to obtain a simultaneous escape wiring sequence. By calculating the position of the simultaneous escape track, the simultaneous escape wiring sequence is rapidly obtained, and the wiring length of the two interconnected core particles is balanced while the bus length is optimized.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and particularly to a method for quickly planning the wire order of simultaneous escape routing. Background Art

[0002] In the wiring of advanced packaging silicon interposers, according to the wiring area, the escape routing inside the die and the area wiring between dies are divided. Since the wire order of the escape routing will affect the quality of the area wiring, usually the same escape routing wire order (simultaneous escape routing wire order) is determined for two interconnected dies to avoid complex area routing. The simultaneous escape routing wire order will affect the quality of the silicon interposer wiring. Therefore, the present invention mainly solves the problem of planning the simultaneous escape routing wire order.

[0003] The existing methods for planning the simultaneous escape routing wire order are roughly divided into two categories: one is to determine the simultaneous escape routing wire order according to the escape routing of any die. This method for planning the simultaneous escape routing wire order will increase the difficulty of the escape routing of the other die and the utilization of the wiring resources of the two dies is unbalanced; the other is to consider the escape routing of two interconnected dies at the same time and determine the simultaneous escape routing wire order according to the escape routing of both, so as to balance the wire lengths of the two, such as the dynamic wire order planning method based on the longest common subsequence. However, this method needs to solve the longest common subsequence, and as the problem scale increases, the time consumption increases rapidly. In addition, the above two types of methods for planning the simultaneous escape routing wire order do not optimize the wire lengths of the wiring.

[0004] Actually, when the wiring resources are sufficient, the wiring success rate of the escape routing is not the main goal. In this scenario, the existing methods for planning the simultaneous escape routing wire order are no longer applicable, and even lead to problems such as too long wire order planning time and increased wire lengths of the wiring. In view of the problems of too long time consumption and decreased wire length performance caused by the existing simultaneous escape routing wire order planning, there is no relevant solution in the industry at present. It is very necessary to study a method for quickly planning the simultaneous escape routing wire order. Summary of the Invention

[0005] In order to solve the defects of the prior art, the purpose of the present invention is to provide a method for quickly planning the simultaneous escape routing wire order, quickly plan the simultaneous escape routing wire order, and optimize the wire lengths of each net under this wire order.

[0006] In order to achieve the above purpose, the method for quickly planning the simultaneous escape routing wire order provided by the present invention includes:

[0007] Determine the initial escape track positions of two interconnected dies respectively according to the pad positions of the nets to be wired and the candidate track positions of the area wiring of the die.

[0008] Obtain the simultaneous escape orbit positions based on the initial escape orbit positions of the two interconnected dies.

[0009] Sort the nets to be routed according to the simultaneous escape orbit positions to obtain the simultaneous escape routing net order.

[0010] Further, the step of respectively determining the initial escape orbit positions of the two interconnected dies according to the pad positions of the nets to be routed on the dies and the candidate orbit positions for regional routing further includes:

[0011] Select the pads of the nets to be routed from each row of pads of each die, and assign candidate orbits for regional routing to the pads.

[0012] Traverse all the pad rows in each die to determine the initial escape orbit position of each die.

[0013] Further, the step of selecting the pads of the nets to be routed from each row of pads of each die and assigning candidate orbits for regional routing to the pads further includes:

[0014] Determine the number K of pads of the nets to be routed.

[0015] Select K candidate orbits for regional routing to be assigned from the central position of the pad rows of the nets to be routed to both sides.

[0016] Start selecting the pads of the nets to be routed from the side far from the other die, and assign the selected candidate orbits for regional routing to the pads in descending order of the candidate orbit position coordinates.

[0017] Further, the step of obtaining the simultaneous escape orbit positions based on the initial escape orbit positions of the two interconnected dies further includes: the sum of the distances from the simultaneous escape orbit positions to the initial escape orbit positions of the two interconnected dies is the smallest, and the distance difference is the smallest.

[0018] Further, the step of obtaining the simultaneous escape orbit positions based on the initial escape orbit positions of the two interconnected dies further includes:

[0019] Solve for yts n , such that

[0020]

[0021] where ytp m , ytq m are respectively the initial escape orbit positions of the nets to be routed in the two interconnected dies, and yts nIt is the simultaneous escape orbit position of the net to be routed n. min[x] represents taking the minimum value of x, where 0 ≤ n ≤ N - 1, 0 ≤ m ≤ M - 1, N ≤ M, N represents the total number of nets, and M represents the total number of candidate orbits;

[0022] Solve for yts n =(ytp m +ytq m ) / 2.

[0023] Further, the step of sorting according to the simultaneous escape orbit position to obtain the simultaneous escape routing order further includes: for all nets to be routed, obtaining the simultaneous escape routing order in descending order of the coordinates of the simultaneous escape orbit position.

[0024] Furthermore, if a conflict occurs in the calculated simultaneous escape orbit position, the nets to be routed with conflicts are processed to further determine the simultaneous escape routing order of the conflicting nets to be routed, including:

[0025] Determine the simultaneous escape routing order starting from the net to be routed whose pad position is closer to the other die side according to the pad positions of the conflicting nets to be routed in any die.

[0026] To achieve the above object, the present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor is used to execute the computer program stored in the memory to implement the method for quickly planning the simultaneous escape routing order as described above.

[0027] To achieve the above object, the present invention also provides a computer-readable storage medium. A computer program is stored in the storage medium, and the computer program is loaded and executed by a processor to implement the method for quickly planning the simultaneous escape routing order as described above.

[0028] The method for quickly planning the simultaneous escape routing order provided by the present invention has the following beneficial effects compared with the prior art:

[0029] By calculating the simultaneous escape orbit position, the simultaneous escape routing order is quickly obtained, while optimizing the total wire length, the wire lengths of the two interconnected dies are balanced.

[0030] Other features and advantages of the present invention will be described in the following specification, and part of them will become obvious from the specification or be understood by implementing the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings are used to provide a further understanding of the present invention, and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation to the present invention. In the drawings:

[0032] Figure 1 A flowchart of a method for quickly planning the wire sequence of simultaneous escape routing according to an embodiment of the present invention;

[0033] Figure 2 A schematic diagram of the pad positions of the net to be routed and the candidate tracks for area routing according to an embodiment of the present invention;

[0034] Figure 3 A schematic diagram of the initial escape track allocation according to an embodiment of the present invention;

[0035] Figure 4 A schematic diagram of the calculation result of the simultaneous escape track positions and the finally determined wire sequence of simultaneous escape routing according to an embodiment of the present invention;

[0036] Figure 5 A schematic diagram of a possible routing result after determining the wire sequence of simultaneous escape routing according to the escape routing of any die;

[0037] Figure 6 A schematic diagram of a possible routing result under the wire sequence of simultaneous escape routing determined according to an embodiment of the present invention;

[0038] Figure 7 A schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Detailed implementation manners

[0039] The following describes the preferred embodiments of the present invention with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0040] The embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to more thoroughly and completely understand the present invention. It should be understood that the drawings and embodiments of the present invention are only for exemplary purposes and are not used to limit the protection scope of the present invention.

[0041] As used herein, the term "including" and its variations are open-ended, that is, "including but not limited to". The term "based on" is "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

[0042] It should be understood that concepts such as "first" and "second" mentioned in the present invention are only used to distinguish different data or units, and are not used to limit the order or interdependence of the functions performed by these data or units. These terms are only used to distinguish one feature from another. For example, without departing from the scope of the exemplary embodiments, the first feature may be referred to as the second feature, and similarly the second feature may be referred to as the first feature.

[0043] Figure 1 FIG. is a flowchart of a method for quickly planning the escape routing wire sequence according to an embodiment of the present invention. The following will be combined with Figure 1 to further describe the embodiments of the present invention in detail.

[0044] First, in step 101, determine the initial escape orbit positions of two interconnected dielets. For two given interconnected dielets (the first dielet and the second dielet), determine the initial escape orbit positions of each dielet according to the pad positions of the nets to be routed and the candidate track positions for area routing in each dielet. Specifically, select the pads of the nets to be routed from each row of pads in the dielet, and assign candidate tracks for area routing to the pads of the nets to be routed; traverse all pad rows in the dielet to determine the initial escape orbit position of the dielet. The initial escape orbit position of the dielet is the candidate track position for area routing assigned to all pads of the nets to be routed in the dielet.

[0045] In the embodiments of the present invention, the pad positions and candidate track positions for area routing of the nets to be routed of the first dielet and the second dielet are (xp n , yp n ), (xq n , yq n ), yt m respectively, where n represents the nets to be routed (0 ≤ n ≤ N - 1), m represents the candidate tracks (0 ≤ m ≤ M - 1, N ≤ M), N represents the total number of nets, and M represents the total number of candidate tracks. Figure 2 is a schematic diagram. In step 101, the step of selecting the pads of the nets to be routed from each row of pads in the dielet and assigning candidate tracks for area routing to them specifically includes:

[0046] a) Determine the number K of pads of the nets to be routed;

[0047] b) Select K candidate tracks for area routing to be assigned from both sides of the pad row position;

[0048] c) Start selecting the pads of the nets to be routed from the side far from the other dielet, and assign the selected candidate tracks for area routing to them in descending order of track position coordinates.

[0049] TakingFigure 3 Taking the first row of pads of the left die as an example, there are two nets to be routed, net 0 and net 1, and the number of pads of the nets to be routed is 2. Select two candidate regions for routing from the center position of the pad row to both sides, the routing candidate tracks yt 1 and yt 2 . Press Figure 3 Select the pads of the nets to be routed, net 0 and net 1, in the direction of the blue arrow, and sequentially assign them to the selected candidate regions for routing, the routing candidate tracks yt 1 and yt 2 in the direction of the red arrow. The determination method of the remaining initial escape track positions of the two dies is the same, and the result is as Figure 3 shown. The red dotted line represents the selected candidate regions for routing, and the numbers on both sides are the corresponding nets to be routed in the respective dies.

[0050] In step 102, according to the initial escape track positions of the two interconnected dies, obtain the simultaneous escape track positions. In this step, for each net to be routed of the two interconnected dies, calculate the simultaneous escape track positions that balance the routing wire lengths of the two interconnected dies and optimize the total wire length.

[0051] In the embodiment of the present invention, the calculation problem of the simultaneous escape track positions of the nets to be routed can be modeled as: find yts n such that

[0052]

[0053] where ytp m , ytq m are the initial escape track positions of the net n to be routed in the two dies respectively, yts n is the simultaneous escape track position of the net n to be routed, and min[x] represents taking the minimum value of x.

[0054] According to equation (1), the objective function is a convex function, so this problem can be regarded as a convex optimization problem. By solving this problem, the sum of the distances from the simultaneous escape track positions to the initial escape track positions of the two interconnected dies can be minimized, and the distance difference can be minimized.

[0055] Taking Figure 4 net 0 in the figure as an example, then the problem of solving its simultaneous escape track position is: find yts 0 such that min[(yts 0 -ytp 0 ) 2 +(yts 0 -ytq 0 ) 2 . Solving gives yts 0 =(ytp 0 +ytq 0 ) / 2, asFigure 4 as shown by the blue solid line marked with 0. The calculation of the simultaneous escape orbit positions of the remaining wire networks is the same, and the results are as Figure 4 shown. The blue solid line with markings is the simultaneous escape orbit position of the non-conflicting wire network, and the red solid line with markings is the simultaneous escape orbit position of the conflicting wire network.

[0056] In step 103, according to the simultaneous escape orbit positions, the wire networks to be routed are sorted to obtain the simultaneous escape routing wire order.

[0057] In some exemplary embodiments, for all wire networks to be routed, the simultaneous escape routing wire order is obtained by descending the coordinates of the simultaneous escape orbit positions. Since the simultaneous escape orbit positions calculated in step 102 may conflict (the simultaneous escape orbit positions are the same), it is necessary to process the conflicting wire networks to be routed to further determine their simultaneous escape routing wire order. The solution to the wire networks to be routed with conflicting simultaneous escape orbit positions is: uniformly determine the simultaneous escape routing wire order starting from the wire network with the pad closer to the other die side among the conflicting wire networks to be routed in any die. For example:

[0058] Perform a preliminary sorting on the simultaneous escape orbit positions in step 102 to obtain a preliminary simultaneous escape routing wire order of 1 / 2 -> 5 -> 0 -> 3 -> 4 -> 6 -> 7. Since the simultaneous escape orbit positions calculated for wire network 1 and wire network 2 in step 102 conflict, it is necessary to process wire network 1 and wire network 2: in the left die, since the pad of wire network 1 is closer to the right die side, the simultaneous escape routing wire order is determined starting from wire network 1, and the final simultaneous escape routing wire order is 1 -> 2 -> 5 -> 0 -> 3 -> 4 -> 6 -> 7. As Figure 5 shown, a possible routing result after determining the simultaneous escape routing wire order according to the escape routing of any die is given; Figure 6 shown, a possible routing result under the simultaneous escape routing wire order in step 103 is given. From Figure 5 and Figure 6 it can be seen that compared with the result of Figure 5 , based on the simultaneous escape routing wire order in step 103, the result of Figure 6 can optimize the total routing wire length while making the routing wire lengths of the two interconnected dies more balanced.

[0059] Experiments prove that by selecting a test case of 78 wire networks for simultaneous escape routing wire order planning, an optimized result can be obtained within about 0.009 s. It can be seen that the method of the present invention can quickly plan the simultaneous escape routing wire order.

[0060] Compared with the prior art, the present invention models the problem of simultaneously escaping wiring line sequence planning as a convex optimization problem, and quickly obtains the simultaneously escaping wiring line sequence by calculating the simultaneously escaping orbit positions. While initially optimizing the total wire length, the wire lengths of the two interconnected die chips are balanced. Further, to solve the problem of simultaneous escape position conflicts obtained by calculation, when obtaining the simultaneously escaping wiring line sequence, the conflicting nets are processed to further determine the simultaneously escaping wiring line sequence of the conflicting nets. That is to say, a method for quickly planning the simultaneously escaping wiring line sequence provided by the present invention can quickly plan the simultaneously escaping wiring line sequence by solving a convex function under the conditions of the pad positions of the nets to be wired and the candidate orbit positions for area wiring of two interconnected die chips. While initially optimizing the total wire length, the wire lengths of the two interconnected die chips are balanced, and the time for planning the simultaneously escaping wiring line sequence is significantly reduced.

[0061] In an embodiment of the present invention, an electronic device is further provided. Figure 7 As a schematic structural diagram of the electronic device according to an embodiment of the present invention, as Figure 7 shown, the electronic device of the present invention includes a processor 701 and a memory 702. Among them,

[0062] The memory 702 stores a computer program, and when the computer program is read and executed by the processor 701, it executes the steps in the method embodiment of quickly planning the simultaneously escaping wiring line sequence as described above.

[0063] In an embodiment of the present invention, a computer-readable storage medium is further provided. The computer program is stored in the computer-readable storage medium. Among them, the computer program is set to execute the steps in the method embodiment of quickly planning the simultaneously escaping wiring line sequence as described above when running.

[0064] In this embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drives, read-only memories (ROMs), random access memories (RAMs), mobile hard disks, magnetic disks, or optical discs and other various media that can store computer programs.

[0065] Those of ordinary skill in the art can understand that the above are only preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for quickly planning and escaping wiring sequence, characterized in that: include: According to the pad positions of the to-be-routed wire nets of the core particles and the positions of the candidate regional routing tracks, the initial escape track positions of the two interconnected core particles are determined respectively; According to the initial escape trajectory positions of the two interconnected core particles, obtaining simultaneous escape trajectory positions; According to the simultaneous escape track positions, the wire nets to be routed are sorted to obtain a simultaneous escape wiring line sequence.

2. The method for rapidly planning and escaping wiring sequence according to claim 1, characterized in that: The step of determining the initial escape track positions of two interconnected chiplets respectively according to the pad positions of the to-be-routed wire nets of the chiplets and the regional routing candidate track positions further comprises: Selecting pads of a to-be-routed wire net from each row of pads of each core particle, and assigning regional routing candidate tracks to the pads; All pad rows in each chip are traversed to determine the initial escape trajectory position of each chip.

3. The method for rapidly planning and escaping wiring sequence according to claim 2, characterized in that: The step of selecting pads of a to-be-routed wire net from each row of pads of each core particle and allocating regional routing candidate tracks to the pads further comprises: Determine the number K of pads of the wire net to be routed; From the center position of the pad row of the to-be-routed wire net, select K candidate tracks for regional routing to be allocated on both sides; The pads of the to-be-routed net are selected starting from the side farthest from the other core particle, and the selected regional routing candidate tracks are allocated to the pads in descending order of the position coordinates of the regional routing candidate tracks.

4. The method for rapidly planning and escaping wiring sequence according to claim 1, characterized in that: The step of obtaining the simultaneous escape trajectory position according to the initial escape trajectory positions of the two interconnected chiplets further comprises: the sum of the distances from the simultaneous escape trajectory position to the initial escape trajectory positions of the two interconnected chiplets is the smallest, and the distance difference is the smallest.

5. The method for rapidly planning and escaping wiring sequence according to claim 4, characterized in that: The step of obtaining simultaneous escape trajectory positions according to the initial escape trajectory positions of the two interconnected core particles further comprises: Solving for yts n ,make Among them, ytp m ,ytq m are the initial escape trajectory positions of the wire nets to be routed in the two interconnected core particles, yts n is the simultaneous escape track position of the wire net n to be routed, min[x] represents the minimum value of x, 0≤n≤N-1, 0≤m≤M-1, N≤M, N represents the total number of wire nets, and M represents the total number of candidate tracks; Solve for yts n =(ytp m +ytq m ) / 2.

6. The method for rapidly planning and escaping wiring sequence according to claim 1, characterized in that: The step of sorting the wire nets to be routed according to the simultaneous escape track positions to obtain the simultaneous escape wiring sequence further includes: for all the wire nets to be routed, sorting them according to the coordinates of the simultaneous escape track positions in descending order to obtain the simultaneous escape wiring sequence.

7. The method for rapidly planning and escaping wiring sequence according to claim 6, characterized in that: If the calculated simultaneous escape track positions conflict, the conflicting wire nets to be routed are processed to further determine the simultaneous escape wiring sequence of the conflicting wire nets to be routed, including: According to the pad position of the conflicting to-be-routed wire net in any core particle, the simultaneous escape wiring line sequence is determined starting from the side close to the other core particle.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: The processor is used to execute the computer program stored in the memory to implement the method for quickly planning and escaping wiring sequence as described in any one of claims 1-7.

9. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, which is loaded and executed by a processor to implement the method for rapidly planning and escaping wiring sequence as described in any one of claims 1 to 7.

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