Gate drive circuit and display device

Abstract

The invention discloses a gate drive circuit and a display device. The gate drive circuit comprises a plurality of cascaded drive units, and each drive unit comprises an input module connected with a first node and used for adjusting the voltage of the first node according to an input signal; the output module is connected with the first node and is used for providing a current-stage driving signal according to the first clock signal and the voltage of the first node; the control module is connected between the first node and the second node and used for adjusting the voltage of the second node according to the voltage of the first node; the stabilizing module is used for maintaining the first node and the current-stage driving signal at the grid cut-off voltage when the second node is the effective level; the compensation module is connected with the second node and used for maintaining the effective level of the second node according to an effective control signal, and the control signal represents the working temperature of the gate drive circuit. On the basis of guaranteeing the display quality, the gate drive circuit provided by the invention has a larger working temperature interval.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a gate driving circuit and a display device. Background Art

[0002] With the rapid development of display technologies, display devices are widely used in various electronic devices, covering multiple fields such as mobile phones and tablet computers for daily use, to professional industrial control devices and in-vehicle display systems.

[0003] The diverse usage environments pose higher requirements for the applicable temperature range of display devices. In particular, the gate driving circuit inside the display device is extremely vulnerable to high temperatures. At high temperatures, the capacitance coupling and inductance coupling effects in the circuit are aggravated, interfering with the scan signal provided by the gate driving circuit to the display panel, thereby causing display streaks and seriously affecting the display quality and reliability of the display device. Summary of the Invention

[0004] In view of the above problems, the purpose of the present application is to provide a gate driving circuit and a display device, which can effectively increase the applicable temperature range while ensuring the display quality.

[0005] According to one aspect of the present application, a gate driving circuit is provided, which includes a plurality of cascaded driving units. Each of the driving units includes: an input module connected to a first node, configured to adjust the voltage of the first node according to an input signal; an output module connected to the first node, configured to provide a driving signal of the current stage according to a first clock signal and the voltage of the first node; a control module connected between the first node and a second node, configured to adjust the voltage of the second node according to the voltage of the first node; a stabilization module configured to maintain the first node and the driving signal of the current stage at a gate cut-off voltage when the second node is at an effective level; and a compensation module connected to the second node, configured to maintain the effective level of the second node according to an effective control signal, where the control signal represents the operating temperature of the gate driving circuit.

[0006] Optionally, the gate driving circuit further includes: a control signal generation unit configured to provide the control signal according to the gate cut-off voltage or the gate turn-on voltage.

[0007] Optionally, the compensation module includes: a ninth transistor, with a first end connected to a third power supply terminal, a second end connected to the second node, and a control end receiving a first control signal. The control signal generation unit obtains the first control signal according to the gate cut-off voltage when the operating temperature is less than a first preset temperature, and obtains the first control signal according to the gate turn-on voltage when the operating temperature is greater than or equal to the first preset temperature.

[0008] Optionally, the compensation module further includes: a tenth transistor, with the first end connected to the second node, and the control end and the second end connected and receiving a second control signal. When the operating temperature is less than a second preset temperature, the control signal generating unit obtains the second control signal according to the gate cut-off voltage, and when the operating temperature is greater than or equal to the second preset temperature, obtains the second control signal according to the gate turn-on voltage.

[0009] Optionally, the first preset temperature is lower than the second preset temperature.

[0010] Optionally, the input module includes: a first transistor, with the first end connected to a first power supply terminal, the second end connected to the first node, and the control end receiving a pre-stage driving signal; and a second transistor, with the first end connected to the first node, the control end receiving a post-stage driving signal, and the second end connected to a second power supply terminal. The output module includes: a third transistor, with the control end connected to the first node, the first end receiving the first clock signal, and the second end providing the current-stage driving signal; and a capacitor connected between the control end and the second end of the third transistor.

[0011] Optionally, the control module includes: a fourth transistor, with the control end and the first end connected to a third power supply terminal, and the second end connected to the second node; and a fifth transistor, with the control end connected to the first node, the first end connected to the second node, and the second end connected to a second power supply terminal. The stabilization module includes: a sixth transistor, with the control end connected to the second node, the first end connected to the first node, and the second end connected to a second power supply terminal; and a seventh transistor, with the control end connected to the second node, the first end connected to the output end of the output module, and the second end connected to a second power supply terminal.

[0012] Optionally, the gate driving circuit further includes: an eighth transistor, with the control end receiving a second clock signal, the first end connected to the output end of the output module, and the second end connected to a second power supply terminal.

[0013] According to another aspect of the present application, there is provided a display device, which includes: the gate driving circuit as described in any one of the above; and a power management circuit for providing the gate cut-off voltage, the gate turn-on voltage, and the first power supply voltage according to the input voltage of the display device.

[0014] Optionally, the display device further includes: a temperature detection circuit for obtaining the operating temperature of the gate driving circuit.

[0015] According to the gate driving circuit and the display device provided by the present application, compensation is provided to the second node through a compensation module at high temperatures to stabilize the potential of the second node, avoiding changes in the scan signal provided by the gate driving circuit due to fluctuations in the potential of the second node. Therefore, the gate driving circuit provided by the present application can provide a stable scan signal even at high temperatures, solving the problem of display horizontal stripes at high temperatures, improving the display quality, and enabling the display device to have a larger operating temperature range.

[0016] Furthermore, by multiplexing the gate cut-off voltage and the gate turn-on voltage to provide a control signal to the compensation module, it has no impact on the second node at low temperatures and can compensate the second node at high temperatures, making the gate driving circuit more adaptable to temperature. At the same time, due to the multiplexing of signals, it is possible to control the compensation module without setting up an additional level shift circuit, which is beneficial for saving production costs and the layout area of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0018] Figure 1 A schematic structural diagram of the display device showing an embodiment of the present application is presented;

[0019] Figure 2 A schematic structural diagram of a single driving unit in the gate driving circuit showing an embodiment of the present application is presented;

[0020] Figure 3 A schematic structural diagram of the control signal generation unit in the gate driving circuit showing an embodiment of the present application is presented;

[0021] Figure 4 A schematic circuit diagram of a single driving unit in some embodiments of the present application is presented;

[0022] Figure 5 Shows Figure 4 A schematic working waveform diagram of the driving circuit in

[0023] Figure 6 Shows Figure 4 A schematic waveform diagram of the first control signal in

[0024] Figure 7 A schematic circuit diagram of a single driving unit in some other embodiments of the present application is presented;

[0025] Figure 8 Shows Figure 7 A schematic waveform diagram of the first control signal and the second control signal in DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the respective drawings, the same elements are denoted by the same or similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale.

[0027] It should be understood that in the following description, "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is referred to as "connected to" another element or when an element or circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. In contrast, when an element is referred to as "directly coupled to" or "directly connected to" another element, it means there are no intermediate elements between the two.

[0028] Meanwhile, in this patent specification and claims, certain terms are used to refer to specific components. Those of ordinary skill in the art should understand that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not use the difference in names as a way to distinguish components, but rather use the difference in functions of components as the criterion for distinction.

[0029] In addition, it should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0030] This application provides a display device. Taking a liquid crystal display panel as an example, Figure 1 A schematic structural block diagram of the display device according to the embodiment of this application is shown. As Figure 1 shown, the display device 1 includes a display panel, a gate driving circuit 100, a source driving circuit 200, a timing control circuit 300, and a power management circuit 400.

[0031] The display panel includes pixel units arranged in an array for displaying an image. Each pixel unit includes a thin film transistor T and a pixel capacitor (not shown in the figure) formed between the pixel electrode and the common electrode. Each pixel unit is connected to the source driver circuit 200 via a corresponding data line S to receive a data signal, and is connected to the gate driver circuit 100 via a corresponding scan line G to receive a scan signal. When the thin film transistor T is turned on under the control of the scan signal, display is performed according to the data signal. In Figure 1 it, as an example, the display panel includes i×j pixel units, and the data lines S1~Sj and the scan lines G1~Gi are correspondingly shown, where i and j are positive integers.

[0032] The timing control circuit 300 provides display data Data and a source control signal Cd to the source driver circuit 200 according to the received image data IMG and a timing control signal Cont, and provides a gate control signal Cg to the gate driver circuit 100. Among them, the timing control signal Cont should be understood as a type of signal, such as including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a clock signal CLK, etc.

[0033] The source driver circuit 200 converts the display data Data into corresponding data signals according to the source control signal Cd and provides them to the corresponding pixel units via the respective data lines S.

[0034] The power management circuit 400 provides a gate turn-on voltage VGH, a gate turn-off voltage VGL, and a first voltage AVDD according to the power supply voltage of the display device 1. Among them, the gate turn-on voltage VGH is a voltage that can turn on the thin film transistor T, the gate turn-off voltage VGL is a voltage that can turn off the thin film transistor T, and the first voltage AVDD can be a positive voltage between VGH and VGL. For example, VGH is 18V, VGL is -7V, and AVDD is 5.5V.

[0035] Furthermore, as Figure 1 shown, the gate driver circuit 100 of the embodiment of the present application includes a plurality of cascaded driving units 110. In Figure 1Among them, 110-1 to 110-n are taken as examples. Each driving unit 110 converts the gate-on voltage VGH, the gate-off voltage VGL, and the first voltage AVDD into a scanning signal according to the corresponding gate control signal Cg and provides it to the corresponding pixel unit through the scanning line G connected to the driving unit 110. Among them, when the driving unit 110 provides the gate-on voltage VGH through the scanning line G, the thin-film transistor T connected to the scanning line G is turned on, so that the corresponding pixel unit displays according to the data signal provided by the source driving circuit 200; when the driving unit 110 provides the gate-off voltage VGL through the scanning line G, the thin-film transistor T connected to the scanning line G is turned off.

[0036] It should be noted that the source control signal Cd, the gate control signal Cg, and the gate control signal Vgc should also be understood as a general term for a type of signal rather than a single signal. For example, the gate control signal Cg usually includes at least one gate start pulse signal and multiple clock signals.

[0037] Correspondingly, as Figure 1 shown, the gate driving circuit 100 further includes a control signal generation unit 120 for providing a control signal TC to the compensation module. In a preferred embodiment, the control signal generation unit 120 includes, for example, a temperature control switch, so as to select and multiplex the gate-off voltage VGL or the gate-on voltage VGH according to the operating temperature of the gate driving circuit 100 to provide the above control signal, which is beneficial to cost savings.

[0038] Figure 2 Shows a schematic structural diagram of a single driving unit in the gate driving circuit according to an embodiment of the present application. As Figure 2 shown, the gate driving circuit 100 of the embodiment of the present application includes a plurality of cascaded driving units 110. Each stage of the driving unit 110 can be connected to a row of pixel units on the display panel through the corresponding scanning line G, so as to apply the scanning signal, that is, the local driving signal output by the driving unit 110 at this stage, to these pixel units to control the on or off of the thin-film transistor T.

[0039] In the embodiment of the present application, the driving unit 110 includes a driving circuit and a compensation module 115.

[0040] The driving circuit is used to provide the local driving signal Gn. Referring to Figure 2 , the driving circuit may include an input module 111, an output module 112, a control module 113, and a stabilization module 114. In some embodiments, the driving circuit may further include a reset module 116. More specifically, referring to Figure 2, the input module 111 is connected to the first node Q and is used to adjust the voltage of the first node Q according to the input signal. The output module 112 is connected to the first node Q and is used to provide the local driving signal Gn according to the first clock signal and the voltage of the first node Q. The control module 113 is connected between the first node Q and the second node QB and is used to adjust the voltage of the second node QB according to the voltage of the first node Q. The stabilization module 114 is connected to the second node QB and the output end of the output module 112 and is used to maintain the first node Q and the local driving signal Gn at the gate cut-off voltage VGL when the second node QB is at the effective level. The reset module 116 is connected to the output end of the output module 112 and is used to reset the local driving signal Gn according to the effective second clock signal.

[0041] The compensation module 115 is connected to the driving circuit, specifically, it can be connected to the second node QB, and is used to maintain the effective level of the second node according to the effective control signal TC. Wherein, the control signal TC represents the operating temperature of the gate driving circuit 100. More specifically, when the operating temperature is greater than or equal to the preset temperature, the control signal TC has an effective level.

[0042] Figure 3 Shows a schematic structural diagram of the control signal generation unit in the gate driving circuit according to an embodiment of the present application; as Figure 3 shown, the gate driving circuit 100 further includes a control signal generation unit 120. The control signal generation unit 120 is used to provide the control signal TC according to the operating temperature of the gate driving circuit 100. In some embodiments, as Figure 3 shown, the control signal generation unit 120 may include a temperature control switch, and the conduction state of the temperature control switch is controlled by the operating temperature T, so as to multiplex the gate turn-on voltage VGH or the gate cut-off voltage VGL as the control signal TC.

[0043] It should be noted that, in the embodiments of the present application, the driving circuit can be implemented with reference to any relevant technology. For the convenience of understanding the driving unit provided by the present application, in the following, a driving circuit of 8T1C is taken as an example, that is, it is taken as an example that the driving circuit includes 8 transistors and 1 capacitor, and the driving unit 110 provided by the present application is introduced in detail. Among them, these transistors are, for example, thin film transistors, and each thin film transistor includes a first end, a second end and a control end. Each thin film transistor is turned on or off according to the control end voltage, and when it is turned on, the current flows from the end with the higher potential to the end with the lower potential between the first end and the second end.

[0044] Figure 4 Shows a schematic circuit diagram of a single driving unit in some embodiments of the present application. Refer to Figure 4, in the driving unit 110a of some embodiments, for the nth-level driving unit, the input module 111 is connected to the first node Q and is used to adjust the voltage of the first node Q according to the input signal. In the example, the input module 111 includes a first transistor T1 and a second transistor T2. The first end of the first transistor T1 is connected to the first power supply terminal, the second end is connected to the first node Q, and the control end receives the driving signal of the previous stage, for example, the driving signal Gn-4 provided for the driving unit with a four-stage difference forward. The first end of the second transistor T2 is connected to the first node Q, the second end is connected to the second power supply terminal, and the control end receives the driving signal of the next stage, for example, the driving signal Gn+4 provided for the driving unit with a four-stage difference backward.

[0045] In the example as Figure 4 shown, the first power supply terminal provides the gate turn-on voltage VGH, and the second power supply terminal provides the gate turn-off voltage VGL. That is to say, in the example as Figure 4 shown, the input signal may include the gate turn-on voltage VGH, the gate turn-off voltage VGL, the driving signal Gn-4 of the previous stage, and the driving signal Gn+4 of the next stage.

[0046] The output module 112 is connected to the first node Q and is used to provide the driving signal Gn of this stage according to the first clock signal CLK2 and the voltage of the first node Q. In the example, the output module 112 includes a third transistor T3 and a capacitor C. The first end of the third transistor T3 receives the first clock signal CLK2, the second end provides the driving signal Gn of this stage, and the control end is connected to the first node Q. The capacitor C is connected between the control end and the second end of the third transistor T3. In some embodiments, the capacitor C is the parasitic capacitance between the control end and the second end of the third transistor. However, it should be understood that in other embodiments, in order to improve the coupling effect of the capacitor and thus improve the effect of pulling up the voltage of the first node Q, an independent capacitor is also provided between the control end and the second end of the third transistor T3, and the capacitor C is the sum of the parasitic capacitance and the independent capacitance between the control end and the second end of the third transistor. The first clock signal CLK2 may be a clock signal that is two clock cycles different from the basic clock signal.

[0047] The control module 113 is connected between the first node Q and the second node QB and is used to adjust the voltage of the second node QB according to the voltage of the first node Q. In the example, the control module 113 includes a fourth transistor T4 and a fifth transistor T5. The control end and the first end of the fourth transistor T4 are connected and connected to the third power supply terminal, and the second end is connected to the second node QB. The control end of the fifth transistor T5 is connected to the first node Q, the first end is connected to the second node QB, and the second end is connected to the second power supply terminal.

[0048] In the example as Figure 4 shown, the third power supply terminal may be to provide the first voltage AVDD.

[0049] The stabilization module 114 is configured to maintain the first node Q and the local driving signal Gn at the gate cut-off voltage VGL when the second node QB is at an effective potential. In the example, the stabilization module 114 includes a sixth transistor T6 and a seventh transistor T7. The control terminal of the sixth transistor T6 is connected to the second node QB, the first terminal is connected to the first node Q, and the second terminal is connected to the second power supply terminal. The control terminal of the seventh transistor T7 is connected to the second node QB, the first terminal is connected to the second terminal of the third transistor T3, i.e., the output terminal of the output module 112, and the second terminal is connected to the second power supply terminal.

[0050]

[0049] The reset module 116 is configured to reset the local driving signal Gn to the gate cut-off voltage VGL according to the valid second clock signal CLK4. In the example, the reset module 116 includes an eighth transistor T8. The control terminal of the eighth transistor T8 receives the second clock signal CLK4, the first terminal is connected to the second terminal of the third transistor T3, and the second terminal is connected to the second power supply terminal. Wherein, the second clock signal may be a clock signal that is 4 clock cycles different from the reference clock signal. More specifically, the second clock signal CLK4 is the inverted signal of the first clock signal CLK2.

[0051] Figure 5 Taking the first transistor T1 to the eighth transistor T8 as N-type transistors as an example, the effective level of the second node QB is a high level. Figure 5 Shown Figure 4 Figure 4 The schematic working waveform diagram of the driving circuit in the middle is shown. Refer to Figure 5 Figure 5 , the working process of the driving circuit in each stage of the driving unit is divided into a pre-charge stage, a pull-up stage, a pull-down stage, and a stabilization stage.

[0052] Pre-charge stage: In the embodiment of the present application, the previous stage driving signal Gn-4 is used as the pre-charge signal. The level of the previous stage driving signal Gn-4 output by the driving unit four levels ahead changes from low to high, and the first transistor T1 is turned on. The first node Q is pre-charged through the turned-on first transistor T1. As the voltage of the first node Q increases, the third transistor T3 and the fifth transistor T5 are gradually turned on. And, as the fifth transistor T5 is turned on, the voltage of the second node QB is pulled down to the gate cut-off voltage VGL. Therefore, the sixth transistor T6 and the seventh transistor T7 are gradually turned off.

[0053] Pull-up stage: After the pre-charge stage, the first node Q has been pre-charged and the third transistor T3 is turned on. When the high level of the first clock signal CLK2 arrives, the local gate drive signal Gn output by the drive unit is pulled up by the first clock signal CLK2 through the turned-on third transistor T3. Due to the bootstrap effect of the capacitor C, the voltage of the first node Q is further pulled up, making the third transistor T3 turn on more fully. At the same time, the second clock signal CLK4 controls the eighth transistor T8 to be cut off.

[0054] Pull-down stage: In the present application, the subsequent stage drive signal Gn+4 is used as the pull-down signal. When the subsequent stage drive signal Gn+4 changes from low level to high level, the second transistor T2 is turned on, and the potential of the first node Q is pulled down, and the third transistor T3 gradually turns off. When the level of the first clock signal CLK2 changes from high to low, the level of the second clock signal CLK4 changes from low to high, and the eighth transistor T8 is turned on. The local drive signal Gn is pulled down to the voltage of the second power supply terminal, that is, the gate cut-off voltage VGL, through the turned-on eighth transistor T8.

[0055] Stable stage: In the pull-down stage, the voltage of the first node Q is pulled down, and the fifth transistor T5 is cut off. The turned-on fourth transistor T4 gradually pulls up the potential of the second node QB to the effective level, thereby gradually turning on the sixth transistor T6 and the seventh transistor T7, and stabilizing the first node Q and the local drive signal Gn at the voltage of the second power supply terminal, that is, the gate cut-off voltage VGL, so as to obtain an ideal waveform of the local drive signal. It should be noted that compared with the fourth transistor T4, the fifth transistor T5 should have a larger size to provide a stronger current driving ability, so that the voltage of the second node QB can be pulled down by the turned-on fifth transistor T5.

[0056] Since at high temperatures, the coupling effect of the second node QB is aggravated, the voltage of the second node QB will fluctuate, and the stable module 114 cannot play a stable maintenance role, resulting in fluctuations in the first node Q and the local drive signal Gn. Such fluctuations will cause the corresponding pixel unit to be wrongly turned on, resulting in display streaks.

[0057] In some embodiments, in order to avoid display streaks, it is necessary to increase the voltage of the first power supply terminal. If a gate turn-on voltage VGH higher than the first voltage AVDD is directly provided to the first power supply terminal, the potential of the second node QB will be relatively high, and in the case of low temperature, the second node QB is not easily pulled down. If other voltages higher than the first voltage AVDD are provided at the first power supply terminal, an additional level shift circuit is required, and the production cost is relatively high.

[0058] In the embodiment of the present application, a compensation module connected to the second node QB is provided to maintain the effective level of the second node QB according to the effective control signal TC.

[0059] Further, in Figure 4 the embodiment shown, the compensation module 115a is configured to provide compensation to the second node QB according to the valid control signal TC when the operating temperature is greater than or equal to the first preset temperature, so as to stabilize the voltage of the second node QB, thereby improving the display effect at high temperatures and facilitating the expansion of the operating temperature range of the display device.

[0060] In the embodiment as Figure 4 shown, the compensation module 115a includes a ninth transistor T9. Correspondingly, the control signal TC includes a first control signal TC1. The first end of the ninth transistor T9 is connected to the third power supply terminal, the second end is connected to the second node QB, and the control end receives the first control signal TC1.

[0061] Figure 6 shows a schematic working waveform diagram of the first control signal TC1. Combining Figure 3 、 Figure 4 and Figure 6 , the control signal TC includes the first control signal TC1. When the operating temperature is less than the first preset temperature T1, the control signal generation unit 120 multiplexes the gate cut-off voltage VGL as the first control signal TC1. At this time, the ninth transistor T9 is turned off and has no influence on the second node QB. When the operating temperature is greater than or equal to the first preset temperature T1, the control signal generation unit 120 multiplexes the gate turn-on voltage VGH as the first control signal TC1. At this time, the ninth transistor T9 is turned on to stabilize the voltage of the second node QB, thereby avoiding the fluctuations of the first node Q and the local driving signal Gn caused by the potential fluctuation of the second node QB, and also avoiding the display streaks caused by the fluctuations of the first node Q and the local driving signal Gn. Therefore, the gate driving circuit provided by the present application can provide a stable scanning signal even at high temperatures, solves the problem of display streaks at high temperatures, improves the display quality, and enables the display device to have a larger operating temperature range.

[0062] Further, Figure 7 shows a schematic circuit diagram of a single driving unit in some other embodiments of the present application. As Figure 7 shown, in the driving unit 110b of some other embodiments, an 8T1C structure is also taken as an example of the driving circuit. Correspondingly, the connection manners of the first transistor T1 and the second transistor T2 in the input module 111, the third transistor T3 and the capacitor C in the output module 112, the fourth transistor T4 and the fifth transistor T5 in the control module 113, the sixth transistor T6 and the seventh transistor T7 in the stabilization module 114, and the eighth transistor T8 in the reset module 116, as well as the signals of the input driving circuit or the output driving circuit, are the same as those in the Figure 4 embodiment shown, and will not be described herein again.

[0063] Unlike the embodiment shown, Figure 4 in the embodiment shown, Figure 7 the compensation module 115b includes not only the ninth transistor T9, but also the tenth transistor T10. Accordingly, the control signal TC includes a first control signal TC1 and a second control signal TC2. Among them, the ninth transistor T9 also receives the first control signal TC1 at the control terminal, the first terminal is connected to the third power supply terminal to receive the first voltage AVDD, and the second terminal is connected to the second node QB. The first terminal of the tenth transistor T10 is connected to the second node QB, and the control terminal and the second terminal are connected and receive the second control signal TC2.

[0064] Figure 8 shows in the Figure 7 embodiment shown, a schematic waveform diagram of the first control signal TC1 and the second control signal TC2. Combining Figure 3 , Figure 7 and Figure 8 , the control signal TC includes the first control signal TC1 and the second control signal TC2. When the operating temperature is less than the first preset temperature T1, the control signal generation unit 120 multiplexes the gate cut-off voltage VGL as the first control signal TC1 and the second control signal TC2. At this time, both the ninth transistor T9 and the tenth transistor T10 are cut off and do not affect the second node QB. When the operating temperature is greater than or equal to the first preset temperature T1 but less than the second preset temperature T2, the control signal generation unit 120 multiplexes the gate turn-on voltage VGH as the first control signal TC1 and multiplexes the gate cut-off voltage VGL as the second control signal TC2. At this time, the ninth transistor T9 is turned on and the tenth transistor T10 is cut off, and the voltage of the second node QB is stabilized by the ninth transistor T9. When the operating temperature is greater than or equal to the second preset temperature T2, the control signal generation unit 120 multiplexes the gate turn-on voltage VGH as the first control signal TC1 and the second control signal TC2. At this time, both the ninth transistor T9 and the tenth transistor T10 are turned on, so the ability to maintain the potential of the second node QB can be enhanced. Even when the potential of the first voltage AVDD is limited, the ability to suppress the potential fluctuations of the first node Q and the local drive signal Gn can be improved, which is more conducive to improving the operating stability of the drive unit and the gate drive circuit.

[0065] The above-mentioned first preset temperature T1 is less than the second preset temperature T2. By way of example, the first preset temperature may be 50 °C, and the second preset temperature may be 85 °C. That is to say, when the operating temperature is less than 50 °C, there is no need to provide compensation to the second node QB; when the operating temperature is between 50 °C and 85 °C, the ninth transistor T9 provides compensation to the second node QB; when the operating temperature is greater than or equal to 85 °C, the ninth transistor T9 and the tenth transistor T10 jointly provide compensation to the second node QB.

[0066] Furthermore, a temperature detection circuit is usually provided in the display device to obtain the operating temperature of the gate driving circuit 100. The above-mentioned control signal generation unit 120 is, for example, connected to the temperature detection circuit to obtain the operating temperature, with a simple structure and low cost.

[0067] According to the gate driving circuit and the display device provided by the present application, compensation is provided to the second node through the compensation module at high temperatures to stabilize the potential of the second node, avoiding the scanning signal provided by the gate driving circuit from changing due to the potential fluctuation of the second node. Therefore, the gate driving circuit provided by the present application can provide a stable scanning signal even at high temperatures, solves the problem of display horizontal stripes at high temperatures, improves the display quality, and enables the display device to have a larger operating temperature range.

[0068] Furthermore, by multiplexing the gate cut-off voltage and the gate turn-on voltage to provide a control signal to the compensation module, it will not affect the second node at low temperatures and can compensate the second node at high temperatures, making the temperature adaptability of the gate driving circuit stronger. At the same time, due to the multiplexing of signals, there is no need to set up an additional level shift circuit to control the compensation module, which is beneficial to saving production costs and the layout area of the circuit.

[0069] According to the embodiments of the present application as described above, these embodiments do not elaborate on all the details, nor do they limit the present application to only the specific embodiments. Obviously, many modifications and variations can be made according to the above description. The present specification selects and specifically describes these embodiments in order to better explain the principle and practical application of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application.

Claims

1. A gate drive circuit, comprising a plurality of cascaded drive units, wherein: Each of the drive units comprises: An input module, connected to the first node, and used to adjust the voltage of the first node according to an input signal; an output module, connected to the first node, and configured to provide a current-stage driving signal according to the first clock signal and the voltage of the first node; a control module, connected between the first node and the second node, and configured to adjust a voltage of the second node according to a voltage of the first node; a stabilization module, configured to maintain the first node and the current-stage driving signal at a gate cut-off voltage when the second node is at a valid level; and a compensation module, connected to the second node, and configured to maintain a valid level of the second node according to a valid control signal, Wherein, the control signal represents the operating temperature of the gate drive circuit.

2. The gate drive circuit according to claim 1, wherein: The gate drive circuit further includes: A control signal generating unit is used to provide the control signal according to the gate cut-off voltage or the gate start voltage.

3. The gate driving circuit according to claim 2, wherein: The compensation module comprises: a ninth transistor, wherein the first end is connected to the third power supply end, the second end is connected to the second node, and the control end receives the first control signal, The control signal generating unit obtains the first control signal according to the gate cut-off voltage when the operating temperature is lower than a first preset temperature, and obtains the first control signal according to the gate start-up voltage when the operating temperature is greater than or equal to the first preset temperature.

4. The gate driving circuit according to claim 3, wherein: The compensation module also includes: a tenth transistor, a first terminal connected to the second node, a control terminal connected to the second terminal and receiving a second control signal, The control signal generating unit obtains the second control signal according to the gate cut-off voltage when the operating temperature is lower than a second preset temperature, and obtains the second control signal according to the gate start-up voltage when the operating temperature is greater than or equal to the second preset temperature.

5. The gate driving circuit according to claim 4, wherein: The first preset temperature is lower than the second preset temperature.

6. The gate driving circuit according to claim 1, wherein: The input module comprises: a first transistor, a first end of which is connected to the first power supply end, a second end of which is connected to the first node, and a control end of which receives a previous stage driving signal; and A second transistor, a first end of which is connected to the first node, a control end of which receives a subsequent driving signal, and a second end of which is connected to a second power supply end. The output module comprises: a third transistor, a control end of which is connected to the first node, a first end of which receives the first clock signal, and a second end of which provides the current stage driving signal; and The capacitor is connected between the control terminal and the second terminal of the third transistor.

7. The gate driving circuit according to claim 1, wherein: The control module comprises: a fourth transistor, having a control terminal and a first terminal connected to the third power supply terminal, and a second terminal connected to the second node; and a fifth transistor, a control end connected to the first node, a first end connected to the second node, and a second end connected to the second power supply end, The stabilization module comprises: a sixth transistor, having a control end connected to the second node, a first end connected to the first node, and a second end connected to the second power supply end; and A seventh transistor has a control end connected to the second node, a first end connected to the output end of the output module, and a second end connected to the second power supply end.

8. The gate driving circuit according to claim 1, wherein: The gate drive circuit further includes: An eighth transistor, having a control end receiving a second clock signal, a first end connected to the output end of the output module, and a second end connected to the second power supply end.

9. A display device, wherein: include: The gate drive circuit according to any one of claims 1 to 8; as well as The power management circuit is used for providing the gate cut-off voltage, the gate start-up voltage and the first power supply voltage according to the input voltage of the display device.

10. The display device according to claim 9, wherein: The display device further includes: The temperature detection circuit is used to obtain the operating temperature of the gate drive circuit.

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