Gate wiring repair circuit and method thereof and display panel

Abstract

The present application discloses a gate wiring repair circuit and method thereof, and a display panel, relating to the field of display technology. The circuit includes a logic control module, a dual disconnection detection module, and multiple gate wirings. The logic control module provides a disconnection detection signal to the dual disconnection detection module. After receiving the disconnection detection signal sent by the logic control module, the dual disconnection detection module determines a gate disconnection fault based on a preset wiring abnormality detection mode and the disconnection detection signal, and sends the gate disconnection fault to the logic control module so that the logic control module can perform a disconnection repair operation based on the gate disconnection fault. That is, the present application improves the panel display quality by optimizing the circuit design for gate wiring disconnection repair.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate wiring repair circuit and method thereof, as well as a display panel. Background Art

[0002] In the field of liquid crystal display technology, especially for large-size display panels with high resolution and high refresh rate, such as UHD (Ultra High Definition), 5K, 8K, etc., as well as products that adopt DRD (dual rate data) architecture and support high refresh rates such as 100Hz to 240Hz, higher requirements are placed on the stability and reliability of gate routing (i.e., gate routing).

[0003] The gate trace design for large-size display panels typically utilizes a horizontal dual-drive mode, interconnecting the scan lines on both sides to ensure stable signal transmission. However, during the actual manufacturing process, gate trace breakage or dark lines frequently occur due to factors such as thin-film transistor anomalies or gate trace corrosion and fracture. The exact location of the breakage is highly uncertain and could occur anywhere on the panel, making it difficult to repair gate trace breaks. Current mainstream repair solutions rely on manual microscopic observation and laser repair technology, which are not only inefficient and costly, but also face multiple challenges such as poor connections, unstable repair results, difficulty selecting OP (operational amplifier), signal delays, and limited repair line resources. Existing solutions are particularly ineffective when the Gn signals (i.e., gate scan signals) on both sides of the dual-drive circuit are disconnected.

[0004] Therefore, how to optimize the circuit design for repairing gate line breakage to improve the display quality of the display panel is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] The main purpose of this application is to provide a gate wiring repair circuit and method thereof, as well as a display panel, aiming to optimize the circuit design for repairing broken gate wiring to improve the display quality of the display panel.

[0006] To achieve the above objectives, the present application provides a gate wiring repair circuit, which includes:

[0007] Multiple gate traces;

[0008] a logic control module, wherein the logic control module is configured to provide a disconnection detection signal;

[0009] A dual disconnection detection module, wherein one disconnection detection module in the dual disconnection detection module is a first disconnection detection element, and the other disconnection detection module in the dual disconnection detection module is a second disconnection detection element. Two sides of the first disconnection detection element are respectively electrically connected to a first voltage side of the logic control module and a first routing end of each gate routing. Two sides of the second disconnection detection element are respectively electrically connected to a second voltage side of the logic control module and a second routing end of each gate routing. A control end of the first disconnection detection element and a control end of the second disconnection detection element are respectively electrically connected to a detection control end of the logic control module.

[0010] The dual disconnection detection module is configured to determine a gate disconnection fault based on a preset routing abnormality detection mode and the disconnection detection signal after receiving the disconnection detection signal sent by the logic control module, and send the gate disconnection fault to the logic control module so that the logic control module can perform a disconnection repair operation based on the gate disconnection fault.

[0011] In one embodiment, the first disconnection detection element includes a first shift register and first thin film transistors corresponding to each of the first routing ends, wherein a gate end of each of the first thin film transistors is electrically connected to a driving side of the first shift register, a first channel end of each of the first thin film transistors is electrically connected to the first voltage side, and each of the first routing ends is electrically connected to a second channel end of the corresponding first thin film transistor;

[0012] The second disconnection detection device includes a second shift register and second thin film transistors corresponding to each second wiring end, the gate end of each second thin film transistor is electrically connected to the driving side of the second shift register, the first channel end of each second thin film transistor is electrically connected to the second voltage side, and each second wiring end is electrically connected to the second channel end of the corresponding second thin film transistor.

[0013] In one embodiment, the gate wiring repair circuit includes a double-sided gate driving module, one of the double-sided gate driving modules is a first gate driving component, and the other gate driving module in the double-sided gate driving module is a second gate driving component;

[0014] The first gate driver is disposed on a side of the first shift register close to the plurality of gate lines arranged along the row direction, and the second gate driver is disposed on a side of the second shift register close to the plurality of gate lines arranged along the row direction;

[0015] The first gate driver is electrically connected to the first wiring end of each gate wiring, and the second gate driver is electrically connected to the second wiring end of each gate wiring.

[0016] In addition, to achieve the above-mentioned purpose, the present application also provides a gate wiring repair method, which is applied to the gate wiring repair circuit described in any one of the above items, and the gate wiring repair method includes:

[0017] Obtain the disconnection detection signal of the logic control module through the dual disconnection detection module;

[0018] A gate disconnection fault is determined according to a preset wiring abnormality detection mode and the disconnection detection signal, and the logic control module is enabled to perform a disconnection repair operation according to the gate disconnection fault.

[0019] In one embodiment, when the wiring abnormality detection mode is the disconnection detection mode, the step of determining a gate disconnection fault according to the preset wiring abnormality detection mode and the disconnection detection signal includes:

[0020] In response to the disconnection detection signal, connecting the two sides of the same gate line to the dual disconnection detection module row by row to form a disconnection detection path from the first disconnection detection element to the second disconnection detection element via the gate line;

[0021] When the first voltage side of the logic control module provides the first voltage to the gate lines row by row, the second voltage side of the logic control module detects whether the first voltage has a voltage value output after passing through the disconnection detection path;

[0022] If no voltage value is outputted after the first voltage passes through the disconnection detection path, it is determined that the gate disconnection fault is caused by a break in the gate wiring.

[0023] In one embodiment, when the wiring abnormality detection mode is the unilateral fault detection mode, the step of determining a gate disconnection fault according to the preset wiring abnormality detection mode and the disconnection detection signal includes:

[0024] In response to the disconnection detection signal, the first disconnection detection element is enabled to be inoperative when the first gate driver provides a first gate voltage signal to the gate target trace, and the second disconnection detection element is simultaneously enabled to communicate with the gate target trace when the second gate driver is inoperative, so as to form a first unilateral detection path from the first gate driver to the second disconnection detection element via the gate target trace, and to determine a voltage output result of the first gate voltage signal after passing through the first unilateral detection path;

[0025] When the wiring abnormality detection mode is switched from the single-side fault detection mode to the double-side fault detection mode, a gate disconnection fault is determined according to the double-side fault detection mode and the voltage output result.

[0026] In one embodiment, the step of determining a gate disconnection fault based on the bilateral fault detection mode and the voltage output result includes:

[0027] enabling the second disconnection detection element to be inoperative when the second gate driver provides a second gate voltage signal to the gate target trace, and simultaneously enabling the first disconnection detection element to be connected to the gate target trace when the first gate driver is inoperative, so as to form a second unilateral detection path from the second gate driver to the first disconnection detection element via the gate target trace;

[0028] If the second gate voltage signal has no voltage output after passing through the second unilateral detection path, and the voltage output result shows that the first gate voltage signal has no voltage output after passing through the first unilateral detection path, it is determined that the gate disconnection fault is a failure of the double-sided gate drive module;

[0029] If the second gate voltage signal has no voltage output after passing through the second unilateral detection path, and the voltage output result shows that the first gate voltage signal has a voltage output after passing through the first unilateral detection path, then it is determined that the gate disconnection fault is a failure of the second gate driver;

[0030] If the second gate voltage signal outputs a voltage value after passing through the second unilateral detection path, and the voltage output result shows that the first gate voltage signal has no voltage value output after passing through the first unilateral detection path, it is determined that the gate disconnection fault is a failure of the first gate driver.

[0031] In one embodiment, the step of enabling the logic control module to perform a disconnection repair operation according to the gate disconnection fault includes:

[0032] Controlling the logic control module to determine, in response to the gate line breakage fault being a breakage of the gate line body, a display partition where the gate line breakage is located, and determining a compensation mean voltage of the gate line breakage based on a block compensation voltage corresponding to each gate line in the display partition and the number of gate lines of all the gate lines in the display partition;

[0033] When the connection between the gate break and the first break detection device is turned on, the connection between the gate break and the second break detection device is turned on simultaneously, so that when the logic control module provides the compensation mean voltage to the side of the gate break close to the first break detection device, the logic control module also provides the compensation mean voltage to the side of the gate break close to the second break detection device.

[0034] In one embodiment, the step of enabling the logic control module to perform a disconnection repair operation according to the gate disconnection fault includes:

[0035] Controlling the logic control module to synchronously connect the gate target line with the first disconnection detection element in response to the gate disconnection fault being a failure of the first gate driver, when providing the second gate scanning voltage to the gate target line through the second gate driver, so that the logic control module provides the gate target line with a first voltage that is the same as the second gate scanning voltage through the first disconnection detection element; or

[0036] Controlling the logic control module to synchronously connect the gate target line with the second disconnection detection element in response to the gate disconnection fault being a failure of the second gate driver, when providing the first gate scanning voltage to the gate target line through the first gate driver, so that the logic control module can provide the gate target line with a second voltage that is the same as the first gate scanning voltage through the second disconnection detection element; or

[0037] The logic control module is controlled to respond to the gate disconnection fault as a failure of the double-sided gate drive module, and when the connection between the gate target trace and the first disconnection detection device is connected, the connection between the gate target trace and the second disconnection detection device is simultaneously connected, so that when the logic control module provides a repair compensation voltage to the side of the gate target trace close to the first disconnection detection device, the repair compensation voltage is simultaneously provided to the side of the gate target trace close to the second disconnection detection device.

[0038] In addition, to achieve the above-mentioned purpose, the present application also provides a display panel, which includes a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer is arranged between the array substrate and the color filter substrate, and the array substrate includes the gate wiring repair circuit described in any one of the above items.

[0039] In order to optimize the circuit design of gate line break repair to improve the display quality of the display panel, the present application provides a gate line repair circuit, which realizes efficient and accurate detection and fully automatic repair of gate line break faults through the coordinated work of a dual line break detection module and a logic control module that integrates a first line break detection device and a second line break detection device. Specifically, the first line break detection device is electrically connected between the first voltage side of the logic control module and the first line end of all gate lines, and the second line break detection device is electrically connected between the second voltage side of the logic control module and the second line end of all gate lines; next, the dual line break detection module controls the operation of the first line break detection device and the second line break detection device based on the line break detection signal provided by the detection control end of the logic control module and the preset line abnormality detection mode, so as to perform synchronous detection or separate detection on both ends of each gate line, and then quickly locate whether the gate line break fault is a break in the gate line body, a failure of the single-side gate drive module of the gate line, or a failure of the double-side gate drive module of the gate line, thereby greatly improving The accuracy and efficiency of gate line break fault detection, compared with traditional detection methods, does not require manual line-by-line inspection, saving a lot of time and labor costs, while avoiding omissions that may occur in manual detection, and providing accurate and reliable data support for the subsequent line break repair work of the logic control module; subsequently, the logic control module implements a fully automated line break repair operation based on the gate line break fault sent by the dual line break detection module, compressing the several hours of process required for traditional manual laser repair to millisecond-level automatic completion, significantly improving the repair efficiency of the faulty gate line, so that the gate line after the gate line break fault is repaired has the same performance as the normal gate line, thereby effectively improving the display quality of the display panel applied to the gate line repair circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0042] Figure 1 It is a schematic diagram of the dual-drive structure in the horizontal direction of the display panel;

[0043] Figure 2 This is a structural block diagram of the first embodiment of the gate wiring repair circuit of the present application;

[0044] Figure 3This is a schematic diagram of a gate wiring repair circuit according to an embodiment of the present application;

[0045] Figure 4 Schematic diagram of GOA damage detection according to an embodiment of the present application;

[0046] Figure 5 1 is a schematic diagram of a gate drive module circuit according to an embodiment of the present application;

[0047] Figure 6 Schematic diagram of the gate disconnection partition repair structure involved in the embodiment of the present application;

[0048] Figure 7 1 is a waveform diagram of a line break repair process according to an embodiment of the present application;

[0049] Figure 8 This is a schematic diagram of the structure of the display device involved in the embodiment of the present application.

[0050] Explanation of the accompanying drawings: 10, logic control module; 20, dual disconnection detection module; 21, first disconnection detection element; 22, second disconnection detection element; 210, first shift register; T1, first thin film transistor; 220, second shift register; T2, second thin film transistor; 31, first gate driver; 32, second gate driver; T3, third thin film transistor; T4, fourth thin film transistor; T5, fifth thin film transistor; T6, sixth thin film transistor.

[0051] The realization of the objectives, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0053] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back, etc.), such directional indications are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0054] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present application, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0055] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this application.

[0056] In the field of liquid crystal display technology, especially for large-size display panels with high resolution and high refresh rate, such as UHD (Ultra High Definition), 5K, 8K, etc., as well as products that adopt DRD architecture and support high refresh rates such as 100Hz to 240Hz, higher requirements are placed on the stability and reliability of gate routing (i.e., gate routing).

[0057] In the manufacturing process of large-size display panels, the gate routing design often adopts a horizontal dual-drive mode, that is, the scanning lines connected on both sides are used to ensure stable signal transmission. Figure 1This is clearly demonstrated in a demonstration of the dual-drive mode, with two GOA (Gate Driven on Array) units forming the core of this dual-drive mode. However, in actual production, gate traces may experience breakage or dark lines, resulting in only one side of the gate line being able to function properly. Breakage may not be noticeable on small, low-resolution panels. However, in the current market, high-resolution products such as UHD, 5K, and 8K, as well as large-format TVs using DRD architecture and offering high refresh rates such as 100Hz, 120Hz, 144Hz, 165Hz, and 240Hz, have become mainstream. These products face shorter charging times, and large-format panels have longer signal transmission distances from one scan line to the other. Therefore, when a break occurs, the subpixels adjacent to the broken portion may not reach the target grayscale voltage level due to insufficient charging, resulting in a noticeable difference in the display. Given the high cost and high repair costs of these products, precise location and repair of the break are particularly important. However, the location of the broken wire is uncertain and may appear in any area of ​​the panel, which undoubtedly increases the difficulty of repair.

[0058] Existing gate trace break repair solutions primarily rely on microscopic observation and laser repair technology. This existing process involves first using a microscope to locate the specific broken scan line, then using laser technology to connect the broken scan line to the repair line to establish a repair path. Finally, the Gn signal is collected from the unaffected side of the dual drive, processed by an operational amplifier (OP), and then transmitted back. However, existing gate trace break repair solutions have many drawbacks: 1. Each panel requires manual observation to determine the specific location of the break before laser repair, which is inefficient and costly. 2. The laser connection process may result in poor connection, resulting in poor repair results. 3. The required operational amplifier must withstand large voltage differentials, making selection difficult. 4. Signal acquisition and transmission introduce delays. 5. If the Gn signal on both sides of the dual drive is disconnected, effective repair cannot be performed. 6. Due to the limited number of glass traces, each gate trace repair requires a repair line, so at most only one or two breaks can be repaired.

[0059] The above content is only used to assist in understanding the technical solution of this application and does not constitute an admission that the above content is prior art.

[0060] In order to solve the technical defects existing in the above content, the present application provides a gate wiring repair circuit and method thereof, as well as a display panel.

[0061] The embodiment of the present application provides a gate wiring repair circuit, referring to Figure 2 As shown, Figure 2This is a block diagram of the first embodiment of the gate wiring repair circuit of the present application. The gate wiring repair circuit includes:

[0062] Multiple gate traces.

[0063] In this embodiment, referring to Figure 2 , Figure 2 The G1, G2, G3, G4, G5, G6, G7, ..., Gn-1, Gn, Gn+1 shown can represent multiple gate lines.

[0064] The logic control module 10 is configured to provide a disconnection detection signal.

[0065] In this embodiment, the logic control module 10 provided in the present application is configured to provide a break detection signal to the dual break detection module 20, thereby significantly improving the degree of automation and accuracy of the gate line break detection in the display panel, effectively reducing the need for manual intervention, and at the same time, significantly increasing the logic control module 10's collaborative work with the dual break detection module 20 to quickly respond to and efficiently repair gate line break faults.

[0066] In a specific embodiment, the logic control module 10 can be directly set at Figure 3 On the PCBA (Printed Circuit Board Assembly) board shown, the logic control module 10 can also be packaged in a SOC chip (System-on-a-Chip), which is arranged on the PCBA board. Figure 3 The circles R, G, and B shown represent red, green, and blue sub-pixels, respectively.

[0067] A dual disconnection detection module 20, wherein one disconnection detection module in the dual disconnection detection module 20 is a first disconnection detection element 21, and the other disconnection detection module in the dual disconnection detection module 20 is a second disconnection detection element 22. The two sides of the first disconnection detection element 21 are respectively electrically connected to the first voltage side of the logic control module 10 and the first wiring end of each gate wiring. The two sides of the second disconnection detection element 22 are respectively electrically connected to the second voltage side of the logic control module 10 and the second wiring end of each gate wiring. The control end of the first disconnection detection element 21 and the control end of the second disconnection detection element 22 are respectively electrically connected to the detection control end of the logic control module 10.

[0068] In this embodiment, the dual disconnection detection module 20 provided in this application realizes efficient detection of gate line disconnection faults by integrating the first disconnection detection element 21 and the second disconnection detection element 22. Figure 2The first disconnection detection element 21 is electrically connected to the first voltage side of the logic control module 10 (ie Figure 2 The second disconnection detection element 22 is electrically connected to the second voltage side of the logic control module 10 (ie, the V1 side shown in FIG. 1 ) and the first wiring end of all gate wirings. Figure 2 The first disconnection detection element 21 and the second disconnection detection element 22 are controlled based on the disconnection detection signal provided by the detection control end of the logic control module 10 to perform synchronous detection or separate detection on both ends of each gate line, thereby quickly locating the gate disconnection fault and determining whether the gate line body is broken, or the first gate driver near the first line end is abnormal, or the second gate driver near the second line end is abnormal, or even the gate drivers on both sides of the gate line are abnormal, thereby greatly improving the accuracy and efficiency of gate disconnection fault detection. Compared with traditional detection methods, there is no need for manual line-by-line troubleshooting, saving a lot of time and labor costs, while avoiding omissions that may occur in manual detection, and providing accurate and reliable data support for subsequent disconnection repair work of the logic control module 10.

[0069] The dual disconnection detection module 20 is configured to determine a gate disconnection fault based on a preset routing abnormality detection mode and the disconnection detection signal after receiving the disconnection detection signal sent by the logic control module 10, and send the gate disconnection fault to the logic control module 10 so that the logic control module 10 enables the logic control module to perform a disconnection repair operation based on the gate disconnection fault.

[0070] In this embodiment, after receiving the disconnection detection signal sent by the logic control module 10, the dual disconnection detection module 20 realizes full-scenario coverage diagnosis of gate wiring faults based on the preset wiring abnormality detection mode (including the disconnection detection mode, the single-side fault detection mode, and the double-side fault detection mode) and the disconnection detection signal; next, after the dual disconnection detection module 20 transmits the gate disconnection fault back to the logic control module 10 in real time, the logic control module 10 automatically switches the disconnection repair compensation path according to the specific fault type corresponding to the gate disconnection fault, thereby realizing a fully automated disconnection repair operation, thereby compressing the several hours required for traditional manual laser repair to automatically complete it in milliseconds, significantly improving the repair efficiency of the faulty gate wiring, and ensuring that the performance of the gate wiring after the gate disconnection fault is consistent with that of the normal gate wiring, thereby effectively improving the display quality of the display panel applied to the gate wiring repair circuit.

[0071] Further, in some feasible embodiments, referring to Figure 3The first disconnection detection device 21 includes a first shift register 210 and a first thin film transistor T1 corresponding to each first wiring end. The gate end of each first thin film transistor T1 is electrically connected to the driving side of the first shift register 210, the first channel end of each first thin film transistor T1 is electrically connected to the first voltage side, and each first wiring end is electrically connected to the second channel end of the corresponding first thin film transistor T1.

[0072] In this embodiment, referring to Figure 3 In the present application, a first disconnection detection element 21 is provided that integrates a first shift register 210 and a plurality of first thin-film transistors T1. The driving side of the first shift register 210 is electrically connected to the gate end of the first thin-film transistor T1 electrically connected to the first wiring end of each gate wiring, so that the first shift register 210 drives the first thin-film transistors T1 of the corresponding row from the off state to the on state row by row according to a preset gate row driving sequence, thereby ensuring that the first wiring end of each gate wiring can establish a path with the first voltage side of the logic control module 10 through the corresponding first thin-film transistor T1.

[0073] It should be noted that the first disconnection detection element 21 integrates the first shift register 210 and a plurality of first thin film transistors T1. Figure 3 The first shift register 210, first thin-film transistor T1-(n-1), first thin-film transistor T1-n, and first thin-film transistor T1-(n+1) are shown. The number of first thin-film transistors T1 is the same as the number of gate lines, and each first thin-film transistor T1 is connected to a corresponding gate line. Specifically, the first thin-film transistor T1-(n-1) is connected to the first line terminal of the gate line Gn-1, the first thin-film transistor T1-n is connected to the first line terminal of the gate line Gn, and the first thin-film transistor T1-(n+1) is connected to the first line terminal of the gate line Gn+1.

[0074] The second disconnection detection device 22 includes a second shift register 220 and second thin-film transistors T2 corresponding to each second wiring end. The gate end of each second thin-film transistor T2 is electrically connected to the driving side of the second shift register 220, the first channel end of each second thin-film transistor T2 is electrically connected to the second voltage side, and each second wiring end is electrically connected to the second channel end of the corresponding second thin-film transistor T2.

[0075] In this embodiment, referring to Figure 3In the present application, a second disconnection detection element 22 is provided that integrates a second shift register 220 and a plurality of second thin-film transistors T2. The driving side of the second shift register 220 is electrically connected to the gate end of the second thin-film transistor T2 electrically connected to the second wiring end of each gate wiring. Thus, the second shift register 220 drives the second thin-film transistors T2 of the corresponding row from the off state to the on state row by row according to a preset gate row driving sequence, thereby ensuring that the second wiring end of each gate wiring can establish a path with the second voltage side of the logic control module 10 through the corresponding second thin-film transistor T2.

[0076] It should be noted that the second disconnection detection element 22 is integrated with the second shift register 220 and a plurality of second thin film transistors T2. Figure 3 The second shift register 220, second thin-film transistor T2-(n-1), second thin-film transistor T2-n, and second thin-film transistor T2-(n+1) are shown. The number of second thin-film transistors T2 is the same as the number of gate lines, and each second thin-film transistor T2 is connected to the second wiring terminal of a gate line. Specifically, the second thin-film transistor T2-(n-1) is connected to the second wiring terminal of the gate line Gn-1, the second thin-film transistor T2-n is connected to the second wiring terminal of the gate line Gn, and the second thin-film transistor T2-(n+1) is connected to the second wiring terminal of the gate line Gn+1.

[0077] Furthermore, in some other feasible embodiments, referring to Figure 3 The gate wiring repair circuit includes a double-sided gate driving module, one gate driving module in the double-sided gate driving module is a first gate driving component 31, and the other gate driving module in the double-sided gate driving module is a second gate driving component 32; the first gate driving component 31 is arranged on a side of the first shift register 210 close to the multiple gate wirings arranged along the row direction, and the second gate driving component 32 is arranged on a side of the second shift register 220 close to the multiple gate wirings arranged along the row direction; the first gate driving component 31 is electrically connected to the first wiring end of each of the gate wirings, and the second gate driving component 32 is electrically connected to the second wiring end of each of the gate wirings.

[0078] In this embodiment, referring to Figure 2 For large-size display panels with high resolution and high refresh rate, such as UHD, 5K, 8K, and display panels that use DRD architecture and support high refresh rates such as 100Hz to 240Hz, both ends of each gate line are equipped with GOA units with the same driving timing (i.e., the first gate driver and the second gate driver). Figure 4The gate wiring repair circuit provided in the present application enables the first shift register 210 to shift the gate target line (ie Figure 4 The gate trace Gn shown in FIG. 1 provides a first gate voltage signal (i.e. Figure 4 When the second gate driver 32 is not working, the first thin film transistor T1-n electrically connected to the gate line Gn is not turned on, and the second shift register 220 is synchronously enabled to turn on the second thin film transistor T2-n connected to the gate line Gn, thereby forming a first unilateral detection path from the first gate driver 31 to the second shift register 220 via the gate line Gn to detect whether the first gate driver fails, thereby realizing the disconnection fault detection of the first gate driver.

[0079] Alternatively, the gate wiring repair circuit provided in the present application enables the second shift register 220 to shift the gate target line (ie, Figure 4 The gate trace Gn shown in FIG. 1 provides a second gate voltage signal (i.e. Figure 4 When the first gate driver 31 is not working, the second thin film transistor T2-n electrically connected to the gate wiring Gn is not turned on, and the first shift register 210 is synchronously enabled to turn on the first thin film transistor T1-n connected to the gate wiring Gn, thereby forming a second unilateral detection path from the second gate driver 32 to the first shift register 210 via the gate wiring Gn to detect whether the second gate driver fails, thereby realizing the disconnection fault detection of the second gate driver.

[0080] That is to say, the gate wiring repair circuit set up in the present application coordinates the control of the gate driving module on the corresponding side through the first / second shift register, cuts off the thin film transistor on the same side and turns on the thin film transistor on the opposite side to form a unidirectional detection loop when the single-sided gate driving module is driven, so that the precise positioning accuracy of the broken line fault is improved to the level of the single-sided driving unit, effectively avoiding the misjudgment caused by signal interference in the traditional bidirectional driving mode.

[0081] Furthermore, in some other feasible embodiments, referring to Figure 5 , Figure 5: This is a schematic diagram of the gate drive module circuit involved in the embodiment of the present application. The first gate driver and the second gate driver are both the same gate driver module, and the gate driver module includes a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, and a sixth thin film transistor T6; the first channel end of the third thin film transistor T3 and the gate end of the third thin film transistor T3 are electrically connected to the first gate scanning end respectively, the second channel end of the third thin film transistor T3 is electrically connected to the gate end of the fourth thin film transistor T4 and the first channel end of the fifth thin film transistor T5 respectively, the first channel end of the fourth thin film transistor T4 is electrically connected to the step-by-step output end, and the fourth thin film transistor T4 is electrically connected to the step-by-step output end. The second channel end of the transistor T4 is electrically connected to the first channel end of the sixth thin film transistor T6, the gate end of the sixth thin film transistor T6 is electrically connected to the gate end of the fifth thin film transistor T5, and the second channel end of the fifth thin film transistor T5 and the second channel end of the sixth thin film transistor T6 are electrically connected to the low potential end respectively; the second channel end of the fourth thin film transistor T4 is electrically connected to the connection node of the first channel end of the sixth thin film transistor T6 and is electrically connected to the second gate scanning end; the gate end of the sixth thin film transistor T6 is electrically connected to the connection node of the gate end of the fifth thin film transistor T5 and is electrically connected to the third scanning end.

[0082] In this embodiment, Figure 5 The four thin film transistors (the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5 and the sixth thin film transistor T6) shown in FIG constitute a single-stage GOA basic circuit (i.e., a gate drive module), wherein the second gate scanning terminal is used to provide a gate scanning signal for the current row gate line (i.e., Figure 5As shown, the output of the current row gate wiring is turned on, and the step-by-step output terminal is used to provide the signal CK / XCK of the step-by-step output of the control signal G(N). The signal VSS provided by the low potential terminal is set to pull the low potential of the signal G(N) down to the low potential terminal output; the first gate scanning terminal is used to provide the signal G(N-1) of the gate wiring of the previous row of the current row gate wiring; the third gate scanning terminal is used to provide the signal G(N+1) of the gate wiring of the next row of the current row gate wiring. Exemplarily, when the gate driver is operating normally, the third thin film transistor T3, driven by the signal G(N-1), sends the voltage provided by the first gate scanning terminal to the gate terminal of the fourth thin film transistor T4, so as to switch the fourth thin film transistor T4 from the off state to the on state, enabling the second gate scanning terminal to be pulled up to the voltage value corresponding to the signal CK / XCK in the step-by-step output terminal to provide the signal G(N) for the current row gate line, until the fifth thin film transistor T5 and the sixth thin film transistor T6 are enabled to be turned on at the same time under the drive of the signal G(N+1) provided by the third gate scanning terminal, so as to pull the signal G(N-1) provided by the first gate scanning terminal and the signal G(N) provided by the second gate scanning terminal down to the low potential end, thereby ending the gate drive of each sub-pixel electrically connected to the current row gate line. However, when the gate driver is operating abnormally, that is, Figure 5 The third thin film transistor T3 and the fourth thin film transistor T4 are abnormal. Figure 5 When the third thin film transistor T3 is damaged and cannot provide a gate driving signal to the gate terminal of the fourth thin film transistor T4 under the action of the signal G(N-1), and / or Figure 5 The fourth thin-film transistor T4 shown is damaged, so it cannot be turned on under the gate drive signal provided when the third thin-film transistor T3 is normal, resulting in no signal G(N) output from the second gate scanning end, which in turn causes abnormal display of each sub-pixel electrically connected to the current row gate wiring, with dark lines or broken lines.

[0083] In summary, in order to optimize the circuit design of gate wiring break repair to improve the display quality of the display panel, the present application provides a gate wiring repair circuit, which realizes efficient and accurate detection and fully automatic repair of gate wiring break faults through the coordinated work of a dual break detection module 20 integrating a first break detection device 21 and a second break detection device 22 and a logic control module 10. Specifically, the first disconnection detection element 21 is electrically connected between the first voltage side of the logic control module 10 and the first wiring ends of all gate wirings, and the second disconnection detection element 22 is electrically connected between the second voltage side of the logic control module 10 and the second wiring ends of all gate wirings; next, the dual disconnection detection module 20 controls the first disconnection detection element 21 and the second disconnection detection element 22 to work respectively based on the disconnection detection signal provided by the detection control end of the logic control module 10 and the preset wiring abnormality detection mode, so as to perform synchronous detection or separate detection on both ends of each gate wiring, thereby quickly locating whether the gate disconnection fault is caused by the breakage of the gate wiring body, the failure of the single-side gate driving module of the gate wiring, or the failure of the double-side gate driving modules of the gate wiring, thereby The accuracy and efficiency of gate line break fault detection are greatly improved. Compared with traditional detection methods, there is no need for manual line-by-line inspection, which saves a lot of time and labor costs, while avoiding omissions that may occur in manual detection, and provides accurate and reliable data support for the subsequent line break repair work of the logic control module 10; then, the logic control module 10 realizes a fully automated line break repair operation based on the gate line break fault sent by the dual line break detection module 20, so as to compress the several hours of process required for traditional manual laser repair to millisecond-level automatic completion, significantly improving the repair efficiency of the faulty gate line, so that the performance of the gate line after the gate line break fault is consistent with that of the normal gate line, thereby effectively improving the display quality of the display panel applied to the gate line repair circuit.

[0084] Furthermore, based on the first embodiment of the gate wiring repair circuit of the present application, a second embodiment of the gate wiring repair method of the present application is proposed.

[0085] The gate wiring repair method of the present application is applied to any of the above-mentioned gate wiring repair circuits. The gate wiring repair method of the present application is executed by a terminal device (such as a display device) that drives and controls the gate wiring repair circuit. The gate wiring repair method of the present application includes the following implementation steps S10 to S20.

[0086] Step S10: obtaining a disconnection detection signal from the logic control module through the dual disconnection detection module.

[0087] In this embodiment, during the device startup and power-on phase of the display panel, the dual disconnection detection module will receive a disconnection detection signal actively provided by the logic control module, so that the dual disconnection detection module can automatically perform gate disconnection fault detection under the drive of the disconnection detection signal, thereby effectively reducing dependence on manual intervention and greatly improving the automation and accuracy of gate line disconnection detection in the display panel.

[0088] Step S20 : ​​determining a gate disconnection fault according to a preset wiring abnormality detection mode and a disconnection detection signal, and enabling the logic control module to perform a disconnection repair operation according to the gate disconnection fault.

[0089] In this embodiment, after receiving the disconnection detection signal sent by the logic control module, the dual disconnection detection module implements full-scenario coverage diagnosis of gate wiring faults based on a preset wiring anomaly detection mode (including a disconnection detection mode, a single-side fault detection mode, and a double-side fault detection mode) and the disconnection detection signal. Next, after the dual disconnection detection module transmits the gate disconnection fault back to the logic control module in real time, the logic control module automatically switches the disconnection repair compensation path based on the specific fault type corresponding to the gate disconnection fault (i.e., a break in the gate wiring body, a failure of a single-side gate driver module of the gate wiring, or a failure of both-side gate driver modules of the gate wiring), thereby achieving a fully automated disconnection repair operation. This reduces the several hours required for traditional manual laser repair to a millisecond-level automatic completion, significantly improving the repair efficiency of the faulty gate wiring, ensuring that the performance of the gate wiring after the gate disconnection fault is consistent with that of a normal gate wiring, thereby effectively improving the display quality of the display panel applied to the gate wiring repair circuit.

[0090] Furthermore, in other feasible embodiments, when the wiring abnormality detection mode is the disconnection detection mode, the above step S20: determining the gate disconnection fault according to the preset wiring abnormality detection mode and the disconnection detection signal, also includes the following implementation steps S201 to S203.

[0091] Step S201 : In response to a disconnection detection signal, connect both sides of a gate line to a dual disconnection detection module row by row to form a disconnection detection path from a first disconnection detection element to a second disconnection detection element via the gate line.

[0092] In this embodiment, referring to Figure 4The dual disconnection detection module 20 provided in the present application achieves efficient detection of gate line disconnection faults by integrating a first disconnection detection element 21 comprising a first shift register 210 and a plurality of first thin-film transistors T1, and a second disconnection detection element 22 comprising a second shift register 220 and a plurality of second thin-film transistors T2. Specifically, when the line abnormality detection mode is the disconnection detection mode, based on the electrical connection between the detection control terminal of the logic control module 10 and the first shift register 210 and the second shift register 220, the first shift register 210, driven by the disconnection detection signal provided by the detection control terminal of the logic control module 10, turns on the first thin-film transistor T1 electrically connected to the first line end of each gate line row by row, while the second shift register 220, driven by the disconnection detection signal provided by the detection control terminal of the logic control module 10, turns on the second thin-film transistor T2 electrically connected to the second line end of the same gate line, thereby forming a voltage supply from the first voltage side (i.e., the voltage supply side) of the logic control module 10 for each gate line. Figure 4 The V1 side shown in FIG. 1 is connected to the second voltage side of the logic control module 10 (ie, the V1 side shown in FIG. 1 ) via its own wiring body. Figure 4 The logic control module 10 detects whether the corresponding gate line is unobstructed row by row based on the disconnection detection path of each gate line, thereby significantly improving the detection efficiency and accuracy of the gate line disconnection fault.

[0093] Step S202 : When the first voltage side of the logic control module provides the first voltage to the gate lines row by row, the second voltage side of the logic control module detects whether the first voltage has a voltage value output after passing through the disconnection detection path.

[0094] In this embodiment, after establishing a disconnection detection path for each gate trace, taking gate trace Gn as an example, when scanning gate trace Gn row by row, a first voltage is provided to gate trace Gn via the first voltage side of the logic control module, and the second voltage side of the logic control module detects whether a voltage value is output after the first voltage passes through the disconnection detection path, thereby realizing disconnection detection of the gate trace body.

[0095] Step S203: If no voltage value is output after the first voltage passes through the disconnection detection path, it is determined that the gate disconnection fault is caused by a break in the gate wiring.

[0096] In this embodiment, during the line-by-line scanning process, if the gate line Gn is scanned line by line, the logic control module actively injects the first voltage through the first voltage side, and simultaneously uses the second voltage side to detect the output feedback of the disconnection detection path in real time. If the voltage output after the first voltage passes through the disconnection detection path is missing, it can be directly and quickly determined that the gate line Gn is broken. The gate line Gn body break can be used to Figure 3The cross indicated by the reference numeral F1 indicates that the efficiency and accuracy of detecting the broken gate wiring are achieved, thereby improving the efficiency of subsequently repairing the broken gate wiring.

[0097] Furthermore, in some feasible embodiments, when the routing anomaly detection mode is a unilateral fault detection mode, the above-mentioned step S20: determining the gate disconnection fault according to the preset routing anomaly detection mode and the disconnection detection signal, may also include the following implementation steps A10 to A20.

[0098] Step A10: In response to the disconnection detection signal, the first disconnection detection element is enabled to be inoperative when the first gate driver provides the first gate voltage signal to the gate target wiring, and the second disconnection detection element is simultaneously enabled to be connected to the gate target wiring when the second gate driver is inoperative, so as to form a first unilateral detection path from the first gate driver to the second disconnection detection element via the gate target wiring, and determine the voltage output result of the first gate voltage signal after passing through the first unilateral detection path.

[0099] In this embodiment, the gate target line can be any gate line among multiple gate lines. Figure 4 The gate line Gn shown is a gate target line. When the line abnormality detection mode is the single-side fault detection mode, the double disconnection detection module 20 responds to the disconnection detection signal, enabling the first shift register 210 to provide the first gate voltage signal (i.e., Figure 4 When the second gate driver 32 is not working, the first thin film transistor T1-n electrically connected to the gate line Gn is not turned on, and the second shift register 220 is synchronously enabled to turn on the second thin film transistor T2-n connected to the gate line Gn, thereby forming a first unilateral detection path from the first gate driver 31 to the second shift register 220 via the gate line Gn; next, it is detected whether the first gate voltage signal has a voltage output after passing through the first unilateral detection path. If the first gate voltage signal has no voltage output after passing through the first unilateral detection path, it is determined that the voltage output result is no voltage value output; if the first gate voltage signal has a voltage output after passing through the first unilateral detection path, it is determined that the voltage output result is a voltage value output, so as to detect whether the first gate driver has failed based on the voltage output result, thereby achieving accurate detection of a disconnection fault of the first gate driver.

[0100] Step A20: When the wiring abnormality detection mode is switched from the single-side fault detection mode to the double-side fault detection mode, a gate disconnection fault is determined based on the double-side fault detection mode and the voltage output result.

[0101] In this embodiment, when the wiring abnormality detection mode is switched from the unilateral fault detection mode to the bilateral fault detection mode, the gate line break fault can be accurately determined based on the bilateral fault detection mode and the voltage output result, thereby achieving comprehensive detection of the display panel line break fault.

[0102] Furthermore, in some other feasible embodiments, the above-mentioned step A20: determining the gate disconnection fault according to the bilateral fault detection mode and the voltage output result, may also include the following implementation steps A201 to A204.

[0103] Step A201: Enable the second disconnection detection device to be inoperative when the second gate driver provides the second gate voltage signal to the gate target trace, and simultaneously enable the first disconnection detection device to be connected to the gate target trace when the first gate driver is inoperative, so as to form a second unilateral detection path from the second gate driver to the first disconnection detection device via the gate target trace.

[0104] In this embodiment, after determining that the first gate driver 31 is disconnected in the single-side fault detection mode, when the routing abnormality detection mode is switched from the single-side fault detection mode to the double-side fault detection mode, the double disconnection detection module 20 immediately responds to the disconnection detection signal, enabling the second shift register 220 to shift the second gate driver 32 to the gate target line (i.e., Figure 4 The gate trace Gn shown in FIG. 1 provides a second gate voltage signal (i.e. Figure 4 When the first gate driver 31 is not working, the second thin film transistor T2-n electrically connected to the gate wiring Gn is not turned on, and the first shift register 210 is synchronously enabled to turn on the first thin film transistor T1-n connected to the gate wiring Gn, thereby forming a second unilateral detection path from the second gate driver 32 to the first shift register 210 via the gate wiring Gn to detect whether the second gate driver fails, thereby realizing the disconnection fault detection of the second gate driver.

[0105] Step A202: If the second gate voltage signal has no voltage output after passing through the second unilateral detection path, and the voltage output result is that the first gate voltage signal has no voltage output after passing through the first unilateral detection path, then the gate disconnection fault is determined to be a failure of the double-sided gate driving module.

[0106] In this embodiment, after the first unilateral detection path and the second unilateral detection path are established, the voltage output of the first gate voltage signal via the first unilateral detection path and the voltage output of the second gate voltage signal via the second unilateral detection path are determined. If the second gate voltage signal does not output a voltage value after passing through the second unilateral detection path, and the voltage output result indicates that the first gate voltage signal does not output a voltage value after passing through the first unilateral detection path, then the gate disconnection fault is determined to be a failure of the double-sided gate driver module, i.e., both the first gate driver and the second gate driver have failed.

[0107] Step A203: If the second gate voltage signal has no voltage output after passing through the second unilateral detection path, and the voltage output result shows that the first gate voltage signal has a voltage output after passing through the first unilateral detection path, then the gate disconnection fault is determined to be a failure of the second gate driver.

[0108] In this embodiment, after utilizing the first unilateral detection path and the second gate driver to respectively detect the first gate voltage signal and the second gate voltage signal, if it is detected that the second gate voltage signal has no voltage output after passing through the second unilateral detection path, and the voltage output result shows that the first gate voltage signal has a voltage output after passing through the first unilateral detection path, then the gate disconnection fault is determined to be a failure of the second gate driver.

[0109] Step A204: If the second gate voltage signal outputs a voltage value after passing through the second unilateral detection path, and the voltage output result is that the first gate voltage signal outputs no voltage value after passing through the first unilateral detection path, then the gate disconnection fault is determined to be a failure of the first gate driver.

[0110] In this embodiment, after utilizing the first unilateral detection path and the second gate driver to respectively detect the first gate voltage signal and the second gate voltage signal, if it is detected that the second gate voltage signal outputs a voltage value after passing through the second unilateral detection path, and the voltage output result indicates that the first gate voltage signal outputs no voltage value after passing through the first unilateral detection path, then the gate disconnection fault is determined to be a failure of the first gate driver.

[0111] In summary, the dual-sided gate drive failure diagnosis mechanism proposed in this embodiment achieves accurate classification and rapid location of fault types through multi-conditional logic judgment. Specifically, when there is no voltage feedback in both the first and second unilateral detection paths, the gate trace repair circuit can clearly determine that the dual-sided drive module has failed as a whole, avoiding the bilateral false alarm problem caused by unilateral signal interference in traditional solutions. In addition, by cross-verifying the voltage output status of the two detection paths (for example, when only the second unilateral detection path has no feedback, the second gate drive component is identified as failed), the efficiency of targeted fault source identification is significantly improved.

[0112] Furthermore, in some feasible embodiments, the above step S20: enabling the logic control module to perform a disconnection repair operation according to the gate disconnection fault, may also include the following implementation steps B10 to B20.

[0113] Step B10: When the gate line break fault is caused by a break in the gate line body, the control logic control module determines the display partition where the gate line break is located, and determines the compensation mean voltage of the gate line break based on the block compensation voltage corresponding to each gate line in the display partition and the number of gate lines of all gate lines in the display partition.

[0114] In this embodiment, referring to Figure 6 , Figure 6 Schematic diagram of the gate line partition repair structure involved in the embodiment of the present application. Specifically, the display panel is partitioned, for example, the gate lines arranged row by row are divided into Figure 6 The five blocks shown are Block 1, Block 2, Block 3, Block 4, and Block 5. Based on the response of the logic control module to the gate line break fault being a gate line body break, the display partition where the gate line break is located is determined, and the first line terminal voltage V11 and the second line terminal voltage V22 of each gate line in the display partition are obtained row by row; next, the voltage drop between the first line terminal voltage V11 and the second line terminal voltage V22 is determined, and the voltage drop and the first line terminal voltage V11 are calculated according to a preset compensation voltage calculation algorithm to accurately obtain the gate compensation voltage of each gate line; next, the gate compensation voltage of each gate line in the display partition is summed to obtain a compensation sum voltage, and average processing is performed based on the compensation sum voltage and the number of gate lines of all gate lines in the display partition to accurately obtain the compensation mean voltage for the gate line break.

[0115] It should be noted that a gate break can be understood as a gate trace with a broken body.

[0116] The preset compensation voltage calculation algorithm expression is: Vcompensation = V11 + (V11-V22) / 2, where Vcompensation represents the gate compensation voltage, V11 represents the first routing end voltage corresponding to the gate routing, and V22 represents the second routing end voltage corresponding to the gate routing.

[0117] Step B20: When the gate disconnection is connected to the first disconnection detection device, the gate disconnection is simultaneously connected to the second disconnection detection device, so that when the logic control module provides a compensation mean voltage to the side of the gate disconnection close to the first disconnection detection device, the logic control module also provides a compensation mean voltage to the side of the gate disconnection close to the second disconnection detection device.

[0118] In this embodiment, when a gate break is detected during row-by-row scanning, the gate driving components on both sides of the gate break are disabled. At this time, the logic control module provides a compensating mean voltage to the first wiring end of the gate break through the first voltage side when the first break detection component connects the gate break to the corresponding thin film transistor. Simultaneously, the logic control module provides a compensating mean voltage to the second wiring end of the gate break through the second voltage side when the second break detection component connects the gate break to the corresponding thin film transistor. This enables immediate repair of the gate break fault caused by the break of the gate wiring body.

[0119] Furthermore, in some feasible embodiments, the above step S20: enabling the logic control module to perform a disconnection repair operation according to the gate disconnection fault, may also include the following implementation steps C10 to C30.

[0120] Step C10: In response to the gate disconnection fault being a failure of the first gate driver, the control logic control module synchronously connects the gate target line to the first disconnection detection element when providing the second gate scanning voltage to the gate target line through the second gate driver, so that the logic control module provides a first voltage that is the same as the second gate scanning voltage to the gate target line via the first disconnection detection element.

[0121] In this embodiment, once the logic control module confirms that the first gate driver has failed in scanning the gate target line row by row, when the second gate driver provides the second gate scanning voltage to the gate target line, the first shift register is synchronously enabled to conduct the electrical connection between the gate target line and the corresponding thin film transistor at the same driving timing as the second gate driver to access the first voltage, which is the same as the second gate scanning voltage, provided by the logic control module to the gate target line via the first voltage side, thereby achieving immediate replacement of the faulty gate driver, so that the repaired display panel can be used normally, thereby significantly improving the display quality of the display panel.

[0122] Step C20: In response to the gate disconnection fault being a failure of the second gate driver, the control logic control module synchronously connects the gate target line to the second disconnection detection element when providing the first gate scanning voltage to the gate target line through the first gate driver, so that the logic control module can provide a second voltage that is the same as the first gate scanning voltage to the gate target line via the second disconnection detection element.

[0123] In this embodiment, once the logic control module confirms that the second gate driver has failed in scanning the gate target line row by row, when the first gate driver provides the first gate scanning voltage to the gate target line, the second shift register is synchronously enabled to conduct the electrical connection between the gate target line and the corresponding thin film transistor under the same driving timing as the first gate driver to access the second voltage, which is the same as the first gate scanning voltage, provided by the logic control module to the gate target line via the second voltage side, thereby achieving immediate replacement of the faulty gate driver, so that the repaired display panel can be used normally, thereby significantly improving the display quality of the display panel.

[0124] Step C30: In response to the gate disconnection fault being a failure of the double-sided gate drive module, the control logic control module simultaneously connects the connection between the gate target trace and the first disconnection detection device when conducting the connection between the gate target trace and the second disconnection detection device, so that when the logic control module provides a repair compensation voltage to the side of the gate target trace close to the first disconnection detection device, it also provides a repair compensation voltage to the side of the gate target trace close to the second disconnection detection device.

[0125] In this embodiment, once the logic control module confirms that the first gate driver and the second gate driver scan the gate target line (ie Figure 7 After the broken line rows shown in the figure fail, specifically, the electrical connections between the two ends of the gate target line and the corresponding gate driving devices are disconnected, and when the first shift register is enabled to conduct the electrical connection between the gate target line and the corresponding thin film transistor under the driving timing corresponding to the gate target line to access the logic control module to provide the repair compensation voltage to the gate target line via the first voltage side (i.e., V1 side), the second shift register is synchronously enabled to conduct the electrical connection between the gate target line and the corresponding thin film transistor under the same driving timing as the first shift register to access the logic control module to provide the same repair compensation voltage to the gate target line via the second voltage side (i.e., V2 side), so as to Figure 7 The same repair compensation voltage is provided on both sides of the broken line to present Figure 7 The display effect of the repaired row is shown, thereby significantly improving the display quality of the display panel.

[0126] In addition, to achieve the above-mentioned purpose, the present application also provides a display panel, which includes a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer is arranged between the array substrate and the color filter substrate, and the array substrate includes the gate wiring repair circuit described in any one of the above items.

[0127] In addition, this application also provides a display device. Figure 8 , Figure 8Schematic diagram of the structure of the display device involved in the embodiment of the present application. The display device of the embodiment of the present application can be a device for locally running the gate wiring repair method.

[0128] like Figure 8 As shown, the display device of the embodiment of the present application may include: the above-mentioned gate trace repair circuit; or, a processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to implement connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit such as a keyboard (Keyboard), and optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0129] Memory 1005 is provided on the display device body and stores programs that, when executed by processor 1001, implement corresponding operations. Memory 1005 is also used to store parameters used by the display device. Memory 1005 can be high-speed RAM or non-volatile memory, such as disk storage. Memory 1005 can also optionally be a storage device independent of processor 1001.

[0130] Those skilled in the art will understand that Figure 8 The display device structure shown in the figure does not constitute a limitation on the display device, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0131] like Figure 8 As shown, the memory 1005 as a storage medium may include an operating system, a network communication module, a user interface module, and a gate wiring repair program.

[0132] exist Figure 8 In the display device shown, the processor 1001 can be used to call the gate wiring repair program stored in the memory 1005 and execute the steps of the gate wiring repair method as described above.

[0133] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or system comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or system. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or system comprising the element.

[0134] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0135] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium such as ROM / RAM, magnetic disk, or optical disk as mentioned above, and includes a number of instructions for enabling a display device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0136] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A gate wiring repair circuit, characterized in that: The gate wiring repair circuit includes: Multiple gate traces; a logic control module, wherein the logic control module is configured to provide a disconnection detection signal; A dual disconnection detection module, wherein one disconnection detection module in the dual disconnection detection module is a first disconnection detection element, and the other disconnection detection module in the dual disconnection detection module is a second disconnection detection element. Two sides of the first disconnection detection element are respectively electrically connected to a first voltage side of the logic control module and a first routing end of each gate routing. Two sides of the second disconnection detection element are respectively electrically connected to a second voltage side of the logic control module and a second routing end of each gate routing. A control end of the first disconnection detection element and a control end of the second disconnection detection element are respectively electrically connected to a detection control end of the logic control module. The dual disconnection detection module is configured to determine a gate disconnection fault according to a preset routing abnormality detection mode and the disconnection detection signal after receiving the disconnection detection signal sent by the logic control module, and send the gate disconnection fault to the logic control module so that the logic control module can enable the logic control module to perform a disconnection repair operation according to the gate disconnection fault; wherein, The first disconnection detection device includes a first shift register and first thin film transistors corresponding to each of the first wiring ends, wherein a gate end of each of the first thin film transistors is electrically connected to a driving side of the first shift register, a first channel end of each of the first thin film transistors is electrically connected to the first voltage side, and each of the first wiring ends is electrically connected to a second channel end of the corresponding first thin film transistor; The second disconnection detection device includes a second shift register and second thin film transistors corresponding to each second wiring end, the gate end of each second thin film transistor is electrically connected to the driving side of the second shift register, the first channel end of each second thin film transistor is electrically connected to the second voltage side, and each second wiring end is electrically connected to the second channel end of the corresponding second thin film transistor.

2. The gate wiring repair circuit according to claim 1, wherein: The gate wiring repair circuit includes a double-sided gate driving module, one of the gate driving modules is a first gate driving component, and the other gate driving module is a second gate driving component; The first gate driver is disposed on a side of the first shift register close to the plurality of gate lines arranged along the row direction, and the second gate driver is disposed on a side of the second shift register close to the plurality of gate lines arranged along the row direction; The first gate driver is electrically connected to the first wiring end of each gate wiring, and the second gate driver is electrically connected to the second wiring end of each gate wiring.

3. A gate wiring repair method, characterized in that: The gate wiring repair method is applied to the gate wiring repair circuit according to any one of claims 1 to 2, and the gate wiring repair method includes: Obtain the disconnection detection signal of the logic control module through the dual disconnection detection module; Determine the gate disconnection fault according to the preset wiring abnormality detection mode and the disconnection detection signal, and enable the logic control module to perform a disconnection repair operation according to the gate disconnection fault; wherein, One of the dual disconnection detection modules is a first disconnection detection element, and the other of the dual disconnection detection modules is a second disconnection detection element. The first disconnection detection device includes a first shift register and first thin film transistors corresponding to each of the first wiring ends, wherein a gate end of each of the first thin film transistors is electrically connected to a driving side of the first shift register, a first channel end of each of the first thin film transistors is electrically connected to the first voltage side, and each of the first wiring ends is electrically connected to a second channel end of the corresponding first thin film transistor; The second disconnection detection device includes a second shift register and second thin film transistors corresponding to each second wiring end, the gate end of each second thin film transistor is electrically connected to the driving side of the second shift register, the first channel end of each second thin film transistor is electrically connected to the second voltage side, and each second wiring end is electrically connected to the second channel end of the corresponding second thin film transistor.

4. The gate wiring repair method according to claim 3, wherein: When the wiring abnormality detection mode is the disconnection detection mode, the step of determining a gate disconnection fault according to the preset wiring abnormality detection mode and the disconnection detection signal includes: In response to the disconnection detection signal, connecting the two sides of the same gate line to the dual disconnection detection module row by row to form a disconnection detection path from the first disconnection detection element to the second disconnection detection element via the gate line; When the first voltage side of the logic control module provides the first voltage to the gate lines row by row, the second voltage side of the logic control module detects whether the first voltage has a voltage value output after passing through the disconnection detection path; If no voltage value is outputted after the first voltage passes through the disconnection detection path, it is determined that the gate disconnection fault is caused by a break in the gate wiring.

5. The gate wiring repair method according to claim 3, wherein: When the wiring abnormality detection mode is the unilateral fault detection mode, the step of determining the gate disconnection fault according to the preset wiring abnormality detection mode and the disconnection detection signal includes: In response to the disconnection detection signal, the first disconnection detection element is enabled to be inoperative when the first gate driver provides a first gate voltage signal to the gate target trace, and the second disconnection detection element is simultaneously enabled to communicate with the gate target trace when the second gate driver is inoperative, so as to form a first unilateral detection path from the first gate driver to the second disconnection detection element via the gate target trace, and to determine a voltage output result of the first gate voltage signal after passing through the first unilateral detection path; When the wiring abnormality detection mode is switched from the single-side fault detection mode to the double-side fault detection mode, a gate disconnection fault is determined according to the double-side fault detection mode and the voltage output result.

6. The gate wiring repair method according to claim 5, wherein: The step of determining a gate disconnection fault based on the bilateral fault detection mode and the voltage output result includes: enabling the second disconnection detection element to be inoperative when the second gate driver provides a second gate voltage signal to the gate target trace, and simultaneously enabling the first disconnection detection element to be connected to the gate target trace when the first gate driver is inoperative, so as to form a second unilateral detection path from the second gate driver to the first disconnection detection element via the gate target trace; If the second gate voltage signal has no voltage output after passing through the second unilateral detection path, and the voltage output result shows that the first gate voltage signal has no voltage output after passing through the first unilateral detection path, it is determined that the gate disconnection fault is a failure of the double-sided gate drive module; If the second gate voltage signal has no voltage output after passing through the second unilateral detection path, and the voltage output result shows that the first gate voltage signal has a voltage output after passing through the first unilateral detection path, then it is determined that the gate disconnection fault is a failure of the second gate driver; If the second gate voltage signal outputs a voltage value after passing through the second unilateral detection path, and the voltage output result shows that the first gate voltage signal has no voltage value output after passing through the first unilateral detection path, it is determined that the gate disconnection fault is a failure of the first gate driver.

7. The gate wiring repair method according to claim 3, wherein: The step of enabling the logic control module to perform a disconnection repair operation according to the gate disconnection fault includes: Controlling the logic control module to determine, in response to the gate line breakage fault being a breakage of the gate line body, a display partition where the gate line breakage is located, and determining a compensation mean voltage of the gate line breakage based on a block compensation voltage corresponding to each gate line in the display partition and the number of gate lines of all the gate lines in the display partition; When the connection between the gate break and the first break detection device is turned on, the connection between the gate break and the second break detection device is turned on simultaneously, so that when the logic control module provides the compensation mean voltage to the side of the gate break close to the first break detection device, the logic control module also provides the compensation mean voltage to the side of the gate break close to the second break detection device.

8. The gate wiring repair method according to claim 3, wherein: The step of enabling the logic control module to perform a disconnection repair operation according to the gate disconnection fault includes: Controlling the logic control module to synchronously connect the gate target line with the first disconnection detection element in response to the gate disconnection fault being a failure of the first gate driver, when providing the second gate scanning voltage to the gate target line through the second gate driver, so that the logic control module provides the gate target line with a first voltage that is the same as the second gate scanning voltage through the first disconnection detection element; or Controlling the logic control module to synchronously connect the gate target line with the second disconnection detection element in response to the gate disconnection fault being a failure of the second gate driver, when providing the first gate scanning voltage to the gate target line through the first gate driver, so that the logic control module can provide the gate target line with a second voltage that is the same as the first gate scanning voltage through the second disconnection detection element; or The logic control module is controlled to respond to the gate disconnection fault as a failure of the double-sided gate drive module, and when the connection between the gate target trace and the first disconnection detection device is connected, the connection between the gate target trace and the second disconnection detection device is simultaneously connected, so that when the logic control module provides a repair compensation voltage to the side of the gate target trace close to the first disconnection detection device, the repair compensation voltage is simultaneously provided to the side of the gate target trace close to the second disconnection detection device.

9. A display panel, characterized in that: The display panel includes a color filter substrate, a liquid crystal layer and an array substrate, wherein the liquid crystal layer is provided between the array substrate and the color filter substrate, and the array substrate includes the gate wiring repair circuit according to any one of claims 1 to 2.

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