Flash memory chip testing method

Abstract

The invention discloses a flash memory chip test method. The method comprises the following steps: providing a plurality of flash memory chips; the method comprises the following steps: carrying out dynamic power consumption test when first erasing operation is carried out on a plurality of flash memory chips before a conventional function test to obtain a first power consumption value corresponding to each flash memory chip; performing a dynamic power consumption test when a second erasure operation is performed on the flash memory chip passing the conventional function test to obtain a second power consumption value corresponding to each flash memory chip; calculating a power consumption change value of each flash memory chip according to the first power consumption value and the second power consumption value; performing outlier statistics according to the power consumption change values of the plurality of flash memory chips, and determining outlier flash memory chips; and removing the outlier flash memory chips. According to the scheme, the reliability of the flash memory chip can be effectively improved, and the risk that the flash memory chip with potential problems, especially electric leakage of the charge pump, flows into the terminal market and further causes terminal failure is reduced.

Description

Technical Field

[0001] This application relates to the technical field of flash memory testing, and particularly to a method for testing flash memory chips. Background Art

[0002] As an integrated circuit storage device, flash memory is widely used in electronic products such as laptop computers, mobile phones, and digital music players because it has the function of electrically erasable and writable storage of information, and the stored information will not be lost after power-off.

[0003] In the power supply scheme design, multiple charge pumps are usually designed on the flash memory chip to provide corresponding voltages for each storage unit in the flash memory. When the charge pump operates at high frequency, some process defects will cause some devices in the charge pump to fail during frequent use, and then cause device damage, such as burnout of high-voltage NMOS and leakage in the flash memory area. In the existing flash memory yield testing, it is difficult to simulate the situation of frequent use of the charge pump at the terminal by conventional flash memory function tests such as fine-tuning (trim) of the conventional erase voltage VEE and programming voltage VEP. Once a chip with such defects is shipped as a normal sample and put into the terminal market, during the continuous use of the terminal user, it may cause the charge pump to fail quickly, and then become a terminal reliability failure event. Summary of the Invention

[0004] Embodiments of this application provide a method for testing flash memory chips to eliminate as many flash memories with some process defects as possible during the yield testing stage and ensure the quality of the flash memories flowing into the hands of end users.

[0005] To this end, embodiments of this application provide the following technical solutions:

[0006] Embodiments of this application provide a method for testing flash memory chips, the method comprising:

[0007] Providing a plurality of flash memory chips;

[0008] Performing dynamic power consumption testing on the plurality of flash memory chips during a first erase operation before conventional function testing to obtain a first power consumption value corresponding to each flash memory chip;

[0009] Performing dynamic power consumption testing on the flash memory chips that pass the conventional function testing during a second erase operation to obtain a second power consumption value corresponding to each flash memory chip;

[0010] Calculating a power consumption change value of each flash memory chip according to the first power consumption value and the second power consumption value;

[0011] Performing outlier statistics according to the power consumption change values of the plurality of flash memory chips to determine outlier flash memory chips;

[0012] Eliminating the outlier flash memory chips.

[0013] Optionally, the method further includes:

[0014] Performing DC characteristic and parameter trimming tests on the multiple flash memory chips;

[0015] After passing the tests, performing a dynamic power consumption test when performing a first erasing operation on the multiple flash memory chips before the regular function test.

[0016] Optionally, the regular function test includes any one or more of the following tests: read test, write test, erase test, logic test, performance test, programming, and interference test.

[0017] Optionally, performing a dynamic power consumption test when erasing the multiple flash memory chips, and obtaining the power consumption values corresponding to each flash memory chip includes:

[0018] Connecting the power supply terminal of the flash memory chip to the working power supply, applying an erase voltage on all word lines and maintaining it for a certain period of time, and measuring the current flowing through the power supply terminal;

[0019] Calculating the power consumption value of the flash memory chip according to the voltage of the working power supply and the measured current.

[0020] Optionally, the erase voltages during the dynamic power consumption tests for two erasing operations are the same.

[0021] Optionally, the outlier statistics based on the power consumption change values of the multiple flash memory chips to determine the outlier flash memory chips includes:

[0022] Calculating the mean and standard deviation of the power consumption change values of the multiple flash memory chips;

[0023] Determining the outlier flash memory chips according to the mean and standard deviation.

[0024] Optionally, the method further includes:

[0025] Performing outlier statistics based on the first power consumption values of the multiple flash memory chips, determining and removing the outlier flash memory chips;

[0026] Performing a regular function test on the remaining flash memory chips.

[0027] Optionally, the method further includes: performing outlier statistics based on the second power consumption values of the multiple flash memory chips to determine the outlier flash memory chips.

[0028] Optionally, the flash memory chip includes a memory cell array, the memory cell array includes a plurality of memory cells arranged in a matrix, the memory cells are split-gate flash memory cells; each of the memory cells includes a floating gate and a bit line; the memory cells in each column share the bit line.

[0029] Optionally, the split-gate flash memory cell includes two storage structures that share a common source region and are symmetrically distributed; each storage structure includes a drain region and the source region in a substrate, the drain region is connected to the bit line, a floating gate and a word line are formed on the substrate between the source region and the drain region, a floating gate tip is formed on one side of the floating gate close to the word line, and a tunneling oxide layer is formed between the floating gate and the word line.

[0030] In the flash memory chip testing method provided by the embodiments of the present application, during the CP test, by performing dynamic power consumption tests on multiple flash memory chips before and after a conventional functional test respectively when erasing operations are carried out, calculating the power consumption change value of each flash memory chip based on the power consumption values obtained from the two tests, performing outlier statistics according to the power consumption change value, and screening out and removing the flash memory chips with outlier power consumption changes in the yield test stage, the reliability of the flash memory chips is effectively improved, and the risk that flash memory chips with potential problems, especially charge pump leakage, flow into the terminal market and cause terminal failures is greatly reduced.

[0031] Furthermore, outlier statistics can also be performed by combining the power consumption values of each flash memory chip obtained from any one or both of the tests to determine the outlier flash memory chips, so as to fully remove the outlier flash memory chips with potential problems and ensure the quality of the flash memory chips flowing into the market. Description of the Drawings

[0032] Figure 1 is a flowchart of a flash memory testing method provided by an embodiment of the present application;

[0033] Figure 2 is a schematic structural diagram of a flash memory in an embodiment of the present application;

[0034] Figure 3 is a schematic principle diagram of a flash memory in an embodiment of the present application;

[0035] Figure 4 is another flowchart of a flash memory testing method provided by an embodiment of the present application;

[0036] Figure 5 is another flowchart of a flash memory testing method provided by an embodiment of the present application. Detailed Embodiments

[0037] To make the above objects, features, and beneficial effects of the present application more obvious and understandable, the following detailed description of the specific embodiments of the present application is provided in conjunction with the accompanying drawings.

[0038] It should be noted that unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the description of this application in this specification are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0039] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0040] Through the statistical analysis of some terminal failure samples of flash memory chips applied, it can be known that there are usually the following two commonalities for terminal failures caused by process defects:

[0041] (1) The charge pump of the flash memory chip operates abnormally;

[0042] (2) Some data during flash memory erasure and programming show obvious differences from normal flash memory chips, and this phenomenon is more obvious during flash memory erasure.

[0043] In view of the above problems and based on the statistical analysis of terminal failure samples, the embodiments of this application provide a flash memory testing method. In the CP (Chip Probing) testing stage, by performing dynamic power consumption testing on multiple flash memory chips during erasure operations before and after conventional functional testing respectively, calculating the power consumption change value of each flash memory chip based on the power consumption values obtained from the two tests, and performing outlier statistical analysis according to the power consumption change value to screen out outlier samples. Although the anomalies of outlier samples are not all caused by the failure of the charge pump, in this way, flash memory chips with potential risks caused by various process defects can be screened out to a certain extent to avoid shipping them as normal samples.

[0044] CP testing is for uncut wafers and requires probes to contact the test pads on the wafer, and can test single or multiple Dies (chips) on the wafer at a time. CP testing generally includes three stages of testing, namely: CP1 tests the basic storage read and write functions and writes certain content into the storage chip; then after the wafer is baked at high temperature, CP2 testing is performed to detect whether the previously written data can be retained; finally, logical function testing is performed on the MCU (main control unit) part.

[0045] The main test processes of CP1 are as follows:

[0046] (1) DC parameter and trim testing:

[0047] DC parameter testing mainly includes: short circuit, open circuit, maximum current, leakage current, output drive current, turn-on level testing, etc. For example, the open / short test is mainly used to detect whether there is a short circuit between the pins of the chip and whether there is a missing bonding wire during chip packaging; the leakage current test is to detect the leakage current of the input pins of the chip when a voltage is applied.

[0048] Trim is the process of adjusting some internal circuit parameters during chip testing. These parameters can be reference voltage, bias current, bandgap voltage, and / or oscillator circuit frequency, etc. The trim test can measure the values of some parameters in the circuit. If the parameter values deviate from the target values, the parameters can also be corrected and adjusted to meet the requirements of the parameter specifications. By trimming the parameters through trim, the yield of the chip can be greatly improved. The trimming of parameters in the chip can be achieved by increasing or decreasing the resistance values of the corresponding resistor networks.

[0049] (2)Flash conventional function testing:

[0050] It mainly includes but is not limited to: read testing, write testing, erase testing, logic testing, performance testing, programming, and interference testing, etc. For example, the erase / read test is mainly used to screen out chips that cannot complete basic erase, programming, and read / write operations. During the test, the chip performs erase and programming operations on a single sector or the entire flash memory array at different operating voltages, and then performs a read operation on the chip to determine whether it can pass the test.

[0051] (3)Write a flag to NVR1 and erase the chip

[0052] During this process, all sectors will be erased.

[0053] CP2 testing is mainly to perform functional testing on the baked chips to detect their data retention ability. Usually, the CP2 testing process mainly includes the following steps:

[0054] (1)Open / short test and leakage test

[0055] Similar to the corresponding steps in CP1 testing, the open / short test is mainly used to detect whether there is a short circuit between the pins of the chip and whether there is a missing bonding wire during chip packaging; the leakage current test is to detect the leakage current of the input pins of the chip when a voltage is applied.

[0056] (2)NVR1 verification

[0057] It is used to verify whether the flag written to NVR1 in CP1 testing is correct.

[0058] (3)Data retention ability and endurance test

[0059] Data retention ability refers to the ability of a storage cell to maintain its programmed state within an acceptable time period.

[0060] Endurance test is to characterize the maximum number of program / erase (P / E) cycles that a storage cell can withstand without failure.

[0061] In the flash memory test method provided by the embodiments of the present application, two dynamic power consumption tests are added during the CP1 test phase when erasing the flash memory chip, namely before and after the conventional function test. According to the power consumption changes in the two tests, outlier flash memory chips are screened and excluded. It should be noted that the specific items and test methods of the conventional function test may vary depending on the type of flash memory chip and the manufacturer, and the embodiments of the present application do not limit this.

[0062] As Figure 1 shown, it is a flowchart of a flash memory test method provided by the embodiments of the present application, including the following steps:

[0063] Step 101, provide a plurality of flash memory chips.

[0064] The flash memory chip includes a storage cell array, and the storage cell array includes a plurality of storage cells arranged in a matrix. The storage cell can be a split-gate flash memory cell or a storage cell of other structures involving a charge pump, and the embodiments of the present application do not limit this. Each of the storage cells includes a floating gate and a bit line.

[0065] The flash memory chip can be of NAND type (storage cells connected in series) or NOR type (storage cells connected in parallel, that is, the storage cells in each column are connected to the same bit line), and the embodiments of the present application do not limit this.

[0066] Taking the split-gate flash memory cell as an example below, its structure and principle will be briefly described. At the same time, refer to Figure 2 and Figure 3 , where Figure 2 is a schematic structural diagram of a flash memory in the embodiments of the present application, Figure 3 is a schematic principle diagram of a flash memory in the embodiments of the present application.

[0067] The flash memory includes a memory cell array. The memory cell array includes a plurality of memory cells A arranged in a matrix, and the memory cells are split-gate flash memory cells; each memory cell includes a floating gate 11 and a bit line 13; the memory cells in each column share one bit line 13. A plurality of split-gate flash memory cells are formed side by side on a semiconductor substrate. The material of the semiconductor substrate can be silicon, germanium, silicon-germanium, silicon carbide, etc., or it can be silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or it can also be other materials, such as group III-V compounds like gallium arsenide.

[0068] In this embodiment, a split-gate flash memory cell includes two memory structures that share a source region 14 and are symmetrically distributed. Each split-gate flash memory cell includes a drain region 15 formed in the semiconductor substrate, a source region 14, and a source line (not shown) formed on the semiconductor substrate and connected to the source region 14, and the source line is located above the source region 14. Among them, the drain region 15 is connected to the bit line 13, a word line 21 is formed between the source region 14 and the drain region 15, and two word lines 21 of the same split-gate flash memory cell are formed on both sides of the corresponding source line. A floating gate oxide layer, a floating gate 11, and sidewalls are formed on the semiconductor substrate between the source line and the word line 21, and a tunneling oxide layer is formed between the floating gate 11 and the word line 21. The materials of the floating gate 11, the word line 21, and the source line can all be polysilicon. A floating gate tip is formed on one side of the floating gate 11 close to the word line 21. The left memory structure and the right memory structure are symmetrically distributed and share the source line. In this embodiment, the source region 14 and the drain region 15 are both, for example, N-type doped.

[0069] When programming this split-gate flash memory cell, the word line 21 serves as a control gate. A high voltage is applied to the source region 14, a voltage that can open the channel is applied to the word line 21, and a constant current is injected through the drain region 15. And the source region 14 is at a high potential. Under the action of the high potential, on the one hand, hot electrons are generated in the channel, and on the other hand, the high potential is coupled to the floating gate 11, and the floating gate 11 generates a coupling voltage. Under the action of the coupling voltage, electrons are injected from the channel into the floating gate 11, thereby realizing programming, and programming is also called the write "0" operation.

[0070] Step 102, perform a dynamic power consumption test on the plurality of flash memory chips during the first erasing operation before the conventional function test, and obtain a first power consumption value corresponding to each flash memory chip.

[0071] It should be noted that the plurality of flash memory chips can be flash memory chips that have passed the DC parameter and trim tests.

[0072] Specifically, connect the power supply terminals of each flash memory chip to the working power supply, apply an erase voltage to all word lines and maintain it for a certain period of time, and measure the current flowing through the power supply terminals; calculate the power consumption values of each flash memory chip based on the voltage of the working power supply and the measured current.

[0073] In a conventional CP test, the normal erase voltage VEE applied to the word lines is, for example, 12V.

[0074] Meanwhile, referring to Figure 2 and Figure 3 When erasing the split-gate flash memory cell, apply an erase voltage VEE to all word lines 21. Through the principle of tip discharge at the floating gate tip, the channel voltage of the tunneling effect is reduced, enabling electrons to pass through the tunneling oxide layer from the tip of the floating gate 11 into the word line 21. After the storage cell is erased, the stored bit of the storage cell is in the "1" state, that is, all the storage cells of the flash memory are erased and set to "1".

[0075] Since the duration of a complete erase process is very short, in order to obtain an accurate current measurement value, after applying the erase voltage, it can be maintained for a period of time (such as 5 - 10 ms) to make the current flowing through the power supply terminal reach stability.

[0076] Step 103: Conduct a dynamic power consumption test during the second erase operation on the flash memory chips that have passed the conventional function test, and obtain the second power consumption values corresponding to each flash memory chip.

[0077] It should be noted that the dynamic power consumption test during the first erase operation and the dynamic power consumption test during the second erase operation only represent the dynamic power consumption tests during two different stages of the erase operation. The specific implementation methods of the two test processes are the same, and the erase voltages during the two erase operations can be the same.

[0078] In addition, the dynamic power consumption test during the second erase operation can be performed only on the flash memory chips that have passed the conventional function test. That is to say, the flash memory chips that have not passed the conventional function test can be directly excluded at this stage and no longer undergo the dynamic power consumption test during the second erase operation.

[0079] Step 104: Calculate the power consumption change values of each flash memory chip based on the first power consumption value and the second power consumption value.

[0080] It should be noted that since the flash memory chips that have not passed the conventional test have been excluded, in step 104, the flash memory chips for which the power consumption change values need to be calculated are only those that have passed the conventional test. The measurement values (i.e., the first power consumption values) of the flash memory chips that have not passed the conventional test can be directly discarded.

[0081] Step 105: Perform outlier statistics based on the power consumption change values of each flash memory chip to determine outlier flash memory chips.

[0082] In some embodiments, the outlier statistics for the power consumption change values can adopt the n-sigma principle. The n-sigma principle is based on the assumption of normal distribution, calculates the deviation values of data points from the mean, and classifies the data points into two categories: outliers and normal values according to the magnitude of the deviation.

[0083] The process of determining outlier flash memory chips is as follows: First, calculate the mean and standard deviation of the power consumption change values of the multiple flash memory chips; then determine the outlier flash memory chips according to the mean and standard deviation. Specifically, calculate the deviation value of each power consumption change value from the mean. For the power consumption change value whose deviation value is greater than n (n can take values such as 3, 5, 9, etc.) times the standard deviation, it is determined as an outlier, and the flash memory chip corresponding to this outlier is the outlier flash memory chip.

[0084] In some embodiments, other outlier statistical algorithms can also be used to determine outlier flash memory chips, such as: Dixon algorithm, Grubbs algorithm, box plot, Mahalanobis distance, Local Outlier Factor (LOF) algorithm, etc. The embodiments of this application do not limit this.

[0085] Step 106: Remove the outlier flash memory chips.

[0086] The flash memory chip testing method provided by the embodiments of this application, during the CP testing process, through dynamically testing the power consumption during the erase operation of multiple flash memory chips before and after the conventional functional testing respectively to simulate the use of flash memory chips on terminal products, calculates the power consumption change values of each flash memory chip based on the power consumption values obtained from the two tests, performs outlier statistics according to the power consumption change values, screens out and removes the flash memory chips with outlier power consumption changes during the yield testing stage, effectively improves the reliability of flash memory chips, greatly reduces the risk that flash memory chips with potential problems, especially charge pump leakage, flow into the terminal market and cause terminal failures.

[0087] As Figure 4 shown, it is another flowchart of the flash memory testing method provided by the embodiments of this application, including the following steps:

[0088] Step 401: Provide multiple flash memory chips.

[0089] The multiple flash memory chips can be flash memory chips that have passed the DC parameter and trim tests.

[0090] Step 402: Perform dynamic power consumption testing on the multiple flash memory chips during the first erase operation to obtain the first power consumption value corresponding to each flash memory chip.

[0091] Step 403: Perform outlier statistics based on the first power consumption values of the multiple flash memory chips, and determine and eliminate the outlier flash memory chips.

[0092] In some embodiments, the outlier statistics for the power consumption values can adopt the 3-sigma principle. The 3-sigma principle is based on the normal distribution hypothesis. It calculates the deviation values of the data points from the mean, and classifies the data points into two categories: outliers and normal values according to the magnitude of the deviation.

[0093] The process of determining the outlier flash memory chips is as follows: First, calculate the mean and standard deviation of the power consumption values of the multiple flash memory chips; then determine the outlier flash memory chips according to the mean and the standard deviation. Specifically, calculate the deviation value of each power consumption value from the mean. For the power consumption value whose deviation value is greater than 3 times the standard deviation, it is determined as an outlier, and the flash memory chip corresponding to this power consumption value is the outlier flash memory chip.

[0094] In some embodiments, other outlier statistical algorithms can also be used to determine the outlier flash memory chips, such as: Dixon algorithm, Grubbs algorithm, box plot, Mahalanobis distance, Local Outlier Factor (LOF) algorithm, etc. The embodiments of this application do not make limitations in this regard.

[0095] Step 404: Perform conventional function tests on the remaining flash memory chips.

[0096] Step 405: Perform dynamic power consumption tests on the flash memory chips after passing the conventional function tests during the second erasure operation, and obtain the second power consumption values corresponding to the respective flash memory chips.

[0097] Step 406: Calculate the power consumption change values of the respective flash memory chips according to the first power consumption values and the second power consumption values.

[0098] Similarly, since the outlier flash memory chips determined by the first power consumption values and the flash memory chips that do not pass the conventional tests have been eliminated, the flash memory chips for which the power consumption change values need to be calculated in Step 406 are only the remaining flash memory chips after screening. The number of the remaining flash memory chips after screening is less than or equal to the number of flash memory chips provided in Step 401.

[0099] Step 407: Perform outlier statistics based on the power consumption change values of the multiple flash memory chips, and determine the outlier flash memory chips.

[0100] For the specific method of determining the outlier flash memory chips according to the power consumption change values of the flash memory chips, reference can be made to the description of Step 105 in the foregoing embodiments shown Figure 1 which will not be elaborated herein.

[0101] Step 408: Eliminate the outlier flash memory chips.

[0102] In some embodiments, outlier flash memory chips can be determined respectively according to the first power consumption values of each flash memory chip and the power consumption change values before and after two consecutive times, to obtain respective outlier flash memory chip sets, and then the union of the two outlier flash memory chip sets is taken to obtain the final outlier flash memory chips, and these finally determined outlier flash memory chips are excluded to avoid misjudgment caused by test errors.

[0103] As Figure 5 shown, it is another flowchart of the flash memory test method provided by the embodiments of the present application, including the following steps:

[0104] Step 501, provide a plurality of flash memory chips.

[0105] The plurality of flash memory chips may be flash memory chips that have passed the DC parameter and trim tests.

[0106] Step 502, perform dynamic power consumption testing during the first erasing operation on the plurality of flash memory chips to obtain the first power consumption value corresponding to each flash memory chip.

[0107] Step 503, perform a conventional function test on the plurality of flash memory chips.

[0108] Step 504, perform dynamic power consumption testing during the second erasing operation on the flash memory chips that have passed the conventional function test to obtain the second power consumption value corresponding to each flash memory chip.

[0109] Step 505, perform outlier statistics according to the second power consumption values of the plurality of flash memory chips to determine outlier flash memory chips.

[0110] In some embodiments, the outlier statistics for the power consumption values can adopt the 3-sigma principle. The 3-sigma principle is based on the normal distribution assumption, calculates the deviation value of the data point from the mean value, and classifies the data points into two categories: outliers and normal values according to the magnitude of the deviation.

[0111] The process of determining the outlier flash memory chips is as follows: First, calculate the mean value and standard deviation of the power consumption values of the plurality of flash memory chips; then determine the outlier flash memory chips according to the mean value and standard deviation. Specifically, calculate the deviation value of each power consumption value from the mean value. For the power consumption value whose deviation value is greater than 3 times the standard deviation, it is determined as an outlier, and the flash memory chip corresponding to this power consumption value is the outlier flash memory chip.

[0112] In some embodiments, other outlier statistical algorithms can also be used to determine the outlier flash memory chips, such as: Dixon algorithm, Grubbs algorithm, box plot, Mahalanobis distance, local outlier factor (LOF) algorithm, etc. The embodiments of the present application do not make any limitations in this regard.

[0113] Step 506, calculate the power consumption change value of each flash memory chip according to the first power consumption value and the second power consumption value.

[0114] Step 507: Perform outlier statistics based on the power consumption change values of the multiple flash memory chips to determine outlier flash memory chips.

[0115] For the specific method of determining outlier flash memory chips based on the power consumption change values of the flash memory chips, reference can be made to the description of step 105 in the foregoing embodiments shown, which will not be elaborated herein. Figure 1 shown in the embodiments for step 105, and will not be repeated here.

[0116] Step 508: Remove the outlier flash memory chips.

[0117] In some embodiments, outlier flash memory chips can be determined respectively according to the second power consumption values of the flash memory chips and the power consumption change values of the two previous times, to obtain respective corresponding outlier flash memory chip sets, and then the union of the two outlier flash memory chip sets is taken to obtain the final outlier flash memory chips, and these finally determined outlier flash memory chips are removed to avoid misjudgment caused by test errors.

[0118] In some other embodiments, outlier flash memory chips can also be first determined and removed according to the second power consumption values, and then outlier flash memory chips can be determined and removed according to the power consumption change values of the two previous times.

[0119] In some other embodiments, outlier flash memory chips can also be determined and removed in sequence according to the first power consumption value, the second power consumption value, and the power consumption change value.

[0120] In some other embodiments, outlier flash memory chip sets corresponding to the first power consumption value, the second power consumption value, and the power consumption change value can be determined respectively, and the union of the outlier flash memory chip sets determined by these three methods is taken to obtain the final outlier flash memory chips, and these finally determined outlier flash memory chips are removed to avoid misjudgment caused by test errors.

[0121] Of course, there can be other deformation methods for the flash memory chip testing method of the embodiments of the present application, which will not be exemplified one by one herein.

[0122] By using the flash memory chip testing method of the embodiments of the present application, outlier flash memory chips with potential problems can be removed through power consumption testing of flash memory chips in the yield testing stage, the reliability of the flash memory chips can be improved, and the quality of the flash memory chips flowing into the market can be effectively guaranteed.

[0123] It should be understood that the term "and / or" in this article is merely a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0124] In the embodiments of the present application, "a plurality of" means two or more.

[0125] In the embodiments of the present application, the first, second, etc. descriptions are only for the purpose of illustration and distinguishing the described objects, without any order, nor do they represent special limitations on the number of devices in the embodiments of the present application, and cannot constitute any limitation to the embodiments of the present application.

[0126] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions. The foregoing program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps including the above method embodiments: the foregoing storage medium may include: various media such as ROM, RAM, magnetic disk, or optical disk that can store program codes.

[0127] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A flash memory chip testing method, characterized in that: The method comprises: Providing multiple flash memory chips; Performing a dynamic power consumption test on the plurality of flash memory chips during a first erasing operation before a conventional functional test, to obtain a first power consumption value corresponding to each flash memory chip; Performing a dynamic power consumption test during a second erasing operation on the flash memory chips that have passed the conventional functional test, and obtaining a second power consumption value corresponding to each flash memory chip; Calculating a power consumption change value of each flash memory chip according to the first power consumption value and the second power consumption value; Perform outlier statistics according to the power consumption change values ​​of the plurality of flash memory chips to determine the outlier flash memory chip; The outlier flash memory chip is removed.

2. The flash memory chip testing method according to claim 1, characterized in that: The method further comprises: Performing DC characteristic and parameter adjustment tests on the plurality of flash memory chips; After the test is passed, a dynamic power consumption test is performed when the first erasing operation is performed on the plurality of flash memory chips before a conventional functional test.

3. The flash memory chip testing method according to claim 1, characterized in that: The conventional functional test includes any one or more of the following tests: read test, write test, erase test, logic test, performance test, programming and interference test.

4. The flash memory chip testing method according to claim 1, characterized in that: The dynamic power consumption test of the multiple flash memory chips during the erasing operation is performed to obtain the power consumption value of each flash memory chip, including: Connecting the power supply terminal of the flash memory chip to a working power supply, applying an erase voltage to all word lines for a certain period of time, and measuring the current flowing through the power supply terminal; The power consumption value of the flash memory chip is calculated based on the voltage of the working power supply and the measured current.

5. The flash memory chip testing method according to claim 1, characterized in that: The erase voltage during the dynamic power consumption test during the two erase operations is the same.

6. The flash memory chip testing method according to claim 1, characterized in that: The performing outlier statistics according to the power consumption change values ​​of the plurality of flash memory chips to determine the outlier flash memory chip comprises: Calculating the mean and standard deviation of the power consumption variation values ​​of the plurality of flash memory chips; Outlier flash memory chips are determined based on the mean and the standard deviation.

7. The flash memory chip testing method according to claim 1, characterized in that: The method further comprises: Perform outlier statistics according to the first power consumption values ​​of the plurality of flash memory chips, and determine and eliminate outlier flash memory chips; Perform routine functional tests on the remaining flash chips.

8. The flash memory chip testing method according to claim 1, characterized in that: The method further comprises: Outlier statistics are performed according to the second power consumption values ​​of the plurality of flash memory chips to determine the outlier flash memory chip.

9. The flash memory chip testing method according to any one of claims 1 to 8, characterized in that: The flash memory chip comprises a memory cell array, which comprises a plurality of memory cells arranged in a matrix, and the memory cells are split-gate flash memory cells; each of the memory cells comprises a floating gate and a bit line; and the memory cells in each column share the bit line.

10. The flash memory chip testing method according to claim 9, characterized in that: The split-gate flash memory unit includes two storage structures that share a source region and are symmetrically distributed; the storage structure includes a drain region and the source region located in a substrate, the drain region is connected to the bit line, the floating gate and the word line are formed on the substrate between the source region and the drain region, a floating gate tip is formed on the side of the floating gate close to the word line, and a tunneling oxide layer is formed between the floating gate and the word line.

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