Semiconductor processing method and semiconductor structure

Abstract

The invention discloses a semiconductor processing method. The method comprises the following steps: forming a small-caliber deep groove and a photoetching process alignment structure on a substrate from a first surface of the substrate to the interior of the substrate; depositing a functional film layer in the small-caliber deep groove and the photoetching process alignment structure until the small-caliber deep groove is completely filled; depositing a first fill material to the substrate including the voids of the lithographic process alignment structure; and removing the redundant first filling material outside the alignment structure of the photoetching process. According to the method provided by the invention, the deep groove is filled with the filling material such as silicon dioxide, so that the photoresist can be prevented from entering the deep groove in the subsequent photoetching process. The invention also discloses a corresponding semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor processing technology, and particularly to post-etching of small-diameter deep trench filling. Background Art

[0002] Currently, the width of the alignment structure in the lithography process is approximately in the range of 1 um to 8 um. Therefore, for small-diameter deep trenches filled by a high-step coverage filling process, such as small-diameter deep trenches with a width range of 0.1 um to 1 um, when the deep trench structure is filled, there is still a relatively large range of voids in the alignment structure. Therefore, in the subsequent lithography process, the photoresist may enter the voids of the alignment structure after coating, and stress will be generated in the alignment structure during the baking stage, resulting in deformation, and thus large size deviations will occur in each subsequent lithography process.

[0003] To solve the above problems, a pre-alignment mark process section (Zero Mark Loop) is added before the small-diameter deep trench process section. This process section includes steps such as deposition of a thin film, lithography and etching of alignment marks, and removal of photoresist. After that, all lithography processes, including the deep trench process section, are aligned with this alignment mark. This method requires adding a process section and an additional mask, thus increasing the cost of the process. Summary of the Invention

[0004] The purpose of this application is to provide an optimized semiconductor processing method.

[0005] For this purpose, this application provides a semiconductor processing method, which includes the steps of: forming a small-diameter deep groove and a lithography process alignment structure from the first surface of the substrate into the substrate on the substrate; depositing a functional film layer in the small-diameter deep groove and the lithography process alignment structure until the small-diameter deep groove is completely filled; depositing a first filling material on the substrate including the voids of the lithography process alignment structure; and removing the excess first filling material outside the lithography process alignment structure.

[0006] In some embodiments, the first filling material is a high-hardness insulating material, including but not limited to silicon dioxide, phosphosilicate glass, or borophosphosilicate glass.

[0007] In some embodiments, a high aspect ratio filling process is used to fill the voids in the lithography process alignment structure, forming a first part of the first filling material in the lithography process alignment structure and a second part of the first filling material on the first surface outside the lithography process alignment structure.

[0008] In some embodiments, the small-diameter deep groove and the lithography process alignment structure are etched by a dry etching method.

[0009] In some embodiments, forming a small-diameter deep groove and a lithography process alignment structure from the first surface of the substrate into the substrate on the substrate includes depositing a hard mask on the substrate; depositing a photoresist on the hard mask, and forming a pattern of the small-diameter deep groove and the lithography process alignment structure on the photoresist using a lithography process; forming a pattern of the small-diameter deep groove and the lithography process alignment structure on the hard mask using a dry etching process based on the pattern of the small-diameter deep groove and the lithography process alignment structure formed on the photoresist; etching the small-diameter deep groove and the lithography process alignment structure on the substrate based on the pattern of the small-diameter deep groove and the lithography process alignment structure formed on the hard mask.

[0010] In some embodiments, the width of the lithography process alignment structure is much larger than the width of the small-diameter deep groove.

[0011] In some embodiments, the width of the small-diameter deep groove is 0.1 to 1 μm, and the width of the lithography process alignment structure is 1 to 8 μm.

[0012] In some embodiments, a functional film layer is deposited in the small-diameter deep groove and the lithography process alignment structure using a high-step coverage filling method until the small-diameter deep groove is completely filled.

[0013] In some embodiments, the high-step coverage filling method includes thermal oxidation, chemical vapor deposition, or atomic layer deposition.

[0014] In some embodiments, a hard mask is deposited on the substrate using chemical vapor deposition.

[0015] In some embodiments, a small-diameter deep groove and a lithography process alignment structure are etched on a silicon substrate using deep reactive ion etching.

[0016] In some embodiments, a first filling material is polished flat to the surface of the last filled functional film layer using chemical mechanical polishing.

[0017] Some other embodiments of the present application provide a semiconductor structure processed according to any one of the above semiconductor processing methods.

[0018] A semiconductor structure, characterized in that it is made according to any one of the semiconductor processing methods in claims 1 to 12.

[0019] Some other embodiments of the present application provide a semiconductor structure in which the small-diameter deep groove on the substrate is completely filled with a deposited functional film layer, and a first filling material is filled in the micron-level voids of the lithography process alignment structure.

[0020] In some embodiments, the first filling material is silica, phosphosilicate glass, or borophosphosilicate glass.

[0021] In some embodiments, the functional film layer is simultaneously deposited on the first surface of the substrate.

[0022] The beneficial effects of the present application are as follows: By filling the deep trench with a filling material such as silica, it is possible to prevent photoresist from entering the interior of the deep trench during subsequent lithography processes. In some embodiments, the use of the HARP process can be compatible with the STI filling process, eliminating the need for an additional alignment mark process section and reducing the process cost based on the previous process. Description of the Drawings

[0023] Figure 1 is a schematic flow diagram of a semiconductor processing method according to an embodiment of the present application.

[0024] Figure 2A is a schematic diagram of the first process processing result of a semiconductor processing method according to some embodiments of the present application.

[0025] Figure 2B is a schematic diagram of the second process processing result of a semiconductor processing method according to some embodiments of the present application.

[0026] Figure 2C is a schematic diagram of the third process processing result of a semiconductor processing method according to some embodiments of the present application.

[0027] Figure 2D is a schematic diagram of the fourth process processing result of a semiconductor processing method according to some embodiments of the present application.

[0028] Figure 2E is a schematic diagram of the fifth process processing result of a semiconductor processing method according to some embodiments of the present application.

[0029] Figure 2F is a schematic diagram of the sixth process processing result of a semiconductor processing method according to some embodiments of the present application.

[0030] Figure 3A is a schematic three-dimensional structure diagram of the third main processing result of a semiconductor structure according to some embodiments of the present application.

[0031] Figure 3B is a schematic three-dimensional structure diagram of the fourth main processing result of a semiconductor structure according to some embodiments of the present application.

[0032] Figure 3C is a schematic three-dimensional structure diagram of the fifth main processing result of a semiconductor structure according to some embodiments of the present application.

[0033] Figure 3D It is a three-dimensional structural schematic diagram of the sixth main processing result of a semiconductor structure according to some embodiments of the present application. Detailed implementation manners

[0034] Next, in conjunction with the accompanying drawings, the technical solutions in the present application will be clearly and completely described. Obviously, the described embodiments are part of the embodiments of the present application, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope protected by the present application.

[0035] As Figure 1 shown, a semiconductor manufacturing method according to an embodiment of the present application includes: forming a small-diameter deep groove 120 and a lithography process alignment structure 110 from the first surface 101 of the substrate into the substrate 100 on the substrate 100, step S104; depositing a functional film layer in the small-diameter deep groove and the lithography process alignment structure until the small-diameter deep groove is completely filled, step S105; filling a first filling material in the micron-level voids of the lithography process alignment structure, step S106; and removing the excess first filling material on the first surface of the substrate, step S107.

[0036] This method is particularly suitable for the process of etching after filling a small-diameter deep groove.

[0037] Next, the processes involved in the method of the present application will be described in detail, including the description of a specific exemplary method for forming a small-diameter deep groove 120 and a lithography process alignment structure 110 from the first surface 101 of the substrate into the substrate 100 on the substrate 100.

[0038] First, deposit a hard mask 170 on a substrate, such as a silicon substrate 100, using, for example, chemical vapor deposition, step S101; the material of the hard mask can be: quartz, silicate ceramics, metals such as chromium, nickel, molybdenum, polymer materials such as polymethyl methacrylate (PMMA), and silicon carbide, etc.

[0039] Deposit a photoresist 180 on the hard mask 170, and form a pattern of a small-diameter deep groove 181 and a lithography process alignment structure 182 on the photoresist 180 using a lithography process, that is, step S102. An exemplary processing result of the semiconductor structure at this time is as Figure 2A shown.

[0040] Use a dry etching process to form a pattern of a small-diameter deep groove 171 and a lithography process alignment structure 172 on the hard mask 170 based on the pattern of the small-diameter deep groove and the lithography process alignment structure 181, 182 formed on the photoresist 180, step S103.

[0041] Using a deep reactive ion etching method, small-diameter deep trenches 120 and lithography process alignment structures 110 are etched on a silicon substrate 100. The width of the small-diameter deep trenches is about 0.1 to 1 μm, and the width of the lithography process alignment structures is about 1 to 8 μm. Step S104, an exemplary processing result of the semiconductor structure at this time is as Figure 2B shown.

[0042] It should be understood that the above process for simultaneously forming the small-diameter deep trenches 120 and the lithography process alignment structures 110 on the same substrate is only exemplary, and these steps are not the focus of the present invention.

[0043] Using a filling method with high step coverage, a functional film layer, such as a plurality of different functional film layers, is deposited in the small-diameter deep trenches 120 and the lithography process alignment structures 110 until the deep trenches are completely filled. At this time, the functional film layer may cover the first surface of the substrate, and there are still micron-level voids in the lithography process alignment structures; Step S105, an exemplary processing result of the semiconductor structure at this time is as Figure 2C 、 Figure 3A shown. The filling method with high step coverage is, for example, a thermal oxidation method, a chemical vapor deposition method, or an atomic layer deposition method.

[0044] Using a high aspect ratio filling process (HARP), a first filling material is filled in the voids of the lithography process alignment structures 110 to form a first part 210 of the first filling material inside the lithography process alignment structures 110 and a second part 220 of the first filling material outside the lithography process alignment structures 110. Step S106, an exemplary processing result of the semiconductor structure at this time is as Figure 2D 、 Figure 3B shown.

[0045] Using a chemical mechanical polishing method for the first filling material polishing process, grinding until the second part 220 of the first filling material is completely removed, and finally reaching the surface of the first part 210 of the filled first filling material, or reaching the surface of the deposited functional film layer. Step S107, an exemplary processing result of the semiconductor structure at this time is as Figure 2E 、 Figure 3C shown.

[0046] The deposition of the first filling material is for the entire wafer, and it is inevitable that the material will be deposited on the substrate surface. Therefore, the generation of the second part 220 cannot be avoided. If deposition is only carried out on the alignment structures, an additional lithography process is required to completely cover the area outside the alignment structures with photoresist, increasing additional costs.

[0047] Silica, phosphosilicate glass, and borophosphosilicate glass have excellent fillability, avoiding the generation of gaps during the filling of deep trench optical alignment structures. At the same time, these materials also have a low coefficient of thermal expansion and chemical stability, which can well adapt to temperature changes and the influence of chemical environments, thereby reducing factors that may cause cracks and damage.

[0048] The silicon substrate filled with the second silica portion in the voids obtained by the above process is subjected to subsequent lithography and other related processes, such as depositing a photoresist 300 for subsequent lithography processes, etc., as Figure 2F 、 Figure 3D shown.

[0049] Therefore, the most preferred embodiment of the semiconductor processing method of the present application includes manufacturing processes such as etching deep trenches on a substrate and filling thin films in the trenches; depositing silica within the lithography process alignment structure 110 using a high aspect ratio filling process (HARP) and planarizing the silica outside the lithography process alignment structure 110, and then performing subsequent lithography and other processes.

[0050] It should be understood that the above etching process includes, in addition to the dry etching process, a wet etching process, other etching processes, or a combination of the foregoing.

[0051] It should be understood that the above deposition process includes, in addition to chemical vapor deposition, physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), metal organic chemical vapor deposition (MOCVD), remote plasma chemical vapor deposition (RPCVD), plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer chemical vapor deposition (ALCVD), atmospheric pressure chemical vapor deposition (APCVD), plasma enhanced atomic layer deposition (PEALD), electroplating, other suitable methods, or a combination of the foregoing.

[0052] It should be understood that the above semiconductor processing technology may be a chemical vapor deposition (CVD) technology (such as vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low-pressure CVD (LPCVD), and / or plasma-assisted CVD (PECVD)), molecular beam epitaxy, other suitable selective epitaxial growth (SEG) processes, or a combination of the foregoing.

[0053] In the semiconductor field, small-diameter deep trenches are mainly used for processing microprocessors, optoelectronic devices, integrated circuits, and other similar devices. In these devices, small size and high-precision processing are very important. Therefore, using small-diameter deep trenches can achieve high-precision processing, resulting in better performance and stability.

[0054] For example, in a microprocessor, small-diameter deep trenches can be used to process microstructures and interconnect lines. In optoelectronic devices, small-diameter deep trenches can be used to fabricate micro optical fiber connectors, waveguides, etc. In integrated circuits, small-diameter deep trenches can be used to process microchannels, electrodes, wires, etc.

[0055] Therefore, the semiconductor processing technology of the present application can be applied to the manufacture of the whole or part of an integrated circuit device. Such an integrated circuit device may be included in a microprocessor, a memory, and / or other integrated circuit devices. In some embodiments, the integrated circuit device may be a part of an integrated circuit chip, a system-on-chip (SoC), or a part of the foregoing combination, including various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or a combination of the foregoing. According to the design requirements of the integrated circuit device 200, various transistors may be planar transistors or multi-gate transistors, such as fin field-effect transistors (FinFETs). Additional components may be added to the integrated circuit device, and some of the components described below may be replaced, modified, or deleted in other embodiments of the integrated circuit device.

[0056] The semiconductor processing technology proposed in the embodiments of the present application can be applied to integrated circuit components with the following structures. Such integrated circuit components generally include a substrate, also known as a wafer. In the described embodiments, the substrate includes silicon. Alternatively or even more, the substrate includes other elemental semiconductors, such as germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations of the foregoing. Alternatively, the substrate is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. The substrate can include doped regions formed by ion implantation processes, diffusion processes, and / or other suitable doping processes according to the design requirements of the integrated circuit device. In some embodiments, the substrate includes a P-type doped region (such as a P-type well) implanted with a P-type dopant (such as boron, indium, other P-type dopants, or combinations of the foregoing). In some embodiments, the substrate includes an N-type doped region (such as an N-type well) implanted with an N-type dopant (such as phosphorus, arsenic, other N-type dopants, or combinations of the foregoing). In some embodiments, the substrate includes a doped region formed by a combination of P-type and N-type dopants. Various doped regions can be directly formed on and / or within the substrate, such as providing a P-type well structure, an N-type well structure, a dual-well structure, a raised structure, or combinations of the foregoing.

[0057] Typically, such an integrated circuit component may form isolation components above and / or within a substrate to separate regions (such as device regions) of the integrated circuit device. For example, the isolation components define active device regions and / or passive device regions and electrically isolate the active device regions and / or passive device regions from each other. The isolation components include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (such as those containing silicon, oxygen, nitrogen, carbon, or other suitable isolation components), or combinations of the foregoing. The isolation components can include different structures, such as a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, and / or a local oxidation of silicon (LOCOS) structure. In some embodiments, the isolation components are formed by etching trenches in the substrate and filling the trenches with an insulating material (e.g., using a chemical vapor deposition (CVD) process or a spin-on glass process). A chemical mechanical polishing (CMP) process can be implemented to remove excess insulating material and / or planarize the top surface of the isolation components. In some embodiments, after forming a fin structure, an isolation component can be formed by depositing an insulating material above the substrate (in some embodiments, such that the insulating material layer fills the gaps (trenches) between the fin structures), and then back-etching the insulating material layer. In some implementations, the isolation component includes a multi-layer structure that fills the trench, such as a bulk dielectric layer disposed above a liner dielectric layer, where the bulk dielectric layer and the liner dielectric layer include materials depending on design requirements (for example, a bulk dielectric layer containing silicon nitride is disposed above a liner dielectric layer containing thermal oxide). In some embodiments, the isolation component includes a dielectric layer disposed above a doped liner layer (such as a layer containing boron silicate glass (BSG) or phosphosilicate glass (PSG)).

[0058] Typically, such an integrated circuit component has respective gate structures disposed above a substrate, such as gate structure and gate structure. The gate structures are respectively joined to their respective channel regions, which are defined between their respective source regions and their respective drain regions, such that current can flow between the respective source / drain regions during operation. In some embodiments, the gate structures are formed above fin structures such that the gate structures respectively cover a portion of the fin structures and are inserted into the respective source regions and the respective drain regions (collectively referred to as source / drain regions) of the fin structures. Each of the gate structures includes a metal gate (MG) stack, such as a metal gate stack. The formation of the metal gate stack is by a deposition process, a lithography process, an etching process, other suitable processes, or a combination of the foregoing. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), plasma enhanced ALD (PEALD), electroplating, other suitable methods, or a combination of the foregoing. The lithography patterning process includes photoresist coating (such as spin coating), soft bake, mask alignment, exposure, post-exposure bake, photoresist development, cleaning, drying (such as hard bake), other suitable processes, or a combination of the foregoing. Alternatively, the lithography exposure process can be assisted, implemented, or replaced by other methods, such as maskless lithography, electron-beam writing, or ion-beam writing. The etching process includes dry etching processes, wet etching processes, other etching processes, or a combination of the foregoing. The fabrication of the metal gate stack is based on a gate last process, a gate first process, or a hybrid gate last / gate first process. In embodiments of the gate last process, the gate structures 230A, 230B include dummy gate stacks that are subsequently replaced by the metal gate stacks.The dummy gate stack includes, for example, an interface layer (e.g., including silicon oxide) and a dummy gate electrode layer (e.g., including polysilicon). In such an embodiment, the dummy gate electrode layer is removed, thereby forming an opening (trench) that is subsequently filled with the metal gate stack 232.

[0059] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and should not be construed as indicating or implying relative importance.

[0060] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

Claims

1. A semiconductor processing method, characterized in that: It includes the steps of: forming a small-diameter deep groove and a lithography process alignment structure from the first surface of the substrate into the substrate; depositing a functional film layer in the small-diameter deep groove and the lithography process alignment structure until the small-diameter deep groove is completely filled; depositing a first filling material on the substrate including the voids of the lithography process alignment structure; removing the excess first filling material outside the lithography process alignment structure.

2. The semiconductor processing method according to claim 1, characterized in that: The first filling material is a high-hardness insulating material, including but not limited to silicon dioxide, phosphosilicate glass or borophosphosilicate glass.

3. The semiconductor processing method according to claim 1, characterized in that: Using a high aspect ratio filling process to fill the first filling material in the voids of the lithography process alignment structure, forming a first part of the first filling material in the lithography process alignment structure and a second part of the first filling material on the first surface outside the lithography process alignment structure.

4. The semiconductor processing method according to claim 1, characterized in that: Using a dry etching process to etch out the small-diameter deep groove and the lithography process alignment structure.

5. The semiconductor processing method according to claim 1, characterized in that: The forming of the small-diameter deep groove and the lithography process alignment structure from the first surface of the substrate into the substrate includes: depositing a hard mask on the substrate; depositing a photoresist on the hard mask, and using a lithography process to form patterns of the small-diameter deep groove and the lithography process alignment structure on the photoresist; using a dry etching process to form patterns of the small-diameter deep groove and the lithography process alignment structure on the hard mask based on the patterns of the small-diameter deep groove and the lithography process alignment structure formed on the photoresist; etching the small-diameter deep groove and the lithography process alignment structure on the substrate based on the patterns of the small-diameter deep groove and the lithography process alignment structure formed on the hard mask.

6. The semiconductor processing method according to claim 5, characterized in that: The width of the lithography process alignment structure is much larger than the width of the small-diameter deep groove.

7. The semiconductor processing method according to claim 6, characterized in that: The width of the small-diameter deep groove is 0.1 to 1 um, and the width of the lithography process alignment structure is 1 to 8 um.

8. The semiconductor processing method according to claim 5, characterized in that: Using a high step coverage filling method to deposit the functional film layer in the small-diameter deep groove and the lithography process alignment structure until the small-diameter deep groove is completely filled.

9. The semiconductor processing method according to claim 8, characterized in that: The high step coverage filling method includes thermal oxidation method, chemical vapor deposition method or atomic layer deposition method.

10. The semiconductor processing method according to claim 5, characterized in that: Using chemical vapor deposition method to deposit the hard mask on the substrate.

11. The semiconductor processing method according to claim 5, It is characterized in that: A small-diameter deep groove and a lithography process alignment structure are etched on a silicon substrate by using a deep reactive ion etching method.

12. The semiconductor processing method according to claim 1, It is characterized in that: The first filling material is polished flat to the surface of the last filled functional film layer by using a chemical mechanical polishing method.

13. A semiconductor structure, It is characterized in that, It is made according to any one of the semiconductor processing methods in claims 1 to 12.

14. A semiconductor structure, It is characterized in that: The small-diameter deep groove on the substrate is completely filled with a deposited functional film layer, and the first filling material is filled in the micron-level voids of the lithography process alignment structure.

15. The semiconductor structure according to claim 13, It is characterized in that: The first filling material is silicon dioxide, phosphosilicate glass or borophosphosilicate glass.

16. The semiconductor structure according to claim 13, It is characterized in that: The functional film layer is simultaneously deposited on the first surface of the substrate.

Images