Semiconductor device and method for forming a semiconductor device

Abstract

The invention relates to a semiconductor device and a method for forming a semiconductor device. The invention discloses a semiconductor device, and an embodiment of the semiconductor device may include a die having a first side and a second side; a contact pad, the contact pad being coupled to the first side of the die; and a metal layer coupled to the second side of the die. A thickness of the die may not exceed four times a thickness of the metal layer.

Description

[0001] Relevant information of divisional application

[0002] This application is a divisional application of a Chinese patent application with an application number of 201910137647.1, a filing date of February 25, 2019, and an invention title of "Semiconductor Device and Method for Forming Semiconductor Device". Technical Field

[0003] Aspects of this document generally relate to semiconductor devices, semiconductor wafers, and device processing methods. Background Art

[0004] Semiconductor manufacturing processes can involve many steps. In some processes, a wafer receives one or more layers, such as a conductive layer. The conductive layer can be used to provide electrical contact regions for individual semiconductor devices cut from the wafer. The conductive layer is typically formed using sputtering, evaporation, or electroplating operations. Summary of the Invention

[0005] Embodiments of a semiconductor device can include a die having a first side and a second side; a contact pad coupled to the first side of the die; and a metal layer coupled to the second side of the die. The thickness of the die can be no more than four times the thickness of the metal layer.

[0006] Embodiments of a semiconductor device can include one, all, or any of the following:

[0007] The thickness of the die can be less than 30 micrometers (μm).

[0008] The thickness of the die can be substantially the same as the thickness of the metal layer.

[0009] The device can include a molding compound directly coupled to the metal layer.

[0010] The device can include a molding compound directly coupled above the metal layer.

[0011] Embodiments of a semiconductor device can include a die having a first side and a second side; a contact pad coupled to the first side of the die; a metal layer coupled to the second side of the die; and a molding compound directly coupled to the metal layer. The thickness of the die can be less than 30 μm.

[0012] Embodiments of a semiconductor device can include one, all, or any of the following:

[0013] The thickness of the die can be substantially the same as the thickness of the metal layer.

[0014] The molding compound can be directly coupled above the metal layer.

[0015] Embodiments of a method for forming a semiconductor die may include forming a plurality of contact pads coupled to a first side of a wafer; forming a recess in a second side of the wafer opposite the first side by back-grinding the wafer; forming a metal layer within the recess; patterning the metal layer within the recess; and dicing the wafer into a plurality of semiconductor devices.

[0016] Embodiments of a method for forming a semiconductor device may include one, all, or any of the following:

[0017] The method may include coupling a molding compound to the metal layer within the recess.

[0018] The metal layer may be exposed through the molding compound.

[0019] The molding compound may be directly coupled over the metal layer.

[0020] The method may include back-grinding a portion of the wafer until the portion of the wafer is coplanar with a plane formed by a portion of the molding compound.

[0021] The method may include thinning the wafer by forming a recess, wherein a portion of the wafer is thinned to less than 30 μm.

[0022] The method may include coating the recess with a seed layer.

[0023] The method may include forming a plurality of bumps over the metal layer.

[0024] The method may include coupling one of the metal layer, the molding compound, and the plurality of bumps to a backside protection layer and then dicing the wafer.

[0025] Embodiments of a method for forming a semiconductor die may include forming a plurality of contact pads coupled to a first side of a wafer; forming a recess in a second side of the wafer opposite the first side by back-grinding the second side of the wafer; forming a metal layer within the recess; forming a plurality of openings within the metal layer; forming a molding compound into the openings of the metal layer; and dicing the wafer into a plurality of semiconductor devices.

[0026] Embodiments of a method for forming a semiconductor device may include one, all, or any of the following:

[0027] The method may further include forming a metal layer between the contact pads and the first side of the wafer.

[0028] The thickness of the metal layer may be substantially the same as the thickness of the wafer.

[0029] The thickness of the metal layer may be substantially three times the thickness of the wafer.

[0030] The method may include coupling a second metal layer over the metal layer.

[0031] The molding compound may encapsulate the metal layer.

[0032] For those of ordinary skill in the art, the above and other aspects, features, and advantages will be apparent from the detailed description, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The embodiments will be described hereinafter with reference to the drawings, in which like reference numerals denote like elements, and:

[0034] Figure 1 is a cross-sectional side view of a first embodiment of a semiconductor device;

[0035] Figure 2 is a cross-sectional side view of a second embodiment of a semiconductor device;

[0036] Figure 3 is a cross-sectional side view of a third embodiment of a semiconductor device;

[0037] Figure 4 is a cross-sectional side view of a fourth embodiment of a semiconductor device;

[0038] Figure 5 is a cross-sectional side view of a fifth embodiment of a semiconductor device;

[0039] Figure 6 is a cross-sectional side view of a sixth embodiment of a semiconductor device;

[0040] Figure 7 is a cross-sectional side view of a seventh embodiment of a semiconductor device;

[0041] Figure 8 is a graph showing the on-resistance of various embodiments of a semiconductor device;

[0042] Figure 9 is a cross-sectional side view of a wafer;

[0043] Figure 10 is a Figure 9 cross-sectional side view of a wafer having a groove formed therein;

[0044] Figure 11 is a Figure 10 cross-sectional side view of a wafer, in which a mask is formed in the groove;

[0045] Figure 12 is a Figure 10 cross-sectional side view of a wafer, in which a metal layer is formed in the groove;

[0046] Figure 13 is Figure 12 a cross-sectional side view of a wafer in which a molding compound is formed over a metal layer;

[0047] Figure 14 is Figure 13 a cross-sectional side view of a wafer in which a portion of the ring of the wafer is removed;

[0048] Figure 15 is a cross-sectional side view of a wafer that rotates with a tape applied to the molding compound; Figure 14 of the wafer;

[0049] Figure 16 is a cut Figure 15 cross-sectional side view of the wafer;

[0050] Figure 17 is Figure 13 a cross-sectional side view of a wafer in which a tape is applied to the molding compound;

[0051] Figure 18 is a cut Figure 17 cross-sectional side view of the wafer;

[0052] Figure 19 is Figure 12 a cross-sectional side view of a wafer in which the molding compound fills a groove;

[0053] Figure 20 is Figure 10 a cross-sectional side view of a wafer in which an unpatterned metal layer is formed within the groove;

[0054] Figure 21 is Figure 12 a cross-sectional side view of a wafer in which a portion of the ring of the wafer is removed;

[0055] Figure 22 is Figure 21 a cross-sectional side view of a wafer in which bumps are formed over the metal layer;

[0056] Figure 23 is Figure 21 a cross-sectional side view of a wafer in which the molding compound is formed between openings in the metal layer;

[0057] Figure 24 is Figure 22 a cross-sectional side view of a wafer in which the molding compound is formed between openings in the metal layer;

[0058] Figure 25A - Figure 25B shows a process for cutting a wafer having a BSP layer applied thereto; and

[0059] Figure 26A - Figure 26B A process for cutting a wafer without a BSP layer applied thereto is shown. DETAILED DESCRIPTION

[0060] The present disclosure, its aspects, and embodiments are not limited to the specific components, assembly processes, or method elements disclosed herein. Many additional components, assembly processes, and / or method elements known in the art for semiconductor devices meeting the intended requirements will obviously be able to be used in conjunction with the specific embodiments of the present disclosure. Thus, for example, although the present invention discloses specific embodiments, such embodiments and implementation components may include any shape, size, style, type, model, version, measure, concentration, material, quantity, method element, step, etc. known in the art for such semiconductor devices and implementation components and methods meeting the intended operations and methods.

[0061] Specific embodiments of semiconductor devices and implementation components and methods may be similar to or the same as the semiconductor devices and implementation components and methods disclosed in the following patents: U.S. Patent No. 9,905,522, titled "Semiconductor Copper Metallization Structure and Related Methods", filed on September 1, 2016, and issued on February 27, 2018, with application serial number 15 / 254,640 ('522 patent), and U.S. Patent No. 9,640,497, titled "Semiconductor Backmetal (BM) and OverPad Metallization (OPM) Structures and Related Methods", filed on June 30, 2016, and issued on May 2, 2017, with application serial number 15 / 198,859 ('497 patent). The disclosures of each of these patents are hereby incorporated by reference in their entirety.

[0062] In various embodiments, the semiconductor devices disclosed herein may be power semiconductor devices, by way of non-limiting example, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs). In other embodiments, the device may be other types of power semiconductor devices, or may be semiconductor devices that are not power semiconductor devices. See Figure 1, showing a cross-sectional side view of a first embodiment of a semiconductor device. The semiconductor device 2 includes a die 4 having a first side 6 and a second side 8. The die 4 may include silicon, and in various embodiments, may include an epitaxial portion 10. It should be understood that in the case where the present disclosure relates to a silicon die, the silicon die can be any type of silicon die, by way of non-limiting example, including an epitaxial silicon die, silicon-on-insulator, polysilicon, any combination thereof, or any other silicon-containing die material. Additionally, it should also be understood that in various embodiments, dies other than silicon-containing dies can be used, by way of non-limiting example, such as gallium arsenide or metal-containing dies. In Figure 1 the illustrated embodiment, the semiconductor device can be a trench MOSFET device, as indicated by the patterned portion 24 in the epitaxial portion 10 of the die 4, showing the location of the trenches. However, other embodiments may not include a trench MOSFET structure, but may include different semiconductor devices that can be or can not be power semiconductor devices. In various embodiments, the thickness of the die 4 can be about 25 micrometers (μm), about 40 μm, about 75 μm, greater than about 75 μm, between about 25 μm and about 75 μm, less than about 30 μm, and less than about 25 μm.

[0063] In various embodiments, the semiconductor device 2 may include a conductive layer 12 coupled to the first side 6 of the die 4. The conductive layer can be a metal or a metal alloy, and in such embodiments, by way of non-limiting example, may include aluminum, copper, gold, silver, titanium, nickel, any other metal, and any combination thereof. In various embodiments, the length and width of the conductive layer 12 can be the same as those of the die 4. However, in other embodiments, such as Figure 1 shown, the length or width of the conductive layer can be less than the length or width of the die 4.

[0064] In various embodiments, the semiconductor device 2 may include a contact pad 14 coupled to the conductive layer. The contact pad 14 can be any type of metal or metal alloy disclosed herein. In a particular embodiment, the contact pad can be SnAg or NiAu. The length and width of the contact pad 14 can be the same as those of the conductive layer 12. However, in other embodiments, such as Figure 1 shown, the length or width of the contact pad can be less than the length or width of the conductive layer 12. In various embodiments, in addition to the conductive layer 12, the semiconductor device 2 may not include the contact pad 14, but the conductive layer can be used as the contact pad. Similarly, in a particular embodiment, the semiconductor device 2 may not include the conductive layer 12, but may include a contact pad 14 directly coupled to the first side 6 of the die 4.

[0065] In various embodiments, an intermediate pad may be coupled between the conductive layer 12 and the contact pad 14. The intermediate pad may be a metal deposited by electroplating, and in a particular embodiment, may be electroplated copper. In a particular embodiment, the intermediate pad may comprise a metal alloy, and by way of non-limiting example, may include Ni, Au, Pd, Cu, or any combination thereof. In various embodiments, the intermediate pad may have different widths, wherein the cross-sectional width of the first portion of the intermediate pad directly coupled to the conductive layer 12 is less than the cross-sectional width of the second portion of the intermediate pad directly coupled to the contact pad 14. In other embodiments, the cross-sectional width of the first portion of the intermediate pad may be the same as the cross-sectional width of the second portion of the intermediate pad.

[0066] In various embodiments, as Figure 1 shown, the semiconductor device may include a passivation material 72 coupled above the die 4. The surface 74 of the passivation material may be coplanar with the plane formed by the exposed surface of the contact pad 14. In embodiments including an intermediate pad, the passivation layer may cover only a portion of the intermediate pad, such that the entire contact pad 14 is not directly coupled to the passivation layer. In a particular embodiment, the passivation material may at least partially encapsulate the conductive layer 12. By way of non-limiting example, the passivation material may be SiN, SiO 2 , or any other type of passivation material.

[0067] Still referring to Figure 1 , the semiconductor device 2 includes a metal layer / back metal layer 16 coupled to the second side 8 of the die 4. In various embodiments, by way of non-limiting example, the metal layer may include copper, gold, silver, aluminum, titanium, nickel, any other metal, and any combination thereof. In a particular embodiment, the metal layer 16 may be the same as or similar to the back metal layer disclosed in the '522 patent and the '497 patent, which are hereby incorporated by reference. In various embodiments, the metal layer 16 may include a single type of metal or a metal alloy, while in other embodiments, the metal layer may include multiple metal layers of the same or different metals and / or metal alloys. In various embodiments, the thickness of the metal layer 16 may be about 10 μm, about 25 μm, about 40 μm, less than about 10 μm, between about 10 - 40 μm, and greater than about 40 μm, including thicknesses as large as about 200 μm. Compared to the die 4, in various embodiments, the thickness of the die may not exceed about four times the thickness of the metal layer 16. In a more particular embodiment, the thickness of the die 4 may be about three times the thickness of the metal layer 16, about two and a half times the thickness of the metal layer, about twice the thickness of the metal layer, or substantially the same as the thickness of the metal layer 16. In other embodiments, the thickness of the die 4 may be greater than about four times the thickness of the metal layer 16, or less than the thickness of the metal layer 16.

[0068] In various embodiments, the semiconductor device 2 may include a seed layer 18 between the second side 8 of the die 4 and the metal layer 16. The seed layer 18 may be configured to facilitate bonding between the metal layer 16 and the die 4 and / or provide a location for the initiation of electrodeposition during an electroplating operation. The seed layer 18 may include a metal or a metal alloy, and in certain embodiments, may include TiCu or TiWCu. In other embodiments, the seed layer 18 may include any metal previously disclosed herein.

[0069] In various embodiments, the semiconductor device 2 may include a molding compound / resin / protective coating (hereinafter referred to as "molding compound" 20) coupled to the metal layer 16. Although the term "molding compound" is used herein to describe the material above the metal layer, it should be understood that as used herein, the term includes many types of resins, epoxies, and other types of protective coatings. In certain embodiments, the molding compound 20 may be directly coupled to the metal layer 16, and in even more specific embodiments, the molding compound may be directly coupled above the metal layer. As Figure 1 shown, the molding compound 20 may encapsulate the metal layer 16. In other embodiments, as shown and discussed later herein, the metal layer 16 may be exposed through the molding compound 20. The sidewalls 22 of the molding compound 20 may be stepped, however, in other embodiments, the sidewalls 22 may not include steps.

[0070] Figure 1 The semiconductor device as well as other semiconductor devices disclosed herein may be coupled to or paired with other semiconductor devices, which may be of the same type or different types of semiconductor devices. In various embodiments, semiconductor devices may be paired and / or electrically / thermally coupled together through the metal layer 16. By way of non-limiting example, devices may also be paired together using wire bonds, conductive traces, or any other coupling means.

[0071] See Figure 2 , a cross-sectional view of a second embodiment of a semiconductor device is shown. The semiconductor device 26 is similar to Figure 1 the semiconductor device 2, except that the molding compound 28 is thicker than Figure 1 the molding compound 20. However, in various embodiments, the molding compound may be thinner than the thickness of the molding compound shown in Figure 1 . Additionally, in various embodiments, the sidewalls 30 of the molding compound 28 are not stepped.

[0072] See Figure 3 , a cross-sectional side view of a third embodiment of a semiconductor device is shown. The semiconductor device 32 is similar to Figure 1The semiconductor device 2, except that the length and width of the metal layer 34 are the same as the length and width of the die 4. By being the same as the length and width of the die, the metal layer is exposed on the sidewalls of the semiconductor device. The semiconductor device 32 may also include a molding compound 36 coupled to the metal layer 34. As Figure 3 shown, the molding compound may be directly coupled to the metal layer without being directly coupled to any sidewall 38 of the metal layer 34. In various embodiments, Figure 3 the semiconductor device may be paired with any number of other semiconductor devices. The other semiconductor devices may be the same as the Figure 3 device shown. In such embodiments, the devices may be positioned side by side such that the metal layer 16 directly contacts the metal layer of another semiconductor device, thereby allowing the semiconductor devices to be electrically paired through the metal layers on the back of the semiconductor devices.

[0073] In other embodiments, the semiconductor device may have a conductive layer coupled above the metal layer 34 instead of the molding compound 36. The conductive layer may be any type of conductive layer disclosed herein. Such an embodiment is similar to the Figure 5 embodiment shown herein, except that the sidewalls of the conductive layer and the metal layer may co - extend with the sidewalls of the die.

[0074] See Figure 4 , which shows a cross - sectional side view of a fourth embodiment of a semiconductor device. The semiconductor device 40 may be similar to the Figure 1 semiconductor device, except that there is no molding compound coupled to the metal layer 42. In such embodiments, the perimeter of the metal layer may co - extend with the sides of the die 44, as shown by the Figure 3 metal layer, or the perimeter of the metal layer 42 may be set back from the sides of the die, as shown by the Figure 4 figure.

[0075] See Figure 5 , which shows a cross - sectional view of a fifth embodiment of a semiconductor device. The semiconductor device 46 may be similar to the Figure 4 semiconductor device, except that a conductive layer 48 is formed above the metal layer 50. In various embodiments, the layer may be thermally conductive and / or electrically conductive. In various embodiments, the conductive layer may be a second metal layer and may include any metal or metal alloy disclosed herein, by way of non - limiting example, including Ni, SnAg, and NiAu. In a particular embodiment, the conductive layer 48 may be a bump or a pad. The conductive layer, bump, or pad may co - extend with the side 52 of the metal layer 50 or may not co - extend therewith.

[0076] See Figure 6 , which shows a cross - sectional view of a sixth embodiment of a semiconductor device. The semiconductor device 54 may be similar to the Figure 4The semiconductor device is different in that the molding compound 56 is directly coupled to the sidewall 58 of the metal layer 60. Since the molding compound 56 is only coupled to the sidewall of the metal layer 60, the surface of the metal layer parallel to the plane formed by the maximum surface of the die is exposed through the molding layer 56.

[0077] See Figure 7 , which shows a cross-sectional view of a seventh embodiment of a semiconductor device. The semiconductor device 62 can be similar to Figure 5 the semiconductor device, except that the molding compound 64 is directly coupled to the sidewalls of both the metal layer 66 and the conductive layer 68 coupled above the metal layer. In Figure 7 the embodiment shown, the molding compound is not above the conductive layer 68, so the conductive layer can be exposed through the molding compound 64. The conductive layer can be the same as or similar to Figure 5 the conductive layer.

[0078] Throughout this disclosure, the term "above" is used with respect to various layers and elements. This term does not mean to express a position upward or downward in the drawings, but is intended to express a relative external position. For example, using Figure 7 the upper (above) and lower (below) directions, the layer placed above the die 70 will be "above" the die, and the layer placed below the metal layer 66 will similarly be "above" the metal layer.

[0079] See Figure 8 , which shows a graph of the on-resistance showing various embodiments of a semiconductor device. The Y-axis of the graph shows the on-resistance in milliohms (mΩ). The X-axis of the graph shows the thickness of the silicon die in micrometers. The resistance of dies with different thicknesses of back metal is shown by four lines in the graph. As shown in the graph, as the thickness of the silicon layer decreases, the on-resistance decreases, and as the thickness of the back metal increases, the on-resistance also decreases. The first star represents the first semiconductor device, which has a silicon die with a thickness of 125 μm and a back metal layer with a thickness of 6 μm. It has an on-resistance of 2.6 mΩ. The second star represents the second semiconductor device, which has a silicon die with a thickness of 75 μm and a back metal layer with a thickness of 15 μm. The on-resistance of the second semiconductor device is 1.9 mΩ. The third star represents the third semiconductor device, which has a silicon die with a thickness of 25 μm and a back metal layer with a thickness of 15 μm. The third semiconductor device has an on-resistance of 1.6 mΩ. As shown in the graph, as the thickness of the silicon layer decreases, the on-resistance decreases, and as the thickness of the back metal increases, the on-resistance also decreases. This low on-resistance can be beneficial for semiconductor devices used in various applications, including fast charging systems. Additionally, by significantly reducing the thickness of the die, the overall size of the semiconductor package can be reduced.

[0080] See Figure 9 - Figure 24, showing various methods for forming Figure 1 - Figure 7 the various semiconductor devices shown in Figure 9 . Specifically referring to Figure 9 , a cross-sectional view of a wafer is shown. In various embodiments, the method of forming a semiconductor device includes providing a wafer 76 having a first side 78 and a second side 80. In various embodiments, the wafer 76 may be silicon. It should be understood that in cases where the present disclosure relates to a silicon layer, the silicon layer may be any type of silicon layer, by non-limiting example, including an epitaxial silicon layer, silicon-on-insulator, polysilicon, any combination thereof, or any other silicon-containing substrate material. As Figure 9 shown, the wafer 76 may include an epitaxial silicon portion 82. Additionally, it should also be understood that in various embodiments, substrates other than silicon-containing substrates may be used, by non-limiting example, such as gallium arsenide or metal-containing substrates. In various embodiments, the method may include forming, in part / entirely, a plurality of semiconductor devices within the wafer 76. In a particular embodiment, a plurality of power semiconductor devices may be formed, in part / entirely, within the epitaxial silicon portion 82, by non-limiting example, including MOSFETs, IGBTs, or any other power semiconductor device. In Figure 9 the embodiment shown, a plurality of trench MOSFETs 84 are formed, in part, within the epitaxial silicon portion 82. The portion of the power semiconductor device formed within the wafer 76 may include wiring to allow the semiconductor device to be connected to other package components and / or circuits when in use. In such embodiments, the wiring may be aluminum or any other conductive material disclosed herein.

[0081] In various embodiments, the method of forming a semiconductor device may include forming a conductive layer 86 over the first side 78 of the wafer 76. In various embodiments, and as Figure 9 shown, the conductive layer may be patterned, however, in other embodiments, the conductive layer may not be patterned. The conductive layer may be a metal or a metal alloy, and in such embodiments, by non-limiting example, may include aluminum, copper, gold, silver, titanium, nickel, any other metal, and any combination thereof, including those disclosed herein.

[0082] In various embodiments, the method of forming a semiconductor device may include forming a plurality of contact pads 88 coupled to the first side 78 of the wafer 76. As Figure 9As shown, the conductive layer 86 can separate the contact pads 88 from the wafer 76. In other embodiments, the method can include forming the contact pads directly onto the wafer and omitting the conductive layer from the process of forming the semiconductor device. In various embodiments, the plurality of contact pads 88 can form solder top metal (STM) and can be made of any metal or metal alloy. In a particular embodiment, the plurality of contact pads can be NiAu. In such embodiments, the NiAu contact pads can be formed onto the conductive layer 86 or the wafer 76 by electroless plating. The plurality of contact pads 88 can be considered to be on the source side of the wafer 76.

[0083] Still referring to Figure 9 , a method of forming a semiconductor device can include applying a passivation layer 90 to the wafer 76, the conductive layer 86, and / or the plurality of contact pads 88. The passivation layer 90 can be any type of passivation layer previously disclosed herein. The passivation layer 90 can at least partially encapsulate the conductive layer 86. Additionally, the plurality of contact pads 88 can be exposed through the passivation layer 90. In a particular embodiment, the passivation layer 90 can initially cover the plurality of contact pads 88, and the plurality of contact pads 88 can be exposed through the passivation layer by backgrinding or chemical mechanical polishing (CMP) the passivation layer. Additionally, as Figure 9 shown, the surface 92 of the passivation layer 90 can be coplanar with a plane formed by the exposed portions of the plurality of contact pads 88. By way of non-limiting example, CMP techniques can be used to planarize the passivation layer 90 and the plurality of contact pads 88.

[0084] In other embodiments, a method of forming a semiconductor package can include forming an intermediate layer between the conductive layer 86 and the contact pads 88. The intermediate layer can be an electroplated metal layer and, in a particular embodiment, can be electroplated copper. The intermediate layer can include alloys, by way of non-limiting example, including Ni, Au, Pd, Cu, and any combination thereof. In other embodiments, the intermediate layer can be sputtered onto the conductive layer 86. In various embodiments, the method of forming the intermediate layer can include forming a plurality of layers within the intermediate layer. In such embodiments, one of the plurality of layers can be a seed layer, which can include Ti or Cu. In a particular embodiment, the method of forming a semiconductor package can include patterning the intermediate layer into a plurality of intermediate pads. In cases where the method of forming the intermediate layer includes forming a plurality of layers within the intermediate layer, each layer within the intermediate layer can have a different pattern, and these patterns form intermediate pads having stepped sidewalls. During the process of forming the intermediate layer, the seed layer can be etched after the material for forming the pads 88 is formed. As an example, the intermediate layer can be patterned to form a plurality of intermediate pads having a first portion directly coupled to the conductive layer, the cross-sectional width of the first portion being less than a second portion of the plurality of intermediate pads directly coupled to the contact pads 88. In embodiments in which the intermediate pads are formed, the passivation layer can completely or partially cover the sidewalls of the intermediate pads.

[0085] See Figure 10 , which shows a cross-sectional side view of a Figure 9 wafer having a groove formed therein. In various embodiments, a method of forming a semiconductor device includes forming a groove 94 in a second side 80 of a wafer 76. By forming the groove 94, the wafer 76 can be thinned. In various embodiments, the groove 94 can be formed by backgrinding the second side 80 of the wafer 76. In such embodiments, a backgrinding tape 100 can be coupled to the contact pads. In a particular embodiment, the groove 94 can be formed by backgrinding using a process sold under the trade name TAIKO by DISCO Corporation, Tokyo, Japan. The backgrinding leaves a ring 96 (TAIKO ring) of unremoved material, which helps prevent the wafer from curling, warping, or otherwise bending during processing while removing most of the thickness and material of the second side 80 or the backside of the wafer 76. In other embodiments of the method of forming a semiconductor device, the TAIKO process may not be used, but some other backgrinding or other material removal technique, such as removing material by wet etching, may be used. In various embodiments, the thickness of the thinned portion 98 of the wafer 76 can be thinned to about 25 μm, about 40 μm, about 75 μm, greater than about 75 μm, between about 25 μm and about 75 μm, less than about 30 μm, and less than about 25 μm.

[0086] See Figure 11 , which shows a cross-sectional side view of a Figure 10 wafer in which a mask is formed in the groove. The mask can be formed using various processes, by way of non-limiting example, including photolithography, film attachment, and other methods of forming a pattern in the groove. The method can also include forming a patterned photoresist layer 104 within the groove 94. In various embodiments, the method of forming a semiconductor device further includes coating the groove 94 with a seed layer 102 before or after forming the mask. The seed layer 102 can be a metal or a metal alloy. In a particular embodiment, the seed layer can be TiCu or TiWCu. In various embodiments, the interior of the groove can be coated with the seed layer 102 by sputtering. See Figure 12 , which shows a Figure 10Cross-sectional side view of a wafer, where a metal layer is formed in a groove. In various embodiments, a method of forming a semiconductor device may include forming a metal layer 106 or a back metal within groove 94. The metal layer 106 may include copper, aluminum, gold, silver, nickel, titanium, any other metal, and any combination thereof. In embodiments where the seed layer 102 is coupled to the wafer 76 within the groove 94, the metal layer 106 may be coupled to the wafer 76 through the seed layer 102. In some embodiments, the metal layer may be applied by electroplating copper or other metal plating processes. In other embodiments, the metal layer may be applied using sputtering or evaporation processes.

[0087] In various embodiments, the metal layer 106 may include multiple layers of the same or different metals, while in other embodiments, the metal layer may include only a single layer of metal. In various embodiments, the thickness of the metal layer 106 may be about 10 μm, about 25 μm, about 40 μm, less than about 10 μm, between about 10 - 40 μm, and greater than about 40 μm, including thicknesses as large as about 200 μm. Compared to the thinned portion 98 of the wafer 76, in various embodiments, the thickness of the thinned portion of the wafer does not exceed about four times the thickness of the metal layer 106. In more specific embodiments, the thickness of the thinned portion 98 of the wafer 76 may be substantially three times the thickness of the metal layer 106, two and a half times the thickness of the metal layer, twice the thickness of the metal layer, or approximately the same as the thickness of the metal layer 106. In other embodiments, the thickness of the thinned portion 98 of the wafer 76 may be greater than about four times the thickness of the metal layer 106, or less than the thickness of the metal layer 106.

[0088] In a specific embodiment, and as Figure 12 shown, the method may include patterning or forming an opening 108 within the metal layer 106. Figure 11 The photoresist layer 104 may be used to form the pattern of the opening 108 or the metal layer 106. After forming the metal layer 106 within the groove 94, the photoresist layer 104 and portions of the seed layer 102 may be stripped. In various embodiments, the metal layer 106 may not include a dicing lane, which may reduce debris of the wafer 76 (and thus, the diced die) when the wafer is to be diced.

[0089] See Figure 13 which shows a cross-sectional view of a wafer where a molding compound is formed over the metal layer. A method of forming a semiconductor device may include coupling a molding compound 112 to the metal layer 106 within the groove 94. The molding compound 112 may be applied to prevent oxidation of the metal layer 106 and protect the metal layer from physical damage. In various embodiments, the molding compound 112 may be directly coupled above the metal layer 106, as Figure 12 shown. Figure 13As shown. In embodiments where the metal layer 106 is patterned, the molding compound 112 may also be within the openings 108 in the metal layer 106. In various embodiments, the molding compound 112 may have a substantially constant thickness, such that the openings 108 are not completely filled with the molding compound 112. By way of non-limiting example, liquid dispensing techniques, transfer molding techniques, printer molding techniques, compression molding techniques, or lamination techniques may be used to apply the molding compound 112 to the metal layer 106. In various embodiments, by way of non-limiting example, the molding compound 112 may be an epoxy molding compound, an acrylic molding compound, or any other type of molding compound or protective cover.

[0090] See Figure 14 , shows a Figure 13 cross-sectional side view of a wafer, where a portion of the ring of the wafer is removed. In various embodiments, a method for forming a semiconductor device may include removing a portion of the ring 96. In certain embodiments, the portion of the ring 96 may be removed by backgrinding the ring 96. In other embodiments, other removal techniques or methods may be used to at least partially remove the ring, such as circularly sawing off the ring around the edge of the wafer. In various embodiments, enough of the ring 96 is removed such that the surface 114 of the ring 96 or the wafer 76 is coplanar with the surface 116 of the molding compound 112. In other embodiments, the ring portion may be partially removed, but not to the extent of flattening the surface 114 of the ring 96 with the surface 116 of the molding compound 112. In various embodiments, the method may include removing the backgrinding tape 90 from the source side of the wafer 76, and applying a new backgrinding / cutting tape 118 to the contact pads, as Figure 14 shown.

[0091] See Figure 15 , shows a Figure 14 cross-sectional side view of a wafer rotating with a tape applied to the molding compound. A method for forming a semiconductor device may include applying a tape to the backside of the wafer 76, or to the molding compound 112. In various embodiments, and as Figure 15 shown, the wafer 76 may be removed from the backgrinding / cutting tape 118, as Figure 14 shown, and the wafer may be rotated with the backside of the wafer and / or the molding compound 112, and reapplied to the backgrinding tape 118 (or initially applied to a sawing tape for cutting), as Figure 15 shown.

[0092] See Figure 16 , shows a Figure 15Cross-sectional side view of a wafer. A method for forming a semiconductor device includes cutting a wafer 76 into a plurality of semiconductor devices 120. By way of non-limiting example, the wafer 76 can be cut by blade cutting, laser cutting, water jet cutting, etching, or any other cutting method. As Figure 16 shown, each of the semiconductor devices 120 is identical to the Figure 1 semiconductor device 2 shown.

[0093] See Figure 17 - Figure 18 , which shows an alternative method for forming the Figure 1 semiconductor device. Specifically see Figure 17 , which shows a Figure 13 cross-sectional side view of a wafer in which a tape is applied to the molding compound. Figure 17 It is shown that the method can include applying a tape 122 to the molding compound 112 and applying it to the ring 96 of the wafer 76, rather than backgrinding the ring 96, as Figure 14 shown. Then, as indicated by the cut 124, the ring 96 can be removed from the metal layer by cutting through the passivation layer 90, the wafer 76, and the molding compound 112. See Figure 18 , which shows a Figure 17 cross-sectional side view of the wafer after cutting. The method can include cutting the wafer 76 into a plurality of semiconductor devices 126. Any cutting method disclosed herein can be used to cut the wafer. Figure 18 The plurality of semiconductor devices 126 shown can be identical to the Figure 1 semiconductor device 2 shown.

[0094] See Figure 19 , which shows a Figure 12 cross-sectional side view of a wafer in which the molding compound fills the groove. Figure 19 It shows an alternative method for forming a semiconductor device. Figure 19 The method shown can include completely filling the groove 94 with a molding compound 128, rather than forming a molding compound 112 having a uniform thickness over the entire length of the protective coating covering the metal layer 106, as Figure 13 shown. The molding compound 128 can be applied to the groove using any technique disclosed herein and can be any type of molding compound or other protective coating disclosed herein. As Figure 19 shown, in contrast to Figure 13 , the outer surface 130 of the molding compound 128 has a smooth surface that does not follow the contour of the patterned metal layer 106, so the molding compound 128 can have different thicknesses. In other words, the molding compound 128 can completely fill the opening 108 within the metal layer 106. The molding compound 128 can increase chip strength and can be particularly useful in embodiments where the thickness of the thinned portion 98 of the wafer 76 is less than about 30 μm.

[0095] In other embodiments, the molding compound may only partially fill the recess, rather than having the molding compound 128 completely fill the recess 94. In such embodiments, the outer surface 130 of the molding compound 128 may still have a smooth surface that does not follow the contour of the patterned metal layer 106. However, the outer surface 130 may not be coplanar with the end of the ring 96.

[0096] Still referring to Figure 19 , in various embodiments, the method for forming a semiconductor device may include backgrinding the ring 96, the molding compound 128, or both the ring and the molding compound. The wafer 76 may then be diced into a plurality of semiconductor devices using any of the dicing methods previously disclosed herein. The plurality of diced semiconductor devices may be the same as the semiconductor device 26 shown in Figure 2 . Because the molding compound 128 completely fills the opening 108 within the metal layer 106, the diced semiconductor device may have a molding compound 28 having sidewalls 30 that are not stepped, as shown in Figure 2 .

[0097] Referring to Figure 20 , a cross-sectional side view of a wafer is shown in Figure 10 in which an unpatterned metal layer is formed within the recess. Figure 20 An alternative method for forming a semiconductor device is shown. The method may include forming a solid metal layer 132 coupled to the wafer 76, rather than forming the patterned metal layer 106, as shown in Figure 11 - Figure 12 . In various embodiments, a seed layer 102 may be between the metal layer 132 and the wafer 76. The method may include coating the metal layer 132 with a protective coating that may be a molding compound 134. The molding compound 134 may partially fill the recess 94, while in other embodiments, it may completely fill the recess 94. In various embodiments, the method for forming a semiconductor device may include backgrinding the ring 96, the molding compound 134, or both the ring and the molding compound. The wafer 76 may then be diced into a plurality of semiconductor devices using any of the dicing methods previously disclosed herein. The plurality of diced semiconductor devices may be the same as the semiconductor device 32 shown in Figure 3 . By not patterning the metal layer 132, the method may potentially save costs as compared to the method shown in Figure 11 - Figure 12 .

[0098] In other embodiments, a method for forming a semiconductor device may include forming a conductive layer onto metal layer 132 instead of coating metal layer 132 with a molding compound 134. The conductive layer can be any type of conductive layer disclosed herein, including Ni, NiAu, SnAg. In various embodiments, the method may include plating the conductive layer onto the metal layer, while in other embodiments, the conductive layer is applied to the metal layer by sputtering, evaporation, or other deposition techniques. The method for forming a semiconductor device may include a back grinding ring 96. The wafer 76 can then be diced into a plurality of semiconductor devices using any dicing method previously disclosed herein. The plurality of diced semiconductor devices may be similar to Figure 3 the semiconductor device 32 shown therein, except that instead of a molding compound above the metal layer, the semiconductor device has a conductive layer above the metal layer.

[0099] See Figure 21 , which shows a cross-sectional side view of a wafer of Figure 12 where a portion of the ring of the wafer is removed. Figure 21 shows an alternative method for forming a semiconductor device. The method may include not covering the metal layer 106 with any kind of molding compound or protective cover, instead of forming a molding compound above the metal layer 106, as shown in Figure 13 and Figure 19 . In various embodiments, the method for forming a semiconductor device may include a back grinding ring 96. The wafer 76 can then be diced into a plurality of semiconductor devices using any dicing method previously disclosed herein. The plurality of diced semiconductor devices may be the same as the semiconductor device 40 shown in Figure 4 .

[0100] See Figure 22 , which shows a cross-sectional side view of a wafer of Figure 21 where bumps are formed above the metal layer. Figure 22 shows an alternative method for forming a semiconductor device. The method may include forming a plurality of bumps / pads 136 above the metal layer 106, instead of leaving the metal layer 106 uncovered, as shown in Figure 21 . In various embodiments, the plurality of bumps 136 may be considered a second metal layer above the metal layer 106. The plurality of bumps 136 can be any type of material disclosed herein. In various embodiments, the method for forming a semiconductor device may include a back grinding ring 96. The wafer 76 can then be diced into a plurality of semiconductor devices using any dicing method previously disclosed herein. The plurality of diced semiconductor devices may be the same as the semiconductor device 46 shown in Figure 5 .

[0101] See Figure 23 , which shows a cross-sectional side view of a wafer of Figure 21Cross-sectional side view of a wafer, where the molding compound is formed between openings in the metal layer. Figure 23 An alternative method for forming a semiconductor device is shown. Contrary to Figure 21 as shown in Figure 23 The method shown includes coupling a molding compound 138 within an opening 108 of a metal layer 106 while exposing the metal layer through the molding compound 138. The outer surface of the molding compound 138 may be coplanar or substantially coplanar with the outer surface of the metal layer 106. In various embodiments, the molding compound 138 may initially cover the metal layer 106, as Figure 19 shown, but may then be backgrinded to expose the metal layer 106 through the molding compound 138. In various embodiments, the method for forming a semiconductor device may include a backgrinding ring 96, the molding compound 138, or both the ring and the molding compound. The wafer 76 may then be diced into a plurality of semiconductor devices using any dicing method previously disclosed herein. The plurality of diced semiconductor devices may be the same as the semiconductor device 54 shown in Figure 6 .

[0102] See Figure 24 , which shows Figure 22 Cross-sectional side view of a wafer, where the molding compound is formed between openings in the metal layer. Figure 24 An alternative method for forming a semiconductor device is shown. Contrary to Figure 22 as shown in Figure 24 The method shown includes coupling a molding compound 140 within an opening 108 of a metal layer 106 while exposing a plurality of bumps 136, or a second metal layer, through the molding compound 140. The outer surface of the molding compound 140 may be coplanar with the outer surface of the plurality of bumps 136. In various embodiments, the molding compound 140 may initially cover the plurality of bumps 136, but may then be backgrinded to expose the plurality of bumps through the molding compound 140. In various embodiments, the method for forming a semiconductor device may include a backgrinding ring 96, the molding compound 140, or both the ring and the molding compound. The wafer 76 may then be diced into a plurality of semiconductor devices using any dicing method previously disclosed herein. The plurality of diced semiconductor devices may be the same as the semiconductor device 62 shown in Figure 7 .

[0103] See Figure 25A - Figure 25B , which shows a process for dicing a wafer with a backside protection (BSP) layer applied thereto. Figure 25A - Figure 25B The method shown may be incorporated into any method embodiment previously disclosed herein. As Figure 25AAs shown, the wafer 142 can be coupled to the metal layer 144. In various embodiments, the metal layer can be coupled to the BSP layer 146. In various embodiments, the BSP layer can be a tape including an epoxy resin and can include glass fillers. In a particular embodiment, the BSP layer can be a wafer backside coating tape sold under the trade name by LINTEC Corporation, Tokyo, Japan. The BSP layer can be coupled to a tape 148 for holding the wafer during dicing of the wafer.

[0104] Figure 25B Shown are the wafer 142, the metal layer 144, and the BSP layer 146 after dicing to form the semiconductor device 150. As Figure 25B shown, the sidewall 152 where the wafer, the metal layer, and the BSP are diced forms a clean cut, meaning that the different layers do not extend into adjacent layers, including the tape 148. In contrast, and referring to Figure 26A - Figure 26B , shown is a process for dicing a wafer without a BSP layer applied thereto. Figure 26A Shown is a wafer 154 coupled to a metal layer 156, which is directly coupled to a tape 158 for holding the wafer during dicing. As Figure 26B shown, which shows the wafer and the metal layer diced into the semiconductor device 160 Figure 26A , the material burrs 162 generated by dicing the metal layer 156 can extend into the tape 158. In various embodiments, dicing a metal layer directly coupled to a non-BSP tape can produce burrs similar to the burrs 162, which can impede removal of the semiconductor device 160 from the tape 158 during die pick-up operations.

[0105] In various embodiments of the semiconductor devices disclosed herein, the thickness of the die can be less than 30 microns.

[0106] In other embodiments, the die is substantially as thick as the metal layer.

[0107] In various embodiments, the molding compound can be directly coupled to the metal layer of the device.

[0108] In various embodiments, the molding compound can be directly coupled above the metal layer.

[0109] In various embodiments of methods of forming semiconductor devices such as those disclosed herein, the method can include forming a conductive layer between the contact pads and the first side of the wafer.

[0110] In various method embodiments, the thickness of the metal layer is substantially the same as the thickness of the wafer.

[0111] In various method embodiments, the thickness of the metal layer is substantially three times the thickness of the wafer.

[0112] In various embodiments of the method, the molding compound may encapsulate the metal layer.

[0113] In various method embodiments, the method further includes coating the groove with a seed layer.

[0114] In various method embodiments, the method includes forming a plurality of bumps over the metal layer.

[0115] In various method embodiments, the method may include coupling the metal layer, the molding compound, or the plurality of bumps to a backside protection layer and then dicing the wafer.

[0116] Where specific embodiments of semiconductor devices and the implementing components, sub-components, methods, and sub-methods are mentioned in the above description, it should be readily apparent that various modifications can be made without departing from their essence, and these embodiments, implementing components, sub-components, methods, and sub-methods can be applied to other semiconductor devices.

Claims

1. A semiconductor device, comprising: a die, the die including a first side and a second side; a contact pad, the contact pad being coupled to the first side of the die; a metal layer, the metal layer being coupled to the second side of the die; and a molding compound, the molding compound being directly coupled to the metal layer; wherein an outer sidewall of the molding compound includes a step facing away from the metal layer; wherein a thickness of the die is less than 30 microns; wherein the contact pad is exposed through a passivation layer coupled above the die; wherein the die is a diced die; wherein the molding compound covers and contacts an outermost sidewall of the metal layer; wherein an outer sidewall of the die is coplanar with an outermost sidewall of the molding compound; and wherein a perimeter of the entire metal layer is less than a perimeter of the die and is located within the perimeter of the die.

2. A semiconductor device, comprising: a die, the die including a first side and a second side; a contact pad, the contact pad being coupled to the first side of the die; a metal layer, the metal layer being coupled to the second side of the die; and a molding compound, the molding compound being directly coupled to an entire first surface of the metal layer and being located above the entire first surface of the metal layer, the entire first surface of the metal layer being opposite to a second surface of the metal layer facing the second side of the die; wherein an outer sidewall of the molding compound includes a step; wherein the die is diced from a wafer; wherein the molding compound covers and contacts an outermost sidewall of the metal layer; wherein an outer sidewall of the die is coplanar with an outermost sidewall of the molding compound; and wherein a perimeter of the entire metal layer is less than a perimeter of the die and is located within the perimeter of the die.

3. A method for forming a semiconductor device, comprising: forming a plurality of contact pads coupled to a first side of a wafer; forming a groove in a second side of the wafer by back-grinding the wafer, the second side being opposite to the first side of the wafer; forming a metal layer in the groove; patterning the metal layer in the groove; coupling a molding compound to the metal layer in the groove; removing a portion of the wafer until the portion of the wafer is coplanar with a plane formed by a portion of the molding compound; and dicing the wafer into a plurality of semiconductor devices.

4. The method according to claim 3, wherein the metal layer is exposed through the molding compound.

5. The method according to claim 3, wherein the molding compound is directly coupled above the metal layer.

6. The method according to claim 3, further comprising thinning the wafer by forming the groove, wherein a portion of the wafer is thinned to less than 30 microns.

7. A method for forming a semiconductor device, comprising: forming a plurality of contact pads coupled to a first side of a wafer; forming a groove in a second side of the wafer by back-grinding the second side of the wafer, the second side being opposite to the first side; forming a metal layer in the groove; forming a plurality of openings in the metal layer; Form a molding compound into the plurality of openings of the metal layer; Remove a portion of the wafer until the portion of the wafer is coplanar with a plane formed by a portion of the molding compound; And Cut the wafer into a plurality of semiconductor devices.

8. The method according to claim 7, further comprising coupling a second metal layer over the metal layer.

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