Semiconductor structure and forming method thereof

Abstract

Embodiments of the present disclosure provide a semiconductor structure including a substrate having devices formed thereon and an interconnect structure electrically coupling the devices into an integrated circuit; a passivation structure formed on the interconnection structure; and a capacitor embedded in the passivation structure, wherein the capacitor includes a first metal-insulator-metal (MIM) stack inserted in the first trench and a second MIM stack formed as a first pillar structure. The embodiment of the invention also provides a method for forming the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced several generations of ICs, each generation being smaller and more complex than the previous one. During the evolution of ICs, the functional density (i.e., the number of interconnected devices per chip area) generally increases, while the geometric size (i.e., the smallest component (or line) that can be created using a manufacturing process) shrinks. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. This shrinking also increases the complexity of IC processing and manufacturing, and similar developments in IC processing and production are required to achieve these advances. For example, capacitors, as passive devices, are important devices in integrated circuits and are widely used for various purposes, such as random access memory (RAM) non-volatile storage devices, decoupling capacitors, or RC circuits. When ICs move to advanced technology nodes with smaller component sizes, capacitors are hardly scalable and cannot be scaled down to small sizes due to capacitor characteristics. There is a large loss of circuit area for capacitors. In addition, existing methods of manufacturing capacitors introduce defects in the capacitors and cause undesirable problems such as stress and induced wafer warpage. Therefore, it is desirable to provide a capacitor structure integrated with other circuit devices and a method of manufacturing the same without the above disadvantages. Summary of the Invention

[0003] According to one aspect of an embodiment of the present application, a semiconductor structure is provided, including: a substrate on which devices and an interconnect structure for electrically coupling the devices into an integrated circuit are formed; a passivation structure formed on the interconnect structure; and a capacitor embedded in the passivation structure, wherein the capacitor includes a first metal-insulator-metal (MIM) stack inserted into a first trench and a second MIM stack formed as a first pillar structure.

[0004] According to another aspect of an embodiment of the present application, a semiconductor structure is provided, including: a substrate on which devices and an interconnect structure for electrically coupling the devices into an integrated circuit are formed; a passivation structure formed on the interconnect structure; and a capacitor embedded in the passivation structure, wherein the passivation structure includes a first number N1 of passivation material layers, and the capacitor includes a second number N2 of metal-insulator-metal (MIM) stacks alternately stacked with the first number N1 of passivation material layers, each of N1 and N2 being greater than 2, and the MIM stack includes a first MIM stack inserted into a first trench and a second MIM stack formed as a first pillar structure.

[0005] According to another aspect of the embodiments of the present application, a method of forming a semiconductor structure is provided, including: forming a device on a substrate; forming an interconnect structure on the device and coupling the device into an integrated circuit; and forming a passivation structure on the interconnect structure, wherein forming the passivation structure includes forming a capacitor embedded in the passivation structure, wherein the passivation structure includes a first number N1 of passivation material layers, and the capacitor includes a second number N2 of metal-insulator-metal (MIM) stacks alternately stacked with the first number N1 of passivation material layers, each of N1 and N2 being greater than 2, and the MIM stack includes a first MIM stack inserted into a first trench and a second MIM stack formed as a first pillar structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1A is a cross-sectional view of an integrated circuit (IC) structure with a capacitor constructed in accordance with some embodiments of the present disclosure;

[0008] Figure 1B is a cross-sectional view of an IC structure with a capacitor constructed in accordance with some embodiments of the present disclosure;

[0009] Figure 2A and Figure 2C is a cross-sectional view of an IC structure with a capacitor constructed in accordance with some embodiments of the present disclosure;

[0010] Figure 2B and Figure 2D is a top view of an IC structure with a capacitor constructed in accordance with some embodiments of the present disclosure;

[0011] Figure 2E is a schematic cross-sectional view of a capacitor constructed in accordance with some embodiments of the present disclosure;

[0012] Figure 3 is a cross-sectional view of an IC structure with a capacitor constructed in accordance with some embodiments of the present disclosure;

[0013] Figure 4A is a cross-sectional view of an IC structure with a capacitor constructed in accordance with some embodiments of the present disclosure;

[0014] Figure 4B is a top view of an IC structure with a capacitor constructed in accordance with some embodiments of the present disclosure;

[0015] Figure 5is a cross-sectional view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0016] Figure 6A is a cross-sectional view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0017] Figure 6B is a top view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0018] Figure 7A is a cross-sectional view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0019] Figure 7B is a top view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0020] Figure 8A is a cross-sectional view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0021] Figure 8B is a top view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0022] Figure 8C is a cross-sectional view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0023] Figure 9A is a cross-sectional view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0024] Figure 9B is a top view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0025] Figure 10A is a cross-sectional view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0026] Figure 10B is a schematic cross-sectional view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0027] Figure 11A and Figure 11C is a cross-sectional view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0028] Figure 11B is a top view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0029] Figure 12A 、 Figure 12B 、Figure 12C , Figure 12D , Figure 12E , Figure 12F , Figure 12G , Figure 12H , Figure 12I , Figure 12J , Figure 12K and Figure 12L are cross-sectional views of an IC structure constructed according to some embodiments of the present disclosure at various manufacturing stages;

[0030] Figure 13A , Figure 13B , Figure 13C , Figure 13D and Figure 13E are cross-sectional views of an IC structure constructed according to some embodiments of the present disclosure at various manufacturing stages;

[0031] Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 14E , Figure 14F , Figure 14G and Figure 14H are cross-sectional views of an IC structure constructed according to some embodiments of the present disclosure at various manufacturing stages;

[0032] Figure 15A , Figure 15B , Figure 15C and Figure 15D are cross-sectional views of an IC structure constructed according to some embodiments of the present disclosure at various manufacturing stages;

[0033] Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 16E , Figure 16F , Figure 16G and Figure 16H are cross-sectional views of an IC structure constructed according to some embodiments of the present disclosure at various manufacturing stages;

[0034] Figure 17A , Figure 17C and Figure 17D is a cross-sectional view of an IC structure with a capacitor constructed according to some embodiments of the present disclosure;

[0035] Figure 17B is a top view of an IC structure with a capacitor constructed according to some embodiments of the present disclosure;

[0036] Figure 18A , Figure 18B , Figure 18C and Figure 18Dis a cross-sectional view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0037] Figure 19A and Figure 19C is a cross-sectional view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0038] Figure 19B is a top view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0039] Figure 20A 、 Figure 20B 、 Figure 20C 、 Figure 20D 、 Figure 20E 、 Figure 20F 、 Figure 20G and Figure 20H are cross-sectional views of an IC structure at various manufacturing stages constructed in accordance with some embodiments of the present disclosure;

[0040] Figure 21A is a cross-sectional view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0041] Figure 21B is a top view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0042] Figure 22A is a cross-sectional view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0043] Figure 22B is a top view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0044] Figure 23A and Figure 23C is a cross-sectional view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0045] Figure 23B is a top view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0046] Figure 24A 、 Figure 24B 、 Figure 24C 、 Figure 24D 、 Figure 24E 、 Figure 24F 、 Figure 24G 、 Figure 24H 、 Figure 24I and Figure 24J are cross-sectional views of an IC structure at various manufacturing stages constructed in accordance with some embodiments of the present disclosure;

[0047] Figure 25A , Figure 25B , Figure 25C , Figure 25D , Figure 25E , Figure 25F , Figure 25G , Figure 25H , Figure 25I and Figure 25J are cross-sectional views of an IC structure constructed in accordance with some embodiments of the present disclosure at various manufacturing stages;

[0048] Figure 26A is a cross-sectional view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0049] Figure 26B is a top view of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure;

[0050] Figure 27A , Figure 27B , Figure 27C , Figure 27D , Figure 27E , Figure 27F , Figure 27G , Figure 27H , Figure 27I , Figure 27J , Figure 27K and Figure 27L are cross-sectional views of an IC structure constructed in accordance with some embodiments of the present disclosure at various manufacturing stages;

[0051] Figure 28A , Figure 28B and Figure 28C are cross-sectional views of an IC structure having a capacitor constructed in accordance with some embodiments of the present disclosure; and

[0052] Figure 29 is a cross-sectional view of an IC structure constructed in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION

[0053] The following disclosure provides many different embodiments or examples for implementing the present disclosure. The present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Additionally, specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional features may be formed between the first and second components. Further, in the present disclosure, forming, connecting to, and / or coupling to another component may include embodiments where components are in direct contact, and may also include embodiments where additional components may be formed between the components.

[0054] Furthermore, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity, and does not in itself determine the relationship between the various embodiments and / or configurations discussed. Additionally, in the following present disclosure, a feature formed on, connected to, and / or coupled to another feature may include embodiments where the features are in direct contact, and may also include embodiments where additional features may be formed between the features. Additionally, to facilitate the disclosure of the relationship between one feature and another, spatial relative terms such as "below", "above", "horizontal", "vertical", "over", "under", "lower", "upper", "top", "bottom", etc., and their derivatives (e.g., "horizontally", "downward", "upward", etc.) are used. Spatial relative terms are intended to cover different orientations of devices including the features. Further, when a number or a range of numbers is described with "about", "approximate", etc., the term is intended to include numbers within a reasonable range including the described number, such as within + / - 10% of the described number, or other values understood by those skilled in the art. For example, the term "about 5 nm" includes a size range from 4.5 nm to 5.5 nm.

[0055] The present disclosure generally relates to integrated circuit (IC) structures and methods of manufacturing the same, and more particularly, to capacitors integrated with other devices, such as in a three-dimensional (3D) IC structure. The IC structure also includes other devices, such as field effect transistors (FETs), fin field effect transistors (FinFETs), and other multi-gate devices. In some examples, the multi-gate device includes a gate-all-around (GAA) device.

[0056] The disclosed IC structure includes one or more capacitors formed in a passivation layer and also disposed within and integrated with a redistribution layer (RDL) in a passivation structure. The IC structure includes a substrate (such as a semiconductor substrate); various devices formed on the substrate (such as field effect transistors, memory devices, other suitable devices, or combinations thereof); an interconnect structure formed on the devices and coupling the devices into an integrated circuit; and a passivation structure formed on the interconnect structure, sealing the devices and the interconnect structure, and providing bonding components (such as aluminum pads) through the passivation structure. The passivation structure includes multiple passivation layers of various passivation materials and also includes a redistribution layer as a conductive structure to redistribute the bonding components and couple the interconnect structure to the bonding components. Specifically, capacitors are formed in the passivation structure, such as decoupling capacitors, capacitors for dynamic random access memory (DRAM) devices, other types of capacitors, or combinations thereof, and are integrated with the RDL structure. In the disclosed embodiments, the capacitors have a metal-insulator-metal (MIM) structure. Portions of the RDL structure are patterned to form the electrodes of the corresponding capacitors. The capacitors are formed together with the RDL structure and the passivation material layers of the passivation structure. The passivation structure includes multiple passivation layers, such as a first passivation layer on the interconnect structure and a second passivation layer above the first interconnect structure. Each passivation layer includes silicon nitride, silicon oxide (such as undoped quartz glass or USG), or combinations thereof. In some embodiments, the RDL includes a first portion extending vertically from the top metal line of the interconnect structure in the first passivation layer and a second portion extending laterally in the second passivation layer. To facilitate some embodiments of the present disclosure, each passivation layer is divided into multiple passivation sub-layers. For example, the first passivation layer is divided into five passivation sub-layers, such as a first passivation sub-layer (Pass1-1), a second passivation sub-layer (Pass1-2), a third passivation sub-layer (Pass1-3), a fourth passivation sub-layer (Pass1-4), and a fifth passivation sub-layer (Pass1-5). It can be understood that the number of passivation sub-layers can be any appropriate number n (where n is an integer, such as 2, 3, 4, 5, 6,...), depending on the respective design and application. In the disclosed embodiments, each passivation layer includes multiple passivation sub-layers and is formed by multiple depositions, so that various electrodes of the capacitor can be formed. For example, the process includes depositing a passivation sub-layer; depositing a first metal layer; patterning the deposited first metal layer into the first electrode of the capacitor; depositing a dielectric layer as the dielectric material layer of the capacitor; depositing a second metal layer; patterning the deposited second metal layer into the second electrode of the capacitor; and depositing another passivation sub-layer. This process can be repeated multiple times (such as 3 times or 5 times) to form multiple metal-dielectric-metal (MIM) stacks disposed in one passivation layer (or multiple passivation sub-layers of one passivation layer) of the passivation structure. These MIM stacks are connected to form a MIM capacitor having a comb structure.For example, an odd number of metal layers are electrically connected to the first electrode of the capacitor, and an even number of metal layers are electrically connected to the second electrode.

[0057] Metal components of the RDL structure (including metal vias and metal lines) are also formed in the passivation structure. Portions of the RDL structure are configured to be properly connected to the electrodes of the capacitor. For example, one metal via of the RDL structure lands on an odd metal layer and is electrically connected to the odd metal layer, while another metal via of the RDL structure lands on an even metal layer and is electrically connected to the even metal layer, thereby forming the first and second electrodes of the capacitor, respectively. Thus, the capacitor is encapsulated in a small circuit area but has a large capacitor area with folding and vertical stacking. Additionally, the stacked MIM structure can be further folded into one or more trenches, thereby further reducing the circuit area occupied by the capacitor. The IC structure integrated with one or more capacitors is described in further detail below.

[0058] Figure 1A is a cross-sectional view of an integrated circuit (IC) structure (or semiconductor structure, or workpiece) 100 constructed in accordance with various aspects of the present disclosure in some embodiments. Figure 1B is a cross-sectional view of a semiconductor structure 100 having fin active regions constructed in accordance with other embodiments. Referring to Figure 1A and Figure 1B collectively describe the semiconductor structure 100 and its manufacturing method. In some embodiments, the IC structure 100 includes a planar active region on which various IC devices are formed, such as planar field effect transistors (FETs), as Figure 1A shown. In some embodiments, the IC structure 100 includes fin active regions on which various IC devices are formed, such as Figure 1B shown.

[0059] The IC structure 100 includes a substrate 102, such as a semiconductor substrate. In some embodiments, the substrate 102 includes a silicon substrate. Alternatively, the substrate 102 may include: an elemental semiconductor, such as silicon or germanium in a crystalline structure; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; or a combination thereof. Possible substrates 102 also include silicon-on-insulator (SOI) substrates. The SOI substrate is fabricated by separation by oxygen implantation (SIMOX), wafer bonding, and / or other suitable methods. The substrate 102 includes a top surface 102S on which two orthogonal directions X and Y are defined, and a normal direction Z is perpendicular to the X and Y directions. The directions X, Y, and Z form a Cartesian coordinate system.

[0060] The substrate 102 also includes various isolation components, such as the isolation component 104 formed on the substrate 102, which defines various active regions on the substrate 102, such as the active region 106. The isolation component 104 uses an appropriate isolation technique, such as shallow trench isolation (STI), to define and electrically isolate various active regions. The isolation component 104 includes one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. The isolation component 104 is formed by any suitable process. As an example, the formation of the STI component 104 includes a lithography process to expose portions of the substrate, etching trenches in the exposed portions of the substrate (e.g., by using dry etching and / or wet etching), filling the trenches with one or more dielectric materials (e.g., by using a chemical vapor deposition (CVD) process), and planarizing the substrate and removing excess portions of the dielectric material by a polishing process (such as a chemical mechanical polishing (CMP) process). In some examples, the filled trenches can have a multi-layer structure, such as a thermal oxide liner layer and a filling layer of silicon oxide, silicon nitride, or both.

[0061] The active region 106 is a region having a semiconductor surface on which various doped components are formed and configured to form one or more devices thereon, such as diodes, transistors, and / or other suitable devices. The active region may include a semiconductor material similar to the bulk semiconductor material of the substrate 102 (such as silicon) or a different semiconductor material, such as silicon germanium (SiGe), silicon carbide (SiC), or multiple semiconductor material layers (such as alternating silicon and silicon germanium layers) formed on the substrate 102 by epitaxial growth to improve performance, such as strain effects to increase carrier mobility.

[0062] In Figure 1B In some of the illustrated embodiments, the active region 106 is three-dimensional, such as a fin active region extending above the isolation component 104. The fin active region protrudes from the substrate 102 and has a three-dimensional profile for more efficient coupling between the channel region (or simply the channel) and the gate electrode of the FET. The fin active region 106 can be formed by selectively etching to recess the isolation component 104, or by selectively epitaxially growing an active region having the same or different semiconductor material as the substrate 102, or by a combination thereof. In some embodiments, the channel region includes multiple vertically stacked channels to form multiple gate transistors, such as a gate-all-around (GAA) field effect transistor.

[0063] The substrate 102 also includes various doped components, such as n-type doped wells, p-type doped wells, source and drain electrodes, other doped components, or combinations thereof, which are configured to form various devices or components of the devices. The IC structure 100 includes various IC devices 110 formed on the substrate 102. The IC devices 110 include field effect transistors (FETs), fin field effect transistors (FinFETs), gate-all-around FETs (GAA FETs), diodes, bipolar transistors, imaging sensors, resistors, capacitors, inductors, memory cells, or combinations thereof. In Figure 1A (or Figure 1B ), the FET is for illustration only.

[0064] The IC structure 100 also includes an interconnect structure 120 formed on the IC devices 110. The interconnect structure 120 includes various conductive components to couple the various IC devices 110 into an integrated circuit. The interconnect structure 120 also includes an interlayer dielectric (ILD) layer 122 to separate and isolate the various conductive components. For example, the interconnect structure 120 includes contacts 124; metal wires 126; and vias 128. The metal wires 126 are distributed in multiple metal layers. In Figure 1A , four metal layers are shown. The top metal wires are labeled with numbers 130 respectively. The contacts 124 provide vertical electrical wiring from the substrate 102 to the metal wires. The vias 128 provide vertical electrical wiring between adjacent metal layers. The various conductive components are formed of one or more conductive materials, such as metals, metal alloys, silicides, other suitable conductive materials, or combinations thereof. For example, the metal wires 126 may include copper, aluminum-copper alloys, other suitable conductive materials, or combinations thereof. The vias 128 may include copper, aluminum-copper alloys, other suitable conductive materials, or combinations thereof. The contacts 124 may include tungsten, silicides, nickel, cobalt, copper, other suitable conductive materials, or combinations thereof. In some examples, the various conductive components may also include barrier layers, such as tantalum and tantalum nitride, titanium and titanium nitride, or other suitable materials. In this embodiment, the top metal wires 130 include copper.

[0065] The ILD layer 122 includes one or more dielectric materials to provide an isolation function for various device components (such as gates) and various conductive components (such as metal wires, contacts, and vias). The ILD layer 122 includes dielectric materials such as silicon oxide, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. In some examples, the low-k dielectric materials include fluorinated silica glass (FSG), carbon-doped silicon oxide, xerogel, aerogel, amorphous fluorocarbon, parylene, BCB (bisbenzocyclobutene), polyimide, and / or other suitable dielectric materials with a dielectric constant much smaller than that of thermally grown silicon oxide. The formation of the ILD layer 122 may include deposition and chemical mechanical polishing (CMP). Deposition may include spin coating, CVD, other suitable deposition techniques, or combinations thereof. The ILD layer 122 may include multiple layers and is co-formed with various conductive components by an appropriate process (such as a damascene process). In some embodiments, the interconnect structure 120 or a portion thereof is formed by deposition and patterning. For example, a metal (or metal alloy) is deposited by physical vapor deposition (PVD) and patterned by a lithography process and etching. Then, the ILD layer 122 is disposed thereon by deposition (and CMP). In some embodiments, the interconnect structure 120 uses a damascene process to form metal wires. In the damascene process, the ILD layer is deposited, further planarized by CMP, and then patterned by lithography and etching to form trenches. One or more conductive materials are deposited to fill the trenches, and another CMP process is applied to remove the excess conductive material and planarize the top surface, thereby forming conductive components. The damascene process can be used to form metal wires, vias, and contacts. A dual damascene process can be applied to form a layer of metal wires and vias adjacent to the metal wires.

[0066] The IC structure 100 further includes a passivation structure 140 formed on the interconnect structure 120 to provide a sealing effect for the IC device 110 and the interconnect structure 120. The passivation structure 140 includes one or more passivation layers 142 and a redistribution layer (RDL) structure 144 formed in the passivation layer. The RDL structure 144 is located above the interconnect structure 120 and electrically connected to the interconnect structure 120 to redistribute bond pads. This redistribution allows connections to be formed from the edge to the center of the IC chip, facilitating flip-chip bonding or other suitable packaging techniques to integrate the IC chip with a circuit board (such as a printed circuit board).

[0067] The RDL structure 144 includes various metal components embedded in the passivation layer 142 and may include metal wires and metal vias configured to electrically connect the top metal wire 130 to the bonding pads according to the designed circuit. The portion of the RDL structure 144 in the opening 152 of the passivation layer 142 serves as the bonding pad 150. In this embodiment, the passivation layer 142 includes a first passivation layer 142-1 and a second passivation layer 142-2 disposed on the first passivation layer 142-1. In the disclosed embodiment, the first passivation layer 142-1 includes redistribution via (RV) holes aligned with the top metal wire 130 such that a portion 148 of the RDL structure 144 is formed in the RV holes and directly contacts the top metal wire 130. The portion 148 of the RDL structure 144 is also referred to as the RV pad 148. The RDL structure 144 extends vertically from the first passivation layer 142-1 to the second passivation layer 142-2 and extends horizontally from the RV pad 148 to the bonding pad 150 to redistribute the bonding pads. According to some embodiments, the RDL structure 144 may include multiple metal layers. In the disclosed embodiment, the first passivation layer 142-1 includes a silicon nitride (SiN) layer and an undoped silica glass (USG) layer on the SiN layer; the second passivation layer 142-2 includes a USG layer and a SiN layer disposed on the USG layer. The passivation structure 140 further includes one or more capacitors 158 formed in the passivation layer. Each passivation layer is further divided into multiple sub-layers, and the capacitor 158 is folded and embedded therein, which will be described in detail later.

[0068] Figure 2A and Figure 2C is a cross-sectional view of the IC structure 100, Figure 2B and Figure 2D is a top view of the IC structure 200, Figure 2EFIG. 0 is a partial cross-sectional view of a portion of an IC structure 100 constructed in accordance with various embodiments. The IC structure 100 includes a substrate 102; various devices 110 (such as field effect transistors, memory devices, other suitable devices, or combinations thereof, not shown) formed on the substrate 102; an interconnect structure 120 formed above the devices 110 and coupling the devices 110 into an integrated circuit; and a passivation structure 140 formed on the interconnect structure 120, sealing the devices 110 and the interconnect structure 120 and providing bonding components (such as aluminum pads (AP)). The passivation structure 140 includes a plurality of passivation layers 142 of various passivation materials and also includes a redistribution layer (RDL) structure 144 as a conductive path to redistribute the bonding components and couple the interconnect structure 120 to the bonding components. Specifically, a capacitor 158, such as a decoupling capacitor, other types of capacitors, or combinations thereof, is formed in the passivation structure 140 together with the RDL structure 144. In the disclosed embodiments, the capacitor 158 has a metal-insulator-metal (MIM) structure. In addition to redistributing the bonding components, portions of the RDL structure 144 are patterned to form electrodes of the corresponding capacitor 158.

[0069] As Figure 2A shown, the capacitor 158 is formed together with the RDL structure 144 and the passivation layers 142 of the passivation structure 140. The passivation structure 140 includes a plurality of passivation layers 142 (such as passivation layers 142-1 and 142-2), and at least one of the passivation layers 142 includes a plurality of sub-passivation layers. For example, the first passivation layer 142-1 includes a first passivation sub-layer (P1-1), a second passivation sub-layer (P1-2), a third passivation sub-layer (P1-3), a fourth passivation sub-layer (P1-4), a fifth passivation sub-layer (P1-5), and a sixth passivation sub-layer (P1-6). In the disclosed embodiments, a plurality of passivation sub-layers (such as P1-1 to P1-6) are formed by multiple depositions such that the conductive plates of the capacitor 158 can be interleaved and stacked with the plurality of passivation sub-layers in the passivation structure 140 to increase the capacitance without increasing the die area occupied. Specifically, the passivation sub-layers and the conductive plates are alternately deposited, and the conductive plates are further patterned by a photolithography process and etching. For example, the process includes depositing a passivation sub-layer (such as P1-1); depositing a first metal layer (or bottom metal layer) 206; patterning the deposited first metal layer 206 into a first metal plate of the capacitor 158; depositing a dielectric material layer 208 as the dielectric layer of the capacitor; depositing a second metal layer (or top metal layer) 210; patterning the deposited second metal layer 210 into a second metal plate of the capacitor 158; and depositing another passivation sub-layer (such as P1-2). This process can be repeated multiple times (as Figure 2A shown, such as 3 times) to form a plurality of metal-insulator-metal (MIM) stacks (such asFigure 2B the three MIM stacks shown). These MIM stacks are further connected to form a MIM capacitor 158 having a comb structure. For example, as described in detail below, the first metal layer 206 is electrically connected to the first electrode 202 of the capacitor 158, and the second metal layer 210 is electrically connected to the second electrode 204. In Figure 2A , the capacitor 158 includes three vertically stacked MIM stacks. It should be understood that the capacitor 158 may include any suitable number of MIM stacks, such as 4, 5, or 6 MIM stacks. For better description, the first metal layer 206, the dielectric layer 208, and the second metal layer 210 of these three MIM stacks can be referred to respectively to avoid confusion. Specifically, the first MIM stack includes a first metal layer (or bottom metal layer) 206-1, a dielectric layer 208-1, and a second metal layer (or top metal layer) 210-1; the second MIM stack includes a first metal layer 206-2, a dielectric layer 208-2, and a second metal layer 210-2; the third MIM stack includes a first metal layer 206-3, a dielectric layer 208-3, and a second metal layer 210-3.

[0070] Part 212 of the MIM stack (such as Figure 2A the second MIM stack in the dashed box) is enlarged and further shown in the Figure 2C cross-sectional view of. The capacitor 158 includes a plurality of MIM stacks (each MIM stack includes a first metal layer 206, a dielectric material layer 208, and a second metal layer 210) stacked and sandwiched between passivation sub-layers (such as P1-3 and P1-4). In various embodiments, each of the first and second metal layers 206, 210 includes any suitable conductive material, such as metal, metal alloy, silicide, other suitable conductive substances, or a combination thereof. In some examples, the first metal layer 206 and the second metal layer 210 include titanium nitride (TiN). In various embodiments, the first metal layer 206 and the second metal layer 210 are deposited by physical vapor deposition (PVD), plating, other suitable deposition methods, or a combination thereof.

[0071] The dielectric material layer (or simply referred to as the dielectric layer) 208 serves as the dielectric medium of the capacitor 158 and includes a high-k dielectric material, a low-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. A high-k dielectric material is a dielectric material whose dielectric constant is greater than that of thermally oxidized silicon. In some embodiments, the high-k dielectric material includes metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides. To further implement these embodiments, the high-k dielectric material includes metal aluminates, zirconium silicate, zirconium aluminate, HfO 2 , ZrO 2 , ZrOx N y 、 HfO x N y 、 HfSi x O y 、 ZrSi x O y 、 HfSi x O y N z 、 ZrSi x O y N z 、 Al 2 O 3 、 TiO 2 、 Ta 2 O 5 、 La 2 O 3 、 CeO 2 、 Bi 4 Si 2 O 12 、 WO 3 、 Y 2 O 3 、 LaAlO 3 、 PbTiO 3 、 BaTiO 3 、 SrTiO 3 、 PbZrO 3 、 Other suitable high-k dielectrics or combinations thereof. In various examples, methods of forming a high-k dielectric material layer include chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), PVD, atomic layer deposition (ALD), molecular beam epitaxy (MBE), other suitable techniques, or combinations thereof. In another example, the high-k dielectric material can be formed by UV ozone oxidation, which includes sputtering a metal film; and in-situ oxidizing the metal film in the presence of ultraviolet light by O 2 2.

[0072] The metal components of the RDL structure 144, including metal vias and metal lines, are also formed in the passivation structure 140. A portion of the RDL structure 144 is configured to correctly connect the plates of the capacitor 158 to the corresponding electrodes 202 and 204 of the capacitor 158. In one example, the first metal via (or RV pad) 148 of the RDL structure 144 lands on the first metal layer 206 and is electrically connected to the first metal layer 206, and the second metal via 148 of the RDL structure 144 lands on the second metal layer 210 and is electrically connected to the second metal layer 210, thereby forming the first and second electrodes (202, 204) of the capacitor 158, as Figure 2AAs further shown. It should be noted that each of the first metal vias 148 contacts the bottom metal layer 206 and the top metal layer 210. However, the bottom metal layer 206 and the top metal layer 210 are patterned such that the capacitor 158 is correctly connected to the first electrode 202 and the second electrode 204, which will be further explained below.

[0073] The first and second metal layers (or bottom and top metal layers) 206 and 210 can have different patterns, such as different shapes, sizes, or combinations thereof, so that the vias 148 can be correctly connected to the corresponding metal layers. Taking the MIM stack between the passivation sub-layers P1-3 and P1-4 as an example. The first metal layer 206 is patterned into a main board 206A ( Figure 2A the right part in) and islands 206B ( Figure 2A the left part of) that are disconnected from each other. The second metal layer 210 is patterned into a main board 210A ( Figure 2A the left part in) and islands 210B ( Figure 2A the right part of) that are disconnected from each other. The main board 206A of the first metal layer 206 and the main board 210A of the second metal layer 210 overlap (in a top view) and sandwich the dielectric material layer 208 therebetween. The overlapping main boards 206A, 210A of the first metal layer 206 and the second metal layer 210 and the dielectric material layer 208 constitute the MIM stack of the capacitor 158, as shown by the dashed box 212 in Figure 2A . The islands 206B of the first metal layer 206 and the islands 210B of the second metal layer 210 are not part of the capacitor 158 and can be omitted. However, the presence of the islands 206B and 210B can effectively reduce the fringe effect and increase the capacitance of the capacitor 158 (or especially the capacitance of the corresponding MIM stack of the capacitor 158). In addition, the main board 206A of the first metal layer 206 extends further to the right such that the first metal via 148 lands thereon, thereby forming the first electrode 202 of the first main board 206A of the MIM stack. Even though the first metal via 148 also lands on the island 210B of the second metal layer 210, the island 210B exists independently and is not connected to the main board 210A, so it is disconnected from the MIM stack. Similarly, the main board 210A of the second metal layer 210 extends further to the left such that the second metal via 148 lands thereon, thereby forming the second electrode 204 of the second main board 210A of the MIM stack. Even though the second metal via 148 also lands on the island 206B of the first metal layer 206, the island 206B exists independently and is not connected to the main board 206A, so it is disconnected from the MIM stack.

[0074] In Figure 2BIn some embodiments shown in the top view, for simplicity, only one MIM stack is shown (e.g., the second MIM stack between the passivation sub-layers P1-3 and P1-4. Note that all labels of various features of the second MIM stack are distinguished from other labels by "-2"). As described above, according to some embodiments, the islands 206-2B of the first metal layer 206-2 and the islands 210-2B of the second metal layer 210-2 may be omitted or may be designed to exist in any appropriate shape. The first metal via 148 (right side) is connected to the first main board 206-2A; the second metal via 148 (left side) is connected to the second main board 210-2A.

[0075] Specifically, the first metal layer 206-2 includes a main board 206-2A having a first opening 222-2. The first metal via 148 lands on the main board 206-2A, while the second metal via 148 lands within the first opening 222-2 and is disconnected from the first main board 206-2A. In the disclosed embodiments, the first metal layer 206-2 further includes an island 206-2B formed within the first opening 222-2, which is small in size so as to have sufficient margin to be disconnected from the first main board 206-2A. To further implement this embodiment, the first opening 222-2 and the island 206-2B may be designed in any appropriate shape, such as square, circular, rectangular, other appropriate shapes or combinations thereof.

[0076] Similarly, in Figure 2B the second metal layer 210-2 includes a main board 210-2A having a second opening 224-2. The second metal via 148 lands on the main board 210-2A, while the first metal via 148 lands within the second opening 224-2 and is disconnected from the second main board 210-2A. In the disclosed embodiments, the second metal layer 210-2 further includes an island 210-2B formed within the second opening 224-2, which is small in size so as to have sufficient margin to be disconnected from the second main board 210-2A. To further implement this embodiment, the second opening 224-2 and the island 210-2B may be designed in any appropriate shape, such as square, circular, rectangular, other appropriate shapes or combinations thereof.

[0077] Referring again to Figure 2B the first main board 206-2A of the first metal layer 206-2 and the second main board 210-2A of the second metal layer 210-2 within the region 226 (including Figure 2A the MIM stack in the dashed box 212 of Figure 2BOnly one MIM stack (e.g., the second MIM stack including the first metal layer 206-2, the dielectric layer 208-2, and the second metal layer 210-2) is depicted. Further note that the dielectric layer 208-2 is not shown in Figure 2B and Figure 2D . Other MIM stacks, each also composed of a stack of a first metal layer 206, a dielectric layer 208, and a second metal layer 210, overlap each other in a top view. The first metal layer 206 (or the second metal layer 210) in different MIM stacks can have the same or different patterns. Figure 2D Two MIM stacks of the first metal layer 206, the dielectric layer 208, and the second metal layer 210 are shown in a top view, showing different patterning ways of the first metal layer 106 (or the second metal layer 210). In Figure 2D the disclosed embodiment shown, for simplicity, only the second and third MIM stacks, especially the corresponding metal layers, are shown.

[0078] In Figure 2D , the third (or first) MIM stack is similar to the second MIM stack in Figure 2B , while the design and configuration of the third MIM stack are different. Specifically, in the second MIM stack, the design and configuration of the first metal layer 206-2, the second metal layer 210-2, the first opening 222-2 of the first metal layer, and the second opening 224-2 of the second metal layer are similar to those in Figure 2B . The third MIM stack includes a first metal layer 206-3, a second metal layer 210-3, a first opening 222-3 of the first metal layer 206-3, and a second opening 224-3 of the second metal layer 210-3 with different designs. The first openings 222-2 and 222-3 are different in size and position but overlap, and the second via 148 is provided in the overlapping area of these first openings. Similarly, the second openings 224-2 and 224-3 are also different in size and position but overlap, and the first via 148 is provided in the overlapping area of these second openings. In Figure 2D the disclosed embodiment shown, the islands 206-2B, 206-3B, 210-2B, and 210-3B may exist or alternatively be omitted.

[0079] The capacitor 158 formed in this way is in Figure 2Eis further shown in. Specifically, capacitor 158 includes a plurality of first metal layers 206 (such as 206-1, 206-2, and 206-3), a plurality of dielectric layers 208 (such as 208-1, 208-2, and 208-3), and a plurality of second metal layers 210 (such as 210-1, 210-2, and 210-3) that are alternately stacked to form a plurality of MIM stackings (three MIM stackings in this example), and they are further connected to form an interleaved capacitor 158. The first metal layers 206 (e.g., 206-1, 206-2, and 206-3) are electrically connected through the first metal vias 148 and the first metal lines of the RDL structure 144 to form a first electrode A; the second metal layers 210 (such as 210-1, 210-2, and 210-3) are electrically connected through the second metal vias 148 and the second metal lines of the RDL structure 144 to form a second electrode B. Capacitor 158 includes N 1 MIM stackings (each stacking having interlayers 206, 208, and 210) embedded in the passivation sublayers (P1-1, P1-2, etc.) of the first passivation layer 142-1. N 1 is any suitable integer, such as 2, 3, 4, 5, etc. In the illustrated embodiment, N 1 is 3. The total capacitance of the interleaved capacitor 158 is C = εAN 1 / d, where ε is the dielectric constant of the dielectric layer 208; A is the area of the first and second metal layers 206, 208; d is the distance between adjacent first and second metal layers or the thickness of one dielectric layer 208. Note that the area of A is the overlapping area of the main board 206A of the bottom metal layer 206 and the main board 210A of the top metal layer 210. According to the above formula, increasing the dielectric constant of the dielectric layer 148 and increasing the area of the conductive layer 146 will effectively increase the capacitance of the interleaved capacitor 158. As described above, in order to increase the capacitance of the interleaved capacitor 158, one or more high-k dielectric materials are used to form the dielectric layer 208. Increasing N 1 will also increase the capacitance of capacitor 158. To further increase the capacitance of the interleaved capacitor 158, the MIM stackings of the first metal layer 206, the second metal layer 210, and the dielectric layer 208 are folded into a deep trench or pillar structure (sometimes also referred to as a fin structure, different from the fin active region) to increase the area of the metal layers 206 and 210 without increasing the package area of the capacitor 158 on the substrate 102, which will be further described later. Note that the pillar structure refers to the MIM stacking formed on or formed as a pillar structure such that the MIM stacking can be vertically folded to reduce the area and increase the capacitance.

[0080] Figure 3is a partial cross-sectional view of an IC structure 100 constructed in accordance with various embodiments. The IC structure 100 further includes a capacitor 158 embedded in a passivation structure 144. However, the IC structure 100 includes a first IC die 302 and a second IC die 304 joined thereto through a bonding interface 306, thereby forming a three-dimensional IC (3DIC) structure having a capacitor 158 extending in the first die 302 and the second die 304. The first IC die 302 and the second IC die 304 are joined in a suitable pattern, such as face-to-face joining. The bonding interface 306 can employ any suitable bonding structure, such as a hybrid bonding structure, where the bonding interface 306 includes a conductive bonding interface and a dielectric bonding interface. The conductive bonding interface includes a conductive component 308 to provide electrical wiring. The conductive component 308 can be bonding pads from the first IC die 302 and the second IC die 304 that are directly bonded together. The dielectric bonding interface can be any suitable dielectric material from the first IC die 302 and the second IC die 304, such as silicon oxide that is directly bonded together to provide bonding strength. For example, a silicon oxide layer is formed on the front side of each IC die, such as on the corresponding passivation structure 140. The RDL structure 144 on each IC die can further include other metal lines, vias, or combinations thereof that are configured to be coupled to the conductive bonding interface such that the capacitor 158 of the first IC die 302 and the capacitor 158 of the second IC die 304 are integrated into a single capacitor (still referred to as capacitor 158). After bonding, the substrate of the second IC die 304 can be removed from the 3DIC structure.

[0081] Figure 4A is a cross-sectional view of the IC structure 100, Figure 4B is a top view of the IC structure 200, Figure 5 is a partial cross-sectional view of a portion of the IC structure 100 constructed in accordance with various embodiments.

[0082] Figure 4A 、 Figure 4B and Figure 5 The IC structures 100 in Figure 4A and Figure 4BIn this case, the IC structure 100 includes a capacitor 158 and an RDL structure 144 embedded in a passivation structure 140. Specifically, the RDL structure 144 includes two or more metal layers (e.g., 144-1 and 144-2); and two or more via layers 148 (148-1 and 148-2) configured to connect to the top metal component 130 of the interconnect structure 120, e.g., connect to pads on the RDL structure 144. Accordingly, the passivation structure 140 also includes two or more passivation layers 142, such as a first passivation layer P1, a second passivation layer P2, a third passivation layer P3, and a fourth passivation layer P4. A first via 148-1 is formed in the first passivation layer P1, a first metal line 144-1 is formed in the second passivation layer P2, a second via 148-2 is formed in the third passivation layer P3, and a second metal line 144-2 is formed in the fourth passivation layer P4.

[0083] In addition, the capacitor 158 extends through multiple passivation layers of the passivation structure 140. The capacitor 158 includes a first MIM stack embedded in the first passivation layer P1 and a second MIM stack embedded in the third passivation layer P3. The first passivation layer P1 includes a first sub-layer P1-1 and a second sub-layer P1-2, with the first MIM stack sandwiched therebetween; the third passivation layer P3 includes a first sub-layer P3-1 and a second sub-layer P3-2, with the second MIM stack sandwiched therebetween.

[0084] The RDL structure 144 includes a first metal line 144-1 formed in the second passivation layer P2 and a second metal line 144-2 formed in the fourth passivation layer P4, a first via 148-1 located below the first metal line 144-1, and a second via 148-2 located on the first metal line 144-1. As Figure 4B shown, the first via 148-1 and the second via 148-2 can be designed to have the same or different positions, shapes, sizes, or combinations thereof. For example, the opening 222-1 of the first metal layer 206-1 in the first passivation layer P1 and the opening 222-2 of the first metal layer 206-2 in the third passivation layer P3 are designed differently in terms of position and size. The opening 224-1 of the second metal layer 210-1 in the first passivation layer P1 and the opening 224-2 of the third metal layer 210-2 in the third passivation layer P3 are designed differently in terms of position and size. Specifically, as Figure 4B shown, the first via 148-1 and the second via 148-2 associated with the first electrode 202 of the capacitor 158 can be designed not to overlap; the first via 148-1 and the second via 148-2 associated with the second electrode 202 of the capacitor 158 can be designed not to overlap. It should be noted that Figure 4A and Figure 4B the layout of the capacitor 158 inFigure 4A and Figure 4B As shown, the corresponding vias land on the corresponding metal layers of the MIM stack.

[0085] Figure 5 is a cross-sectional view of an IC structure 100 having a 3DIC structure, wherein a first IC die 502 and a second IC die 504 are configured to be stacked, bonded together through a bonding interface 306, and sealed in the same package. The bonding structure is similar to Figure 3 the bonding structure in, for example, a face-to-face bonding mode, and has a hybrid bonding interface 306 to provide electrical routing. Each of the first IC die 502 and the second IC die 504 is similar to Figure 4A the IC structure 100 in, for example, the MIM stack extends through multiple passivation layers, and the RDL structure 144 includes multiple metal layers and via layers. Specifically, the MIM stacks on the IC dies 502, 504 are coupled together through the bonding interface 306 to form a capacitor 158.

[0086] Figure 6A is a cross-sectional view of the IC structure 100, Figure 6B is a top view of a portion of the IC structure 100 constructed according to various embodiments. As Figure 6A shown, the IC structure 100 includes one or more capacitors 158 having a 3D structure, formed in trenches 602, column structures 604, or both, such that the MIM stack is inserted into one or more trenches 602, folded into one or more column structures 604, or a combination thereof, thereby increasing the capacitance of the capacitor 158 and reducing the package area. The MIM stack inserted into the trench 602 is also referred to as the trench MIM stack 602; the MIM stack formed as a column structure 604 is also referred to as the column MIM stack 604. As Figure 6AAs shown, the IC structure 100 includes a trench MIM stack 602 that is folded and inserted into a deep trench and a pillar MIM stack 604 that is folded into a pillar structure. In the disclosed embodiments, the pillar MIM stack 604 and the trench MIM stack 602 are aligned and overlapped. The trench MIM stack 602 and the pillar MIM stack 604 can be connected to form different capacitors 158, or alternatively connected into one capacitor 158. The trench MIM stack 602 and the corresponding pillar MIM stack 604 are aligned and stacked on top of each other to form a hybrid MIM stack in a cross configuration. The 3D MIM cell 606 includes one or more trench MIM stacks 602, one or more pillar MIM stacks 604, one or more hybrid MIM stacks, or combinations thereof that are vertically stacked, aligned, or optionally offset. In some embodiments, the 3D MIM cell 606 can include one or more trench MIM stacks, one or more pillar MIM stacks, and one or more planar MIM stacks in different configurations. A planar MIM stack is a MIM stack formed on a flat surface or a substantially flat surface. In Figure 6A the illustrated embodiment, the 3D MIM cell 606 includes one hybrid MIM stack and one trench MIM stack 602 that are vertically stacked together. This will be further described later in Figure 6B regard to the shape of a 3D MIM cell 606. Design considerations for various dimensions take into account the packaging density, capacitance, uniformity, and processing quality of the capacitor 158. The MIM stack inserted into the deep trench 602 and the MIM stack formed on the pillar structure 604 can have different dimensions to obtain other advantages such as reduced stress. Note that the dimensions (including width and length) of the MIM stack associated with the trench 602 are defined within the dashed box T, and the dimensions of the MIM stack associated with the pillar structure 604 are defined within the dashed box F.

[0087] In the disclosed embodiments, the 3D MIM cell 606 has a height H and a width W. According to some embodiments, the trench 602 and the pillar structure 604 have different widths such that the trench MIM stack 602 and the pillar MIM stack 604 have the same width W. The MIM stack inserted into the deep trench 602 has a height Ht, and the MIM stack formed on the pillar structure 604 has a height Hf. The 3D MIM cell 606 has a periodic dimension (or pitch P) and a spacing S. In some embodiments, the height H ranges between 0.4 μm and 1.6 μm; the pitch P ranges between 0.2 μm and 0.8 μm; the width W is between 0.1 μm and 0.4 μm; the spacing S is between 0.1 μm and 0.4 μm; the height Ht is between 0.2 μm and 0.8 μm; the height Hf is between 0.2 μm and 0.8 μm. The sidewalls of the MIM stack inserted into the deep trench 602 and the sidewalls of the MIM stack formed on the pillar structure 604 are perpendicular or have angles within a certain range. In some embodiments, the angle of the sidewall of the MIM stack inserted into the deep trench 602 with respect to the plane defined by the X and Y directions is between 75° and 90°; and the angle of the sidewall of the MIM stack formed on the pillar structure 604 with respect to the plane defined by the X and Y directions is between 90° and 105°. The thicknesses of the metal layers 206 and 210 are between 200 angstroms and 700 angstroms between.

[0088] In some embodiments, the top metal layer 210 of the pillar MIM stack 604 and the bottom metal layer 206 of the overlying trench MIM stack 602 are in direct contact with each other. In this case, they are connected to the same capacitor electrode. Additionally, the bottom metal layer 206 of the pillar MIM stack 604 and the top metal layer 210 of the overlying trench MIM stack 602 are connected together through other conductive components (including via 148 and wire 144) to form another capacitor electrode, as Figure 4A shown.

[0089] In some other embodiments, the top metal layer 210 of the pillar MIM stack 604 and the bottom metal layer 206 of the overlying trench MIM stack 602 may be isolated from each other and separated by a dielectric layer (such as a portion of the passivation layer 142). In this case, the trenches in the overlying trench MIM stack 602 are formed in the overlying passivation layer 142, and the bottom of the passivation layer 142 remains in the trenches to provide proper isolation. Thus, depending on the specific design, the electrical connection of the various MIM stacks 602 and 604 can be achieved through other conductive components, including via 148 and wire 144, as Figure 4A shown.

[0090] As Figure 6BAs shown, the 3D MIM unit 606 is configured as an array having various configurations and geometries, such as the square shape shown at (1) in the top view (1), the rectangular shape shown at (2), and the circular shapes shown at (3) and (4). The configuration of the 3D MIM unit 606 can be aligned along the X and Y directions, or aligned with a dense stacking density without alignment, or aligned along a direction inclined from the X and Y directions. Note that the dimensions T and F have been defined in Figure 6A as follows.

[0091] Figure 7A is a cross-sectional view of the IC structure 100, Figure 7B and is a top view of a portion of the IC structure 100 constructed according to various embodiments. The IC structure 100 includes one or more capacitors 158 having a 3D structure and formed in the trenches 602, formed in the trenches 602 or the column structures 604 such that the MIM stack is inserted into one or more trenches 602, folded over one or more column structures 604, or a combination thereof, thereby increasing the capacitance of the capacitor 158 and reducing the package area. As Figure 7A shown, the IC structure 100 includes a MIM stack folded and inserted into the deep trench 602, also denoted by the numeral 602; and a MIM stack folded over the column structure 604, also denoted by the numeral 604, without confusion. In the disclosed embodiments, the column MIM stack 604 and the trench MIM stack 602 are aligned and overlapped. The trench MIM stack 602 and the column MIM stack 604 can form different capacitors 158, or alternatively be connected to form one capacitor 158. In some embodiments, the trench MIM stack 602 and the corresponding column MIM stack 604 are aligned and stacked on top of each other to form a 3D MIM unit 606. The shape of a 3D MIM unit 606 will be further described later in Figure 6B detail. Various dimensions are designed in view of the package density, capacitance, uniformity, and processing quality of the capacitor 158.

[0092] In the disclosed embodiments, the 3D MIM cell 606 has a height H and a width W. According to the specific embodiments disclosed, the trench MIM stack 602 and the pillar MIM stack 604 have the same width W. The trench MIM stack 602 has a height Ht, and the pillar MIM stack 604 has a height Hf. The 3D MIM cell 606 has a periodic dimension (or pitch) P and a spacing S. In various embodiments, the height H ranges between 0.4 μm and 1.6 μm; the pitch P ranges between 0.2 μm and 0.8 μm; the width W is between 0.1 μm and 0.4 μm; the spacing S is between 0.1 μm and 0.4 μm; the height Ht is between 0.2 μm and 0.8 μm; the height Hf is between 0.2 μm and 0.8 μm. The sidewalls of the trench MIM stack 602 and the sidewalls of the pillar MIM stack 604 are vertical or have an angle within a certain range. In some embodiments, the angle of the sidewall of the trench MIM stack 602 with respect to the plane defined by the X and Y directions is between 75° and 90°; and the angle of the sidewall of the pillar MIM stack 604 with respect to the plane defined by the X and Y directions is between 90° and 105°. The thicknesses of the metal layers 206 and 210 are between 200 angstroms and 700 angstroms between.

[0093] The trench MIM stack 602 and the pillar MIM stack 604 may have different sizes and different shapes to obtain other advantages, such as reducing stress. It should be noted that the dimensions (including width and length) of the MIM stack associated with the trench 602 are defined in the dashed box T, and the dimensions of the MIM stack associated with the pillar structure 604 are defined in the dashed box F. As Figure 7B shown, the 3D MIM cell 606 is configured to have an array with various configurations and geometries. For example, the trench MIM stack 602 has a rectangular shape (or trough shape), and the pillar MIM stack 604 has a square shape, as Figure 7B shown in (1) of Figure 7B . The trench MIM stack 602 has a square shape, and the pillar MIM stack 604 has a rectangular shape, as Figure 7B shown in (2) of Figure 7B . The trench MIM stack 602 has a rectangular shape, and the pillar MIM stack 604 has a rectangular shape but smaller in size, as Figure 7B shown in (3) of Figure 7B . In Figure 7B shown in (4), the trench MIM stack 602 has a rectangular shape longitudinally oriented along the Y direction, and the pillar MIM stack 604 has a rectangular shape longitudinally oriented along the X direction. Additionally, the trench MIM stack 602 and the pillar MIM stack 604 may have different sizes, as Figure 7B shown in (1) to Figure 7B shown in (4) of

[0094] Figure 8A is a cross-sectional view of the IC structure 100, Figure 8B is a top view of the IC structure 200, Figure 8C is a cross-sectional view of a portion of the IC structure 100 constructed according to various embodiments. Similarly, the IC structure 100 includes a capacitor 158 in a 3D structure having 3D MIM cells 606. In Figure 8A the present embodiment shown, the 3D MIM cell 606 includes two hybrid MIM stacks vertically aligned and stacked on top of each other. As previously described, each hybrid MIM stack includes a trench MIM stack 602 and a pillar MIM stack 604 stacked thereon. In the disclosed embodiments, the pillar MIM stack 604 and the trench MIM stack 602 in each 3D MIM cell 606 are vertically aligned and overlapped. The metal layers forming the 3D MIM cell 606 include metal layers 802, 804, 806, 808, 812, 814, 816, and 818 configured as shown in Figure 8A and are isolated from each other by dielectric layers 842, 844, 846, 848, 850, and 852. In the present embodiment, the metal layers 802 and 804 and the dielectric layer 842 sandwiched therebetween form one or more first trench MIM stacks 602 as part of the capacitor 158. The metal layers 806 and 808 and the dielectric layer 846 sandwiched therebetween form one or more first pillar MIM stacks 604 as part of the capacitor 158. Similarly, the metal layers 812 and 814 and the dielectric layer 848 sandwiched therebetween form one or more second trench MIM stacks 602; the metal layers 816 and 818 and the dielectric layer 852 sandwiched therebetween form one or more second pillar MIM stacks 604. The first trench MIM stack 602 and the first pillar MIM stack 604 are aligned and stacked, and are also isolated from each other by a dielectric layer 844 having a first cross configuration. The second trench MIM stack 602 and the second pillar MIM stack 604 are aligned and stacked, and in addition, are isolated from each other by a dielectric layer 850 having a second cross configuration. The first trench MIM stack 602, the first pillar MIM stack 604, the second trench MIM stack 604, and the second pillar MIM stack 602 are further vertically aligned and configured to form the 3D MIM cell 606. In Figure 8A , a plurality of 3D MIM stacks 606 are configured in an array and are electrically connected to the capacitor 158 through vias 148 and metal lines 144 of the RDL structure. Specifically, the various metal layers are patterned to form various openings or islands such that the vias 148 are correctly connected to the corresponding metal layers. To form the interleaved capacitor 158, as shown further in Figure 8B .

[0095] Figure 8BShows the layout and configuration of various features of capacitor 158. Specifically, these metal layers are patterned to have openings (or islands), such as openings 832, 834, and 836, such that a certain via 148 can appropriately contact some metal layers while avoiding contact with other metal layers. In Figure 8B , only the metal layers 802, 804, and 808 in the passivation layers P1-1 and P1-2 are shown. The metal layers 812, 814, and 818 in the passivation layers P1-3 and P1-4 can have similar dimensions, shapes, and positions, such as similar openings described below. The metal layer 806 is patterned as a plug directly landing on the metal layer 804 and is thus connected to the same electrode. For simplicity, Figure 8B , the metal layer 806 is not shown. Similarly, the metal layer 816 is patterned as a plug directly landing on the metal layer 814 and is thus connected to the same electrode. In some embodiments, the metal layer 802 has an opening 832; the metal layer 808 has an opening 836; the metal layer 804 has an opening 834. The 3D MIM cell 606 can have a rectangular shape or other suitable shape with uniform spacing and width.

[0096] In the disclosed embodiments, the IC structure 100 includes the following dimensions, which are designed to improve packaging density, capacitance, and pattern uniformity. The metal layer 802 has a width Wc, the metal line 144 of the RDL structure has a width Wr, the top metal layer 130 has a width Wm, and the opening 832 has a size Do. The spacing S1 defines the spacing between the 3D MIM cell 606 and the nearest edge of a metal layer, such as the metal layer 808, and the spacing S2 defines the spacing between the 3D MIMO cell 606 and the metal layer opening. The spacing S3 defines the margin between the openings. M1 defines the margin between the via 148 and the metal line 144 of the RDL structure; M2 defines the margin between the via 148 and the top metal line 130; M3 defines the margin between the openings 832 and 836; M4 defines the margin between the metal layers 804 and 808. The 3D MIM cells 606 are periodically configured with a pitch P. In some embodiments, at least one set of metal lines in the top metal layer 130 and the metal lines 144 of the RDL structure can be designed to have similar shapes and dimensions.

[0097] In various embodiments, the through - hole 148 has dimensions from 0.8μm x 0.8μm to 2.7μm x 2.7μm; the metal lines of the RDL structure 144 have a width Wr ranging between 1.2μm and 35μm; Wm ranges between 1.2μm and 20μm; M1 or M2 is equal to or greater than 0.2μm; Wc ranges between 1μm and 300μm; Do ranges between 2.5μm and 5μm; S3 ranges between 0.05μm and 0.2μm; each of M3 and M4 ranges between 0.05μm and 0.2μm; S1 and S2 are both equal to or greater than 0.1μm; P ranges between 0.2μm and 0.8μm. The remaining parameters are as Figures 6A to 6B shown and will not be repeated.

[0098] Figure 8A The portion of the IC structure 100 within the dashed box 822 in Figure 8C is enlarged and further shown in . The IC structure 100 includes dielectric layers 842, 844, 846, and 848 sandwiched between adjacent metal layers. For example, dielectric layer 842 is sandwiched between metal layers 802 and 804; dielectric layer 844 is sandwiched between metal layers 804 and 808 (or 806 in some portions); dielectric layer 846 is sandwiched between metal layers 806 and 808; dielectric layer 848 is sandwiched between metal layers 812 and 814. These dielectric layers include one or more dielectric materials, such as high - k dielectric materials, other suitable dielectric materials, or combinations thereof, as described above. The thickness of these dielectric layers depends on the corresponding capacitors in each application. The metal layers include any suitable conductive material as described above. For example, the metal layers include titanium nitride, other conductive materials, or combinations thereof. The thickness of these metal layers (802 to 818) is between 200 angstroms and 700 angstroms .

[0099] Figure 9A is a cross - sectional view of the IC structure 100, Figure 9B is a cross - sectional view of a portion of the IC structure 100 constructed according to various embodiments. Specifically, Figure 9A the portion of the IC structure 100 within the dashed box 822 in Figure 9B is enlarged and further shown in The IC structure 100 includes dielectric layers 842, 844, 846, 848, 850, and 852 sandwiched between adjacent metal layers. Similarly, the IC structure 100 includes a 3D - structured capacitor 158 having trench MIM stacks 602 and pillar MIM stacks 604 configured in one or more 3D MIM cells 606. In the disclosed embodiments, each 3D MIM cell 606 includes two pillar MIM stacks 604 and two trench MIM stacks 602 that are vertically aligned and overlapped to form two hybrid MIM stacks.

[0100] Figure 9A and Figure 9B the IC structure 100 in Figures 8A to 8C is similar to the IC architecture 100 in Figure 9A and Figure 9B However, the IC structure 100 in

[0101] the above-mentioned Figures 6A to 9B various embodiments of the IC structure 100 described in

[0102] Figure 10A show a cross-sectional view of the IC structure 100 according to various embodiments, Figure 10B show a cross-sectional view of a part of the IC structure 100. Specifically, Figure 10A only shows a part of the capacitor 158 of the IC structure 100, while Figure 10B only shows an entire IC die on which the corresponding IC structure 100 is formed.

[0103] In Figure 10A the (1) in Figure 10B and the first embodiment shown in the (1) in Figure 10B the IC structure 100 only includes the pillar MIM stack 604 without the trench MIM stack 602, and the IC die will be deformed and warped, as shown in

[0104] In Figure 10A the (2) in Figure 10B and the second embodiment shown in the (2) in Figure 10B the IC structure 100 only includes the trench MIM stack 602 without the pillar MIM stack 604, and the IC die will be deformed and warped, as shown in

[0105] In Figure 10A the (3) in Figure 10BIn the third embodiment shown in (3) therein, the IC structure 100 includes a trench MIM stack 602 and a pillar MIM stack 604. To further implement this embodiment, the trench MIM stack 602 and the pillar MIM stack 604 are vertically aligned, matched (in terms of size, composition, or both), and stacked to form a hybrid MIM stack 606, thereby eliminating the stress generated by both. Therefore, the deformation of the IC die will be eliminated or minimized, so that the IC die has no warpage, as Figure 10B shown in (3) therein.

[0106] Figure 11A is a cross-sectional view of the IC structure 100, Figure 11B is a top view of the IC structure 200, Figure 11C is a partial cross-sectional view of a portion of the IC structure 100 constructed according to various embodiments. As Figure 11A shown, the IC structure 100 includes one or more capacitors 158, and the capacitor 158 has 3D MIM cells 606, and each cell has one or more trench MIM stacks 602 and one or more pillar MIM stacks 604 configured in a cross shape. Specifically, each 3D MIM cell 606 includes two hybrid MIM stacks that are vertically aligned and stacked. As described above, the hybrid MIM stack includes a trench MIM stack 602 and a pillar MIM stack 604 that are vertically aligned and stacked in a cross configuration. Each 3D MIM cell 606 may include N (such as three) hybrid MIMs that are vertically aligned and stacked together. It is understood that the number N can be any suitable integer, such as 2, 3, 4, etc. In Figure 11A the present embodiment shown, each 3D MIM cell 606 includes two hybrid MIM stacks that are vertically aligned and stacked together. In some embodiments, the hybrid MIM stacks may be vertically spaced apart.

[0107] Figure 11B A portion of the IC structure 100 is shown in a top view. Specifically, Figure 11B only the metal layers 902 and 904 are shown in. Specifically, the metal layer 902 includes an opening 952 such that the metal via 148 on the left can land on the metal layer 904 without landing on the metal layer 902. The metal layer 902 may include islands in the opening 952, as Figure 11A shown, which will change the electric field distribution in the capacitor 158 and reduce the edge effect. The island is optional and can be omitted. Similarly, the metal layer 904 includes an opening 954 such that the metal via 148 on the right can land on the metal layer 902 without landing on the metal layer 904. The metal layer 904 may include islands in the opening 954, as Figure 11AAs shown. In the disclosed embodiments, metal layers 910 and 918 may have a pattern and openings similar to or the same as those of metal layer 902; and metal layers 912 and 920 may have a pattern and openings similar to or the same as those of metal layer 904.

[0108] Similarly, the IC structure 100 may also include a 3D IC structure, such as Figure 11C shown. Figure 11C The IC structure 100 in [reference] includes a first IC die 302 and a second IC die 304 joined to it through a bonding interface 306, thereby forming a 3D IC structure that has a capacitor 158 extending in the first die 302 and the second die 304. The first IC die 302 and the second IC die 304 are joined in a suitable pattern, such as face-to-face bonding. The bonding interface 306 may employ any suitable bonding structure, such as a hybrid bonding structure, similar to Figure 3 those described in [reference]. The capacitor structure in the first IC die 302 and the capacitor structure in the second IC die 304 are similar to Figure 11A the capacitor 158 in [reference]. However, these capacitor structures are electrically connected and integrated together through the conductive traces of the bonding interface 306. In the disclosed embodiments, the capacitor structure of the first IC die 302 and the capacitor structure of the second IC die 304 are integrated into a single capacitor (still referred to as capacitor 158).

[0109] Figures 12A to 12L is a partial cross-sectional view of the IC structure 100 at different manufacturing stages constructed according to some embodiments. The IC structure 100 and its manufacturing method are described jointly by Figures 12A to 12L [references].

[0110] In Figure 12A [reference], an IC structure (or workpiece) 100 is provided. The IC structure 100 includes a substrate 102 and an interconnect structure 120. Figure 1A and Figure 1B describe the substrate 102, the devices formed thereon, and the interconnect structure 120. For simplicity, they are not described again here. For example, the interconnect structure 120 includes top metal lines 130. In Figure 12A [reference], a first passivation sub-layer P1-1 is formed on the workpiece 100. The first passivation sub-layer P1-1 includes silicon nitride with a thickness between and [specified values]. The formation of the first passivation sub-layer P1-1 includes deposition (e.g., by CVD) and chemical mechanical polishing (CMP).

[0111] In Figure 12BIn [the above], the first passivation sub-layer P1-1 is patterned by a patterning process, which also includes a photolithography process to form a patterned photoresist layer 962, and an etching process of using the patterned photoresist layer 962 as an etching mask to pattern the passivation sub-layer P1-1. The photolithography process includes coating, exposure, and development of the photoresist layer 962 to form the patterned photoresist layer 962, and may also include various baking processes, and the photoresist layer 962 is removed after etching by wet stripping or plasma ashing. The etching process may include wet etching, dry etching, or a combination thereof.

[0112] In Figure 12C [the above], a MIM stack is deposited and patterned. For example, a bottom metal layer 902 is deposited and patterned. A dielectric layer 932 is deposited and may be patterned. A top metal layer 904 is deposited and patterned, thereby forming one or more trench MIM stacks 602. The bottom and top metal layers 902, 904 may include any suitable conductive material, such as titanium nitride, tantalum, tantalum nitride, titanium, other suitable metals, or a combination thereof. The dielectric layer 932 may include any suitable dielectric material, such as a high-k dielectric material. High-k dielectric materials include SiN x ; Ta 2 O 5 、Al 2 O 3 、ZrO 2 and HfO 2 、HfAlO、ZrAlO or a combination thereof. The metal layers 802, 804 may be deposited by any suitable method, such as atomic layer deposition (ALD), physical vapor deposition (PVD), other suitable methods, or a combination thereof. The dielectric layer 932 may be deposited by chemical vapor deposition (CVD), ALD, other suitable methods, or a combination thereof. Each of the metal layers 902 and 904 may have a thickness between and . The thickness range of the dielectric layer 932 may be between and .

[0113] In Figure 12D [the above], another dielectric layer 934 is deposited by a suitable method such as CVD. The thickness range of the dielectric layer may be between and .

[0114] In Figures 12E to 12H [the above], another metal layer 906 is deposited and patterned. The thickness range of the metal layer 906 may be between and . As shown in Figure 12E the metal layer 906 is deposited; as shown in Figure 12F the photoresist layer 964 is coated; asFigure 12G As shown, the photoresist layer 964 is patterned by exposure and development; as Figure 12H shown, the patterned photoresist layer 964 is used as an etch mask, and the metal layer 906 is patterned by etching.

[0115] In Figure , another dielectric layer 936 (similar to dielectric layers 932 and 934) is further deposited on the metal layer 906, and another metal layer 908 is deposited and patterned, thereby forming the pillar MIM stack 604. The thickness of the metal layer 908 can range between and .

[0116] In ​ , the second passivation sub-layer P1-2 is deposited and planarized by CMP. The thickness of the second passivation sub-layer P1-2 can range between and .

[0117] In ​ , the second passivation sub-layer P1-2 is patterned by a patterning process further including a photolithography process and an etching process to form a trench 966 for the trench MIM stack 602. The photolithography process includes coating, exposure, and development of a photoresist layer 968, and may also include various baking processes, and the photoresist is removed by wet stripping or plasma ashing after etching. The etching process can include wet etching, dry etching, or a combination thereof.

[0118] In ​ , the MIM stack is deposited and patterned. For example, the bottom metal layer 946 is deposited and patterned, thereby forming the trench MIM stack 602. A dielectric layer is deposited and may be patterned. For simplicity, the dielectric layer is not shown. The top metal layer 948 is deposited and patterned, thereby forming the trench MIM stack 602, which is similar in formation and composition to that in ​ .

[0119] ​ Similar to ​ , a dielectric layer 940 is deposited. The dielectric layer 940 includes any suitable dielectric material, such as a high-k dielectric material. The thickness of the dielectric layer 940 can range between and .

[0120] In ​ , another MIM is deposited and patterned, thereby forming the pillar MIM stack 604. Specifically, the metal layer 914 is deposited and patterned to form metal pillars. Another dielectric layer 942 is further deposited on the metal layer 914. Another metal layer 916 is deposited and patterned, jointly forming the pillar MIM stack 604.

[0121] In Figure 13C , the third passivation layer P1-3 is deposited and planarized by CMP. In the disclosed embodiments, the third passivation layer P1-3 includes silicon nitride. The thickness range of the third passivation layer P1-3 can be between and .

[0122] In Figure 13D , the workpiece 100 is patterned to form an opening 970 such that the top metal component 130 is exposed within the trench 970. In the disclosed embodiments, the trench 970 extends through the passivation layers P1-1, P1-2, and P1-3. The patterning process also includes a photolithography process and an etching process. The photolithography process includes coating, exposing, and developing a photoresist layer 972 to form a patterned photoresist layer 972, and may also include various baking processes, and the photoresist is removed by wet stripping or plasma ashing after etching. The etching process can include wet etching, dry etching, or a combination thereof. The etching process uses the patterned photoresist layer 972 as an etching mask. The trench depth is between and .

[0123] In Figure 13E , one or more conductive materials are deposited to fill the opening 970, thereby forming a via 148 and a metal wire 144 as electrodes 202 and 204 of the capacitor 158. In the disclosed embodiments, the conductive material includes a metal, a metal alloy, other conductive materials, or a combination thereof. In a further embodiment, the conductive material includes copper. The formation of the metal wire 144 and the via 148 includes deposition, CMP, and patterning. Deposition can include PVD, plating, other suitable methods, or a combination thereof. In some embodiments, deposition includes depositing a seed layer by PVD and plating on the seed layer, such as electroless plating deposition (ECP). Thereafter, the second passivation layer P2 is deposited and planarized by CMP. In some embodiments, the second passivation layer P2 includes silicon nitride. In some other embodiments, the second passivation layer P2 includes silicon nitride and USG. The above method can be used to form various IC structures 100, such as the IC structure 100 in Figure 11A according to some embodiments.

[0124] Figures 14A to 14H is a partial cross-sectional view of the IC structure 100 constructed according to some embodiments at different manufacturing stages. The IC structure 100 and its manufacturing method are described jointly by Figures 14A to 14H . Figures 14A to 14H Similar to that described in Figures 12A to 12J . For simplicity, similar descriptions are not repeated here.

[0125] In Figure 14ATherein, an IC structure (or workpiece) 100 is provided. The IC structure 100 includes a substrate 102 and an interconnect structure 120. Figure 1A and Figure 1B The substrate 102, the devices formed thereon, and the interconnect structure 120 are described in. For simplicity, they will not be described again here. For example, the interconnect structure 120 includes top metal lines 130. In Figure 14A therein, a first passivation sub-layer P1-1 is formed on the workpiece 100. The first passivation sub-layer P1-1 includes silicon nitride with a thickness between and The formation of the first passivation sub-layer P1-1 includes deposition (e.g., by CVD) and CMP.

[0126] In Figure 14B therein, the first passivation sub-layer P1-1 is patterned by a patterning process that also includes a lithography process and an etching process. The lithography process includes coating, exposing, and developing a photoresist layer 974, and may also include various baking processes, and removing the photoresist after etching by wet stripping or plasma ashing. The etching process may include wet etching, dry etching, or a combination thereof.

[0127] In Figure 14C therein, a MIM stack is deposited and patterned. For example, a bottom metal layer 902 is deposited and patterned. A dielectric layer 932 is deposited and may be patterned. A top metal layer 904 is deposited and patterned, thereby forming a trench MIM stack 602. The bottom and top metal layers 902, 904 may include any suitable conductive material, such as titanium nitride, tantalum, tantalum nitride, titanium, other suitable metals, or a combination thereof. The dielectric layer may include any suitable dielectric material, such as a high-k dielectric material. The metal layers may be deposited by any suitable method, such as ALD, PVD, other suitable methods, or a combination thereof. The dielectric layer 932 may be deposited by CVD, ALD, other suitable methods, or a combination thereof. Each of the metal layers 902 and 904 may have a thickness between and The thickness range of the dielectric layer may be between and between.

[0128] In Figure 14D therein, another dielectric layer 934 is deposited by a suitable method such as CVD. The thickness range of the dielectric layer 934 may be between and between.

[0129] In Figure 14ETherein, another MIM stack is deposited and patterned to form a pillar MIM stack 604. Specifically, a metal layer 906 is deposited and patterned to form metal pillars. Another dielectric layer 936 is deposited on the metal layer 906. Another metal layer 908 is deposited and patterned, together forming the pillar MIM stack 604.

[0130] In Figure 14F therein, a second passivation sub-layer P1-2 is deposited and planarized by CMP. The thickness range of the second passivation sub-layer P1-2 can be between and .

[0131] In Figure 14G therein, the workpiece 100 is patterned to form an opening 976 such that the top metal component 130 is exposed within the trench 976. In the disclosed embodiments, the trench 976 extends through the passivation sub-layers P1-1 and P1-2. The patterning process also includes a lithography process and an etching process. The lithography process includes coating, exposing, and developing a photoresist layer 978 to form a patterned photoresist layer 977, and may also include various baking processes, and removing the photoresist by wet stripping or plasma ashing after etching. The etching process may include wet etching, dry etching, or a combination thereof. The etching process uses the patterned photoresist layer 978 as an etching mask.

[0132] In Figure 14H therein, one or more conductive materials are deposited to fill the opening 954, thereby forming through-holes 958 and metal lines 960 as electrodes 202 and 204 of the capacitor 158. In the disclosed embodiments, the conductive material includes metal, metal alloy, other conductive materials, or a combination thereof. In a further embodiment, the conductive material includes copper. The formation of the metal lines 960 and through-holes 958 includes deposition, CMP, and patterning. Deposition may include PVD, plating, other suitable methods, or a combination thereof. In some embodiments, deposition includes depositing a seed layer by PVD and plating on the seed layer, such as electroless chemical plating (ECP). Thereafter, a second passivation layer P2 is deposited and planarized by CMP. In some embodiments, the second passivation layer P2 includes silicon nitride. In some other embodiments, the second passivation layer P2 includes silicon nitride and USG. According to some embodiments, the above method can be used to form Figure 8A the IC structure in

[0133] Figures 15A to 15D is a partial cross-sectional view of an IC structure 100 constructed according to some embodiments at different manufacturing stages. The IC structure 100 and its manufacturing method are described jointly by Figures 15A to 15D . The IC structure 100 and its manufacturing method continue from Figures 14A to 14H .

[0134] Figure 15A WithFigure 14H Same. An IC structure (or workpiece) 100 is provided.

[0135] In Figure 15B it, a hybrid MIM stack 606 is formed in the third passivation layer P3, similar to or the same as the method described in Figures 14A to 14F it. The third passivation layer P3 includes passivation sub-layers P3-1 and P3-2. The hybrid MIM stack 606 includes vertically aligned and stacked trench MIM stack 602 and pillar MIM stack 604 to form the hybrid MIM stack 602.

[0136] In Figure 15C it, the workpiece 100 is patterned to form an opening 976 such that the metal line 144 is exposed within the trench 976. In the disclosed embodiments, the trench 976 extends through the passivation sub-layers P3-1 and P3-2. The patterning process also includes a photolithography process and an etching process. The photolithography process includes coating a photoresist layer 978, exposing and developing to form a patterned photoresist layer 977, and may also include various baking processes, and removing the photoresist by wet stripping or plasma ashing after etching. The etching process may include wet etching, dry etching, or a combination thereof. The etching process uses the patterned photoresist layer 978 as an etching mask.

[0137] In Figure 15D it, one or more conductive materials are deposited to fill the opening 976, thereby forming via 148T and metal line 144T together with the metal line 144 and via 148 which are electrodes 202 and 204 of the capacitor 158. Thus, the hybrid MIM stack 606 in the first passivation layer P1 and the hybrid MIM stack 606 in the third passivation layer P3 are electrically connected to form an integrated capacitor 158. In the disclosed embodiments, the conductive material includes metal, metal alloy, other conductive materials, or a combination thereof. In a further embodiment, the conductive material includes copper. The formation of the metal line 144T and via 148T includes deposition, CMP, and patterning. Deposition may include PVD, plating, other suitable methods, or a combination thereof. In some embodiments, deposition includes depositing a seed layer by PVD and plating on the seed layer, such as electroless plating deposition (ECP). Thereafter, the second passivation layer P2 is deposited and planarized by CMP. In some embodiments, the second passivation layer P2 includes silicon nitride. In some other embodiments, the second passivation layer P2 includes silicon nitride and USG. According to some embodiments, the above method can be used to form the Figure 9A IC structure in it. In this case, the vias are formed by different processes, and the top and bottom of the vias are electrically connected but not necessarily aligned, thus providing more freedom for different layouts and configurations for various advantages, such as adjusting the pattern density and reducing the stress on the workpiece caused by the vias.

[0138] Figures 16A to 16H FIG. 100 is a partial cross-sectional view of an IC structure 100 constructed according to some embodiments at different manufacturing stages. The IC structure 100 and its manufacturing method are described by Figures 16A to 16H collectively. Figures 16A to 16H The methods and structures in Figures 12A to 12L are similar or analogous to those described in

[0139] In Figure 16A an IC structure (or workpiece) 100 is provided. The IC structure 100 includes a substrate 102 and an interconnect structure 120. For example, the interconnect structure 120 includes top metal lines 130. In Figure 16A a first passivation sub-layer P1-1 is formed on the workpiece 100. The first passivation sub-layer P1-1 includes silicon nitride having a thickness between and The formation of the first passivation sub-layer P1-1 includes depositions such as by CVD and CMP.

[0140] In Figure 16B the first passivation sub-layer P1-1 is patterned to form trenches 982 by a patterning process that further includes a photolithography process and an etching process. The photolithography process includes coating, exposing, and developing a photoresist layer 980, and may also include various baking processes, and removing the photoresist after etching by wet stripping or plasma ashing. The etching process may include wet etching, dry etching, or a combination thereof.

[0141] In Figure 16C a MIM stack is deposited and patterned. For example, a bottom metal layer 902 is deposited and patterned. A dielectric layer 932 is deposited and may be patterned. A top metal layer 904 is deposited and patterned, thereby forming a trench MIM stack 602. The bottom and top metal layers 902, 904 may include any suitable conductive material, such as titanium nitride, tantalum, tantalum nitride, titanium, other suitable metals, or a combination thereof. The dielectric layer 932 may include any suitable dielectric material, such as a high-k dielectric material. The metal layers may be deposited by any suitable method, such as ALD, PVD, other suitable methods, or a combination thereof. The dielectric layer 932 may be deposited by CVD, ALD, other suitable methods, or a combination thereof. Each of the metal layers 902 and 904 may have a thickness between and The thickness range of the dielectric layer 932 may be between and Therebetween. In some embodiments, another dielectric layer 934 may be deposited on the trench MIM stack 602 to isolate it from other MIM stacks formed in subsequent processes. Dielectric layer 934 is similar to dielectric layer 932 in composition and formation.

[0142] In Figure 16D , another metal layer 906 is directly deposited on metal layer 904 and patterned. Note that the dielectric layer between metal layers 904 and 906 is omitted, so the corresponding two metal layers 904 and 906 are in contact and electrically connected. The thickness range of metal layer 906 can be between and Therebetween. In alternative embodiments, there is a dielectric layer 934 to provide isolation. In this case, the connection of the various metal layers is different.

[0143] In Figures 16E - 16H , metal layer 906 is patterned to form a pillar structure. As Figure 16E shown, a photoresist layer 984 is coated; as Figure 16F shown, the photoresist layer 984 is patterned by exposure and development; as Figure 16G shown, metal layer 906 is patterned by etching using the patterned photoresist layer 984 as an etch mask; as Figure 16H shown, another dielectric layer 936 is further deposited on metal layer 906. The remaining features are then formed as Figures 12I to 12L and Figures 13A to 13E shown.

[0144] Figures 17A to 17D For illustrating the IC structure 100 according to some embodiments. Figure 17A is a cross-sectional view of the IC structure 100; Figure 17B is a top view of the IC structure 100; Figure 17C is a cross-sectional view of the IC structure 100; Figure 17D is a partial cross-sectional view of the IC structure 100 constructed according to various embodiments of the present disclosure. Figures 17A to 17DThe IC structure 100 therein is similar to the IC architectures 100 in the various embodiments described above. For simplicity, similar descriptions will not be repeated. However, the trench MIM stack 602 (or the post MIM stack 604) is different in that the MIM stack includes a plurality of dielectric layers and a plurality of metal layers that are interleaved and properly connected to form an interleaved capacitor 158, thereby further increasing the capacitance of the capacitor 158. For example, the MIM stack 211 may include a dielectric layer 208 and two metal layers 206, 210 in a sandwich configuration. Alternatively, the MIM stack 211 includes N dielectric layers and N + 1 metal layers alternately stacked in an interleaved structure. N is any suitable integer, such as 2, 3, 4, etc. To further implement this embodiment, the various material layers of the MIM stack 211 are subsequently deposited and then patterned to have openings for proper connection to form the electrodes of the capacitor 158.

[0145] Figure 17B A partial view of the IC structure 100 in the dashed box 971 and a partial view in the dashed box 973 are shown in a top view. The 3D MIM stack 211 in the top view can be square, as shown in (1) of Figure 17B ; rectangular, as shown in (2) of Figure 17B ; circular, as shown in (3) of Figure 17B ; or circular with a different configuration, as shown in (4) of Figure 17B Specifically, the MIM stack 211 is configured in an interleaved structure, as shown in (4) of Figure 17B .

[0146] The portion of the IC structure 100 in the dashed box 973 is further shown in the cross-sectional views of Figure 17C and Figure 17D . The MIM stack 211 may include a single dielectric layer 208 as shown in Figure 17C ; or include a plurality of dielectric layers (such as 208A to 208D) and a plurality of metal layers (such as metal layers 206A to 206E) configured in an interleaved structure, as shown in Figure 17D .

[0147] The IC structure 100 may include other material layers, such as 732, 734, 736, 738, and 739. In some embodiments, the material layer 732 is a passivation layer, the material layer 734 is a metal layer; the material layer 736 is another passivation layer; the material layer 738 is a metal layer; the material layer 739 is another passivation layer.

[0148] Figures 18A to 18D For illustrating the IC structure 100 according to some embodiments. Figures 18A to 18D is a partial cross-sectional view of the IC structure 100 constructed according to various embodiments of the present disclosure. Figures 18A to 18D The IC structure 100 inFigures 17A to 17D the IC structure described in

[0149] Figure 18B is further shown Figure 18A a portion of the IC structure 100 within the dashed box 742 of Figure 18B a portion of the IC structure 100 within the dashed box 971 of Figure 18C and Figure 18D is shown in cross - section in Figure 18C The 3D MIM stack 211 may include a single dielectric layer 208 as shown in Figure 18D ; or may include multiple dielectric layers (such as 208A to 208D) and multiple metal layers (such as metal layers 206A to 206E) configured in an interleaved structure, as shown in Figure 6A The various dimensions are similar or the same as those described in Figure 18A The IC structure 100 in

[0150] Figures 19A to 19C also includes vias 148 and metal lines 144, which are configured to connect the various metal layers in the MIM stack 211, serving as the first electrode 202 and the second electrode 204 of the capacitor 158. Figure 19A is a cross - sectional view of the IC structure 100; Figure 19B is a top view of the IC structure 100; Figure 19C is a partial cross - sectional view of the IC structure 100 constructed according to various embodiments of the present disclosure. Figures 19A to 19C The IC structure 100 in Figures 11A to 11C is similar to the above - mentioned IC structure 100 in the IC structure 100 of

[0151] As shown in Figure 19AAs shown, the IC structure 100 includes one or more capacitors 158 having a 3D structure, which are formed by 3D MIM cells 606, each cell having a trench MIM stack 602 but no pillar MIM stack 604. Specifically, each 3D MIM cell 606 includes N (e.g., three) trench MIM stacks 602 that are vertically aligned and stacked together. It should be understood that the number N can be any suitable integer, such as 2, 3, 4, etc. In the illustrated embodiment, N is equal to 3. In some embodiments, the trench MIM stacks 602 in each 3D MIM cell 606 can be vertically spaced apart. For example, the first trench MIM stack 602 formed in the passivation sub-layers P1-1, P1-2 includes a bottom metal layer 206A, a dielectric layer 208A, and a top metal layer 210A. Material layers 734A and 738A are further disposed below and above the first trench MIM stack 602. In some embodiments, the material layers 734A and 738A are conductive materials, such as metals, metal alloys, other suitable conductive materials, or combinations thereof. The conductive layers 734A and 738A are configured to improve the electric field distribution and enhance the performance of the capacitor 158. Similarly, the second trench MIM stack 602 formed in the passivation sub-layers P1-3, P1-4 includes a bottom metal layer 206B, a dielectric layer 208B, and a top metal layer 210B, and may also include conductive layers 734B and 738B disposed below and above the second trench MIM stack 602; the third trench MIM stack 602 formed in the passivation sub-layers P1-5, P1-6 includes a bottom metal layer 206C, a dielectric layer 208C, and a top metal layer 210C, and may also include conductive layers 734C and 738C disposed below and above the third trench MIM stack 602. A dielectric material layer 752 may also be disposed on the interconnect structure 120. In an alternative embodiment, an additional dielectric material layer is inserted between the metal layer 210A and the metal layer 738A; another dielectric material layer is inserted between the metal layer 206A and the metal layer 734A. In this case, four metal layers and three dielectric layers are alternately arranged in a staggered structure and connected to the capacitor 158 with increased capacitance.

[0152] Figure 19BShows the metal layers 206A and 210A in the first trench MIM stack 602 and the corresponding openings 744, 746, 748, and 750. The second and third trench MIM stacks 602 have similar patterns and layouts. In the disclosed embodiments, the metal layer 206A includes the opening 744 such that the through-hole 148 on the left side can land on the metal layer 210A rather than on the metal layer 206A. The metal layer 206A may also include independent islands formed in the opening 744. In this case, the through-hole 148 on the left side lands directly on an island of the main board away from the metal layer 206A. Similarly, the metal layer 210A includes the opening 746 such that the through-hole 148 on the right side can land on the metal layer 206A rather than on the metal layer 210A. The metal layer 210A may also include independent islands formed in the opening 746. In this case, the through-hole 148 on the right side lands directly on an island of the main board away from the metal layer 210A. The metal layers in other trench MIM stacks 602, such as the second or third trench MIM stack 602, may have openings similar to the openings 744 and 746, or may have offset openings (such as 748 and 750), but are still configured such that the corresponding through-holes 148 land within the corresponding openings.

[0153] Similarly, the IC structure 100 may also include a 3D IC structure, such as Figure 19C shown. Figure 19C The IC structure 100 in Figure 3 includes a first IC die 302 and a second IC die 304 bonded thereto through a bonding interface 306, thereby forming a 3D IC structure having a capacitor 158 extending in the first die 302 and the second die 304. The first IC die 302 and the second IC die 304 are bonded in an appropriate pattern, such as face-to-face bonding. The bonding interface 306 may employ any suitable bonding structure, such as a hybrid bonding structure, similar to the hybrid bonding structure described in Figure 19A . The capacitor 158 in the first IC die 302 and the capacitor 158 in the second IC die 304 are similar to the capacitor 158 in

[0154] Figures 20A to 20H is a partial cross-sectional view of the IC structure 100 at different manufacturing stages constructed according to some embodiments. The IC structure 100 and its manufacturing method are described jointly by Figures 20A to 20H .

[0155] In Figure 20A , an IC structure (or workpiece) 100 is provided. The IC structure 100 includes a substrate 102 and an interconnect structure 120.Figure 1A and Figure 1B The substrate 102, the devices formed thereon, and the interconnect structure 120 are described in Figure 1B . For simplicity, they will not be described again here. For example, the interconnect structure 120 includes top metal lines 130. In Figure 20A a dielectric layer 752 is formed on the workpiece 100. The dielectric layer 752 includes silicon nitride having a thickness between and . The formation of the dielectric layer 752 includes deposition (e.g., by CVD).

[0156] A metal layer 734A is further formed on the workpiece 100 by a suitable method (such as PVD). The metal layer 734A may include titanium nitride, other suitable conductive materials, or a combination thereof. The thickness range of the metal layer 734A is between 200 angstroms and 700 angstroms.

[0157] The metal layer 734A is further patterned. A patterned photoresist layer 983 is formed on the metal layer 734A by a photolithography process. The metal layer 734A is etched through the openings of the photoresist layer 983. Thereafter, the photoresist layer 983 can be removed from the workpiece by wet stripping or plasma ashing.

[0158] In Figure 20B a first passivation sublayer P1-1 is formed on the patterned metal layer 734A by deposition (such as CVD) and CMP. The first passivation sublayer P1-1 includes silicon nitride, other suitable dielectric materials, or a combination thereof. The thickness range of the first passivation sublayer P1-1 is between and .

[0159] In Figure 20C the first passivation sublayer P1-1 is patterned to form trenches 756 by a patterning process further including a photolithography process and an etching process. The photolithography process includes coating, exposure, and development of a photoresist layer 754, and may also include various baking processes, and the photoresist is removed by wet stripping or plasma ashing after etching. The etching process may include wet etching, dry etching, or a combination thereof.

[0160] In Figure 20DIn [description], a MIM material stack is deposited and patterned. For example, a bottom metal layer 206A is deposited and patterned. A dielectric layer 208A is deposited. A top metal layer 210A is deposited and patterned, thereby forming a trench MIM stack 602. The bottom and top metal layers 206A, 210A may include any suitable conductive material, such as titanium nitride, tantalum, tantalum nitride, titanium, other suitable metals, or combinations thereof. The dielectric layer 208A may include any suitable dielectric material, such as a high-k dielectric material. The metal layers may be deposited by any suitable method, such as ALD, CVD, other suitable methods, or combinations thereof. The dielectric layer 208A may be deposited by CVD, ALD, other suitable methods, or combinations thereof. The dielectric layer 208A includes a high-k dielectric material. Each of the metal layers 206A and 210A may have a thickness between and . The thickness range of the dielectric layer may be between and . An additional metal layer 738A may also be deposited and patterned. The metal layer 738A may include a conductive material different from that of the top metal layer 210A. For example, the top metal layer 210A includes titanium, while the metal layer 210A includes titanium nitride.

[0161] In Figure 20E , a second passivation sub-layer P1-2 is formed by deposition and CMP. The second passivation sub-layer P1-2 includes silicon nitride, other suitable dielectric materials, or combinations thereof. The thickness range of the second passivation sub-layer P1-2 is between and .

[0162] In Figure 20F , the workpiece 100 is patterned to form an opening 758 such that the top metal component 130 is exposed within the trench 758. In the disclosed embodiments, the trench 758 extends through the passivation sub-layers P1-1 and P1-2. The patterning process also includes a lithography process and an etching process. The lithography process includes coating, exposing, and developing a photoresist layer 760 to form a patterned photoresist layer 760, and may also include various baking processes, as well as removing the photoresist after etching by wet stripping or plasma ashing. The etching process may include wet etching, dry etching, or combinations thereof. The etching process uses the patterned photoresist layer 760 as an etching mask.

[0163] In Figure 20GTherein, one or more conductive materials are deposited to fill the opening 758, thereby forming the via 148 and the metal line 144. In the disclosed embodiments, the conductive material includes a metal, a metal alloy, other conductive materials, or a combination thereof. In a further embodiment, the conductive material includes copper. The formation of the metal line 144 and the via 148 includes deposition, CMP, and patterning. The deposition may include PVD, plating, other suitable methods, or a combination thereof. In some embodiments, the deposition includes depositing a seed layer by PVD and plating on the seed layer, such as ECP.

[0164] In Figure 20H therein, the second passivation layer P2 is deposited and planarized by CMP. In some embodiments, the second passivation layer P2 includes silicon nitride. In some other embodiments, the second passivation layer P2 includes silicon nitride, USG, or a combination thereof.

[0165] Figure 21A is a cross-sectional view of the IC structure 100, Figure 21B is a top view of a portion of the IC structure 100 constructed according to various embodiments. The IC structure 100 is similar to the IC structure described in various embodiments, such as Figure 6A the IC structure 100 in Figure 21A For simplicity, similar descriptions are not repeated. However, as Figure 21A shown, the capacitor 158 only includes the pillar MIM stack 604. The IC structure 100 includes one or more capacitors 158 having a 3D structure and is formed with 3D MIM cells 606, each cell having a pillar MIM stack 604 and no trench MIM stack.

[0166] Figure 21B shows a portion of the IC structure 100 within the dashed box 988 in a top view. The 3D MIM stack 211 in the top view can be a square as shown in (1) of Figure 21B ; a rectangle as shown in (2) of Figure 21B ; a circle as shown in (3) of Figure 21B ; or a different configuration as shown in (4) of Figure 21B . Figure 21B The dimensions of the dashed box 988 and F in the top view in Figure 21A correspond to the dashed box 988 and the dimension F defined in

[0167] Figure 22A is a cross-sectional view of the IC structure 100, Figure 22B is a top view of a portion of the IC structure 100 constructed according to various embodiments. The IC structure 100 is similar to Figure 21A and Figure 21BThe IC structure described in. For simplicity, similar descriptions will not be repeated. The IC structure 100 includes one or more capacitors 158 having a 3D structure, and 3D MIM cells 606 are formed, each cell having a column MIM stack 604 without any trench MIM stacks. In addition, Figure 22A Each 3D MIM cell 606 in includes two column MIM stacks 604 that are vertically spaced apart and stacked. Although Figure 22A Two vertically stacked column MIM stacks are shown, it is understood that Figure 22A Each 3D MIM cell 606 in can include any suitable number of column MIM stacks 604 stacked vertically, such as 3, 4, 5, etc. Figure 22A and Figure 22B The various features in are similar or identical to the features in Figure 8A and Figure 8B For simplicity, similar descriptions will not be repeated.

[0168] Figure 22B shows the layout and configuration of the various features of the capacitor 158. Specifically, these metal layers are patterned to have openings (or islands), such as openings 832, 834, and 836, so that some vias 148 can appropriately contact some metal layers while avoiding contact with other metal layers. In Figure 22B only the metal layers 802, 804, and 808 in the passivation layers P1-1 and P1-2 are shown. The metal layers 812, 814, and 818 in the passivation layers P1-3 and P1-4 can have similar dimensions, shapes, and positions, such as similar openings described below. The metal layer 806 is patterned as a plug on the metal layer 804, separated by a dielectric layer 844; or alternatively can land directly on the metal layer 804 to connect to the same electrode. For simplicity, Figure 8B the metal layer 806 is not shown in. Similarly, the metal layer 816 is patterned as a plug on the metal layer 814, separated by a dielectric layer 850; or alternatively can land directly on the metal 814 to connect to the same electrode. In some embodiments, the metal layer 802 has an opening 832; the metal layer 808 has an opening 836; the metal layer 804 has an opening 834. The 3D MIM cell 606 can have a rectangular shape or other suitable shapes with uniform spacing and width.

[0169] Figures 23A to 23C is used to illustrate the IC structure 100 according to some embodiments. Figure 23A is a cross-sectional view of the IC structure 100; Figure 23B is a top view of the IC structure 100; Figure 23C is a partial cross-sectional view of the IC structure 100 constructed according to various embodiments of the present disclosure. Figures 23A to 23CThe IC structure 100 in Figures 11A to 11C and Figures 23A to 23C is similar to the above-mentioned IC structure 100 in the IC structure 100. For simplicity, similar descriptions will not be repeated.

[0170] As Figure 23A shown, the IC structure 100 includes one or more capacitors 158 having a 3D structure, which are formed by 3D MIM cells 606, and each cell has a column MIM stack 604 and a planar trench MIM stack located below the column MIM stack 604. Specifically, each 3D MIM cell 606 includes N (e.g., three) column MIM stacks 604 aligned and stacked together. It should be understood that the number N can be any suitable integer, such as 2, 3, 4, etc. In the illustrated embodiment, N is equal to 3. In some embodiments, the column MIM stacks 604 in each 3D MIM cell 606 may be vertically spaced apart. In some embodiments, each 3D MIM cell 606 includes three column MIM stacks 604 and three planar MIM stacks configured as Figure 23A shown. Note that the planar MIM stacks are inserted into trenches or folded into columnar structures and formed on a plane. For example, the first planar MIM stack includes a metal layer 902, a dielectric layer 932, and a metal layer 904 configured in a sandwich structure. The second planar MIM stack includes a metal layer 910, a dielectric layer 938, and a metal layer 912 configured in a sandwich structure. The third planar MIM stack includes a metal layer 918, a dielectric layer 944, and a metal layer 920 configured in a sandwich structure.

[0171] Figure 23B shows the metal layers 902 and 904 and the corresponding openings 922 and 924. Only one planar MIM stack is shown. In the disclosed embodiment, the metal layer 902 includes an opening 922; and the metal layer 904 includes an opening 924, which is configured such that the via 148 can appropriately land on the corresponding metal layer to form the electrodes of the capacitor 158. The other metal layers in the column MIM stack and the planar MIM stack may have the same openings or similar offset openings to reduce stress. In some embodiments, each metal layer may also include independent islands located in the openings of the metal layer to redistribute the electric field and improve the performance of the capacitor 158.

[0172] Similarly, the IC structure 100 may also include a 3D IC structure, as Figure 23C shown. Figure 23CThe IC structure 100 therein includes a first IC die 302 and a second IC die 304 bonded thereto through a bonding interface 306, thereby forming a 3D IC structure having a capacitor 158 extending in the first die 302 and the second die 304. The first IC die 302 and the second IC die 304 are bonded in a suitable pattern, such as face-to-face bonding. The bonding interface 306 can adopt any suitable bonding structure, such as a hybrid bonding structure, similar to Figure 3 the hybrid bonding structure described in Figure 19A . The capacitor 158 in the first IC die 302 and the capacitor 158 in the second IC die 304 are similar to the capacitor 158 in Figure 19A . In the disclosed embodiment, the capacitor 158 of the first IC die 302 and the capacitor 158 of the second IC die 304 are integrated into a single capacitor (still referred to as capacitor 158). Note that for simplicity, the dielectric layers of the MIM stack are not shown, and it can be understood that these dielectric layers are present.

[0173] Figures 24A to 24J FIG. is a partial cross-sectional view of the IC structure 100 constructed according to some embodiments at different manufacturing stages. The IC structure 100 and its manufacturing method are described by Figures 24A to 24J collectively.

[0174] In Figure 24A , an IC structure (or workpiece) 100 is provided. The IC structure 100 includes a substrate 102 and an interconnect structure 120. Figure 1A And Figure 1B describe the substrate 102, the devices formed thereon, and the interconnect structure 120. For simplicity, the description is not repeated here. For example, the interconnect structure 120 includes top metal lines 130. In Figure 24A , a first passivation sub-layer P1-1 is formed on the workpiece 100. The first passivation sub-layer P1-1 includes silicon nitride with a thickness between and . The formation of the first passivation sub-layer P1-1 includes deposition (e.g., by CVD) and CMP.

[0175] In Figure 24BIn [description], a MIM stack is deposited and patterned. For example, a bottom metal layer 902 is deposited and patterned. A dielectric layer 932 is deposited and may be patterned. A top metal layer 904 is deposited and patterned. The bottom and top metal layers 902, 904 may include any suitable conductive material, such as titanium nitride, tantalum, tantalum nitride, titanium, other suitable metals, or combinations thereof. The dielectric layer 932 may include any suitable dielectric material, such as a high-k dielectric material. The metal layers 902, 904 may be deposited by any suitable method, such as ALD, PVD, other suitable methods, or combinations thereof. The dielectric layer 932 may be deposited by CVD, ALD, other suitable methods, or combinations thereof. Each of the metal layers 902 and 904 may have a thickness between and . The thickness range of the dielectric layer 932 may be between and .

[0176] In Figure 24C , a dielectric layer 934 is deposited, and its thickness range is between and . The dielectric layer 934 includes a high-k dielectric material. Another metal layer 906 is deposited thereon and patterned to form a pillar structure. The thickness range of the metal layer 906 may be between and . The metal layer 906 is patterned by etching using a patterned photoresist layer as an etch mask. The metal layer 906 may be deposited by any suitable method, such as ALD, PVD, other suitable methods, or combinations thereof. The dielectric layer 934 may be deposited by CVD, ALD, other suitable methods, or combinations thereof. The thickness range of the metal layer 906 may be between and .

[0177] In Figure 24D , a dielectric layer 936 is deposited, and its thickness range is between and . The dielectric layer 936 includes a high-k dielectric material. Another metal layer 908 is deposited on the pillar MIM stack 604 and patterned to form a pillar MIM stack. The thickness range of the metal layer 908 may be between and . The metal layer 908 is patterned by etching using a patterned photoresist layer as an etch mask. The metal layer 908 may be deposited by any suitable method, such as ALD, PVD, other suitable methods, or combinations thereof. The dielectric layer 936 may be deposited by CVD, ALD, other suitable methods, or combinations thereof.

[0178] In Figure 24EIn [reference], a second passivation sub-layer P1-2 is formed by deposition and CMP. The second passivation sub-layer P1-2 includes silicon nitride, and its thickness range can be between and .

[0179] In Figure 24F , a planar MIM stack is deposited and patterned. For example, a bottom metal layer 910 is deposited and patterned. A dielectric layer 938 is deposited and can be patterned. A top metal layer 912 is deposited and patterned. The bottom and top metal layers 910, 912 can include any suitable conductive material, such as titanium nitride, tantalum, tantalum nitride, titanium, other suitable metals, or combinations thereof. The dielectric layer 938 can include any suitable dielectric material, such as a high-k dielectric material. The metal layers 910, 912 can be deposited by any suitable method, such as ALD, PVD, other suitable methods, or combinations thereof. The dielectric layer 938 can be deposited by CVD, ALD, other suitable methods, or combinations thereof. Each of the metal layers 910 and 912 can have a thickness between and . The thickness range of the dielectric layer 938 can be between and .

[0180] In Figure 24G , another pillar MIM stack 604 is deposited and patterned. In some embodiments, a dielectric layer 940 is deposited by a suitable method (such as CVD) before the MIM stack, and can have a thickness between and . The pillar MIM stack 604 is deposited and patterned. For example, a bottom metal layer 914 is deposited and patterned to form a pillar structure. A dielectric layer 942 is deposited and can be patterned. A top metal layer 916 is deposited and patterned, thereby forming another pillar MIM stack 604. The bottom and top metal layers 914, 916 can include any suitable conductive material, such as titanium nitride, tantalum, tantalum nitride, titanium, other suitable metals, or combinations thereof. The dielectric layers 940, 942 can include any suitable dielectric material, such as a high-k dielectric material. The metal layers 914, 916 can be deposited by any suitable method, such as ALD, PVD, other suitable methods, or combinations thereof. The dielectric layers 940, 942 can be deposited by CVD, ALD, other suitable methods, or combinations thereof. Each of the metal layers 914 and 916 can have a thickness between and . Each of the dielectric layers 940 and 942 can have a thickness between and .

[0181] In Figure 24HIn [reference], a third passivation sub-layer P1-3 is formed by deposition and CMP. The third passivation sub-layer P1-3 includes silicon nitride, and its thickness range can be between and .

[0182] In Figure 24I , the workpiece 100 is patterned to form an opening 762, such that the top metal component 130 is exposed within the trench 762. In the disclosed embodiments, the trench 762 extends through the passivation sub-layers P1-1, P1-2, and P1-3. The patterning process also includes a photolithography process and an etching process. The photolithography process includes coating, exposing, and developing a photoresist layer 764 to form a patterned photoresist layer 764, and may also include various baking processes, and the photoresist is removed by wet stripping or plasma ashing after etching. The etching process may include wet etching, dry etching, or a combination thereof. The etching process uses the patterned photoresist layer 764 as an etching mask. According to some embodiments, the depth of the opening 762 is between and .

[0183] In Figure 24J , one or more conductive materials are deposited to fill the opening 762, thereby forming a via 148 and a metal line 144 as electrodes 202 and 204 of the capacitor 158. In the disclosed embodiments, the conductive material includes a metal, a metal alloy, other conductive materials, or a combination thereof. In a further embodiment, the conductive material includes copper. The formation of the metal line 144 and the via 148 includes deposition, CMP, and patterning. The deposition may include PVD, plating, other suitable methods, or a combination thereof. In some embodiments, the deposition includes depositing a seed layer by PVD and plating on the seed layer, such as ECP. Thereafter, the second passivation layer P2 is deposited and planarized by CMP. In some embodiments, the second passivation layer P2 includes silicon nitride. In some other embodiments, the second passivation layer P2 includes silicon nitride and USG. The above method can be used to form the IC structure 100, such as the IC structure 100 in Figure 22A or Figure 23A according to some embodiments.

[0184] Figures 25A to 25J is a partial cross-sectional view of the IC structure 100 at different manufacturing stages constructed according to some embodiments. The IC structure 100 and its manufacturing method are jointly described by Figures 25A to 25J .

[0185] In Figure 25A , an IC structure (or workpiece) 100 is provided. Figures 25A to 25E It is similar to Figures 24A to 24E in terms of features, configuration, and formation. For simplicity, similar descriptions are not repeated. Specifically, in Figures 25A to 25EIn it, a planar MIM stack and a pillar MIM stack 604 are formed on a workpiece 100 and separated by a dielectric layer 934. The planar MIM stack includes a bottom metal layer 902, a dielectric layer 932, and a top metal layer 904; the pillar MIM stack 604 includes a bottom metal layer 906, a dielectric layer 936, and a top metal layer 908.

[0186] In Figure 25F it, the workpiece 100 is patterned to form an opening 766 such that the top metal component 130 is exposed within the trench 766. In the disclosed embodiments, the trench 766 extends through the passivation sub-layers P1-1 and P1-2. The patterning process also includes a photolithography process and an etching process. The photolithography process includes coating, exposing, and developing a photoresist layer 768 to form a patterned photoresist layer 768, and may also include various baking processes, as well as removing the photoresist after etching by wet stripping or plasma ashing. The etching process may include wet etching, dry etching, or a combination thereof. The etching process uses the patterned photoresist layer 768 as an etching mask. The depth of the opening 766 is between and ...

[0187] In Figure 25G it, one or more conductive materials are deposited to fill the opening 766, thereby forming a via 148 and a metal line 144 of a capacitor 158. In the disclosed embodiments, the conductive material includes a metal, a metal alloy, other conductive materials, or a combination thereof. In a further embodiment, the conductive material includes copper. The formation of the metal line 144 and the via 148 includes deposition, CMP, and patterning. The deposition may include PVD, plating, other suitable methods, or a combination thereof. In some embodiments, the deposition includes depositing a seed layer by PVD and plating on the seed layer, such as ECP. Thereafter, a second passivation layer P2 is deposited and planarized by CMP. In some embodiments, the second passivation layer P2 includes silicon nitride. In some other embodiments, the second passivation layer P2 includes silicon nitride and USG. The above methods can be used to form an IC structure 100, such as the IC structure 100 in Figure 21A ...

[0188] In Figure 25H it, the pillar MIM stack is formed in a third passivation layer P3, similar to the method described in Figures 14A to 14F ... Figure 25HIn , a planar MIM stack and a pillar MIM stack 604 are formed on a workpiece 100 and separated by a dielectric layer 940. The planar MIM stack includes a bottom metal layer 910, a dielectric layer 938, and a top metal layer 912; the pillar MIM stack 604 includes a bottom metal layer 914, a dielectric layer 942, and a top metal layer 916.

[0189] In Figure 25I , the workpiece 100 is patterned to form an opening 770 such that a metal wire 144 is exposed within the opening 770. In the disclosed embodiments, the trench 770 extends through the passivation sub-layers P3-2, P3-1, and P2. The patterning process also includes a photolithography process and an etching process. The photolithography process includes coating, exposing, and developing a photoresist layer 772 to form a patterned photoresist layer 772, and may also include various baking processes, and the photoresist is removed by wet stripping or plasma ashing after etching. The etching process may include wet etching, dry etching, or a combination thereof. The etching process uses the patterned photoresist layer 772 as an etching mask.

[0190] In Figure 25J , one or more conductive materials are deposited to fill the opening 770, thereby forming a via 148T and a metal wire 144T, which together with the metal wire 144 and the via 148 serve as electrodes 202 and 204 of a capacitor 158. Thus, the hybrid MIM stacks in the first passivation layer P1 and the hybrid MIM stacks in the third passivation layer P3 are electrically connected to form a combined capacitor 158. Each hybrid MIM stack includes a planar MIM stack and a pillar MIM stack 604. In the disclosed embodiments, the conductive material includes a metal, a metal alloy, other conductive materials, or a combination thereof. In a further embodiment, the conductive material includes copper. The formation of the metal wire 144T and the via 148T includes deposition, CMP, and patterning. Deposition may include PVD, plating, other suitable methods, or a combination thereof. In some embodiments, the deposition includes depositing a seed layer by PVD and plating on the seed layer, such as electroless plating deposition (ECP). Thereafter, the second passivation layer P2 is deposited and planarized by CMP. In some embodiments, the second passivation layer P2 includes silicon nitride. In some other embodiments, the second passivation layer P2 includes silicon nitride and USG. According to some embodiments, the above method can be used to form an IC structure 100. In this case, the vias are formed by different processes, and the top and bottom of the vias are electrically connected but not necessarily aligned, thus providing more freedom for different layouts and configurations for various advantages, such as adjusting the pattern density and reducing the stress on the workpiece by the vias.

[0191] Figure 26A is a cross-sectional view of the IC structure 100, Figure 26B is a top view of a portion of the IC structure 100 constructed according to various embodiments. The IC structure 100 is related toFigure 22A and Figure 22B is similar to or the same as the IC structure 100 described in. For simplicity, similar descriptions are not repeated. The IC structure 100 includes one or more capacitors 158 having a 3D structure, which are formed with 3D MIM cells 606, and each cell has a pillar MIM stack 604 and a trench MIM stack 602. Figure 26A Each 3D MIM cell 606 in includes three hybrid MIM stacks stacked vertically. Although Figure 26A shows two pillar MIM stacks stacked vertically, it can be understood that Figure 26A each 3D MIM cell 606 in may include any suitable number of hybrid MIM stacks stacked vertically, such as 3, 4, 5, etc. However, the hybrid MIM stacks in different layers are offset and staggered. Figure 26B is similar to Figure 8B . For simplicity, similar descriptions are not repeated.

[0192] Figures 27A to 27L is a partial cross-sectional view of the IC structure 100 constructed according to some embodiments at different manufacturing stages. Through Figures 27A to 27L collectively describe the IC structure 100 and its manufacturing method.

[0193] In Figure 27A , an IC structure (or workpiece) 100 is provided. The IC structure 100 includes a substrate 102 and an interconnect structure 120. Figure 1A and Figure 1B describe the substrate 102, the devices formed thereon, and the interconnect structure 120. For simplicity, the descriptions are not repeated here. For example, the interconnect structure 120 includes top metal lines 130. In Figure 27A , a first passivation sub-layer P1-1 is formed on the workpiece 100. The first passivation sub-layer P1-1 includes silicon nitride with a thickness between and . The formation of the first passivation sub-layer P1-1 includes deposition (e.g., by CVD) and CMP.

[0194] In Figure 27B , the first passivation sub-layer P1-1 is patterned by a lithography process and an etching process to form a trench 986. The lithography process forms a patterned photoresist layer 987. The etching process uses the patterned photoresist layer 955 as an etching mask.

[0195] In Figure 27CIn [description], a MIM stack is deposited and patterned. For example, a bottom metal layer 902 is deposited and patterned; a dielectric layer 932 is deposited and may be patterned; and a top metal layer 904 is deposited and patterned. Thereby, a trench MIM stack 602 is formed. The bottom and top metal layers 902, 904 may include any suitable conductive material, such as titanium nitride, tantalum, tantalum nitride, titanium, other suitable metals, or combinations thereof. The dielectric layer 932 may include any suitable dielectric material, such as a high-k dielectric material. The metal layers 902, 904 may be deposited by any suitable method, such as ALD, PVD, other suitable methods, or combinations thereof. The dielectric layer 932 may be deposited by CVD, ALD, other suitable methods, or combinations thereof. Each of the metal layers 902 and 904 may have a thickness between and . The thickness range of the dielectric layer 932 may be between and .

[0196] In Figure 27D , a dielectric layer 934 is deposited, and its thickness range is between and . The dielectric layer 934 includes a high-k dielectric material. Another metal layer 906 is deposited thereon and patterned to form a pillar structure. The thickness range of the metal layer 906 may be between and . The metal layer 906 is patterned by etching using a patterned photoresist layer as an etch mask. The metal layer 906 may be deposited by any suitable method, such as ALD, PVD, other suitable methods, or combinations thereof. The dielectric layer may be deposited by CVD, ALD, other suitable methods, or combinations thereof. The thickness range of the metal layer 906 may be between and .

[0197] In Figure 27E , a dielectric layer 936 is deposited, and its thickness range is between and . The dielectric layer 936 includes a high-k dielectric material. Another metal layer 908 is deposited on the pillar MIM stack 604 and patterned to form a pillar MIM stack. The thickness range of the metal layer 908 may be between and . The metal layer 908 is patterned by etching using a patterned photoresist layer as an etch mask. The metal layer 908 may be deposited by any suitable method, such as ALD, PVD, other suitable methods, or combinations thereof. The dielectric layer may be deposited by CVD, ALD, other suitable methods, or combinations thereof.

[0198] In Figure 27FIn [description], a second passivation sub-layer P1-2 is formed by deposition and CMP. The second passivation sub-layer P1-2 includes silicon nitride, and its thickness range can be between and .

[0199] In Figure 27G the second passivation sub-layer P1-2 is patterned to form trenches 1002 through a lithography process and an etching process. The lithography process forms a patterned photoresist layer 1004. The etching process uses the patterned photoresist layer 994 as an etching mask.

[0200] In Figure 27H another MIM stack is deposited and patterned. For example, a bottom metal layer 910 is deposited and patterned. A dielectric layer 938 is deposited and can be patterned. A top metal layer 912 is deposited and patterned. The bottom and top metal layers 910, 912 can include any suitable conductive material, such as titanium nitride, tantalum, tantalum nitride, titanium, other suitable metals, or combinations thereof. The dielectric layer 938 can include any suitable dielectric material, such as a high-k dielectric material. The metal layers 910, 912 can be deposited by any suitable method, such as ALD, PVD, other suitable methods, or combinations thereof. The dielectric layer 938 can be deposited by CVD, ALD, other suitable methods, or combinations thereof. Each of the metal layers 910 and 912 can have a thickness between and . The thickness range of the dielectric layer 038 can be between and .

[0201] In Figure 27I a dielectric layer 940 is deposited and can be patterned. Another MIM stack is deposited and patterned. The dielectric layer 940 is deposited by a suitable method (such as CVD) before the MIM stack and can have a thickness between and . A MIM stack is deposited and patterned. For example, a bottom metal layer 914 is deposited and patterned; a dielectric layer 942 is deposited and can be patterned; and a top metal layer 916 is deposited and patterned to form another column MIM stack 604. The bottom and top metal layers 914, 916 can include any suitable conductive material, such as titanium nitride, tantalum, tantalum nitride, titanium, other suitable metals, or combinations thereof. The dielectric layer 942 can include any suitable dielectric material, such as a high-k dielectric material. The metal layers 914, 916 can be deposited by any suitable method, such as ALD, PVD, other suitable methods, or combinations thereof. The dielectric layer 942 can be deposited by CVD, ALD, other suitable methods, or combinations thereof. Each of the metal layers 914 and 916 can have a thickness between and The thickness between. The thickness range of the dielectric layer 942 can be between and between.

[0202] In Figure 27J a third passivation sub-layer P1-3 is formed by deposition and CMP. The third passivation sub-layer P1-3 includes silicon nitride, and its thickness range can be between and between.

[0203] In Figure 27K a workpiece 100 is patterned to form an opening 954, such that the top metal component 130 is exposed within the trench 954. In the disclosed embodiments, the trench 954 extends through the passivation sub-layers P1-1, P1-2, and P1-3. The patterning process also includes a photolithography process and an etching process. The photolithography process includes coating, exposing, and developing a photoresist layer 956 to form a patterned photoresist layer 956, and may also include various baking processes, and the photoresist is removed by wet stripping or plasma ashing after etching. The etching process can include wet etching, dry etching, or a combination thereof. The etching process uses the patterned photoresist layer 956 as an etching mask. The trench depth is between and between.

[0204] In Figure 27L one or more conductive materials are deposited to fill the opening 954, thereby forming a via 148 and a metal wire 144 as electrodes 202 and 204 of the capacitor 158. In the disclosed embodiments, the conductive material includes a metal, a metal alloy, other conductive materials, or a combination thereof. In a further embodiment, the conductive material includes copper. The formation of the metal wire 144 and the via 148 includes deposition, CMP, and patterning. Deposition can include PVD, plating, other suitable methods, or a combination thereof. In some embodiments, deposition includes depositing a seed layer by PVD and plating on the seed layer, such as ECP. Thereafter, the second passivation layer P2 is deposited and planarized by CMP. In some embodiments, the second passivation layer P2 includes silicon nitride. In some other embodiments, the second passivation layer P2 includes silicon nitride and USG. The above method can be used to form the IC structure 100, such as the IC structure 100 in Figure 26A according to some embodiments.

[0205] Figures 28A to 28C is a partial cross-sectional view of an IC structure 100 constructed according to some embodiments. Through Figures 28A to 28C collectively describe the IC structure 100 and its manufacturing method.

[0206] In Figure 28AIn this case, the IC structure (or workpiece) 100 includes a substrate 102 and devices formed thereon; an interconnect structure 120; and a passivation structure 140 formed on the interconnect structure 120. The passivation structure 140 includes one or more capacitors 158, which may have any suitable structure described in the various embodiments above. For example, the capacitor 158 includes a plurality of 3D MIM cells 606, which include trench MIM stacks 602, pillar MIM stacks 604, planar MM stacks, hybrid MIM stacks, or combinations thereof that are vertically stacked, aligned, or offset. Each 3D MIM cell 606 may include vertically stacked multi-layer trench MIM stacks 602, pillar MIM stacks 604, and planar MIM stacks. The multi-layer trench MIM stacks are aligned and overlapped, or staggered. Specifically, the IC structure 100 further includes a bonding structure formed on the passivation structure 140, and the bonding structure is configured to provide bonding components to other IC structures (such as another IC die, a printed circuit board (PCB), or other suitable packaging structures). In this embodiment, the bonding structure 1102 is a controlled collapse chip connection (C4) bump. A suitable material layer 1104 may be formed on the passivation structure 140 and around the bonding structure 1102. For example, the material layer 1104 may be a polymer material such as polyimide, other suitable material layers, or combinations thereof. In some embodiments, the C4 bumps are designed to have dimensions and compositions for die-to-package integration; the material layer 1104 is an underfill material for filling the gap between the die and the package structure.

[0207] Alternatively, the bonding structure may be a microbump (μ-bump) 1106 as shown in Figure 28B or a hybrid bonding structure 1108 as shown in Figure 28C . In the embodiment shown in Figure 28C , the IC structure 100 may be bonded to another IC die to form a 3D IC or system-on-integrated-chip (SoIC) hybrid bonding sealed in the same package. A dielectric layer 1110, such as silicon nitride, silicon oxide, other suitable dielectric materials, or combinations thereof, may be present at the bonding interface. In addition, the bottom surface of the top metal component 130 may be connected to various components of the interconnect structure 120, such as other metal wires and vias, devices (such as transistors), other capacitors, resistors, etc. In some embodiments, the dimensions and compositions of the microbumps 1106 are designed to provide die-to-die bonding of the IC substrate, such as chip-to-wafer bonding, chip-to-chip bonding, or other suitable bonding.

[0208] Figure 29FIG. 0 is a partial cross-sectional view of an IC structure 100 constructed in accordance with some embodiments. Specifically, only portions of the interconnect structure 120 and the passivation structure 140 are shown. One or more capacitors 158 are embedded in the passivation structure 140. The RDL structure 144 includes various conductive components, a subset 1122 of which is configured to provide connections to corresponding capacitors 158 and another subset 1124 is configured to redistribute bonding components.

[0209] The present disclosure provides an IC structure having one or more capacitors and a method of manufacturing the same. The capacitors include a plurality of conductive layers and dielectric layers that are alternately stacked and connected by conductive components to form interleaved capacitors. Additionally, the stack of conductive layers and dielectric layers is folded and inserted into one or more deep trenches, formed in a column structure, or a combination of both. The capacitors include a plurality of 3D MIM cells that include trench MIM stacks, column MIM stacks, or hybrid MIM stacks that are aligned and stacked. Each 3D MIM cell may include multiple vertically stacked trench MIM stacks, column MIM stacks, or both. The multiple trench MIM stacks, column MIM stacks, or both are aligned and overlapped, or interleaved. By implementing the disclosed structure and method of manufacturing the same, the package area of the capacitors is significantly reduced, and stress is greatly reduced by implementing aligned and overlapping hybrid MIM stacks. All of these spatial configurations together further relieve stress. While not intended to be limiting, the embodiments of the present disclosure provide benefits to semiconductor processes and semiconductor devices. For example, the disclosed structure and method together reduce stress and prevent workpiece warping or other deformations.

[0210] In one aspect, the present disclosure provides a semiconductor structure that includes: a substrate having devices formed thereon and an interconnect structure that electrically couples the devices into an integrated circuit; a passivation structure formed on the interconnect structure; and a capacitor embedded in the passivation structure, wherein the capacitor includes a first metal-insulator-metal (MIM) stack inserted into a first trench and a second MIM stack formed as a first column structure.

[0211] In some embodiments, each of the first MIM stack and the second MIM stack includes a first metal layer, a first dielectric layer disposed on the first metal layer, and a second metal layer disposed on the first dielectric layer.

[0212] In some embodiments, the first metal layer and the second metal layer include offset corresponding openings for electrically connecting to a first conductive via and a second conductive via to the first metal layer and the second metal layer, respectively.

[0213] In some embodiments, each of the first MIM stack and the second MIM stack further includes a second dielectric layer disposed on the second metal layer and a third metal layer disposed on the second dielectric layer.

[0214] In some embodiments, the first MIM stack and the second MIM stack are aligned and vertically overlapped.

[0215] In some embodiments, the capacitor further includes a third MIM stack inserted into the second trench and a fourth MIM stack formed as a second pillar structure.

[0216] In some embodiments, the third MIM stack and the fourth MIM stack are vertically stacked and further stacked above the first MIM stack and the second MIM stack.

[0217] In some embodiments, the third MIM stack and the fourth MIM stack are aligned and overlapped with the first MIM stack and the second MIM stack.

[0218] In some embodiments, the third MIM stack and the fourth MIM stack are offset from the first MIM stack and the second MIM stack in a staggered configuration.

[0219] In some embodiments, the capacitor includes a first number N1 of MIM stacks folded in the trench and a second number N2 of MIM stacks in the pillar structure, where each of N1 and N2 is greater than 2.

[0220] In some embodiments, each of N1 is different from N2.

[0221] In some embodiments, the semiconductor structure further includes a redistribution structure formed in the passivation structure, where the redistribution structure includes conductive components connected to the capacitor as the first electrode and the second electrode of the capacitor.

[0222] In some embodiments, the capacitor includes a plurality of three-dimensional MIM units that are electrically connected, where each of the 3D MIM units includes a first MIM stack and a second MIM stack.

[0223] In some embodiments, each of the 3D MIM units includes the same shape in a top view.

[0224] In some embodiments, the shape of the 3D MIM unit includes one of a square, a circle, and a rectangle.

[0225] In another aspect, the present disclosure provides a semiconductor structure including: a substrate having devices formed thereon and an interconnect structure that electrically couples the devices into an integrated circuit; a passivation structure formed on the interconnect structure; and a capacitor embedded in the passivation structure, wherein the passivation structure includes a first number N1 of passivation material layers, the capacitor includes a second number N2 of metal-insulator-metal (MIM) stacks that are alternately stacked with the first number N1 of passivation material layers, each of N1 and N2 is greater than 2, and the MIM stack includes a first MIM stack inserted into a first trench and a second MIM stack formed as a first pillar structure.

[0226] In some embodiments, each of the first MIM stack and the second MIM stack includes a first metal layer, a first dielectric layer disposed on the first metal layer, and a second metal layer disposed on the first dielectric layer; and the first MIM stack and the second MIM stack are aligned and vertically overlapped.

[0227] In some embodiments, the capacitor further includes: a third MIM stack inserted into a second trench and a fourth MIM stack formed as a second pillar structure; the third MIM stack and the fourth MIM stack are vertically stacked and further stacked above the first MIM stack and the second MIM stack; and the third MIM stack and the fourth MIM stack are offset from the first MIM stack and the second MIM stack in a staggered configuration.

[0228] In another aspect, the present disclosure provides a method of forming a semiconductor structure, including: forming devices on a substrate; forming an interconnect structure on the devices that couples the devices into an integrated circuit; and forming a passivation structure on the interconnect structure, wherein forming the passivation structure includes forming a capacitor embedded in the passivation structure, wherein the passivation structure includes a first number N1 of passivation material layers, the capacitor includes a second number N2 of metal-insulator-metal (MIM) stacks that are alternately stacked with the first number N1 of passivation material layers, each of N1 and N2 is greater than 2, and the MIM stack includes a first MIM stack inserted into a first trench and a second MIM stack formed as a first pillar structure.

[0229] In some embodiments, each of the first MIM stack and the second MIM stack includes a first metal layer, a first dielectric layer disposed on the first metal layer, and a second metal layer disposed on the first dielectric layer; and the first MIM stack is aligned and vertically overlapped with the second MIM stack.

[0230] The foregoing outlines the features of several embodiments so that those skilled in the art may better understand various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages as those introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: a substrate on which devices and interconnect structures for electrically coupling the devices into an integrated circuit are formed; a passivation structure formed on the interconnect structure; as well as A capacitor is embedded in the passivation structure, wherein the capacitor includes a first metal-insulator-metal stack inserted into the first trench and a second metal-insulator-metal stack formed as a first pillar structure.

2. The semiconductor structure according to claim 1, wherein: Each of the first metal-insulator-metal stack and the second metal-insulator-metal stack includes a first metal layer, a first dielectric layer disposed on the first metal layer, and a second metal layer disposed on the first dielectric layer.

3. The semiconductor structure according to claim 2, wherein: The first and second metal layers include corresponding openings offset from one another for first and second conductive vias electrically connecting to the first and second metal layers, respectively.

4. The semiconductor structure according to claim 2, wherein: Each of the first metal-insulator-metal stack and the second metal-insulator-metal stack further includes a second dielectric layer disposed on the second metal layer and a third metal layer disposed on the second dielectric layer.

5. The semiconductor structure according to claim 1, wherein: The first metal-insulator-metal stack and the second metal-insulator-metal stack are aligned and vertically overlapped.

6. The semiconductor structure according to claim 5, wherein: The capacitor also includes a third metal-insulator-metal stack inserted into the second trench and a fourth metal-insulator-metal stack formed into a second pillar structure.

7. The semiconductor structure according to claim 6, wherein: The third MIM stack and the fourth MIM stack are vertically stacked and further stacked above the first MIM stack and the second MIM stack.

8. The semiconductor structure according to claim 1, wherein: The capacitor includes a plurality of electrically connected three-dimensional metal-insulator-metal units, wherein each of the three-dimensional metal-insulator-metal units includes the first metal-insulator-metal stack and the second metal-insulator-metal stack.

9. A semiconductor structure comprising: a substrate on which devices and interconnect structures for electrically coupling the devices into an integrated circuit are formed; a passivation structure formed on the interconnect structure; as well as A capacitor is embedded in the passivation structure, wherein The passivation structure comprises a first number N1 of passivation material layers, The capacitor includes a second number N2 of metal-insulator-metal stacks alternately stacked with a first number N1 of passivation material layers, Each of N1 and N2 is greater than 2, and The MIM stack includes a first MIM stack inserted into the first trench and a second MIM stack formed into a first pillar structure.

10. A method of forming a semiconductor structure, comprising: forming a device on a substrate; forming an interconnect structure located on the device and coupling the device into an integrated circuit; as well as forming a passivation structure on the interconnect structure, wherein forming the passivation structure comprises forming a capacitor embedded in the passivation structure, wherein: The passivation structure comprises a first number N1 of passivation material layers, The capacitor includes a second number N2 of metal-insulator-metal stacks alternately stacked with a first number N1 of passivation material layers, Each of N1 and N2 is greater than 2, and The MIM stack includes a first MIM stack inserted into the first trench and a second MIM stack formed into a first pillar structure.

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