Semiconductor structural element and method for producing semiconductor structural element

Abstract

The invention relates to a semiconductor structural element, in particular a transistor, comprising a source layer of a first type of doping, in particular a channel layer of a second type of doping, a drift region of the first type of doping, and a substrate layer; the channel layer is located between the source layer and the substrate layer and in particular adjoins the source layer, the drift region is located between the channel layer and the substrate layer, the semiconductor structure element further has a gate trench, which extends from the source layer in a vertical direction towards the drift region and adjoins at least part of the channel layer and the source layer, the semiconductor structure element further has a shielding region of the second type of doping, which extends in a vertical direction from the source layer towards the drift region, adjoins the channel layer and the source layer and is laterally separated from the gate trench, the drift region comprising a plurality of drift layers of the first type of doping, the drift layers each having a different doping concentration. The invention also relates to a method for producing a semiconductor structure element.

Description

Field of the Invention

[0001] The present invention relates to a semiconductor structure element, in particular a transistor, such as a so-called trench MISFET, and a method for manufacturing such a semiconductor structure element. Background Art

[0002] Semiconductor structure elements such as field effect transistors (FETs), in particular so-called MOSFETs or MISFETs, are used in different fields. One variant is the so-called trench MISFET or T-MISFET, in which the channel is constructed vertically. Here, trenches (English: "Trenches") are used to connect, for example, an n-type doped source layer and a channel layer located between it and an n-type doped drift layer; then a gate electrode is arranged in such a trench. Summary of the Invention

[0003] According to the present invention, a semiconductor structure element and a method for manufacturing a semiconductor structure element are provided. Advantageous configurations are described below.

[0004] The present invention relates to a semiconductor structure element, in particular a transistor, having:

[0005] - A source layer doped with a first type,

[0006] - A channel layer doped with a second type in particular,

[0007] - A drift region doped with a first type,

[0008] - A substrate layer,

[0009] wherein the channel layer is located between the source layer and the substrate layer and in particular adjacent to the source layer,

[0010] wherein the drift region is located between the channel layer and the substrate layer,

[0011] wherein the semiconductor structure element further has a gate trench that extends in a vertical direction from the source layer towards the drift region and is adjacent to at least a part of the channel layer and the source layer,

[0012] wherein the semiconductor structure element further has a second type doped shielding region that extends in a vertical direction from the source layer towards the drift region, is adjacent to the channel layer and the source layer and is laterally separated from the gate trench, and

[0013] Wherein, the drift region includes a plurality of drift layers doped with a first type, and the plurality of drift layers doped with the first type have different doping concentrations respectively.

[0014] The present invention studies semiconductor structure elements and their manufacturing. As semiconductor structure elements, transistors can be considered in particular, preferably field effect transistors, more precisely, in particular transistors having trenches or channels. Here, then, for example, T-MOSFETs or T-MISFETs can be involved. In semiconductor materials, different types of doping are used, namely n-type doping and p-type doping, wherein different components can be doped differently. Hereinafter, for better understanding, semiconductor structure elements will be described by a specific type of doping. The n-type doping shall be the first type of doping, and the p-type doping shall be the second type of doping. However, it goes without saying that the n-type doping and the p-type doping can also be swapped, that is to say, the n-type doping can be the second type of doping and the p-type doping can be the first type of doping.

[0015] The field effect transistor has, for example, a source layer doped with n-type, a channel layer (also a body layer) typically doped with p-type, a drift region doped with n-type, and a substrate layer. The channel layer is located between the source layer and the substrate layer, and is in particular adjacent to the source layer. The drift region is located between the channel layer and the substrate layer. The field effect transistor can also have a diffusion layer doped with n-type located between the channel layer and the drift region. In addition, in addition to the substrate layer, the field effect transistor optionally also has a buffer layer, which is adjacent to the substrate layer and then also adjacent to the drift region.

[0016] In addition, the field effect transistor has, for example, a gate trench that extends in a vertical direction from the source layer towards the drift region and is adjacent to at least a part of the channel layer and the source layer. In addition, the field effect transistor in particular has a gate electrode, which is insulated with respect to the diffusion layer, the source layer and the channel layer, and the gate electrode is introduced into the gate trench. For this purpose, the electrically conductive gate electrode material of the gate electrode is at least partially surrounded by a dielectric (for example, a so-called gate oxide). The field effect transistor can also have a plurality of such gate trenches, and then such a gate electrode can be arranged in each gate trench.

[0017] In addition, the field effect transistor typically has a drain contact layer, for example a metal, which is used for making contact and is adjacent to the substrate layer. Similarly, the field effect transistor can have a source contact layer, for example also a metal, which is used for making contact and is adjacent to the source layer. Here, however, the gate electrode is insulated from the source contact layer by an insulating layer. That is, therefore, there are source joints and drain joints that can be constructed in a conventional manner.

[0018] In addition, such a field-effect transistor may have at least one p-type doped shielding region that extends in a vertical direction from an n-type doped source layer or an adjacent semiconductor surface thereof to an n-type doped drain layer.

[0019] A particular advantage of the trench-type MISFET is, for example, that due to the vertical arrangement, a plurality of gate electrodes can be arranged side by side, wherein a high channel density and a low on-resistance can be achieved. The field-effect transistor can in particular be configured as a SiC or GaN field-effect transistor, that is to say, the substrate and / or the semiconductor material commonly used can be silicon carbide (SiC) or gallium nitride (GaN) because these semiconductor materials have a wide bandgap. However, semiconductor materials with an ultra-wide bandgap such as, for example, gallium oxide can also be considered. However, generally, the present invention can also be used in other semiconductor materials such as, for example, gallium nitride (GaN), silicon (Si), or germanium (Ge).

[0020] In such a field-effect transistor, for example, a silicon carbide (SiC) trench-gate power MISFET, it is generally desirable to minimize the on-resistance Ron*A (in the on-state of the structural element and at a small voltage between the drain and the source) and to maximize the blocking voltage (in the off-state of the structural element and at a high voltage between the drain and the source), while at the same time keeping the field load of the gate oxide below an acceptable value and maximizing the robustness of the field-effect transistor with respect to short-circuit events. These four different requirements cannot hitherto be optimized independently of one another.

[0021] For this purpose, within the framework of the present invention, it is now proposed that the drift layer comprises a plurality of n-type doped (or generally first-type doped) drift layers, each of which has a different doping concentration. In particular, the drift layer can have four such drift layers.

[0022] The drift region mentioned is conventionally a layer that is, for example, uniformly doped and epitaxially applied on a buffer layer or possibly directly on a substrate layer. Here, now, by providing a plurality of layers with different doping concentrations and thus also functions, it is achieved that the contribution of the drift layer to the on-resistance is minimized and the blocking voltage of the field-effect transistor is maximized to a value that approaches the theoretical limit of a non-superjunction unipolar structural element (so-called "non-superjunction-unipolar device").

[0023] In one embodiment, the plurality of drift layers includes a first drift layer located on the side of the substrate layer. In the case where a buffer layer is provided, the first drift layer especially has a smaller doping concentration than the buffer layer. This first drift layer is used to reduce the electric field in the vertical direction when the voltage between the drain and the source is high. The doping concentration can be, for example, in the range of 5E15 to 5E16 cm^-3 in the case of having a thickness of 0.5 μm to 10 μm. This layer can be used to generate a high gradient in the electric field in the blocking case.

[0024] In one embodiment, the plurality of drift layers includes a second drift layer adjacent to the first drift layer, wherein the second drift film has a smaller doping concentration than the first drift layer. This second drift layer is an intermediate voltage blocking layer. The doping concentration can be, for example, in the range of 1E15 to 5E16 cm^-3 in the case of having a thickness of 0.5 μm to 10 μm. Compared with other layers, this layer can generate an intermediate gradient in the electric field in the blocking case and contribute to supporting the blocking voltage reception in the blocking state.

[0025] In one embodiment, the plurality of drift layers includes a third drift layer adjacent to the second drift layer, wherein the third drift layer has a smaller doping concentration than the first drift layer and than the second drift layer. This third drift layer is the main blocking voltage layer. The doping concentration can be, for example, in the range of 1E15 to 2E16 cm^-3 in the case of having a thickness of 0.5 μm to 10 μm. This layer can be used to generate a small gradient in the electric field in the locking case, so as to maximize the height of the locking voltage (the integral of the electric field over the drift region) at the same maximum field strength.

[0026] In one embodiment, the plurality of drift layers includes a fourth drift layer adjacent to the third drift layer, wherein the fourth drift film has a higher doping concentration than the second drift layer and than the third drift layer. This fourth drift layer can be a diffused epitaxial layer. The doping concentration can be, for example, in the range of 1E15 to 5E16 cm^-3 in the case of having a thickness of 0.5 μm to 10 μm. In one embodiment, the fourth drift layer has the same or a smaller doping concentration than the first drift layer. Alternatively, the fourth drift layer can have a higher doping concentration than the first drift layer. However, the doping concentration is always higher than that of the second and third drift layers. This fourth drift layer can be used to distribute current in the conductive state and thus minimize the contribution of the on-resistance near the trench. In one embodiment, this layer can be additionally enhanced by subsequent ion implantation.

[0027] A field-effect transistor may have a p-type doped (or generally second-type doped) shielding region that extends in a vertical direction from the surface or source layer towards the drift region, adjacent to the channel layer and the source layer and separated from the gate trench in the lateral direction. In one embodiment, the field-effect transistor further has an additional p-type doped (or generally second-type doped) shielding region that extends in a vertical direction below the gate trench to or into the drift region. Here, the additional shielding region is connected to the shielding region, for example, by at least one, in particular deeply implanted, contact region. The additional shielding region can in particular be constructed self-aligningly.

[0028] This is achieved by providing a (self-aligning) shielding region (also referred to as "Gate Screening Implant") below the trench (so-called "bottom p-well", BPW), decoupling the requirement for the maximum field strength in the gate insulator from the requirements for the on-resistance (Ron*A), breakdown voltage, and short-circuit strength. At the same time, the newly created, narrower JFET region between the (new) shielding region and any potentially existing shielding regions (as mentioned above) limits the saturation current density of the field-effect transistor in the case of a short circuit, thereby limiting the power loss density and heating rate of the structural element and possible thermal damage, which gives the field-effect transistor improved short-circuit robustness compared to the situation so far.

[0029] The invention also relates to a method for manufacturing a semiconductor structural element or a field-effect transistor as described above. Here, a substrate layer is provided, and a plurality of n-type doped or first-type doped drift layers are applied to the substrate layer, either directly or indirectly, that is, in the presence of a buffer layer, they are applied to the buffer layer. Then, additional active regions can be constructed on the uppermost (i.e., for example, the fourth) drift layer among the plurality of drift layers.

[0030] The field-effect transistor as described can be used individually or together with other field-effect transistors, for example, as a power switch. Preferred application areas are, for example, in the electric powertrain of a vehicle, where, for example, in current converters (DC / DC converters, inverters), in charging devices for electrically operated vehicles, or also in solar inverters. Description of the Drawings

[0031] The invention is schematically illustrated according to an embodiment in the drawing and will be described below with reference to the drawing.

[0032] Figure 1 A semiconductor structure element is schematically shown to explain the background of the present invention.

[0033] Figure 2 A semiconductor structure element in one embodiment is schematically shown.

[0034] Figure 3 A process flow of a method in one embodiment is schematically shown. Detailed Description

[0035] In Figure 1 a semiconductor structure element 100 (or at least a part thereof) is schematically shown to explain the background of the present invention. More precisely, the semiconductor structure element (or at least a part thereof) is shown as a field effect transistor, in particular a so-called trench MISFET. As the semiconductor material, in particular, silicon carbide (SiC), gallium nitride (GaN) or gallium oxide can be used, since these semiconductor materials have a wide to very wide bandgap, which is advantageous for the RonA breakdown voltage trade-off compared to materials with a narrow bandgap. Here, in Figure 1 a cross-sectional view through the field effect transistor 100 is shown, where the z-direction is the vertical direction; the field effect transistor 100 has a large extension in the x-y plane (here, the y-direction is out of the drawing plane).

[0036] Hereinafter, a field effect transistor 100 with n-type doping as the first type of doping and p-type doping as the second type of doping will be described. As already mentioned, the types of doping can also be swapped.

[0037] The field effect transistor 100 has a substrate layer 101 in the form of a wafer, for example. The substrate layer 101 is in particular composed of a semiconductor material (such as SiC) and has an optionally epitaxially grown buffer layer 101a on its upper side.

[0038] Furthermore, the field effect transistor 100 has an epitaxially grown, low n-type doped layer 102, which has two main functions. In the upper part (the so-called MISFET head, denoted here by 121) of this layer 102, active functional regions with appropriate doping are fabricated (for example, by implantation with a suitable mask), while the lower part of the layer 102 (known as the drift region and denoted here by 120) mainly receives a high voltage as part of a p / n junction in the blocking case.

[0039] The following layers belong to the active, in particular implanted, functional regions: the n+-doped source layer 108, the p-doped channel layer or body layer 106, a (possibly) p-doped edge closure (not shown), and optionally the n-doped diffusion layer 112 and the p+-doped shielding region 107.

[0040] Thus, the layer 102 can first be produced continuously as the drift region 120, whereupon, however, parts thereof are then adjusted by processing to obtain the layers mentioned. However, the drift region 120 remains, which is then a uniformly doped layer.

[0041] Furthermore, the trench MISFET can include additional structures, such as the gate trench 103, the dielectric gate insulating layers 104, 104a (gate oxide) on the trench surface (e.g., SiO2 or other insulating materials, or a combination formed from multiple insulating materials); here, the lateral layer is designated 104 and the layer on the trench bottom is designated 104a. The thicknesses of the lateral gate insulating layer 104 and the gate insulating layer 104a on the trench bottom can be different. Here, the gate electrode (e.g., polysilicon or a metal gate) is designated 105, and the insulating layer 110 is applied to the gate electrode.

[0042] The source contact layer of the field-effect transistor 100, such as a source metal (e.g., aluminum or copper or a combination of different materials), is designated 109; this source contact layer 109 is used to make contact with the source layer 108 and the shielding region 107.

[0043] The drain contact layer of the field-effect transistor 100, such as a drain metal that makes contact with the back side of the substrate layer 101, is designated 111.

[0044] The challenge in a silicon carbide (SiC) trench power MISFET or a comparable field-effect transistor lies in achieving good conductive characteristics in the on-state (low on-resistance Ron*A that varies with the surface) together with good short-circuit strength and a high blocking voltage, and limiting the maximum field strength in the gate insulator of the trench to an acceptable value in the order of 3 MV / cm for reasons of reliability. These four different requirements cannot be optimized independently of one another, resulting in a compromise between them.

[0045] In Figure 2Schematically shown in one embodiment is a semiconductor structural element 200 (or at least a part thereof), more precisely, it is shown as a field-effect transistor, in particular a so-called trench-type MISFET. As the semiconductor material, in particular, silicon carbide (SiC), gallium nitride (GaN) or gallium oxide can be used, because these semiconductor materials have a wide to very wide bandgap. Here, in Figure 2 a cross-sectional view through the field-effect transistor 200 is shown, wherein the z-direction is the vertical direction; the field-effect transistor 200 has a large extension in the x-y plane (here, the y-direction is out of the drawing plane).

[0046] Hereinafter, in particular, the differences between the field-effect transistor 200 and the field-effect transistor 100 according to Figure 1 will be explained. Similar elements, layers or regions are denoted by the same reference numerals, and other or additional elements, layers or regions are denoted by other reference numerals.

[0047] The field-effect transistor 100 has a substrate layer 101 in the form of a wafer, for example. The substrate layer 101 has a low specific resistance and can be doped with a very high n++ concentration. On the upper side of the substrate layer, an optional buffer layer 101a with a specific n+-type doping concentration is epitaxially grown. This buffer layer is grown to control and reduce crystal defects.

[0048] In one embodiment, four drift layers with different doping concentrations and functions are grown on the buffer layer 101a.

[0049] The first drift layer 213 is used as a layer for reducing the electric field in the vertical direction under high voltage between the drain and the source and has a lower doping concentration than the buffer layer (for example, in the region of 5E15 to 5E16 cm^3 in the case of having a thickness of 0.5 μm to 10 μm). This layer is used to generate a high gradient in the electric field in the blocking case.

[0050] The second drift layer 214 is used as an intermediate voltage blocking layer and has a lower doping concentration than the first drift layer (for example, in the region of 1E15 to 5E16 cm^3 in the case of having a thickness of 0.5 μm to 10 μm). Compared with the layers 213 and 215, this drift layer 214 generates an intermediate gradient in the electric field in the blocking case and helps to support the blocking voltage reception in the blocking state.

[0051] The third drift layer 215 is used as the main blocking voltage layer and has a lower doping concentration than the first drift layer and also has a lower doping concentration than the second drift layer (e.g., in the range of 1E15 to 2E16 cm^3 for a thickness of 0.5 μm to 10 μm). This layer is used to create a small gradient in the electric field during blocking, thereby maximizing the height of the blocking voltage (the integral of the electric field over the drift region) at the same maximum field strength.

[0052] The fourth drift layer 222 is, for example, a diffused epitaxial layer and has a higher doping concentration than the second and third drift layers (e.g., in the range of 1E15 to 5E16 cm^3 for a thickness of 0.5 μm to 10 μm). In one variant, it is doped higher than the first layer, and in a second variant, it is doped lower or the same as the first layer (but always higher than the second and third layers). This layer is used to distribute current in the conducting state and thus minimize the contribution of the on-resistance near the trench.

[0053] To obtain the fourth drift layer 222, similar to the layer 102 in Figure 1 , the layer 216 can be produced as a diffused epitaxial layer. In the region above the layer 216, active functional regions with appropriate doping and structure are fabricated. The n+-doped source layer 108, the p-doped channel layer or body layer 106, (possibly) the p-doped edge closure (not shown), and the optional n-doped diffusion layer 112 and p+-doped shielding region 107 belong to the active functional regions that are, for example, implanted.

[0054] Optionally, the layer 216 can be additionally enhanced, for example, by subsequent ion implantation, i.e., an additional diffusion layer 112 can be constructed. This doping (Aufdotierung) does not necessarily have to cover the entire layer 216 and can also have a location-dependent concentration. Thus, similar to the drift layer 120 according to Figure 1 , a part of the layer 216 remains, namely the fourth drift layer 222, as it is fabricated. Here, now, however, instead of the uniform drift region 120, there is a drift region 220 that includes four drift layers 213, 214, 215, 222 with different doping concentrations.

[0055] Supplementally, here, now, in one embodiment, an additional p+-doped shielding region 217 is added, which extends downward in the vertical direction under the gate trench and, in the case shown, extends into the diffusion layer 112 and generally extends toward the drift region 220. The shielding region 217 can be directly adjacent to the gate trench, but can also be spaced apart therefrom vertically. The p+-doped contact region 218 extends from this shielding region 217 toward the shielding region 107, in particular in the horizontal direction.

[0056] The contact region 218 is shown hatched because it can be selectively implemented uniformly in the y-direction, that is, there can be regions 218 at each position y through the cell in the active region of the structural element outside the end of the cell (Zelle), that is, in each x-z cross-section. Alternatively, however, it can also be interrupted segmentally in the y-direction and each segment thereof has a limited extension in the y-direction, so that only the region 112 is present where the region 218 is missing. In both cases described, it is also possible that the contact region 218 is arranged in the right half-cell. In the case where it has an interruption in the y-direction, there can also be such parts of the contact region 218: the parts are arranged in the right half-cell and other parts are arranged in the left half-cell, in particular alternately.

[0057] Furthermore, the trench-type MISFET can include additional structures, such as the gate trench 103, the dielectric gate insulating layers 104, 104a (gate oxide) (such as SiO2 or other insulating materials) on the trench surface; here, the lateral layer is denoted by 104 and the layer on the trench bottom is denoted by 104a. The gate electrode (for example, polysilicon or a metal gate) is denoted by 105 here, and the insulating layer 110 is applied to the gate electrode.

[0058] The source contact layer of the field effect transistor 200, such as source metal (such as aluminum or copper or a combination of different materials), is denoted by 109; this source contact layer 109 is used to make contact with the source layer 108 and the shielding region 107.

[0059] The drain contact layer of the field effect transistor 200, such as drain metal making contact with the back surface of the substrate layer 101, is denoted by 111.

[0060] The surface of the gate trench 103 is covered by a gate insulating layer 104, 104a of a defined thickness, where the gate insulator may have a different, e.g., greater thickness on the trench bottom (layer 104a) than on the sidewalls (layer 104). The insulator may be, e.g., a homogeneous insulator or a non-uniform insulator stack, e.g., consisting of different layers. In general, materials such as SiO2, high-k materials, SiN, Al2O3, HfO may be used. Additionally, the gate insulator may consist of different materials on the trench bottom than on the sidewalls and / or have different ratios of insulator materials in the case of an insulator stack. The gate electrode 105 is located inside the trench 103 and adjacent to the layers 104, 104a. The gate electrode is separated from the source contact layer 109 by an insulating layer 110 (e.g., an intermetallic dielectric).

[0061] The shielding region 217 (also referred to as BPW) located below the trench bottom may contact the trench bottom vertically, but it does not have to. In principle, the shielding region 217 shields the gate insulators 104, 104a from the high electric fields that occur at high drain-source voltages, especially in the trench bottom region 104a. Thus, the p+-type shielding region 107 can be flatter (i.e., extend less vertically deep), which makes the processing less complex, reduces costs, and minimizes damage to the crystal due to the smaller implantation energy used in its manufacture.

[0062] On the other hand, the flatter p+-type shielding region 107 enables a narrower cell pitch because the implantation mask can be defined thinner and structured more finely, which enables a narrower critical dimension. Additionally, the flatter p+-type shielding region 107 results in a better current distribution in the lateral direction and thus a smaller on-resistance Ron*A. Furthermore, the dynamic behavior of the intrinsic body diode of the MISFET (e.g., during reverse recovery (RR)) is improved due to the smaller carrier spillover in the drift region during the forward operation of the diode (smaller total RR charge, smaller snappiness of the intrinsic body diode. The robustness against bipolar degradation is also improved. Additionally, the relaxation of the electric field in the gate insulator region due to the shielding region 217 reduces short-channel effects such as drain-induced barrier lowering (DIBL) and essentially enables a design with a flatter body surface and a shorter channel, which reduces Ron*A.

[0063] The shielding region 217 or a plurality thereof is preferably fabricated in the bottom of the gate trench 103 by performing self-aligned ion implantation. In this way, the self-alignment of the two structures (i.e., the gate trench and the shielding region 217) is achieved, and the best results are obtained while shielding the gate insulators 104, 104a from high electric fields without adversely affecting Ron*A.

[0064] Before implantation, a special mask layer can be grown or deposited, for example, on the inner wall of the trench wall to protect the n-type region laterally adjacent to the trench wall from the influence of compensation caused by the implantation of p-type doping material.

[0065] Alternatively, the shielding region 217 can also be fabricated together with the p+-type shielding region 107 in one step, where doping is performed through the source layer 108 and the body layer or channel layer 106 and into it (in such a region where the trench is located), and then the trench is etched. With this manufacturing method, the processing cost can be saved at the expense of a small part of the power.

[0066] The p+-type shielding region 107 does not have to be deeper than the shielding region 217 and / or the diffusion layer 112. The diffusion layer 112 does not have to be deeper than the shielding region 217.

[0067] The shielding region 217 is connected together with the p+-type shielding region 107 and thus with the source potential through the deeply implanted contact region 218, and the contact region can be implanted periodically in the third dimension (in the y direction not shown here) perpendicular to the main longitudinal axis of the trench.

[0068] The contact region 218 can be preferably implanted at regular intervals on alternating trench sides (only shown on the left in Figure 2 ), but can also be located at the same position in the third dimension on both trench sides. Alternatively, the contact region 218 can also be arranged only on one side of the trench. The spacing from the contact region 218 to the next contact region 218 can be freely selected on the same side of the p+-type shielding region 107. A favorable compromise between the small resistance of the structural element and the good connection of the shielding region 217 to the source potential is, for example, at about 2 to 20 times the cell pitch of the MISFET. Connecting the shielding region 217 to the source potential provides the shielding region 217 with the function of reducing the saturation current of the source-drain current path in the case of a short circuit. Therefore, the shielding region 217 improves the short-circuit strength of the field-effect transistor.

[0069] (Compared with 102, 213, 214, 215, 216, and 222), the highly doped buffer layer 101a is optional and can be used to minimize the on-resistance Ron*A through a Punch-Through-Design (for the high doping level of 101a, which stops the depletion region during the blocking state of the structural element before the depletion region reaches the substrate), and to achieve the robustness of the MISFET against bipolar degradation (the high doping level of 101a is accompanied by a short lifetime of minority carriers, which helps to reduce the plasma concentration in the buffer layer).

[0070] Optionally, an additional doped layer (RR optimization layer, not shown) can be embedded between the buffer layer 101a and the first drift layer 213. The doping and thickness of this layer can be optimized to achieve better reverse recovery of the intrinsic body diode, which may be required in some applications.

[0071] As mentioned, the diffusion layer 112 is also optional. To achieve a low on-resistance, this diffusion layer is more highly doped than the drift regions 120 or 220 and can extend vertically from the channel layer or the body layer 106 to below the p+-type shielding region 107. The diffusion layer 112 can have non-constant doping in the vertical and / or lateral directions and can be fabricated by multiple ion implantations with different doses and energies. In particular, the doping profile of the diffusion layer 112 can be retrograde, that is, the doping concentration reaches a maximum at a specific depth when moving vertically downward from the surface.

[0072] As mentioned, the proposed embodiments are not limited to the illustrated n-channel MISFET, but can also be applied to p-channel MISFETs by replacing n-type doping with p-type doping and vice versa. In addition, the proposed embodiments are not limited to SiC, but can also be applied to other materials with a wide bandgap (such as GaN) or materials without a wide bandgap such as Si.

[0073] In Figure 3 the flow of the method in a preferred embodiment is schematically shown. More precisely, this method is exemplarily used to manufacture a field effect transistor as shown, for example, in Figure 2 Basically, the manufacturing related to Figure 2 has been described in detail, yet it will be briefly summarized below.

[0074] In step 300, a substrate layer may first be provided, and in optional step 302, a buffer layer may be applied thereon. In step 304, a plurality of first-type doped drift layers, including a wide fourth layer, may be applied thereon. There, then the layers mentioned - the source layer, the channel layer, the implant for enhancing the diffusion layer, etc. - may be introduced, thus generating the final fourth layer. In a further process (step 306), then an (additional) active region may be constructed on the uppermost layer of the plurality of drift layers. Such an active region includes, for example, the shielding region, the channel layer, the source layer, and the like as mentioned.

Claims

1. A semiconductor component (200), in particular a transistor, comprising: - a source layer (108) doped with a first type, - a channel layer (106) doped in particular with a second type, - a drift region (220) of first type doping, - a substrate layer (101), in, The channel layer is located between the source layer and the substrate layer and is in particular adjacent to the source layer, Wherein, the drift region (220) is located between the channel layer and the substrate layer, The semiconductor structure (200) further comprises a gate trench (103), which extends in a vertical direction from the source layer (108) toward the drift region and is adjacent to at least a portion of the channel layer (106) and the source layer (108). The semiconductor structure (200) further comprises a shielding region (107) of second type doping, which extends in a vertical direction from the source layer (108) toward the drift region, adjoins the channel layer (106) and the source layer (108) and is laterally separated from the gate trench (103), and The drift region (220) comprises a plurality of first-type doped drift layers, and the plurality of first-type doped drift layers respectively have different doping concentrations.

2. The semiconductor structure (200) according to claim 1, wherein: The plurality of drift layers include: a first drift layer (213), the first drift layer being located on the side of the substrate layer, a second drift layer (214), the second drift layer being adjacent to the first drift layer, wherein the second drift layer has a lower doping concentration than the first drift layer, a third drift layer (215) adjacent to the second drift layer, wherein the third drift layer has a lower doping concentration than the first drift layer and than the second drift layer, and A fourth drift layer (222) adjacent to the third drift layer, wherein the fourth drift layer has a higher doping concentration than the second drift layer and than the third drift layer.

3. The semiconductor structure (200) according to claim 2, wherein: The fourth drift layer (222) has a doping concentration that is the same as or lower than that of the first drift layer, or the fourth drift layer has a doping concentration that is higher than that of the first drift layer.

4. The semiconductor structure (200) according to claim 2 or 3, characterized in that The semiconductor structure further comprises a buffer layer (101a) of a first type of doping arranged on the substrate layer, the buffer layer of the first type of doping being located between the first drift layer and the substrate layer. In particular, the first drift layer (213) has a lower doping concentration than the buffer layer.

5. The semiconductor structure (200) according to claim 1 , further comprising a further shielding region (217) of a second type of doping, which extends in a vertical direction below the gate trench (103) to the drift region (220) or into the drift region (220), wherein: The further shielding region (117) is connected to the shielding region (107) via at least one, in particular deeply implanted, contact region (218).

6. The semiconductor structure (200) according to claim 5, wherein: The shielding region (217) is designed to be self-aligning.

7. The semiconductor structure (200) according to any one of the preceding claims, further comprising a diffusion layer (112) of a first type of doping, which is located between the channel layer (106) and the drift region.

8. The semiconductor structure (200) according to claim 1, further comprising a gate electrode (105), which is insulated from the diffusion layer (108) and the channel layer and is introduced into the gate trench (103).

9. The semiconductor component (200) as claimed in claim 1, which is designed as a SiC field effect transistor or a GaN field effect transistor or a gallium oxide field effect transistor.

10. A method for producing a semiconductor component (200) according to any one of the preceding claims, comprising: providing (300) the substrate layer; applying (304) the plurality of first type doped drift layers directly or indirectly onto the substrate layer; and A further active region is constructed (306) on an uppermost drift layer of the plurality of drift layers.

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