An adaptive constant-on-time buck circuit

Abstract

The present invention relates to the field of buck circuits, and particularly to an adaptive constant-on-time buck circuit, which includes a VIN feedforward module, a frequency locking module, a timer module, a control logic module, and an ACOT unit. The input end of the VIN feedforward module is electrically connected to the input voltage VIN. The first input end of the frequency locking module collects the switching frequency period signal of the control logic module. By combining the VIN feedforward module and the frequency locking module, the integration current of the timer module is modulated and fed back jointly to construct an adaptive ON-TIME compensation mechanism, avoiding dependence on external clock synchronization. While simplifying the structure, it also avoids the problem that the switching frequency of the typical COT is difficult to predict, making the switching frequency more concentrated in the power spectral density, facilitating system-level EMC design, reducing the circuit layout area, and reducing costs and power consumption.

Description

Technical Field

[0001] The present invention relates to the field of buck circuits, and particularly to an adaptive constant on-time buck circuit. Background Art

[0002] The Buck circuit, also known as a buck converter, is a common DC-DC converter. Its core function is to convert a higher input voltage into a lower output voltage while maintaining the stability of the output voltage. It is widely used in various electronic devices, such as power adapters, LED drivers, battery chargers, and circuit systems that require precise voltage regulation.

[0003] The basic structure of the Buck circuit consists of a switching transistor, an inductor, an output filter capacitor, and a freewheeling diode. The working principle is based on the energy storage and release process of the inductor: when the switching transistor is turned on, the input voltage is directly applied to the inductor, and the inductor starts to store energy while the current increases linearly; when the switching transistor is turned off, the energy in the inductor is released to the load through the freewheeling diode, and the inductor current gradually decreases. By quickly controlling the on and off of the switching transistor, the Buck circuit can effectively convert the input voltage into a lower output voltage.

[0004] The on and off of the switching transistor are usually controlled by a pulse width modulation (PWM) signal. The duty cycle of the PWM signal determines the average value of the output voltage. The larger the duty cycle, the higher the output voltage; the smaller the duty cycle, the lower the output voltage. By adjusting the duty cycle of the PWM signal, the Buck circuit can achieve precise control of the output voltage. However, the existing Buck circuit has a large layout area, resulting in a relatively high usage cost and power consumption. Summary of the Invention

[0005] The purpose of the present invention is to provide an adaptive constant on-time buck circuit, aiming to improve the problem that the existing Buck circuit has a large layout area, resulting in a relatively high usage cost and power consumption.

[0006] To achieve the above purpose, the present invention adopts the following technical solutions:

[0007] An adaptive constant on-time buck circuit includes a VIN feedforward module, a frequency locking module, a timer module, a control logic module, and an ACOT unit.

[0008] The input end of the VIN feedforward module is electrically connected to the input voltage VIN. The first input end of the frequency locking module collects the switching frequency period signal of the control logic module. The ACOT unit outputs a current sink I BIAS to the second input ends of the timer module and the frequency locking module. The ACOT unit outputs a reference voltage V REF1To the third input terminal of the frequency locking module, the output terminal of the VIN feedforward module and the output terminal of the frequency locking module are electrically connected to the timer module, and the integration current I of the timer module is S controlled.

[0009] The output terminal of the timer module is electrically connected to the first input terminal of the control logic module. The external enable signal EN is input to the VIN feedforward module, the frequency locking module, the control logic module, and the ACOT unit. The output terminal of the ACOT unit outputs CMP_OUT to the second input terminal of the control logic module. The control logic module outputs the internal clock CLK_INT and the pulse width control signal ONE_SHOT1 and the pulse width control signal ONE_SHOT2 to the ACOT unit;

[0010] The ACOT unit outputs the VDD voltage to the VIN feedforward module, the frequency locking module, and the timer module.

[0011] Further, the VIN feedforward module includes the MOS transistor HVN1, the MOS transistor P1, the MOS transistor P2, the MOS transistor P3, the triode Q1, the triode Q2, the resistor R1, and the polarized capacitor C1;

[0012] One end of the resistor R1 is electrically connected to the input voltage VIN, the other end of the resistor R1 is electrically connected to the drain of the MOS transistor HVN1, the external enable signal EN is input to the gate of the MOS transistor HVN1, and the source of the MOS transistor HVN1 is electrically connected to the collector, base of the triode Q1, and the base of the triode Q2;

[0013] The ACOT unit outputs the VDD voltage to the source of the MOS transistor P1 and the positive electrode of the polarized capacitor C1. The gate and drain of the MOS transistor P1 are electrically connected to the source of the MOS transistor P2. The gate and drain of the MOS transistor P2 are electrically connected to the negative electrode of the polarized capacitor C1, the gate of the MOS transistor P3, and the collector of the triode Q2. The source of the MOS transistor P3 is electrically connected to the frequency locking module, and the drain of the MOS transistor P3 is electrically connected to the timer module;

[0014] The emitter of the triode Q1 and the emitter of the triode Q2 are both grounded.

[0015] Further, the frequency locking module includes the MOS transistors N7, N8, P9, P10, P11, P15, P16, the resistors R3, R4, the polarized capacitors C4, C5, C6, C7, and the transconductance amplifier OTA;

[0016] The ACOT unit outputs the VDD voltage to the drain of MOS transistor N8, the source of MOS transistor P17, the source of MOS transistor P9, the source of MOS transistor P10, and the source of MOS transistor P11;

[0017] The gate of the MOS transistor N8 is electrically connected to the drain of the MOS transistor P17, the output terminal of the transconductance amplifier OTA, and the positive electrode of the polarized capacitor C7. The source of the MOS transistor N8 is electrically connected to the VIN feedforward module. The external enable signal EN is input to the gate of the MOS transistor P17;

[0018] The ACOT unit outputs the current sink I BIAS to the gates of the MOS transistors P9, P10, and P11. The drain of the MOS transistor P9 is electrically connected to the drain of the MOS transistor N7, the positive electrode of the polarized capacitor C4, and the gate of the MOS transistor P15; The gate of the MOS transistor N7 is electrically connected to the control logic module; The drain of the MOS transistor P10 is electrically connected to one end of the resistor R3 and the source of the MOS transistor P15. The other end of the resistor R3 is electrically connected to one end of the resistor R4 and the positive electrode of the polarized capacitor C5. The other end of the resistor R4 is electrically connected to the positive electrode of the polarized capacitor C6 and the non-inverting input terminal of the transconductance amplifier OTA; The drain of the MOS transistor P11 is electrically connected to the source of the MOS transistor P16 and the inverting input terminal of the transconductance amplifier OTA. The ACOT unit outputs the reference voltage V REF1 to the gate of the MOS transistor P16;

[0019] The sources of the MOS transistor N7, the drain of the MOS transistor P15, the drain of the MOS transistor P16, the negative electrode of the polarized capacitor C4, the negative electrode of the polarized capacitor C5, the negative electrode of the polarized capacitor C6, and the negative electrode of the polarized capacitor C7 are all grounded.

[0020] Further, the timer module includes MOS transistors N1, N2, N3, N4, N5, N6, P4, P5, P6, P7, P8, P12, P13, P14, resistor R2, and polarized capacitors C2 and C3;

[0021] The ACOT unit outputs the VDD voltage to the positive electrode of the polarized capacitor C2, the sources of the MOS transistors P4, P5, P6, P7, P8;

[0022] The ACOT unit outputs the current sink I BIASTo the gate of MOS transistor P4, the drain of MOS transistor P4, the negative electrode of polarized capacitor C2, the gate of MOS transistor P5, the gate of MOS transistor P6, the gate of MOS transistor P7, and the gate of MOS transistor P8; the drain of MOS transistor P5 is electrically connected to one end of resistor R2, the gate of MOS transistor N4, and the gate of MOS transistor N2. The other end of resistor R2 is electrically connected to the drain of MOS transistor N2, the gate of MOS transistor N1, and the gate of MOS transistor N3. The source of MOS transistor N2 is electrically connected to the drain of MOS transistor N1;

[0023] The drain of MOS transistor P6 is electrically connected to the drain of MOS transistor N4, the drain of MOS transistor P12, and the control logic module. The source of MOS transistor N4 is electrically connected to the drain of MOS transistor N5, the drain of MOS transistor P13, the gate of MOS transistor N6, and the positive electrode of polarized capacitor C3. The gate of MOS transistor N5 is electrically connected to the gate of MOS transistor P13 and the control logic module. The source of MOS transistor N5 is electrically connected to the drain of MOS transistor N3;

[0024] The drain of MOS transistor P7 is electrically connected to the source of MOS transistor P12. The gate of MOS transistor P12 is electrically connected to the output terminal of the logic control module; the source of MOS transistor P13 is electrically connected to the output terminal of the VIN feedforward module and the source of MOS transistor P14;

[0025] The drain of MOS transistor P8 is electrically connected to the drain of MOS transistor N6 and the first input terminal of the control logic module;

[0026] The sources of MOS transistor N1, MOS transistor N3, the drain and gate of MOS transistor P14, the source of MOS transistor N6, and the negative electrode of polarized capacitor C3 are all grounded.

[0027] Further, the control logic module includes inverter INV1, inverter INV2, inverter INV3, NAND gate NAND, OR gate OR, and flip-flops RS1 and RS2;

[0028] The external enable signal EN is input to the input terminal of inverter INV3 and the first input terminal of NAND gate NAND. The output terminal of inverter INV3 is electrically connected to the first input terminal of OR gate OR;

[0029] The drain of the MOS transistor P8 is electrically connected to the input terminal of the inverter INV1. The output terminal of the inverter INV1 is electrically connected to the input terminal of the inverter INV2 and the first input terminal of the frequency locking module. The output terminal of the inverter INV2 is electrically connected to the second input terminal of the flip-flop RS1. The drain of the MOS transistor P6 is electrically connected to the first input terminal of the flip-flop RS1. The first output terminal of the flip-flop RS1 is electrically connected to the first input terminal of the flip-flop RS2. The second output terminal of the flip-flop RS1 is electrically connected to the gate of the MOS transistor P12. The output terminal of the ACOT unit outputs CMP_OUT to the second input terminal of the flip-flop RS2. The first output terminal of the flip-flop RS2 is electrically connected to the second input terminal of the OR gate OR and outputs the internal clock CLK_INT to the ACOT unit. The second output terminal of the flip-flop RS2 is electrically connected to the second input terminal of the NAND gate NAND. The output terminal of the NAND gate NAND outputs the pulse width control signal ONE_SHOT2 to the ACOT unit. The output terminal of the OR gate OR is electrically connected to the gate of the MOS transistor N5 and outputs the pulse width control signal ONE_SHOT1 to the ACOT unit.

[0030] Further, the ACOT unit includes a topology module, a driver Driv_H, a driver Driv_L, a comparator COMP, a MOS transistor N_H, a MOS transistor N_L, a polarized capacitor C_BOOT, a polarized capacitor CL, a resistor DCR, a resistor ESR, a resistor RL, a resistor Rb1, a resistor Rb2, and an inductor L;

[0031] The topology module and the drain of the MOS transistor N_H are electrically connected to the input voltage VIN. The topology module outputs VDD to the power supply terminal of the driver Driv_H, the power supply terminal of the driver Driv_L, the positive electrode of the polarized capacitor C_BOOT, the power supply terminal of the comparator COMP, and the VIN feedforward module, the frequency locking module, and the timer module. The output terminal of the topology module is electrically connected to the input terminal of the driver Driv_H and the input terminal of the driver Driv_L. The topology module outputs the current sink I BIAS to the second input terminals of the timer module and the frequency locking module. The external enable signal EN, the internal clock CLK_INT, the pulse width control signal ONE_SHOT1, and the pulse width control signal ONE_SHOT2 are input to the topology module;

[0032] The output terminal of the driver Driv_H is electrically connected to the gate of the MOS transistor N_H. The ground terminal of the driver Driv_H is electrically connected to the source of the MOS transistor N_H, the negative electrode of the polarized capacitor C_BOOT, the drain of the MOS transistor N_L, and one end of the inductor L. The output terminal of the driver Driv_L is electrically connected to the gate of the MOS transistor N_L;

[0033] The other end of the inductor L is electrically connected to one end of the resistor DCR. The other end of the resistor DCR is electrically connected to one end of the resistor ESR, one end of the resistor RL, and one end of the resistor Rb1, and outputs VOUT to an external circuit. The other end of the resistor ESR is electrically connected to the positive electrode of the polarized capacitor CL. The other end of the resistor Rb1 is electrically connected to the non-inverting input terminal of the comparator COMP and one end of the resistor Rb2. REF2 The topology module outputs a reference voltage V

[0034] to the inverting input terminal of the comparator COMP. The output terminal of the comparator COMP outputs CMP_OUT to the second input terminal of the control logic module.

[0035] Furthermore, the following conditional expressions are satisfied.

[0036] W / L P4 =W / L P5 ;

[0037] W / L N3 =αW / L N1 ;

[0038] W / L N4 =αW / L N2 ;

[0039] W / L P6 <αW / L P5 ;

[0040] W / L P6 +W / L P7 >αW / L P5 ;

[0041] W / L P8 =βW / L P4 ;

[0042] Among them, W / L Pn is the aspect ratio of the MOS transistor Pn, and W / L Nn is the aspect ratio of the MOS transistor Nn. That is, W / L N1 is the aspect ratio of the MOS transistor N1, W / L N2 is the aspect ratio of the MOS transistor N2, W / L N3 is the aspect ratio of the MOS transistor N3, W / L N4 is the aspect ratio of the MOS transistor N4, W / L P4 is the aspect ratio of the MOS transistor P4, and W / L P5is the aspect ratio of MOS transistor P5, W / L P6 is the aspect ratio of MOS transistor P6, W / L P7 is the aspect ratio of MOS transistor P7, W / L P8 is the aspect ratio of MOS transistor P8; α and β are proportionality coefficients.

[0043] Furthermore, the following conditional expressions are satisfied

[0044] W / L P10 =W / L P11 ;

[0045] W / L P15 =W / L P16 ;

[0046] wherein, W / L Pn is the aspect ratio of MOS transistor Pn; that is, W / L P10 is the aspect ratio of MOS transistor P10, W / L P11 is the aspect ratio of MOS transistor P11, W / L P15 is the aspect ratio of MOS transistor P15, W / L P16 is the aspect ratio of MOS transistor P16.

[0047] After adopting the above technical solution, compared with the background technology, the present invention has the following advantages:

[0048] Combining the VIN feedforward module and the frequency locking module to jointly modulate and feedback the integration current of the timer module, constructing an adaptive ON-TIME compensation mechanism, avoiding dependence on external clock synchronization, and achieving a frequency stability of ±1% under the condition of no external phase-locked loop and without triggering the PSM operation. While simplifying the structure, it avoids the problem that the switching frequency of the typical COT is difficult to predict, makes the switching frequency more concentrated on the power spectral density, facilitates the system-level EMC design, reduces the circuit layout area, and reduces the cost and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 is the circuit diagram of the self-locking type switching frequency control single-pulse trigger unit of the adaptive constant on-time buck circuit described in the present invention;

[0050] Figure 2 is the circuit diagram of the ACOT unit of the adaptive constant on-time buck circuit described in the present invention;

[0051] Figure 3 is the simulation waveform diagram of the switching frequency stability of the adaptive constant on-time buck circuit described in the present invention;

[0052] Figure 4This is the simulation waveform diagram of the function of the adaptive constant on-time buck circuit of the present invention from PWM to PSM to 100% duty cycle. Detailed implementation manners

[0053] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0054] In addition, it should be noted that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are all based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element of the present invention must have a specific orientation, so it cannot be understood as a limitation of the present invention.

[0055] When an element is referred to as being "fixed to" or "arranged on" or "provided on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0056] Unless otherwise clearly defined and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the invention can be understood according to specific circumstances. Embodiment

[0057] Please refer to Figures 1-4 As shown, this embodiment provides an adaptive constant on-time buck circuit, including a self-locking switching frequency control single-pulse trigger unit and an ACOT unit; further, the self-locking switching frequency control single-pulse trigger unit includes a VIN feedforward module, a frequency locking module, a timer module, and a control logic module.

[0058] The input end of the VIN feedforward module is electrically connected to the input voltage VIN, and the first input end of the frequency locking module collects the switching frequency period signal of the control logic module. The ACOT unit outputs a current sink I BIAS to the second input ends of the timer module and the frequency locking module, and the ACOT unit outputs a reference voltage V REF1To the third input terminal of the frequency locking module. The output terminals of the VIN feedforward module and the frequency locking module are electrically connected to the timer module to control the integration current I of the timer module S The output terminal of the timer module is electrically connected to the first input terminal of the control logic module. The external enable signal EN is input to the VIN feedforward module, the frequency locking module, the control logic module, and the ACOT unit. The output terminal of the ACOT unit outputs CMP_OUT to the second input terminal of the control logic module, and the control logic module outputs the internal clock CLK_INT and the pulse width control signals ONE_SHOT1 and ONE_SHOT2 to the ACOT unit. The ACOT unit outputs the VDD voltage to the VIN feedforward module, the frequency locking module, and the timer module.

[0059] By combining the VIN feedforward module and the frequency locking module, they jointly modulate and feedback the integration current of the timer module to construct an adaptive ON-TIME compensation mechanism, avoiding reliance on external clock synchronization. Under the condition of no external phase-locked loop, in the working condition where PSM is not triggered, a frequency stability of ±1% is achieved. While simplifying the structure, it avoids the problem that the switching frequency of the typical COT is difficult to predict, making the switching frequency more concentrated on the power spectral density, facilitating the system-level EMC design, reducing the circuit layout area, and reducing costs and power consumption.

[0060] Please refer to Figure 1 As shown, specifically, the VIN feedforward module includes the MOS transistor HVN1, the MOS transistor P1, the MOS transistor P2, the MOS transistor P3, the triode Q1, the triode Q2, the resistor R1, and the polarized capacitor C1.

[0061] One end of the resistor R1 is electrically connected to the input voltage VIN, the other end of the resistor R1 is electrically connected to the drain of the MOS transistor HVN1, the external enable signal EN is input to the gate of the MOS transistor HVN1, and the source of the MOS transistor HVN1 is electrically connected to the collector, base of the triode Q1, and the base of the triode Q2. The ACOT unit outputs the VDD voltage to the source of the MOS transistor P1 and the positive electrode of the polarized capacitor C1. The gate and drain of the MOS transistor P1 are electrically connected to the source of the MOS transistor P2. The gate and drain of the MOS transistor P2 are electrically connected to the negative electrode of the polarized capacitor C1, the gate of the MOS transistor P3, and the collector of the triode Q2. The source of the MOS transistor P3 is electrically connected to the frequency locking module, and the drain of the MOS transistor P3 is electrically connected to the timer module. The emitter of the triode Q1 and the emitter of the triode Q2 are both grounded.

[0062] When the external enable signal EN is at a low level, the high-voltage MOS transistor HVN1 is in the off state, having a good withstand voltage effect. When the external enable signal EN is at a high level, the high-voltage MOS transistor HVN1 enters the linear region, and the voltage VIN is sampled by the resistor R1, the triode Q1, and the triode Q2. The voltage information of VIN is converted into current information, and then converted into a voltage by the MOS transistors P1 and P2 and output to the gate of the MOS transistor P3 for gate voltage biasing to control the size of the integration current I in a feedforward manner. Among them, the polarized capacitor C1 functions to filter out high-frequency switching signals coupled into the gate potential of the MOS transistor P3. S Specifically, the frequency locking module includes the MOS transistors N7, N8, P9, P10, P11, P15, P16, the resistors R3, R4, the polarized capacitors C4, C5, C6, C7, and the transconductance amplifier OTA.

[0063] The ACOT unit outputs the VDD voltage to the drain of the MOS transistor N8, the source of the MOS transistor P17, the source of the MOS transistors P9, P10, and P11. The gate of the MOS transistor N8 is electrically connected to the drain of the MOS transistor P17, the output terminal of the transconductance amplifier OTA, and the positive electrode of the polarized capacitor C7; the source of the MOS transistor N8 is electrically connected to the VIN feedforward module, that is, the source of the MOS transistor N8 is electrically connected to the source of the MOS transistor P3; the external enable signal EN is input to the gate of the MOS transistor P17.

[0064] The ACOT unit outputs the current sink I to the gates of the MOS transistors P9, P10, and P11. The drain of the MOS transistor P9 is electrically connected to the drain of the MOS transistor N7, the positive electrode of the polarized capacitor C4, and the gate of the MOS transistor P15. The gate of the MOS transistor N7 is electrically connected to the control logic module; the drain of the MOS transistor P10 is electrically connected to one end of the resistor R3 and the source of the MOS transistor P15. The other end of the resistor R3 is electrically connected to one end of the resistor R4 and the positive electrode of the polarized capacitor C5. The other end of the resistor R4 is electrically connected to the positive electrode of the polarized capacitor C6 and the non-inverting input terminal of the transconductance amplifier OTA. The drain of the MOS transistor P11 is electrically connected to the source of the MOS transistor P16 and the inverting input terminal of the transconductance amplifier OTA. The ACOT unit outputs the reference voltage V to the gate of the MOS transistor P16. The sources of the MOS transistors N7, the drain of the MOS transistor P15, the drain of the MOS transistor P16, the negative electrodes of the polarized capacitors C4, C5, C6, and C7 are all grounded.

[0065] The ACOT unit outputs the current sink I BIAS to the gates of the MOS transistors P9, P10, and P11. The drain of the MOS transistor P9 is electrically connected to the drain of the MOS transistor N7, the positive electrode of the polarized capacitor C4, and the gate of the MOS transistor P15. The gate of the MOS transistor N7 is electrically connected to the control logic module; the drain of the MOS transistor P10 is electrically connected to one end of the resistor R3 and the source of the MOS transistor P15. The other end of the resistor R3 is electrically connected to one end of the resistor R4 and the positive electrode of the polarized capacitor C5. The other end of the resistor R4 is electrically connected to the positive electrode of the polarized capacitor C6 and the non-inverting input terminal of the transconductance amplifier OTA. The drain of the MOS transistor P11 is electrically connected to the source of the MOS transistor P16 and the inverting input terminal of the transconductance amplifier OTA. The ACOT unit outputs the reference voltage V REF1 to the gate of the MOS transistor P16. The sources of the MOS transistors N7, the drain of the MOS transistor P15, the drain of the MOS transistor P16, the negative electrodes of the polarized capacitors C4, C5, C6, and C7 are all grounded.

[0066] The gate of MOS transistor N7 samples the switching frequency period signal in the control logic module, and discharges the polarized capacitor C4 once in each switching cycle. MOS transistors P9, P10, and P11 mirror the current sink I BIAS proportionally. MOS transistor P9 continuously charges the polarized capacitor C4 to generate a triangular wave signal with a switching period T SW . Then, the SF (common-drain amplifier) composed of MOS transistors P10 and P15 completes impedance transformation. After passing through the second-order low-pass filter composed of resistor R3, resistor R4, polarized capacitor C5, and polarized capacitor C6, a DC component signal V AVG of the triangular wave is generated at the non-inverting input terminal of the transconductance amplifier OTA. The SF composed of MOS transistors P11 and P16 raises the reference voltage V REF1 to the inverting input terminal of the transconductance amplifier OTA to match the lifted voltage at the non-inverting terminal. OTA and C7 form a Gm-C compensation to limit the bandwidth of the frequency-locked loop. The voltage signal Vc at the output terminal of the transconductance amplifier OTA is reset to the VDD potential by MOS transistor P17 when the enable signal EN is at a low level, and controls the gate of MOS transistor N8 to control the magnitude of the integration current I S when the enable signal EN is at a high level.

[0067] Specifically, the timer module includes MOS transistors N1, N2, N3, N4, N5, N6, P4, P5, P6, P7, P8, P12, P13, P14, resistor R2, and polarized capacitors C2 and C3.

[0068] The ACOT unit outputs the VDD voltage to the positive electrode of the polarized capacitor C2, the source electrodes of MOS transistors P4, P5, P6, P7, and P8.

[0069] The ACOT unit outputs the current sink I BIAS to the gates, drains, and the negative electrode of the polarized capacitor C2, and the gates of MOS transistors P5, P6, P7, and P8. The drain of MOS transistor P5 is electrically connected to one end of resistor R2, the gates of MOS transistors N4 and N2. The other end of resistor R2 is electrically connected to the drains of MOS transistors N2, N1, and the gate of MOS transistor N3. The source of MOS transistor N2 is electrically connected to the drain of MOS transistor N1.

[0070] The drain of MOS transistor P6 is electrically connected to the drains of MOS transistors N4 and P12 and the control logic module. The source of MOS transistor N4 is electrically connected to the drains of MOS transistors N5 and P13, the gate of MOS transistor N6, and the positive electrode of polarized capacitor C3. The gate of MOS transistor N5 is electrically connected to the gates of MOS transistors P13 and the control logic module. The source of MOS transistor N5 is electrically connected to the drain of MOS transistor N3.

[0071] The drain of MOS transistor P7 is electrically connected to the source of MOS transistor P12. The gate of MOS transistor P12 is electrically connected to the output terminal of the logic control module. The source of MOS transistor P13 is electrically connected to the output terminal of the VIN feedforward module and the source of MOS transistor P14, that is, the source of MOS transistor P13 is electrically connected to the drain of MOS transistor P3 and the source of MOS transistor P14.

[0072] The drain of MOS transistor P8 is electrically connected to the drain of MOS transistor N6 and the first input terminal of the control logic module. The sources of MOS transistors N1 and N3, the drain, gate of MOS transistor P14, the source of MOS transistor N6, and the negative electrode of polarized capacitor C3 are all grounded.

[0073] MOS transistors P4, P5, P6, P7, and P8 have a proportional mirror relationship. MOS transistors N1, N2, and resistor R2 form a cascode self-bias and are used to bias the gate voltages of MOS transistors N3 and N4. Polarized capacitor C3 is an integrating capacitor. Through the control timing of MOS transistors N5, P12, P13, and the control logic module as switching transistors, the rising and falling edges of triangular waves with the required On-Time and Min Off-Time pulse widths can be generated respectively for each switching cycle. MOS transistors N6 and P8 form a first-stage CS (single-stage common-source amplifier) to act as a simple comparator. Polarized capacitor C2 filters out the high-frequency switching signals coupled into the gate potential of MOS transistor P4. MOS transistor P14 acts as an inverse ratio transistor to clamp the amplitude of the switching signal at its source end.

[0074] Specifically, the control logic module includes inverter INV1, inverter INV2, inverter INV3, NAND gate NAND, OR gate OR, and flip-flops RS1 and RS2.

[0075] The external enable signal EN is input to the input terminal of inverter INV3 and the first input terminal of NAND gate NAND. The output terminal of inverter INV3 is electrically connected to the first input terminal of OR gate OR.

[0076] The drain of MOS transistor P8 is electrically connected to the input terminal of inverter INV1. The output terminal of inverter INV1 is electrically connected to the input terminal of inverter INV2 and the first input terminal of the frequency locking module, that is, the output terminal of inverter INV1 is electrically connected to the input terminal of inverter INV2 and the gate of MOS transistor N7. The output terminal of inverter INV2 is electrically connected to the second input terminal of flip - flop RS1; the drain of MOS transistor P6 is electrically connected to the first input terminal of flip - flop RS1. The first output terminal of flip - flop RS1 is electrically connected to the first input terminal of flip - flop RS2; the second output terminal of flip - flop RS1 is electrically connected to the gate of MOS transistor P12. The output terminal of the ACOT unit outputs CMP_OUT to the second input terminal of flip - flop RS2. The first output terminal of flip - flop RS2 is electrically connected to the second input terminal of OR gate OR and outputs internal clock CLK_INT to the ACOT unit. The second output terminal of flip - flop RS2 is electrically connected to the second input terminal of NAND gate NAND. The output terminal of NAND gate NAND outputs pulse - width control signal ONE_SHOT2 to the ACOT unit. The output terminal of OR gate OR is electrically connected to the gate of MOS transistor N5 and outputs pulse - width control signal ONE_SHOT1 to the ACOT unit. In this embodiment, the following conditional expressions are satisfied,

[0077] W / L P3 =δW / L P2 ;

[0078] W / L P4 =W / L P5 ; W / L P10 =W / L P11 ; Further, W / L P4 =W / L P5 =W / L P10 =W / L P11 ;

[0079] W / L P15 =W / L P16 ;

[0080] W / L N3 =αW / L N1 ;

[0081] W / L N4 =αW / L N2 ;

[0082] W / L P6 <αW / L P5 ;

[0083] W / L P6 +W / L P7 >αW / L P5 ;

[0084] W / L P8 = βW / L P4 ;

[0085] W / L P9 = γW / L P4 ;

[0086] Among them, W / L Pn is the width-to-length ratio of MOS transistor Pn, W / L Nn is the width-to-length ratio of MOS transistor Nn; that is, W / L N1 is the width-to-length ratio of MOS transistor N1, W / L N2 is the width-to-length ratio of MOS transistor N2, W / L N3 is the width-to-length ratio of MOS transistor N3, W / L N4 is the width-to-length ratio of MOS transistor N4, W / L P2 is the width-to-length ratio of MOS transistor P2, W / L P3 is the width-to-length ratio of MOS transistor P3, W / L P4 is the width-to-length ratio of MOS transistor P4, W / L P5 is the width-to-length ratio of MOS transistor P5, W / L P6 is the width-to-length ratio of MOS transistor P6, W / L P7 is the width-to-length ratio of MOS transistor P7, W / L P8 is the width-to-length ratio of MOS transistor P8; W / L P9 is the width-to-length ratio of MOS transistor P9, W / L P10 is the width-to-length ratio of MOS transistor P10, W / L P11 is the width-to-length ratio of MOS transistor P11, W / L P15 is the width-to-length ratio of MOS transistor P15, W / L P16 is the width-to-length ratio of MOS transistor P16. α, β, γ and δ are proportionality coefficients.

[0087] When VDD is powered on and the enable signal EN is still low, the gates of the reset MOS transistors N5 and P13 are at high level, enabling the polarized capacitor C3 to discharge through the current sink of MOS transistor N3, turning off MOS transistor N6, and then turning on MOS transistor N4; and through the inverter INV1, MOS transistor N7 is turned off, and the polarized capacitor C4 is pulled up to VDD by MOS transistor P9, and through MOS transistors P10 and P15, the initial potential of the non-inverting terminal of the transconductance amplifier OTA is greater than the inverting before the release of the enable signal EN. By adjusting the mirror ratio, the sum of the pull-ups of MOS transistors P6 and P7 is greater than the pull-down of MOS transistor N3, while the pull-up of MOS transistor P6 is less than the pull-down of MOS transistor N3. And MOS transistors P6, P7, P12 and inverter INV2, flip-flop RS1 form an initial potential locking loop to ensure that MOS transistor P12 is turned on and the set input of flip-flop RS2 is at high level before the release of the enable signal EN.

[0088] In this embodiment, the outputs Q and / Q of the flip-flop RS2 may have two states before the release of the enable signal EN, which are 10 and 01 respectively. For the case where CMP_OUT input is 0 after the release of the enable signal EN, it will be determined as 01 and enter the On-Time timing stage. For the case where CMP_OUT input is 1, if it is 01, it will also enter the On-Time timing. After one On-Time pulse width of ONE_SHOT is generated, the CS output flips to low, and then through flip-flop RS1 and flip-flop RS2, the Q and / Q outputs of flip-flop RS2 are 10, and it remains in the Off-Time until the CMP_OUT input is at 0 level to generate another beat of On-Time; if it is 10, one beat of On-Time after the release of EN will be skipped.

[0089] Please refer to Figure 2 As shown, specifically, the ACOT unit includes a topology module, driver Driv_H, driver Driv_L, comparator COMP, MOS transistor N_H, MOS transistor N_L, polarized capacitor C_BOOT, polarized capacitor CL, resistor DCR, resistor ESR, resistor RL, resistor Rb1, resistor Rb2 and inductor L.

[0090] The drain of the topology module and MOS transistor N_H is electrically connected to the input voltage VIN. The topology module outputs VDD to the power supply terminals of driver Driv_H, driver Driv_L, the positive electrode of polarized capacitor C_BOOT, the power supply terminal of comparator COMP and the VIN feed-forward module, frequency locking module and timer module; the output terminal of the topology module is electrically connected to the input terminals of driver Driv_H and driver Driv_L; the topology module outputs a current sink I BIASTo the second input terminals of the timer module and the frequency locking module, the external enable signal EN, the internal clock CLK_INT, the pulse width control signal ONE_SHOT1, and the pulse width control signal ONE_SHOT2 are input to the topology module.

[0091] The output terminal of the driver Driv_H is electrically connected to the gate of the MOS transistor N_H. The ground terminal of the driver Driv_H is electrically connected to the source of the MOS transistor N_H, the negative electrode of the polarized capacitor C_BOOT, the drain of the MOS transistor N_L, and one end of the inductor L. The output terminal of the driver Driv_L is electrically connected to the gate of the MOS transistor N_L.

[0092] The other end of the inductor L is electrically connected to one end of the resistor DCR. The other end of the resistor DCR is electrically connected to one end of the resistor ESR, one end of the resistor RL, and one end of the resistor Rb1, and outputs VOUT to the external circuit. The other end of the resistor ESR is electrically connected to the positive electrode of the polarized capacitor CL. The other end of the resistor Rb1 is electrically connected to the non-inverting input terminal of the comparator COMP and one end of the resistor Rb2. The topology module outputs the reference voltage V REF2 To the inverting input terminal of the comparator COMP, and the output terminal of the comparator COMP outputs CMP_OUT to the second input terminal of the control logic module.

[0093] The ground terminal of the topology module, the ground terminal of the driver Driv_L, the source electrode of the MOS transistor N_L, the negative electrode of the polarized capacitor CL, the other end of the resistor RL, the other end of the resistor Rb2, and the ground terminal of the comparator COMP are all grounded. In this embodiment, the topology module includes VIN-UVLO, BGR, LDO, ZCD, CS, OTP, OCP, SCP, Boot Driv&LS, and Dead-Time CTL. Specifically, VIN-UVLO is an input power supply voltage undervoltage lockout circuit (VIN-Undervotage-Lockout); BGR is a bandgap reference (Bandgap Reference); LDO is a low dropout linear regulator (LowDropout Regulator); ZCD is a zero crossing detection circuit (Zero Crossing Detection); CS is a current sense circuit (Current Sense); OTP is an over temperature protection circuit (Over Temperature Protection); OCP is an over current protection circuit (Over Current Protection); SCP is a short circuit protection circuit (Short Circuit Protection); Boot Driv&LS is a bootstrap (capacitor) drive and level shift circuit (Boot Driver&Level Shift); Dead-Time CTL is a dead-time control circuit (Dead-TimeControl). Similarly, the topology module can also integrate other functional modules.

[0094] Furthermore, Min Off-Time is the Off-Time when, after On-Time, the flip-flop RS1 is set to 0 and the flip-flop RS2 is set to 1. At this time, even if the CMP_OUT input is at the 0 level, if the output voltage undervoltage state persists, the pulse width control signal ONE_SHOT1 remains output at 1. It remains in this state until the voltage on the polarized capacitor C3 discharges through the MOS transistor N3 until the MOS transistor N4 conducts. At this time, the MOS transistor P12 is cut off, so the flip-flop RS1 is set to 1. The pulse width control signal ONE_SHOT1 released by the flip-flop RS2 remains output at the 1 state. Therefore, it can be considered that the time period during which the potential on the polarized capacitor C3 discharges from the conduction threshold of the MOS transistor N6 to the conduction threshold of the MOS transistor N4 is approximately MinOff-Time.

[0095] In the above-mentioned complete switching cycle timing, when the CMP_OUT input persists at the 0 level, the / Q of the flip-flop RS2 is forced to output 1, and the On-Time pulse width of the ONE_SHOT2 output is at the 0 level. Through the external feedback loop of the ACOT unit, FB is raised to be greater than V REF2, the comparator COMP causes CMP_OUT to resume a high level. Under the condition of low VIN or when there is a large load current and a significant voltage drop occurs simultaneously, the output of the comparator COMP is always low, and then it enters the 100% duty cycle output state. Additionally, since the reset terminal of the flip-flop RS2 remains low, a periodic signal with the pulse width of Min Off-Time can be seen on the internal clock CLK_INT. However, through the negative feedback of the frequency locking module, the constant period of T SW can be maintained all the time.

[0096] Furthermore, because CMP_OUT and the set terminal of the flip-flop RS2 are asynchronous signals, the pulse width control signal ONE_SHOT2 can output a high level to enter the Off-Time only when CMP_OUT is at a high level and the flip-flop RS2 is set to a high level by the Min Off-Time pulse width within each T SW period. Under the condition of entering PSM, the steady-state waveform of FB obtained by dividing the VOUT voltage is greater than V REF2 above the trough point of the typical COT control and becomes less than V REF2 below the peak point.

[0097] As the input voltage VIN gradually decreases, the pulse width control signal ONE_SHOT2 at the port that currently outputs a one-shot pulse width every N Min Off-Time pulse widths Pulse will cause the VOUT to decrease because it cannot support a larger SW duty cycle. Through the comparator COMP, the proportion of the low level in the CMP_OUT waveform increases, that is, the proportion of the forced On-Time increases, and then the actual output Off-Time pulse width of the subsequent (N + 1)-th Min Off-Time pulse width Pulse is reduced, and finally the (N + 1)-th Pulse will be skipped. By analogy, a 100% SW output duty cycle can be achieved.

[0098] The version with Min Off-Time has higher frequency stability under the condition of full SW duty cycle output. However, as the Off-Time approaches and is less than Min Off-Time, the output voltage will drop, and there will be excessive power consumption due to the fixed-frequency switching operation. Since the version operating in PSM has the above-mentioned frequency hopping behavior, it can support a 100% SW duty cycle output. However, if it operates under the condition of approaching frequency hopping, there will be significant frequency jitter. Additionally, for the COT control architecture where the high-side switch is an NMOSFET and the bootstrap capacitor C BOOT needs to be charged, it is also necessary to enable a detection of V BOOTA power-down and one-shot charging function module, and the associated one must detect peak over-current events within the On-Time, and cannot use valley over-current protection (OCP) with stronger anti-noise ability. Therefore, the version with Min Off-Time is suitable for usage scenarios with higher input voltages and low EMI requirements, while the version operating in PSM is suitable for scenarios with a larger tolerance for EMI but requiring a higher conversion rate when the input voltage is lower than the output voltage within the operating conditions, such as when powered by a battery.

[0099] In this embodiment, MOS transistors P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16, and P17 are all PMOS transistors. MOS transistors N1, N2, N3, N4, N5, N6, N7, and N8 are all NMOS transistors. MOS transistor HVN1 is a high-voltage NMOS transistor.

[0100] In this embodiment, Vth_N is the threshold voltage of NMOS transistors and high-voltage NMOS transistors; Vov_Nn is the overdrive voltage of MOS transistor Nn; Vdsat_Nn is the saturated drain-source voltage of MOS transistor Nn; Rn is the resistance value of resistor Rn; Cn is the capacitance value of polarized capacitor Cn; Vth_P is the absolute value of the threshold voltage of PMOS transistors; Vov_HVNn is the overdrive voltage of MOS transistor HVNn; Vov_Pn is the overdrive voltage of MOS transistor Pn; Vgs_Nn is the gate-source voltage of MOS transistor Nn; Vgs_HVNn is the gate-source voltage of MOS transistor HVNn; Vsg_Pn is the gate-source voltage of MOS transistor Pn; Vdsat_HVNn is the saturated drain-source voltage of MOS transistor HVNn; Vdsat_Pn is the saturated drain-source voltage of MOS transistor Pn; Av_OTA is the small-signal intrinsic voltage gain of OTA; Gm_OTA is the small-signal input transconductance of OTA; Ro_OTA is the small-signal output impedance of OTA; gm_Nn is the small-signal input transconductance of MOS transistor Nn; gm_Pn is the small-signal input transconductance of MOS transistor Pn; MOT is the minimum off-time; T SW is the switching period; F SW is the switching frequency; D is the duty cycle; Kn is the transconductance coefficient of MOS transistor Nn; Kp is the transconductance coefficient of MOS transistor Pn; I S is the integration current; I SX is the approximate integration current; s is the complex frequency; ξ is the non-ideal factor; V T is the thermal voltage; ω0 is the characteristic angular frequency of the second-order RC filter; PMMIN The minimum phase margin; ε is the proportionality coefficient of the switching period to the characteristic time of the RC filter; I stb is the standby power consumption; I WORK is the operating power consumption; I OTA is the power consumption of the OTA.

[0101] Furthermore, to ensure that MOS transistors N1 and N2 operate in the saturation region, the following conditional expressions are satisfied

[0102]

[0103]

[0104] When operating in PWM:

[0105]

[0106]

[0107]

[0108] Where:

[0109]

[0110] Since MOS transistor P1 needs to be used as a ratioed transistor to ensure that the output voltage Vc of the transconductance amplifier OTA does not exceed the linear output range during the steady state of frequency locking, a diode-connected NMOS transistor Nx can be assumed to replace P1:

[0111]

[0112] Then:

[0113]

[0114]

[0115] It is obtained that:

[0116]

[0117] Obviously, it is easy to achieve:

[0118]

[0119]

[0120] Therefore:

[0121]

[0122]

[0123] After arrangement, we get:

[0124]

[0125] In the typical application scenarios of a Buck controller, this equation is easily satisfied. Therefore, although this structure limits the minimum value of D, it generally does not need to be considered.

[0126] When operating in PSM:

[0127] Attention should be paid to the loop stability controlled by the ACOT unit. Generally, a function module that limits the minimum switching frequency will be activated (such as making the switching frequency greater than the audio frequency of 25KHz), and the selection values of the resistance ESR and the polarized capacitor CL need to be considered. An internal ramp compensation module can also be added to sample the ripple current of the inductor L and superimpose it on the resistor FB. For example, the common Ri compensation. Regarding the loop stability of the ACOT unit control loop, there have been many sufficient studies. Therefore, without proof, we can obtain:

[0128]

[0129] It should be particularly noted that for the stability analysis of the added frequency locking module in this embodiment, whether operating in PWM or PSM, the following analysis is the same:

[0130] Perform small-signal modeling on the frequency locking module:

[0131]

[0132] The loop gain can be obtained:

[0133]

[0134] Where:

[0135]

[0136] For LoopGain(0), it needs to be large enough to ensure that the stable value of the switching frequency after closing the loop is relatively constant with the change of D (V IN , V OUT , I LOAD ). The worst-case scenario needs to be considered, that is, D takes an approximate minimum value of:

[0137]

[0138] Substitute it into LoopGain(0) to get:

[0139]

[0140] Therefore, selecting a single-stage transconductance amplifier OTA can meet the requirements without consuming additional power.

[0141] In addition, when |LoopGain(0)| MAX is satisfied, let D→1, and the approximation of the MOS transistor N8 and the MOS transistor P3 operating in the subthreshold region is as follows:

[0142]

[0143] Also:

[0144]

[0145] We get:

[0146]

[0147] Then considering the stability of LoopGain(s), considering s = -1 / (R O_OTA ·C7) as the dominant pole and pushing the two poles introduced by the second-order low-pass RC network outside the bandwidth BW,

[0148] That is:

[0149]

[0150]

[0151] Let R3 = R4 = R; C5 = C6 = C;

[0152]

[0153] That is:

[0154]

[0155] Considering that the parameters other than R, C, G M_OTA , and C7 have been determined previously, only need to further select R, C, G M_OTA , and C7 to satisfy the above formula. In addition, it can be seen that taking a large C7 and a small G M_OTA are both beneficial to the loop stability. Considering power consumption and area, a single-stage low-bandwidth transconductance amplifier OTA can be used to implement it.

[0156] For example, calculate the minimum value of the phase margin according to the dominant pole approximation:

[0157]

[0158] Among them, take:

[0159]

[0160] And let:

[0161]

[0162] Intuitively, the larger ε is, the faster the response speed of the frequency locking module. However, since the cut-off frequency of the second-order low-pass RC network is pushed to a higher frequency, the in-phase terminal of the transconductance amplifier OTA will see higher-amplitude high-order harmonic components, which may cause the transconductance amplifier OTA to operate in the non-linear region and the loop behavior to be difficult to predict. On the contrary, the smaller ε is, the slower the response speed of the frequency locking module, which causes the overall ACOT unit control loop to generate more EMI energy outside the switching frequency during transient response because the switching frequency cannot be stabilized in time.

[0163] The standby power consumption and working power consumption of this One-Shot module are given as follows:

[0164]

[0165]

[0166] Furthermore:

[0167]

[0168] Therefore, when taking I BIAS , I OTA low enough, the main power consumption ratio will be "(2 + δ)(VIN - VBE) / R1", or the resistance R1 can be made large enough to compensate, but this requires sacrificing the layout area and the speed of the feedforward path.

[0169] Building an actual circuit simulation can prove that it is easy to control the maximum working current within 20uA. Also, due to integrating the functions of the one-shot / min off-time timer and the osc module in the typical COT control circuit topology, it has the advantages of high integration and improved utilization rate of the layout area.

[0170] Please refer to Appendix Figure 3 , Appendix Figure 3 which is the simulation waveform diagram of the switching frequency stability. As can be seen from Appendix Figure 3 , when fixing VOUT and the inductor current I L , with the increase of VIN, the switching frequency will slowly decrease. It is obtained that F SW changes by 13KHz within the duty cycle change range of 20.8% - 72.6%. Since the measured average frequency is about 665KHz, a frequency stability of ±1% can be achieved.

[0171] Please refer to Appendix Figure 4 , Appendix Figure 4 which is the simulation waveform diagram of the function from PWM to PSM to 100% duty cycle. As can be seen from Appendix Figure 4It can be seen that the adaptive constant-on-time buck circuit disclosed in this embodiment can achieve a 100% SW output duty cycle via PSM.

[0172] As described above, the foregoing is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. An adaptive constant on-time buck circuit, characterized in that, It includes a VIN feed-forward module, a frequency-locked module, a timer module, a control logic module, and an ACOT unit; The input end of the VIN feed-forward module is electrically connected to the input voltage VIN. The first input end of the frequency-locking module collects the switching frequency period signal of the control logic module. The ACOT unit outputs a current sink I BIAS to the second input ends of the timer module and the frequency-locking module. The ACOT unit outputs a reference voltage V REF1 to the third input end of the frequency-locking module. The output ends of the VIN feed-forward module and the frequency-locking module are electrically connected to the timer module to control the integrated current I S of the timer module; The output terminal of the timer module is electrically connected to the first input terminal of the control logic module. The external enable signal EN is input to the VIN feed-forward module, the frequency-locked module, the control logic module, and the ACOT unit. The output terminal of the ACOT unit outputs CMP_OUT to the second input terminal of the control logic module. The control logic module outputs the internal clock CLK_INT, the pulse-width control signal ONE_SHOT1, and the pulse-width control signal ONE_SHOT2 to the ACOT unit; The ACOT unit outputs the VDD voltage to the VIN feed-forward module, the frequency-locked module, and the timer module.

2. The adaptive constant on-time buck circuit according to claim 1, wherein: The VIN feed-forward module includes MOS transistor HVN1, MOS transistor P1, MOS transistor P2, MOS transistor P3, bipolar transistor Q1, bipolar transistor Q2, resistor R1, and polarized capacitor C1; One end of the resistor R1 is electrically connected to the input voltage VIN. The other end of the resistor R1 is electrically connected to the drain of the MOS transistor HVN1. The external enable signal EN is input to the gate of the MOS transistor HVN1. The source of the MOS transistor HVN1 is electrically connected to the collector, base of the bipolar transistor Q1, and the base of the bipolar transistor Q2; The ACOT unit outputs the VDD voltage to the source of the MOS transistor P1 and the positive electrode of the polarized capacitor C1. The gate and drain of the MOS transistor P1 are electrically connected to the source of the MOS transistor P2. The gate and drain of the MOS transistor P2 are electrically connected to the negative electrode of the polarized capacitor C1, the gate of the MOS transistor P3, and the collector of the bipolar transistor Q2. The source of the MOS transistor P3 is electrically connected to the frequency-locked module. The drain of the MOS transistor P3 is electrically connected to the timer module; The emitters of the bipolar transistor Q1 and the bipolar transistor Q2 are both grounded.

3. The adaptive constant on-time buck circuit according to claim 1, wherein: The frequency-locked module includes MOS transistor N7, MOS transistor N8, MOS transistor P9, MOS transistor P10, MOS transistor P11, MOS transistor P15, MOS transistor P16, resistor R3, resistor R4, polarized capacitor C4, polarized capacitor C5, polarized capacitor C6, polarized capacitor C7, and transconductance amplifier OTA; The ACOT unit outputs the VDD voltage to the drain of the MOS transistor N8, the source of the MOS transistor P17, the source of the MOS transistor P9, the source of the MOS transistor P10, and the source of the MOS transistor P11; The gate of the MOS transistor N8 is electrically connected to the drain of the MOS transistor P17, the output terminal of the transconductance amplifier OTA, and the positive electrode of the polarized capacitor C7. The source of the MOS transistor N8 is electrically connected to the VIN feed-forward module. The external enable signal EN is input to the gate of the MOS transistor P17; The ACOT unit outputs a current sink I BIAS to the gates of MOS transistor P9, MOS transistor P10, and MOS transistor P11. The drain of MOS transistor P9 is electrically connected to the drain of MOS transistor N7, the positive electrode of polarized capacitor C4, and the gate of MOS transistor P15. The gate of MOS transistor N7 is electrically connected to the control logic module. The drain of MOS transistor P10 is electrically connected to one end of resistor R3 and the source of MOS transistor P15. The other end of resistor R3 is electrically connected to one end of resistor R4 and the positive electrode of polarized capacitor C5. The other end of resistor R4 is electrically connected to the positive electrode of polarized capacitor C6 and the non-inverting input terminal of transconductance amplifier OTA. The drain of MOS transistor P11 is electrically connected to the source of MOS transistor P16 and the inverting input terminal of transconductance amplifier OTA. The ACOT unit outputs a reference voltage V REF1 to the gate of MOS transistor P16; The sources of the MOS transistor N7, the drains of the MOS transistor P15, the drains of the MOS transistor P16, the negative electrodes of the polarized capacitor C4, the negative electrodes of the polarized capacitor C5, the negative electrodes of the polarized capacitor C6, and the negative electrode of the polarized capacitor C7 are all grounded.

4. The adaptive constant on-time buck circuit according to claim 1, wherein: The timer module includes MOS transistors N1, N2, N3, N4, N5, N6, P4, P5, P6, P7, P8, P12, P13, P14, resistor R2, and polarized capacitors C2 and C3; The ACOT unit outputs the VDD voltage to the positive electrode of the polarized capacitor C2, the source electrodes of the MOS transistors P4, P5, P6, P7, P8; The ACOT unit outputs a current sink I BIAS to the gates, drains of MOS transistor P4, the negative electrode of polarized capacitor C2, the gates of MOS transistors P5, P6, P7, and P8; the drain of MOS transistor P5 is electrically connected to one end of resistor R2, the gates of MOS transistors N4 and N2, and the other end of resistor R2 is electrically connected to the drains of MOS transistors N2, N1, and N3, and the source of MOS transistor N2 is electrically connected to the drain of MOS transistor N1; The drain electrode of the MOS transistor P6 is electrically connected to the drain electrodes of the MOS transistors N4 and P12 and the control logic module. The source electrode of the MOS transistor N4 is electrically connected to the drain electrode of the MOS transistor N5, the drain electrodes of the MOS transistors P13 and N6, and the positive electrode of the polarized capacitor C3. The gate electrode of the MOS transistor N5 is electrically connected to the gate electrodes of the MOS transistors P13 and the control logic module. The source electrode of the MOS transistor N5 is electrically connected to the drain electrode of the MOS transistor N3; The drain electrode of the MOS transistor P7 is electrically connected to the source electrode of the MOS transistor P12. The gate electrode of the MOS transistor P12 is electrically connected to the output terminal of the logic control module. The source electrode of the MOS transistor P13 is electrically connected to the output terminal of the VIN feedforward module and the source electrode of the MOS transistor P14; The drain electrode of the MOS transistor P8 is electrically connected to the drain electrode of the MOS transistor N6 and the first input terminal of the control logic module; The source electrodes of the MOS transistors N1 and N3, the drain, gate electrodes of the MOS transistor P14, the source electrode of the MOS transistor N6, and the negative electrode of the polarized capacitor C3 are all grounded.

5. The adaptive constant-on-time buck circuit according to claim 4, wherein: The control logic module includes inverters INV1, INV2, INV3, NAND gate NAND, OR gate OR, and flip-flops RS1 and RS2; The external enable signal EN is input to the input terminal of the inverter INV3 and the first input terminal of the NAND gate NAND. The output terminal of the inverter INV3 is electrically connected to the first input terminal of the OR gate OR; The drain of the MOS transistor P8 is electrically connected to the input terminal of the inverter INV1. The output terminal of the inverter INV1 is electrically connected to the input terminal of the inverter INV2 and the first input terminal of the frequency locking module. The output terminal of the inverter INV2 is electrically connected to the second input terminal of the flip-flop RS1. The drain of the MOS transistor P6 is electrically connected to the first input terminal of the flip-flop RS1. The first output terminal of the flip-flop RS1 is electrically connected to the first input terminal of the flip-flop RS2. The second output terminal of the flip-flop RS1 is electrically connected to the gate of the MOS transistor P12. The output terminal of the ACOT unit outputs CMP_OUT to the second input terminal of the flip-flop RS2. The first output terminal of the flip-flop RS2 is electrically connected to the second input terminal of the OR gate and outputs the internal clock CLK_INT to the ACOT unit. The second output terminal of the flip-flop RS2 is electrically connected to the second input terminal of the NAND gate. The output terminal of the NAND gate outputs the pulse width control signal ONE_SHOT2 to the ACOT unit. The output terminal of the OR gate is electrically connected to the gate of the MOS transistor N5 and outputs the pulse width control signal ONE_SHOT1 to the ACOT unit.

6. The adaptive constant on-time buck circuit according to claim 1, wherein: The ACOT unit includes a topology module, a driver Driv_H, a driver Driv_L, a comparator COMP, a MOS transistor N_H, a MOS transistor N_L, a polarized capacitor C_BOOT, a polarized capacitor CL, a resistor DCR, a resistor ESR, a resistor RL, a resistor Rb1, a resistor Rb2, and an inductor L; The drain of the topology module and MOS transistor N_H is electrically connected to the input voltage VIN. The topology module outputs VDD to the power supply terminal of driver Driv_H, the power supply terminal of driver Driv_L, the positive electrode of polarized capacitor C_BOOT, the power supply terminal of comparator COMP, and the VIN feedforward module, frequency locking module, and timer module. The output terminal of the topology module is electrically connected to the input terminals of driver Driv_H and driver Driv_L. The topology module outputs current sink I BIAS to the second input terminals of the timer module and frequency locking module. The external enable signal EN, internal clock CLK_INT, pulse width control signal ONE_SHOT1, and pulse width control signal ONE_SHOT2 are input to the topology module. The output terminal of the driver Driv_H is electrically connected to the gate of the MOS transistor N_H. The ground terminal of the driver Driv_H is electrically connected to the source of the MOS transistor N_H, the negative electrode of the polarized capacitor C_BOOT, the drain of the MOS transistor N_L, and one end of the inductor L. The output terminal of the driver Driv_L is electrically connected to the gate of the MOS transistor N_L; The other end of the inductor L is electrically connected to one end of the resistor DCR, and the other end of the resistor DCR is electrically connected to one end of the resistor ESR, one end of the resistor RL, and one end of the resistor Rb1, and outputs VOUT to an external circuit; the other end of the resistor ESR is electrically connected to the positive electrode of the polarized capacitor CL, and the other end of the resistor Rb1 is electrically connected to the non-inverting input terminal of the comparator COMP and one end of the resistor Rb2; the topology module outputs a reference voltage V REF2 to the inverting input terminal of the comparator COMP, and the output terminal of the comparator COMP outputs CMP_OUT to the second input terminal of the control logic module; The ground terminal of the topology module, the ground terminal of the driver Driv_L, the source of the MOS transistor N_L, the negative electrode of the polarized capacitor CL, the other end of the resistor RL, the other end of the resistor Rb2, and the ground terminal of the comparator COMP are all grounded.

7. The adaptive constant-on-time buck circuit according to claim 4, wherein: The following conditional expression is satisfied, W / L P4 =W / L P5 ; W / L N3 =αW / L N1 ; W / L N4 = αW / L N2 ; W / L P6 <αW / L P5 ; W / L P6 +W / L P7 >αW / L P5 ; W / L P8 =βW / L P4 ; where, W / L Pn is the width-to-length ratio of MOS transistor Pn, and W / L Nn is the width-to-length ratio of MOS transistor Nn; that is, W / L N1 is the width-to-length ratio of MOS transistor N1, and W / L N2 is the width-to-length ratio of MOS transistor N2, and W / L N3 is the width-to-length ratio of MOS transistor N3, and W / L N4 is the width-to-length ratio of MOS transistor N4, and W / L P4 is the width-to-length ratio of MOS transistor P4, and W / L P5 is the width-to-length ratio of MOS transistor P5, and W / L P6 is the width-to-length ratio of MOS transistor P6, and W / L P7 is the width-to-length ratio of MOS transistor P7, and W / L P8 is the width-to-length ratio of MOS transistor P8; α and β are proportionality coefficients.

8. The adaptive constant-on-time buck circuit according to claim 3, wherein: The following conditional expression is satisfied, W / L P10 =W / L P11 ; W / L P15 =W / L P16 ; Among them, W / L Pn is the width-to-length ratio of MOS transistor Pn; that is, W / L P10 is the width-to-length ratio of MOS transistor P10, W / L P11 is the width-to-length ratio of MOS transistor P11, W / L P15 is the width-to-length ratio of MOS transistor P15, W / L P16 is the width-to-length ratio of MOS transistor P16.

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