A digital predistortion high-precision phase interpolator with constant input load

Abstract

This invention relates to a high-precision digital predistortion phase interpolator with a constant input load, comprising: a multi-phase clock generation circuit, an input buffer circuit, two pre-filter circuits, a phase interpolation core circuit, a CML2CMOS circuit, and a control code decoder circuit. The two pre-filter circuits convert two full-swing square wave signals into two sinusoidal clocks. The phase interpolation core circuit performs nonlinear interpolation on the two sinusoidal clocks with a constant input load based on two weighted control codes, outputting a small-swing signal. This phase interpolator significantly improves interpolation accuracy. Digital predistortion of the interpolation weights can be achieved by adjusting the control code decoder, further enhancing the accuracy of the phase interpolator and enabling high-speed, high-precision output clocks. It is suitable for clock data recovery circuits and phase-locked loops in high-speed SerDes systems.

Description

Technical Field

[0001] This invention belongs to the field of mixed-signal integrated circuit design technology, and specifically relates to a digital predistortion high-precision phase interpolator with constant input load. Background Technology

[0002] The ever-increasing demands for communication and high-performance computing are driving wired transceivers to operate at higher data rates, and the jitter and accuracy of the local clock directly determine the transceiver's operational precision. Therefore, to achieve efficient and high-speed data links, high-speed, high-precision, small-area, and low-power clock generation circuits have become a research hotspot.

[0003] A phase interpolator (PI) is used in clock generation circuits to adjust the clock phase. Its working principle is as follows: the phase interpolator uses multiple input clocks with different phases, selects two adjacent input phases, and performs weighted interpolation. By adjusting the weights of the two phases, a clock of arbitrary phase is output. Because the phase interpolator is entirely driven by an external input clock and does not require an oscillator, it has superior noise performance. Furthermore, the phase interpolator directly provides phase feedback rather than frequency feedback, resulting in more accurate and stable locking compared to a voltage-controlled oscillator (VCO).

[0004] However, traditional linear phase interpolators require the use of triangular waves to achieve high interpolation accuracy, but it is difficult to obtain excellent triangular wave clocks in actual circuits. Furthermore, traditional linear phase interpolators suffer from a certain degree of PI phasor constellation diagram offset and linearity degradation, which further affects the interpolation accuracy of traditional linear phase interpolators. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a high-precision digital predistortion phase interpolator with a constant input load. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] This invention provides a digital predistortion high-precision phase interpolator with constant input load, comprising: a multi-phase clock generation circuit, an input buffer circuit, two pre-filter circuits, a phase interpolation core circuit, a CML2CMOS circuit, and a control code decoder circuit, wherein...

[0007] The multiphase clock generation circuit is used to divide the input differential clock signal and output a four-phase quadrature clock with a frequency of 1 / 2.

[0008] The input buffer circuit is used to adjust the waveform and duty cycle of the four-phase quadrature clock and output two full-swing square wave signals.

[0009] The control code decoder circuit is used to decode the K-Bit binary control code and output the quadrant selection code and two weighted control codes.

[0010] The two pre-filtering circuits are used to sequentially perform interpolation pre-quadrant selection, common-mode level adjustment, signal shaping and filtering on the two full-swing square wave signals according to the quadrant selection code and the first bias level, so as to convert the two full-swing square wave signals into two sinusoidal clocks.

[0011] The phase interpolation core circuit is used to perform nonlinear interpolation on the two sinusoidal clocks with a constant input load according to the two weighted control codes, and output a small swing signal.

[0012] The CML2CMOS circuit is used to expand the small-amplitude signal into a full-amplitude signal and output it.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0014] This invention provides a digital predistortion high-precision phase interpolator with constant input load, which uses two weighted control codes WEIGHT to achieve this. 0～2K-3 For two sinusoidal clocks CLK CML This nonlinear interpolation significantly improves interpolation accuracy, making it suitable for clock generation modules such as clock data recovery circuits and phase-locked loop circuits. Furthermore, this phase interpolator can achieve digital pre-distortion of the interpolation weights by adjusting the control code decoder, further improving the accuracy of the phase interpolator and enabling high-speed, high-precision output clocks. It is suitable for clock data recovery circuits and phase-locked loops in high-speed SerDes (serializer / deserializer) systems. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the circuit structure of a digital predistortion high-precision phase interpolator with constant input load provided in an embodiment of the present invention;

[0016] Figure 2 This is a schematic diagram of the multiphase clock generation circuit provided in an embodiment of the present invention;

[0017] Figure 3 This is a schematic diagram of the structure of the Latch provided in an embodiment of the present invention;

[0018] Figure 4 This is a schematic diagram of the control code decoder circuit provided in an embodiment of the present invention;

[0019] Figure 5 This is a schematic diagram of the pre-filter circuit provided in an embodiment of the present invention;

[0020] Figure 6 This is a schematic diagram of the phase interpolation core circuit provided in an embodiment of the present invention;

[0021] Figure 7 This is a schematic diagram of the phase interpolation unit provided in an embodiment of the present invention;

[0022] Figure 8 This is a performance comparison chart between a traditional interpolation unit and the phase interpolation unit provided in this embodiment of the invention. Detailed Implementation

[0023] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0024] Example 1

[0025] Please see Figure 1 , Figure 1 This is a schematic diagram of the circuit structure of a digital predistortion high-precision phase interpolator with constant input load provided in an embodiment of the present invention.

[0026] This embodiment provides a digital predistortion high-precision phase interpolator with constant input load, comprising: a multi-phase clock generation circuit, an input buffer circuit, two pre-filter circuits, a phase interpolation core circuit, a CML2CMOS circuit, and a control code decoder circuit. The multi-phase clock generation circuit is used to process the input differential clock signal CLK. IN Frequency division is performed to output a quadrature clock CLK with half the frequency. DIV The input buffer circuit is used for the four-phase quadrature clock CLK. DIV Adjust the waveform and duty cycle to output two full-swing square wave signals CLK. CORE_IN The control code decoder circuit is used to decode the K-bit binary control code and output the quadrant selection code SEL. 0～1 and two-way weight control codes WEIGHT 0～2K-3 Two pre-filter circuits are used to select the quadrant code SEL. 0～1 The first bias level VB_CML is used to control the two full-swing square wave signals CLK. CORE_IN The two full-swing square wave signals CLK are sequentially processed by quadrant selection before interpolation, common-mode level adjustment, signal shaping, and filtering. CORE_IN Converted to two-channel sine clock CLK CML The phase interpolation core circuit is used to apply two weighted control codes (WEIGHT) to a constant input load. 0～2K-3 For two sinusoidal clocks CLK CML Perform nonlinear interpolation to output a small-amplitude signal CLK. CORE OUTThe CML2CMOS circuit is used to convert the small-amplitude signal CLK. CORE_OUT Extended to full-swing signal CLK OUT And output it.

[0027] In this embodiment, the differential clock signal CLK IN Includes: positive differential clock signal CLK IN，P and negative differential clock signal CLK IN，N Four-phase quadrature clock CLK DIV Includes: I-channel forward clock CLK DIV，IP CLK (I-channel reverse clock) DIV，IN Q-path forward clock CLK DIV，QP Q-channel reverse clock CLK DIV，QN Two-way weight control code WEIGHT 0～2K-3 Includes: I-way weight code WEIGHT I And Q-way weight code WEIGHT Q Two full-swing square wave signals CLK CORE_IN The duty cycle is 50%, and the two full-swing square wave signals CLK CORE_IN Includes: I-channel full-swing square wave signal CLK CORE_IN，I and Q-channel full-swing square wave signal CLK CORE_IN，Q Two-way sine clock CLK CML Includes: I-channel sine clock CLK CML，I and Q-channel sine clock CLK CML，Q Two-way sine clock CLK CML Two full-swing square wave signals CLK CORE_IN and small swing signal CLK CORE_OUT All are differential signals, therefore, they can be further divided into positive differential signals and negative differential signals. Among them, the I-way weight code WEIGHT... I And Q-way weight code WEIGHT Q These are respectively used to control the phase interpolation core circuit for the I-channel sinusoidal clock CLK. CML，I and Q-channel sine clock CLK CML，Q Interpolation weights.

[0028] Please see Figure 2 , Figure 2 This is a schematic diagram of the multiphase clock generation circuit provided in an embodiment of the present invention. In this embodiment, the multiphase clock generation circuit uses a differential clock signal CLK. IN The two cascaded latches drive a quadrature clock CLK. DIV The multiphase clock generation circuit includes a first-stage latch and a second-stage latch. The first-stage latch receives a positive differential clock signal CLK at its driver input. IN，PThe inverting output of the first-stage latch is connected to the non-inverting input of the second-stage latch, and outputs one positive clock signal CLK. DIV，IP The positive output of the first-stage latch is connected to the inverting input of the second-stage latch, and outputs one inverted clock CLK. DIV，IN The second-stage latch receives a negative differential clock signal CLK as its driver input. IN，N The positive output of the second-stage latch is connected to the positive input of the first-stage latch and outputs a Q-channel reverse clock CLK. DIV，QN The inverting output of the second-stage latch is connected to the inverting input of the first-stage latch and outputs a Q-channel positive clock CLK. DIV，QP The input buffer circuit converts the four-phase quadrature clock CLK into a single input. DIV The waveform is shaped into a full-amplitude square wave, and the duty cycle is adjusted to 50%.

[0029] Please see Figure 3 , Figure 3 This is a schematic diagram of the Latch structure provided in an embodiment of the present invention. In this embodiment, the first-stage Latch and the second-stage Latch have the same structure, both including: transistor M. P1 ~M P2 Transistor M N9 ~M N13 Among them, transistor M N9 The gate of transistor M is the positive input terminal. N10 The gate of transistor M is the inverting input. N9 M N10 The source is connected to transistor M N13 The drain of transistor M. N13 The gate is the driving terminal, and the differential clock signal CLK is input. IN Transistor M N13 The source of transistor M is connected to ground potential GND. N9 The drain of the transistor M P1 The drain of the transistor M N12 The source is connected to transistor M P2 The gate of the transistor is connected, and the output is a positive output terminal. Transistor M N10 The drain of the transistor M P2 The drain of the transistor M N11 The source is connected to transistor M P1 The gate of the transistor is connected, and the output is set as the inverting output. Transistor M P1 M P2 The source and transistor M N11 M N12 The drain of the transistor is connected to the power supply potential VDD. In this latch, transistor M... N11 and transistor MN12 Constructing a source follower increases speed by providing a feedforward path for the output, while minimizing system power consumption. It should be understood that transistor M... P1 ~M P2 For PMOS transistors, transistor M N9 ~M N13 It is an NMOS transistor.

[0030] Please see Figure 4 , Figure 4 This is a schematic diagram of the control code decoder circuit provided in this embodiment of the invention. In this embodiment, the control code decoder circuit is implemented by a pure combinational logic digital circuit. This embodiment uses nonlinear phase interpolation to decouple the weighted control codes of two adjacent clocks, allowing them to be adjusted separately. A single quadrant of the phasor constellation diagram has NxN usable phase points, significantly increasing the design space and providing ample selection for N linear phase outputs in the corresponding quadrant. In this embodiment, the number of I-channels enabled and the number of Q-channels enabled are used as the X-axis and Y-axis, respectively. Figure 4 This refers to its phasor constellation diagram. The control code decoder circuit decodes the K-bit binary control code to obtain the coordinates of the ideal output point of the interpolator, such as... Figure 4 As shown, the nth ideal output point (interpolation point) of the interpolator is However, ideal output points mostly fall between the grid points of available phase points, making it difficult for actual circuits to accurately implement the corresponding weights. Therefore, in this embodiment, the modulus of the distance between the ideal output point and its four adjacent available phase points is calculated using Matlab. The control code decoder circuit selects the available phase point with the smallest modulus as the approximate output point and converts the quadrant where the approximate output point is located into the quadrant selection code SEL. 0～1 The output will output the x and y coordinates corresponding to the approximate output points as I-way weight codes WEIGHT. I And Q-way weight code WEIGHT Q In use, the digital circuit of the control code decoder can be adjusted according to the actual test conditions to modify the output weight value, thereby obtaining higher accuracy and achieving digital predistortion.

[0031] Please see Figure 5 , Figure 5 This is a schematic diagram of the pre-filter circuit provided in an embodiment of the present invention. Each of the two pre-filter circuits has the same structure, and one of the two pre-filter circuits is used to filter the I-channel full-swing square wave signal CLK. CORE_IN，I Convert to I-channel sine clock CLK CML，I The other path is used to convert the full-swing square wave signal CLK from the Q path. CORE_IN，Q Convert to Q-channel sine clock CLK CML，Q .

[0032] In this embodiment, each pre-filter circuit includes a quadrant selection sub-circuit and a filtering sub-circuit. The quadrant selection sub-circuit is used to select the quadrant selection code SEL. 0～1 Control two full-swing square wave signals CLK CORE_IN Selective switching. The filter sub-circuit is connected to the output of the quadrant selection sub-circuit, and selectively switches the two full-swing square wave signals CLK after switching according to the first bias level VB_CML. CORE_IN Common-mode level adjustment is performed, followed by signal shaping and filtering, outputting two sinusoidal clock channels CLK. CML .

[0033] Furthermore, the quadrant selection sub-circuit includes transmission gates TRAN1 to TRAN4. Transmission gates TRAN1, TRAN2, TRAN3, and TRAN4 are all subject to the quadrant selection code SEL. 0～1 The control is such that the input terminals of transmission gate TRAN1 and TRAN2 are used as inverting input terminals, the input terminals of transmission gate TRAN3 and TRAN4 are used as positive input terminals, the output terminals of transmission gate TRAN1 and TRAN3 are used as first output terminals, and the output terminals of transmission gate TRAN2 and TRAN4 are used as second output terminals.

[0034] In this embodiment, the filter sub-circuit includes an AC coupling module, a CML buffer, and a low-pass filter connected in sequence. The AC coupling module includes capacitors C1 and C2, resistors R1 and R2, and the CML buffer includes transistor M. N6 Transistor M N7 Transistor M N8 The low-pass filter includes resistors R3 and R4, and capacitors C3, C4, R5, and R6. The first terminal of capacitor C1 is connected to the outputs of transmission gates TRAN1 and TRAN3, the first terminal of capacitor C2 is connected to the outputs of transmission gates TRAN2 and TRAN4, and the second terminal of capacitor C1 is connected to the first terminal of resistor R1 and transistor M. N6 The gate of the transistor, the second terminal of capacitor C2 is connected to the first terminal of resistor R2 and transistor M. N7 The gate of transistor M is connected to the third bias level VCM via the second terminals of resistors R1 and R2. N6 and M N7 The source terminal is connected to transistor M N8 The drain terminal of transistor M N8 The gate of transistor M is connected to the first bias level VB_CML. N8 The source terminal is connected to ground potential GND, transistor M N6The drain terminal of transistor M is connected to the first terminal of resistor R3 and the first terminal of resistor R5. N7 The drain terminal is connected to the first terminal of the load resistor R4 and the first terminal of the filter resistor R6. The second terminals of the load resistors R3 and R4 are connected to the power supply potential VDD. The second terminal of the filter resistor R5 and the first terminal of the filter capacitor C3 are connected together to form the inverting output terminal. The second terminal of the filter resistor R6 and the first terminal of the filter capacitor C5 are connected together to form the positive output terminal. The second terminals of capacitors C3 and C4 are connected to the ground potential GND. A full-swing square wave signal CLK is used. CORE_IN and I-channel sine clock CLK CML，I For example, the I-channel full-swing square wave signal CLK CORE_IN，I The positive differential signal CLK CORE_IN，IP Input from the positive input terminal, I-channel full-swing square wave signal CLK CORE_IN，I negative differential signal CLK CORE_IN，IN Input from the inverting input terminal, I-channel sine clock CLK CML，I The positive differential signal CLK CML，IP Output from the positive output terminal, I-channel sine clock CLK CML，I negative differential signal CLK CML，IN Output from the reverse output terminal.

[0035] Specifically, the four transmission gates in each pre-filter circuit are selected according to the quadrant selection code SEL. 0～1 This achieves the corresponding clock flip: in the first quadrant, I-path is positive and Q-path is positive; in the second quadrant, I-path is positive and Q-path is negative; in the third quadrant, I-path is negative and Q-path is negative; and in the fourth quadrant, I-path is negative and Q-path is positive. Then, through the AC coupling module, the two full-swing square wave signals CLK are adjusted. CORE_IN The common-mode level ensures the normal operation of the CML buffer. The CML buffer converts the two full-swing square wave signals CLK... CORE_IN The signal is converted into a CML signal that can be processed by the interpolation core. High-pass filtering is achieved through an AC coupling module, and low-pass filtering is achieved jointly by the CML buffer and low-pass filter, thus giving the entire pre-filter circuit band-pass characteristics. This allows the input square wave clock (two full-swing square wave signals CLK) to be processed. CORE_IN Converted to a sine clock more suited to nonlinear interpolation (two-way sine clock CLK) CML ).

[0036] Please see Figure 6 , Figure 6 This is a schematic diagram of the phase interpolation core circuit provided in an embodiment of the present invention. The phase interpolation core circuit includes: an I-channel phase interpolation circuit and a Q-channel phase interpolation circuit. The control code input terminal of the I-channel phase interpolation circuit receives the I-channel weight code WEIGHT. I The differential clock input of the I-channel phase interpolation circuit receives an I-channel sinusoidal clock CLK.CML，I The current source bias input terminal of the I-channel phase interpolation circuit receives the second bias level VB_CORE. The control code input terminal of the Q-channel phase interpolation circuit receives the Q-channel weight code WEIGHT. Q The differential clock input of the Q-channel phase interpolation circuit receives the Q-channel sinusoidal clock CLK. CML，Q The current source bias input of the Q-channel phase interpolation circuit receives the second bias level VB_CORE. The outputs of the I-channel and Q-channel phase interpolation circuits are connected to jointly output a small-swing signal CLK. CORE_OUT .

[0037] In this embodiment, the I-channel phase interpolation circuit and the Q-channel phase interpolation circuit have the same structure, both including: 2 K-2 One phase interpolation unit and one load resistor R L，CORE Each phase interpolation unit has a pair of differential clock inputs, a weight control code input, a current source bias input, and a pair of differential outputs. In the I-channel phase interpolation circuit, 2... K-2 The positive differential output of each phase interpolation unit and the 2 in the Q-path phase interpolation circuit K-2 The positive differential outputs of each phase interpolation unit are connected to output a positive differential small-amplitude signal CLK. CORE_OUT，P And connect the load resistor R in the Q-channel phase interpolation circuit. L，CORE One end. In the I-path phase interpolation circuit, 2 K-2 The negative differential output of each phase interpolation unit and the 2 in the Q-path phase interpolation circuit K-2 The negative differential output terminals of each phase interpolation unit are connected to jointly output a negative differential small-swing signal CLK. CORE_OUT，N And connect the load resistor R in the I-channel phase interpolation circuit. L，CORE One end. The load resistor R in the Q-path phase interpolation circuit. L，CORE The other end and the load resistor R in the I-path phase interpolation circuit L，CORE The other end of each circuit is connected to the power supply potential VDD. There are a total of 2 I-channel phase interpolation circuits and Q-channel phase interpolation circuits. K-1 One phase interpolation unit, two weight control codes WEIGHT 0～2K-3 The weight control code is input in binary form to the corresponding phase interpolation unit's weight control code input terminal.

[0038] Specifically, traditional phase interpolators achieve good interpolation results with linear interpolation when the input clock is a triangular wave, while for nonlinear interpolation, a sine wave input provides higher interpolation accuracy. Furthermore, for a traditional linear phase interpolator with four-phase input, its two sets of clock interpolation weights (ω...) I and ω Q ) has ω I +ω Q=N is a constant value, in two clock paths (CLK) I and CLK Q When it is a triangular wave:

[0039]

[0040] Where θ is the angle between the interpolation point and the y-axis, and the analysis interval is 0 to 2π, it can be simplified to:

[0041]

[0042] From formulas (2) and (3), it can be seen that CLK I and CLK Q The interpolation result is still a piecewise function, and its waveform and amplitude differ under different weight control codes. The zero-crossing point of the piecewise function can be expressed as:

[0043]

[0044] Under the condition of linear interpolation, ω I +ω Q =N is a constant value. The zero-crossing point can be used to approximate the phase of the output waveform at this time. At this time, the phase of the sampling point of the triangular wave interpolation output clock changes linearly with the clock weight. The interpolation accuracy is high and the linearity is good, but there is still AM-to-PM (amplitude to phase) modulation. The interpolation output phase deviates, and the interpolation accuracy has defects.

[0045] For a four-phase input nonlinear phase interpolator, by decoupling the two clock weight control codes, an actual weight code that is as close as possible to the ideal output phase is selected in the phasor constellation diagram, such that the weight ω at the nth output point is... I [n] and ω Q [n] is relative to control code n, ranging from 0 to 2. N -1 approximates a sinusoidal change. At this point, different weights ω... I [n]、ω Q Summing two sets of sinusoidal clocks of [n] can produce a clock with a fine phase step:

[0046]

[0047] Where θ0 is the inherent phase of the input clock, A PI [n] represents the swing of the output clock. θ PI [n] represents the phase of the output clock. That is, A PI [n] is a constant, θ PI[n] varies linearly with the control code n. Therefore, the sinusoidal input can obtain a constant output amplitude and linear phase shift in the nonlinear phase interpolation core circuit, thus achieving higher interpolation accuracy.

[0048] In this embodiment, a pre-filter circuit is used to filter the two full-swing square wave signals CLK in square wave form. CORE_IN Two sinusoidal clocks CLK converted to sinusoidal form CML And by controlling the two sinusoidal clocks CLK CML Separate interpolation units are constructed to decouple the weight codes of the two clock interpolations into an I-way weight code WEIGHT that controls the interpolation weights of the I-way phase interpolation circuit. I The Q-channel weight code WEIGHT controls the interpolation weights of the Q-channel phase interpolation circuit. Q Interpolation is achieved through nonlinear interpolation, significantly increasing the design space and improving interpolation accuracy. Furthermore, by adjusting the combinational logic in the control code decoder, pre-calibration of the interpolation weights can be achieved, thereby optimizing the interpolation accuracy under different PVT conditions.

[0049] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of a phase interpolation unit provided in an embodiment of the present invention. In this embodiment, each phase interpolation unit includes: a transistor M. N1 Transistor M N2 Transistor M N3 Transistor M N4 Transistor M N5 Single-pole double-throw switch S1 and single-pole double-throw switch S2. Among them, transistor M... N1 The source of the transistor M N2 The source of the transistor M N3 The source of the transistor M N4 The source and transistor M N5 The drains of transistor M are connected. N5 The gate of transistor M is connected to the second bias level VB_CORE. N5 The source of transistor M is connected to ground potential GND. N1 Gate and transistor M N2 The gate is connected to the positive differential clock input IN. P transistor M N3 Gate and transistor M N4 The gate is connected to the negative differential clock input IN. N transistor M N1 The drain is connected to the negative differential output terminal OUT. N transistor M N2 The drain of transistor M is connected to the input terminal of single-pole double-throw switch S1. N4 The drain is connected to the positive differential output terminal OUT.P transistor M N3 The drain of the single-pole double-throw switch S2 is connected to its input terminal. The first output terminal of the single-pole double-throw switch S1 is connected to the negative differential output terminal OUT. N The second output terminal of the single-pole double-throw switch S1 is connected to the positive differential output terminal OUT. P The first output terminal of the single-pole double-throw switch S2 is connected to the positive differential output terminal OUT. P The second output terminal of the single-pole double-throw switch S2 is connected to the negative differential output terminal OUT. N The control terminals of single-pole double-throw switches S1 and S2 are connected to the weight control code input terminal.

[0050] Furthermore, please see Figure 8 , Figure 8 Figure (a) is a comparative diagram of the input swing amplitude of traditional linear interpolation and nonlinear interpolation provided in the embodiment of the present invention as the input PI Code (K-Bit binary control code) fluctuates. It can be seen from the figure that the input load of traditional linear interpolation is not constant, which leads to a large variation in the input swing amplitude of the phase interpolator and affects the interpolation accuracy. In contrast, the input swing amplitude of nonlinear interpolation provided in the embodiment of the present invention fluctuates significantly with the input PI Code, and the circuit improvement effect is significant. Figure 8 Figure (b) is a schematic diagram comparing the ideal single-quadrant integral nonlinearity of traditional linear interpolation and nonlinear interpolation provided by the embodiment of the present invention. It can be seen from the figure that the traditional linear interpolation method has low interpolation accuracy and integral nonlinearity of 2.890 LSB; while the nonlinear interpolation method provided by the embodiment of the present invention has significantly improved interpolation accuracy and integral nonlinearity of only 0.712 LSB.

[0051] Traditional interpolation units turn off the input transistors during shutdown, resulting in different numbers of transistors for clock load under different interpolation weights. This means the input load of the interpolation core is not constant, reducing interpolation accuracy. This embodiment controls the current source transistor (transistor M) through a second bias level VB_CORE. N5 The gate voltage of the phase interpolation core circuit is adjusted to ensure that the current in the circuit remains constant at different process corners, thus maintaining a stable operating state. This is achieved by adjusting the input clock (two sinusoidal clocks CLK). CML Connected to two constantly operating transistors (M) N1 M N2 Or M N3 M N4 The interpolation unit is turned on and off by changing the type of signal combination at the output terminal, without changing the operating state of the input transistors. Specifically, when the two outputs (M) of a clock channel... N1 M N2 Drain or M N3 M N4When the drains of the two outputs are connected to the same differential output terminal, differential signal transmission occurs and the phase interpolation unit is turned on; when the two outputs are connected to two different differential output terminals, only common-mode level is transmitted and there is no differential signal, so the phase interpolation unit is turned off. In this embodiment, the input load of the phase interpolation core circuit remains constant, which can effectively improve the interpolation accuracy.

[0052] This embodiment provides a digital predistortion high-precision phase interpolator with constant input load, which uses two weighted control codes WEIGHT to achieve a constant input load. 0～2K-3 For two sinusoidal clocks CLK CML This nonlinear interpolation significantly improves interpolation accuracy, making it suitable for clock generation modules such as clock data recovery circuits and phase-locked loop circuits. Furthermore, the phase interpolator can achieve pre-calibration of interpolation weights by adjusting the control code decoder, further improving the accuracy of the phase interpolator and enabling high-speed, high-precision output clocks. It is suitable for clock generation modules such as clock data recovery circuits and phase-locked loops in high-speed SerDes systems.

[0053] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A digital pre-distorted high precision phase interpolator with constant input load, characterized by, The application relates to a multi-phase clock generation circuit, an input buffer circuit, two pre-filter circuits, a phase interpolation core circuit, a CML2CMOS circuit and a control code decoder circuit. The multi-phase clock generation circuit is used for frequency dividing an input differential clock signal and outputting four-phase quadrature clocks with 1 / 2 frequency. The input buffer circuit is used for waveform and duty cycle adjustment of the four-phase quadrature clocks and outputs two full-swing square wave signals. The control code decoder circuit is used for decoding a K-Bit binary control code and outputting a quadrant selection code and two weight control codes. The two pre-filter circuits are used for sequentially carrying out interpolation quadrant selection, common-mode level adjustment, signal shaping and filtering on the two full-swing square wave signals according to the quadrant selection code and a first bias level, and converting the two full-swing square wave signals into two sinusoidal clocks. The phase interpolation core circuit is used for realizing constant input load by switching of a single-pole double-throw switch S1 and a single-pole double-throw switch S2 controlled by the weight control code, and carrying out nonlinear interpolation on the two sinusoidal clocks according to the two weight control codes and outputting a small-swing signal. The phase interpolation core circuit includes a plurality of phase interpolation units, each of which includes: a transistor M N1 , a transistor M N2 , a transistor M N3 , a transistor M N4 , a transistor M N5 , a single-pole double-throw switch S1 and a single-pole double-throw switch S2; The source of the transistor M N1 The source of the transistor M N2 The source of the transistor M N3 The source of the transistor M N4 The drain of the transistor M N5 The gate of the transistor M N5 The source of the transistor M N5 The gate of the transistor M N1 The gate of the transistor M N2 The positive differential clock input terminal IN P The gate of the transistor M N3 The gate of the transistor M N4 The negative differential clock input terminal IN N The drain of the transistor M N1 The negative differential output terminal OUT N The drain of the transistor M N2 The input terminal of the single-pole double-throw switch S1 N4 The positive differential output terminal OUT P The drain of the transistor M N3 The input terminal of the single-pole double-throw switch S2 The first output terminal of the single-pole double-throw switch S1 is connected to the negative differential output terminal OUT N The second output terminal of the single-pole double-throw switch S1 is connected to the positive differential output terminal OUT P The first output terminal of the single-pole double-throw switch S2 is connected to the positive differential output terminal OUT P The second output terminal of the single-pole double-throw switch S2 is connected to the negative differential output terminal OUT N The control terminals of the single-pole double-throw switch S1 and the single-pole double-throw switch S2 are connected to the weight control code input terminal The CML2CMOS circuit is used for expanding the small-swing signal into a full-swing signal and outputting the same. The control code decoder circuit is used for decoding a K-Bit binary control code and outputting a quadrant selection code and two weight control codes.

2. A digital predistortion high precision phase interpolator with constant input load as claimed in claim 1, wherein, The two-path weight control code includes: I-path weight code WEIGHT I and Q-path weight code WEIGHT Q ; The duty cycle of the two full swing square wave signals is 50%, and the two full swing square wave signals include: an I full swing square wave signal CLK CORE_IN，I and a Q full swing square wave signal CLK CORE_IN，Q ; The two-path sinusoidal clock includes: an I-path sinusoidal clock CLK CML，I and a Q-path sinusoidal clock CLK CML，Q ; The I-path weight code WEIGHT I and the Q-path weight code WEIGHT Q are respectively used to control the interpolation weight of the phase interpolation core circuit to the I-path sinusoidal clock CLK CML，I and the Q-path sinusoidal clock CLK CML，Q .

3. A digital predistortion high precision phase interpolator with constant input load according to claim 2, characterized in that, The phase interpolation core circuit comprises an I-phase interpolation circuit and a Q-phase interpolation circuit. The control code decoder circuit obtains ideal output point coordinates of a phase interpolator according to the K-Bit binary control code, selects an available phase point with the minimum distance modulus value to the ideal output point as an approximate output point, selects a quadrant output quadrant code according to the quadrant of the approximate output point, and outputs I and Q channel weight codes WEIGHT I and WEIGHT Q respectively according to the horizontal and vertical coordinates of the approximate output point.

4. A digital predistortion high precision phase interpolator with constant input load as claimed in claim 2, wherein, The output end of the I-phase interpolation circuit and the output end of the Q-phase interpolation circuit are connected and jointly output the small-swing signal. The I-phase interpolation circuit has a control code input end inputting the I-phase weight code WEIGHT I , a differential clock input end inputting the I-phase sinusoidal clock CLK CML，I , and a current source bias input end inputting a second bias level. The Q-phase phase interpolation circuit has a control code input end inputting the Q-phase weight code WEIGHT Q , a differential clock input end inputting the Q-phase sinusoidal clock CLK CML，Q , and a current source bias input end inputting a second bias level. Each phase interpolation unit has a pair of differential clock input ends, a weight control code input end, a current source tube bias input end and a pair of differential output ends.

5. A digital predistortion high precision phase interpolator with constant input load according to claim 4, characterized in that, The I-phase interpolation circuit and the Q-phase interpolation circuit have the same structure, and each includes: 2 K-2 a phase interpolation unit and a load resistor R L，CORE ​ The multi-phase clock generation circuit comprises a first-stage Latch and a second-stage Latch. The positive differential output end of two phase interpolation units in the I channel phase interpolation circuit is connected with the positive differential output end of two phase interpolation units in the Q channel phase interpolation circuit, and the positive differential small swing signal CLK is output together. K-2 The positive differential output end of two phase interpolation units in the I channel phase interpolation circuit is connected with the positive differential output end of two phase interpolation units in the Q channel phase interpolation circuit, and the positive differential small swing signal CLK is output together. K-2 The positive differential output end of two phase interpolation units in the I channel phase interpolation circuit is connected with the positive differential output end of two phase interpolation units in the Q channel phase interpolation circuit, and the positive differential small swing signal CLK is output together. CORE_OUT，P The positive differential output end of two phase interpolation units in the I channel phase interpolation circuit is connected with the positive differential output end of two phase interpolation units in the Q channel phase interpolation circuit, and the positive differential small swing signal CLK is output together. L，CORE ​ In the I-channel phase interpolation circuit, 2 K-2 The negative differential output of each phase interpolation unit and the 2 in the Q-path phase interpolation circuit K-2 The negative differential output terminals of each phase interpolation unit are connected to jointly output a negative differential small-swing signal CLK. CORE_OUT，N And connect the load resistor R in the I-channel phase interpolation circuit. L，CORE One end; The load resistor R in the Q-path phase interpolation circuit L，CORE The other end and the load resistor R in the I-channel phase interpolation circuit L，CORE The other end of each is connected to the power supply potential VDD.

6. A digital predistortion high precision phase interpolator with constant input load as claimed in claim 1 characterized in that, The differential clock signal includes: a positive differential clock signal CLK IN，P and a negative differential clock signal CLK IN，N ; The four-phase quadrature clock includes: I route forward clock CLK DIV，IP , I route reverse clock CLK DIV，IN , Q route forward clock CLK DIV，QP , Q route reverse clock CLK DIV，QN ; Each pre-filter circuit comprises a quadrant selection sub-circuit and a filtering sub-circuit. The driving end of the first stage Latch inputs positive differential clock signal CLK IN，P The reverse output end of the first stage Latch connects the positive input end of the second stage Latch and outputs I path positive clock CLK DIV，IP The positive output end of the first stage Latch connects the reverse input end of the second stage Latch and outputs I path reverse clock CLK DIV，IN ; The driving end of the second stage Latch inputs a negative differential clock signal CLK IN，N The forward output end of the second stage Latch connects the forward input end of the first stage Latch and outputs a Q path reverse clock CLK DIV，QN The reverse output end of the second stage Latch connects the reverse input end of the first stage Latch and outputs a Q path forward clock CLK DIV，QP .

7. A digital pre-distorted high precision phase interpolator with constant input load as claimed in claim 2, wherein, The two pre-filter circuits are identical in structure, one of the two pre-filter circuits is used to convert the I full swing square wave signal CLK CORE_IN，I into an I sinusoidal clock CLK CML，I , and the other is used to convert the Q full swing square wave signal CLK CORE_IN，Q into a Q sinusoidal clock CLK CML，Q . The quadrant selection sub-circuit is used for selectively inverting the two full-swing square wave signals according to the quadrant selection code. The filtering sub-circuit is connected with the output end of the quadrant selection sub-circuit, adjusts the common-mode level of the selectively inverted two full-swing square wave signals according to the first bias level, and sequentially carries out signal shaping and filtering to output the two sinusoidal clocks. The quadrant selection sub-circuit comprises a transmission gate TRAN1, a transmission gate TRAN2, a transmission gate TRAN3 and a transmission gate TRAN4.

8. A digital predistortion high precision phase interpolator with constant input load according to claim 7, characterized in that, ​ The transmission gate TRAN1, the transmission gate TRAN2, the transmission gate TRAN3, and the transmission gate TRAN4 are controlled by the quadrant selection code, the input end of the transmission gate TRAN1 and the input end of the transmission gate TRAN2 serve as the reverse input end, the input end of the transmission gate TRAN3 and the input end of the transmission gate TRAN4 serve as the forward input end, the output end of the transmission gate TRAN1 and the output end of the transmission gate TRAN3 serve as the first output end, and the output end of the transmission gate TRAN2 and the output end of the transmission gate TRAN4 serve as the second output end.

9. A digital pre-distorted high precision phase interpolator with constant input load according to claim 8, characterized in that, The filter sub-circuit comprises an AC coupling module, a CML buffer and a low-pass filter connected in sequence, wherein the AC coupling module comprises a capacitor C1, a capacitor C2, a resistor R1 and a resistor R2, the CML buffer comprises a transistor M N6 , a transistor M N7 , a transistor M N8 , a resistor R3, a resistor R4 and the low-pass filter comprises a capacitor C3, a capacitor C4, a resistor R5 and a resistor R6. The first terminal of the capacitor C1 is connected to the output terminal of the transmission gate TRAN1 and the output terminal of the transmission gate TRAN3, the first terminal of the capacitor C2 is connected to the output terminal of the transmission gate TRAN2 and the output terminal of the transmission gate TRAN4, the second terminal of the capacitor C1 is connected to the first terminal of the resistor R1 and the gate of the transistor M N6 The second terminal of the capacitor C2 is connected to the first terminal of the resistor R2 and the gate of the transistor M N7 The second terminals of the resistors R1 and R2 are connected to the third bias level VCM, the source of the transistor M N6 and M N7 The drain of the transistor M N8 is connected to the source of the transistor M N8 The gate of the transistor M N8 is connected to the ground potential GND, the drain of the transistor M N6 The first terminal of the resistor R3 and the first terminal of the resistor R5 are connected to the drain of the transistor M N7 The first terminal of the load resistor R4 and the first terminal of the filter resistor R6 are connected to the drain of the transistor M The second terminals of the load resistors R3 and R4 are connected to the power supply potential VDD, the second terminal of the filter resistor R5 and the first terminal of the filter capacitor C3 are connected to the rear as the reverse output terminal, the second terminal of the filter resistor R6 and the first terminal of the filter capacitor C5 are connected to the rear as the forward output terminal, and the second terminals of the capacitors C3 and C4 are connected to the ground potential GND.

Images