High-linearity multi-bit continuous time sigma-delta analog-to-digital converter

Abstract

The invention discloses a high-linearity multi-bit continuous time sigma-delta analog-to-digital converter, which adopts a resistance type digital-to-analog converter and realizes feedback of multi-bit digital output by utilizing a plurality of switches in a time domain segmentation mode. As the accuracy of the feedback analog value is determined by the duty ratio of the clock, the good linearity of the digital-to-analog converter is ensured. Therefore, the problem of mismatch among unit resistors can be solved while multi-bit feedback is realized, the precision and energy efficiency of the continuous time sigma-delta analog-to-digital converter can be effectively improved, the use of linearity improving technologies such as data weighted average and the like is avoided, and the complexity of circuit design is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog-to-digital conversion, and particularly relates to a multi-bit continuous-time Σ-Δ analog-to-digital converter with high linearity. Background Art

[0002] The signals generated in nature and recognizable by humans are analog signals. However, most high-performance signal processing today is completed by computers in the digital domain. Therefore, analog-to-digital converters that convert analog signals with both amplitude and time continuous into digital signals with both amplitude and time discrete have been widely used. As an important part of the signal chain, the accuracy, speed, and power consumption of analog-to-digital converters become the determining factors for the accuracy, speed, and power consumption of signal processing. With the rapid development of fields such as mobile communication, automotive electronics, biomedicine, and the Internet of Things, the requirements for accurate and high-quality data information are also increasing. Therefore, the demand for analog-to-digital converters has also increased significantly.

[0003] Modern automobiles rely on a variety of sensors to monitor and control various functions of the vehicle to ensure safety and efficiency, including sensors such as temperature, pressure, humidity, and light. Due to its noise shaping and built-in anti-aliasing characteristics, the continuous-time Σ-Δ analog-to-digital converter is one of the optimal choices for implementing automotive sensors. However, most of the current continuous-time Σ-Δ analog-to-digital converters used for such sensors use single-bit quantizers such as the literature [M. Jang, C. Lee, and Y. Chae. Analysis and design of a low-power continuous-time Delta-Sigma modulator using a negative-resistance-assisted integrator, IEEE Journal of Solid-State Circuits, January 2019, Vol. 54, No. 1, pp. 277-287], or 1.5-bit quantizers such as the literature [M. Jang, C. Lee, and Y. Chae. A 134-μW 99.4-dB signal-to-noise-and-distortion-ratio audio continuous-time Delta-Sigma modulator using chopped negative resistance and three-level finite impulse response digital-to-analog converter, IEEE Journal of Solid-State Circuits, June 2021, Vol. 56, No. 6, pp. 1761-1771]. Although they have good linearity, they have problems of low accuracy and high loop filter power consumption. Using a multi-bit quantizer can increase the number of stages of the feedback digital-to-analog converter, reduce the difference between the input signal and the output of the feedback digital-to-analog converter, and can effectively improve the accuracy and reduce the power consumption of the loop filter, but the mismatch problem of the feedback digital-to-analog converter needs to be solved. Summary of the Invention

[0004] In view of the above, the present invention provides a multi-bit continuous-time Σ-Δ analog-to-digital converter with high linearity. The resistor-type feedback digital-to-analog converter structure used therein solves the mismatch problem between unit resistors while realizing multi-bit feedback, and can effectively improve the accuracy and energy efficiency of the continuous-time Σ-Δ analog-to-digital converter.

[0005] A high-linearity multi-bit continuous-time Σ-Δ analog-to-digital converter, comprising a first-stage integration unit, a second-stage integration unit, a loop delay compensation unit, a sub-analog-to-digital conversion unit, and a switch control logic unit connected in series in sequence, wherein: the two-stage integration unit is used for integrating after subtracting the differential input signal from the output of the internal digital-to-analog converter DAC1; the loop delay compensation unit is used for summing the output of the first-stage integration unit, the output of the second-stage integration unit, and the output of the internal digital-to-analog converter DAC2; the sub-analog-to-digital conversion unit is used for quantifying the output after summation by the loop delay compensation unit to generate a digital code as the final output result; the switch control logic unit is used for encoding the digital code generated by the sub-analog-to-digital conversion unit to generate a feedback switch signal for controlling DAC1 and DAC2.

[0006] Further, the switch control logic unit is connected to the first-stage integration unit and the loop delay compensation unit to form a feedback loop, so as to provide a feedback switch signal for the first-stage integration unit and the loop delay compensation unit.

[0007] Further, the first-stage integration unit includes two resistors R 1 and R 2 , two capacitors C 1 and C 2 , a digital-to-analog converter DAC1, and an operational amplifier OTA1, wherein one end of R 1 is the non-inverting input end of the first-stage integration unit, the other end of R 1 is connected to the non-inverting input end of OTA1, the non-inverting output end of DAC1, and one end of C 1 , the other end of C 1 is connected to the inverting output end of OTA1 and serves as the inverting output end of the first-stage integration unit, one end of R 2 is the inverting input end of the first-stage integration unit, the other end of R 2 is connected to the inverting input end of OTA1, the inverting output end of DAC1, and one end of C 2 , and the other end of C 2 is connected to the non-inverting output end of OTA1 and serves as the non-inverting output end of the first-stage integration unit.

[0008] Further, the digital-to-analog converter DAC1 includes five switches S 1 ~S 5 and two resistors R 9 and R 10 , wherein one end of S 1 is connected to one end of S 2 and connected to the power supply voltage, the other end of S 1 is connected to one end of S 3 and S4 One end of and R 9 One end of is connected to S 5 One end of is connected to S 4 The other end of is connected to S and grounded 5 The other end of is connected to S 2 The other end of, S 3 The other end of and R 10 One end of is connected to R 9 The other end of is used as the non-inverting output terminal of DAC1, R 10 The other end of is used as the inverting output terminal of DAC1.

[0009] Furthermore, when the switch S 1 , S 3 , S 5 is disconnected, S 2 and S 4 is closed, the output value of DAC1 is -1; when the switch S 1 , S 2 , S 4 , S 5 is disconnected, S 3 is closed, the output value of DAC1 is 0; when the switch S 2 , S 3 , S 4 is disconnected, S 1 and S 5 is closed, the output value of DAC1 is 1.

[0010] Furthermore, the second-stage integration unit includes two resistors R 3 and R 4 , two capacitors C 3 and C 4 , and an operational amplifier OTA2, where one end of R 3 is the non-inverting input terminal of the second-stage integration unit, the other end of R 3 is connected to the non-inverting input terminal of OTA2 and one end of C 3 , one end of C 3 is connected to the inverting output terminal of OTA2 and serves as the inverting output terminal of the second-stage integration unit, one end of R 4 is the inverting input terminal of the second-stage integration unit, the other end of R 4 is connected to the inverting input terminal of OTA2 and one end of C 4 , one end of C 4 is connected to the non-inverting output terminal of OTA2 and serves as the non-inverting output terminal of the second-stage integration unit.

[0011] Furthermore, the loop delay compensation unit includes four resistors R 5 ~R 8and a digital-to-analog converter DAC2, where R 5 One end of is connected to the positive-phase output terminal of the first-stage integration unit, and R 5 The other end of is connected to one end of R 6 and the positive-phase output terminal of DAC2 and serves as the positive-phase output terminal of the loop delay compensation unit. The other end of R 6 is connected to the positive-phase output terminal of the second-stage integration unit, and one end of R 8 is connected to the inverting output terminal of the first-stage integration unit. The other end of R 8 is connected to one end of R 7 and the inverting output terminal of DAC2 and serves as the inverting output terminal of the loop delay compensation unit. The other end of R 7 is connected to the inverting output terminal of the second-stage integration unit.

[0012] Further, the sub-analog-to-digital conversion unit uses a multi-stage flash analog-to-digital converter, and the digital code output by it is a multi-bit binary codeword.

[0013] Further, the switch control logic unit includes a delay module and an encoding module; the delay module delays the feedback clock to generate two complementary-phase switch clocks Clk 1 and Clk 2 , which are used to control the switches in DAC1 and DAC2 to close at high levels. The feedback clock is complementary in phase to the quantization clock of the sub-analog-to-digital conversion unit. The duty cycles of these four clocks are all 50%. The rising edge of Clk 1 is delayed by 1 / 4 of a quantization clock cycle compared to the rising edge of the feedback clock.

[0014] Further, when the number of stages of the sub-analog-to-digital conversion unit is 5, it outputs a 4-bit binary codeword, corresponding to 5 values, namely -2, -1, 0, 1, 2. The encoding module encodes according to the switch clocks Clk 1 and Clk 2 to generate 5 groups of feedback switch signals to control the switches in DAC1 respectively. Specifically: When the value output by the sub-analog-to-digital conversion unit is -2, S 2 , S 3 and S 4 are disconnected, and S 1 and S 5 are closed; When the value output by the sub-analog-to-digital conversion unit is -1, S 2 and S 4 are disconnected, and S 1 and S 5 are only closed at the high level of Clk 1 , and S 3 is only closed at the high level of Clk 2Closed at high level; When the value output by the sub - analog - to - digital conversion unit is 0, S 1 、S 2 、S 4 and S 5 are disconnected, and S 3 is closed; When the value output by the sub - analog - to - digital conversion unit is 1, S 1 and S 5 are disconnected, S 2 and S 4 are closed only when Clk 1 is at high level, and S 3 is closed only when Clk 2 is at high level; When the value output by the sub - analog - to - digital conversion unit is 2, S 1 、S 3 and S 5 are disconnected, and S 2 and S 4 are closed.

[0015] Compared with the prior art, the present invention adopts a resistive multi - bit digital - to - analog converter structure. By reducing the number of unit resistors in the digital - to - analog converter, the linearity problem caused by the mismatch between unit resistors is avoided. Compared with a single - bit digital - to - analog converter, the present invention realizes a loop filter with higher precision and higher energy efficiency; compared with a traditional multi - bit digital - to - analog converter, the present invention avoids the use of the data - weighted averaging technique and reduces the circuit complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a structural block diagram of the multi - bit continuous - time Σ - Δ analog - to - digital converter of the present invention.

[0017] Figure 2 is a schematic diagram of the overall circuit structure of the digital - to - analog converter in the present invention.

[0018] Figure 3 is a schematic diagram of the circuit connection of the digital - to - analog converter in the present invention under different switch states, where (a) corresponds to the switch state when the analog output value is - 1, (b) corresponds to the switch state when the analog output value is 0, and (c) corresponds to the switch state when the analog output value is 1.

[0019] Figure 4 is a schematic diagram of the clock signal used in the present invention.

[0020] Figure 5 is a logic truth table of the switch control logic unit in the present invention.

[0021] Figure 6 is a schematic diagram of the analog output waveform of the digital - to - analog converter in the present invention.

[0022] Figure 7 This is the spectrum diagram of the output digital code of the multi-bit continuous-time Σ-Δ analog-to-digital converter of the present invention. Detailed implementation manners

[0023] In order to describe the present invention more specifically, the technical solutions of the present invention will be described in detail below with reference to the accompanying drawings and specific implementation manners.

[0024] In the application scenario of vehicle sensors, high-precision analog-to-digital converters are often required. To meet the above requirements, this implementation manner provides a multi-bit continuous-time Σ-Δ analog-to-digital converter, which is combined with a resistive digital-to-analog converter structure to achieve high precision while avoiding the low linearity problem caused by unit resistor mismatch.

[0025] As Figure 1 shown, the second-order continuous-time Σ-Δ analog-to-digital converter of this implementation manner includes a first-stage integration unit, a second-stage integration unit, a loop delay compensation unit, a sub-analog-to-digital conversion unit, and a switch control logic unit connected in series in sequence. The switch control logic unit is respectively connected to the first-stage integration unit and the loop delay compensation unit to form a feedback loop for providing multi-bit feedback to the first-stage integration unit and the loop delay compensation unit.

[0026] In this implementation manner, the first-stage integration unit includes a first resistor R 1 , a second resistor R 2 , a first capacitor C 1 , a second capacitor C 2 , a first digital-to-analog converter DAC1, and a first operational amplifier OTA1; wherein, the positive input terminal of the first operational amplifier OTA1 is connected to the positive terminal V 1 of the input voltage after being connected in series with the first resistor R inp , and the positive input terminal of the first operational amplifier OTA1 is also connected to the inverting output terminal of the first operational amplifier OTA1 after being connected in series with the first capacitor C 1 ; the negative input terminal of the first operational amplifier OTA1 is connected to the negative terminal V 2 of the input voltage after being connected in series with the second resistor R inn , and the negative input terminal of the first operational amplifier OTA1 is also connected to the positive output terminal of the first operational amplifier OTA1 after being connected in series with the second capacitor C 2 ; the input terminal of the first digital-to-analog converter DAC1 is connected to the output terminal of the switch control logic unit L, the positive output terminal of the first digital-to-analog converter DAC1 is connected to the positive input terminal of the first operational amplifier OTA1, and the negative output terminal of the first digital-to-analog converter DAC1 is connected to the negative input terminal of the first operational amplifier OTA1.

[0027] In this implementation manner, the second-stage integration unit includes a third resistor R3 , the fourth resistor R 4 , the third capacitor C 3 , the fourth capacitor C 4 and the second operational amplifier OTA2; wherein, the non-inverting input terminal of the second operational amplifier OTA2 is connected to the non-inverting output terminal of the first operational amplifier OTA1 after being connected in series with the third resistor R 3 , and the non-inverting input terminal of the second operational amplifier OTA2 is also connected to the inverting output terminal of the second operational amplifier OTA2 after being connected in series with the third capacitor C 3 ; the inverting input terminal of the second operational amplifier OTA2 is connected to the inverting output terminal of the first operational amplifier OTA1 after being connected in series with the fourth resistor R 4 , and the inverting input terminal of the second operational amplifier OTA2 is also connected to the non-inverting output terminal of the second operational amplifier OTA2 after being connected in series with the fourth capacitor C 4 .

[0028] In this embodiment, the loop delay compensation unit includes the fifth resistor R 5 , the sixth resistor R 6 , the seventh resistor R 7 , the eighth resistor R 8 and the second digital-to-analog converter DAC2; one end of the fifth resistor R 5 is connected to the non-inverting output terminal of the first operational amplifier OTA1, and the other end of the fifth resistor R 5 is connected to the non-inverting input terminal of the sub-analog-to-digital conversion unit; one end of the sixth resistor R 6 is connected to the non-inverting output terminal of the second operational amplifier OTA2, and the other end of the sixth resistor R 6 is connected to the non-inverting input terminal of the sub-analog-to-digital conversion unit; one end of the seventh resistor R 7 is connected to the inverting output terminal of the second operational amplifier OTA2, and the other end of the seventh resistor R 7 is connected to the inverting input terminal of the sub-analog-to-digital conversion unit; one end of the eighth resistor R 8 is connected to the inverting output terminal of the first operational amplifier OTA1, and the other end of the eighth resistor R 8 is connected to the inverting input terminal of the sub-analog-to-digital conversion unit; the non-inverting output terminal of the second digital-to-analog converter DAC2 is connected to the non-inverting input terminal of the sub-analog-to-digital conversion unit, and the inverting output terminal of the second digital-to-analog converter DAC2 is connected to the inverting input terminal of the sub-analog-to-digital conversion unit.

[0029] In this embodiment, the second digital-to-analog converter DAC2 is implemented by a common multi-bit digital-to-analog converter, which includes 4 unit resistors. The sub-analog-to-digital conversion unit uses a 5-stage flash analog-to-digital converter, and its output is a 4-bit binary codeword D outThe switch control logic unit L includes a delay module and an encoding module, which receives a 4-bit binary codeword output by the sub-analog-to-digital conversion unit and provides 5 sets of feedback switch signals for the first-stage integration unit and the loop delay compensation unit.

[0030] like Figure 2 As shown, in this embodiment, the first digital-to-analog converter DAC1 includes a first switch S 1 , the second switch S 2 , the third switch S 3 , the fourth switch S 4 , the fifth switch S 5 、The ninth resistor R 9 And the tenth resistor R 10 ; First switch S 1 One end of the second switch S 2 One end is connected to the power supply voltage V DD ; The fourth switch S 4 One end of the fifth switch S 5 One end is grounded V SS ; First switch S 1 The other end of the fourth switch S 4 The other end and the third switch S 3 One end is connected in series with the ninth resistor R 9 Connected to the positive phase output terminal I of the first digital-to-analog converter DAC1 OP ; Second switch S 2 The other end of the fifth switch S 5 The other end and the third switch S 3 The other end is connected in series with the tenth resistor R 10 Connected to the inverting output terminal I of the first digital-to-analog converter ON .

[0031] like Figure 3 As shown, when S 2 With S 4 When closed, the positive phase output terminal I of the first digital-to-analog converter DAC1 OP R 9 grounded, and its inverting output terminal I ON R 10 Connect to power supply voltage V DD , the realized analog output value is -1, corresponding to Figure 3 (a); when S 3 When closed, the positive phase output terminal I of the first digital-to-analog converter DAC1 OP R 9 With R 10 Connected to its inverting output terminal I ON , the realized analog output value is 0, corresponding to Figure 3 (b); when S 1With S 5 When closed, the non-inverting output terminal I of the first digital-to-analog converter DAC1 OP is connected to the power supply voltage V through the series-connected R 9 , while its inverting output terminal I DD is grounded through the series-connected R ON , and the realized analog output value is 1, corresponding to 10 (c). Figure 3

[0032] As Figure 4 shown, the sub-digital-to-analog conversion unit is controlled by the quantization clock Clk Q , and the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 are controlled by the feedback clock Clk DAC . For one cycle of the feedback clock, it is divided into two sub-clocks Clk 1 and Clk 2 with the same duty cycle but a half-cycle delay. For different 4-bit binary codewords, Clk 1 and Clk 2 control the closing of the switches in the digital-to-analog converter when they are at a high level.

[0033] As Figure 5 shown, when the output of the sub-digital-to-analog conversion unit is -2, S 1 and S 5 are closed throughout the Clk DAC cycle; when the output of the sub-digital-to-analog conversion unit is -1, S 1 and S 5 are only closed when Clk 1 is at a high level, while S 3 is closed when Clk 2 is at a high level; when the output of the sub-digital-to-analog conversion unit is 0, S 3 is closed throughout the Clk DAC cycle; when the output of the sub-digital-to-analog conversion unit is 1, S 2 and S 4 are closed when Clk 1 is at a high level, while S 3 is closed when Clk 2 is at a high level; when the output of the sub-digital-to-analog conversion unit is 2, S 2 and S 4 are closed throughout the Clk DAC cycle; thus, the 4-bit binary codeword input is converted into a 5-level analog output, realizing the function of a 5-level digital-to-analog converter.

[0034] It can be understood that since the resistive digital-to-analog converter of the present invention only has one unit resistor, there is no mismatch problem between the unit resistors. In addition, since Figure 4 ​The three states of -2, 0, and 2 last for a complete Clk DAC cycle, and the accurate analog output values of the two states of -1 and 1 are only determined by Clk 1 and Clk 2 's duty cycle. The analog output value of this digital-to-analog converter has excellent accuracy compared with traditional multi-bit digital-to-analog converters, which helps to realize a high-linearity continuous-time Σ-Δ analog-to-digital converter.

[0035] As Figure 6 shown, when the output D out of the sub-analog-to-digital conversion unit is -2, throughout the Clk DAC cycle, the output DAC out of the first digital-to-analog converter DAC1 is 1; when the output D out of the sub-analog-to-digital conversion unit is -1, when Clk 1 is high, the output DAC out of the first digital-to-analog converter DAC1 is 1, and when Clk 2 is high, the output DAC out of the first digital-to-analog converter DAC1 is 0; when the output D out of the sub-analog-to-digital conversion unit is 0, throughout the Clk DAC cycle, the output DAC out of the first digital-to-analog converter DAC1 is 0; when the output D out of the sub-analog-to-digital conversion unit is 1, when Clk 1 is high, the output DAC out of the first digital-to-analog converter DAC1 is -1, and when Clk 2 is high, the output DAC out of the first digital-to-analog converter DAC1 is 0; when the output D out of the sub-analog-to-digital conversion unit is 2, throughout the Clk DAC cycle, the output DAC out of the first digital-to-analog converter DAC1 is -1. The second digital-to-analog converter DAC2 is directly controlled by the output 4-bit binary codeword.

[0036] As Figure 7 shown, compared with the traditional continuous-time Σ-Δ analog-to-digital converter using a 1.5-bit quantizer, the continuous-time Σ-Δ analog-to-digital converter of the present invention achieves higher accuracy. It can be understood that since the basic structure of the digital-to-analog converter is the same as that of the 1.5-bit quantizer, the continuous-time Σ-Δ analog-to-digital converter of the present invention has no problem of unit resistor mismatch.

[0037] This embodiment is an improvement made to a 5-bit digital-to-analog converter; it can be understood that, similarly, in other embodiments of the present invention, the same structural improvements can also be made to digital-to-analog converters with higher bit numbers, which will not be elaborated here.

[0038] The above description of the embodiments is to facilitate the understanding and application of the present invention by ordinary technicians in the technical field. Those skilled in the art can obviously make various modifications to the above embodiments easily and apply the general principles described herein to other embodiments without creative labor. Therefore, the present invention is not limited to the above embodiments, and all improvements and modifications made by those skilled in the art based on the disclosure of the present invention should be within the protection scope of the present invention.

Claims

1. A high linearity multi-bit continuous-time Σ-Δ analog-to-digital converter, characterized in that: It includes a first-stage integration unit, a second-stage integration unit, a loop delay compensation unit, a sub-analog-to-digital conversion unit and a switch control logic unit which are connected in series in sequence, wherein: the two-stage integration unit is used to integrate the differential input signal and the output of the internal digital-to-analog converter DAC1 after making a difference; the loop delay compensation unit is used to sum the output of the first-stage integration unit, the output of the second-stage integration unit and the output of the internal digital-to-analog converter DAC2; the sub-analog-to-digital conversion unit is used to quantize the summed output of the loop delay compensation unit and generate a digital code as the final output result; the switch control logic unit is used to encode the digital code generated by the sub-analog-to-digital conversion unit and generate a feedback switch signal for controlling DAC1 and DAC2.

2. A high linearity multi-bit continuous-time Σ-Δ analog-to-digital converter according to claim 1, characterized in that: The switch control logic unit is connected with the first-stage integration unit and the loop delay compensation unit to form a feedback loop, thereby providing a feedback switch signal to the first-stage integration unit and the loop delay compensation unit.

3. The high linearity multi-bit continuous-time Σ-Δ analog-to-digital converter according to claim 1, characterized in that: The first-stage integration unit includes two resistors R1 and R2, two capacitors C1 and C2, a digital-to-analog converter DAC1 and an operational amplifier OTA1, wherein one end of R1 is the non-inverting input end of the first-stage integration unit, the other end of R1 is connected to the non-inverting input end of OTA1, the non-inverting output end of DAC1 and one end of C1, the other end of C1 is connected to the inverting output end of OTA1 and serves as the inverting output end of the first-stage integration unit, one end of R2 is the inverting input end of the first-stage integration unit, the other end of R2 is connected to the inverting input end of OTA1, the inverting output end of DAC1 and one end of C2, the other end of C2 is connected to the non-inverting output end of OTA1 and serves as the non-inverting output end of the first-stage integration unit.

4. The high linearity multi-bit continuous-time Σ-Δ analog-to-digital converter according to claim 3, characterized in that: The digital-to-analog converter DAC1 includes five switches S1-S5 and two resistors R9 and R 10 , where one end of S1 is connected to one end of S2 and connected to the power supply voltage, the other end of S1 is connected to one end of S3, one end of S4 and one end of R9, one end of S5 is connected to the other end of S4 and grounded, and the other end of S5 is connected to the other end of S2, the other end of S3 and R 10 One end of R9 is connected to the positive output end of DAC1. 10 The other end serves as the inverting output terminal of DAC1.

5. The high linearity multi-bit continuous-time Σ-Δ analog-to-digital converter according to claim 4, characterized in that: When switches S1, S3, and S5 are open and S2 and S4 are closed, the output value of DAC1 is -1; when switches S1, S2, S4, and S5 are open and S3 is closed, the output value of DAC1 is 0; when switches S2, S3, and S4 are open and S1 and S5 are closed, the output value of DAC1 is 1.

6. The high linearity multi-bit continuous-time Σ-Δ analog-to-digital converter according to claim 1, characterized in that: The second-stage integration unit includes two resistors R3 and R4, two capacitors C3 and C4, and an operational amplifier OTA2, wherein one end of R3 is the non-inverting input end of the second-stage integration unit, the other end of R3 is connected to the non-inverting input end of OTA2 and one end of C3, the other end of C3 is connected to the inverting output end of OTA2 and serves as the inverting output end of the second-stage integration unit, one end of R4 is the inverting input end of the second-stage integration unit, the other end of R4 is connected to the inverting input end of OTA2 and one end of C4, the other end of C4 is connected to the non-inverting output end of OTA2 and serves as the non-inverting output end of the second-stage integration unit.

7. The high linearity multi-bit continuous-time Σ-Δ analog-to-digital converter according to claim 1, characterized in that: The loop delay compensation unit includes four resistors R5~R8 and a digital-to-analog converter DAC2, wherein one end of R5 is connected to the positive phase output end of the first-stage integration unit, the other end of R5 is connected to one end of R6 and the positive phase output end of DAC2 and serves as the positive phase output end of the loop delay compensation unit, the other end of R6 is connected to the positive phase output end of the second-stage integration unit, one end of R8 is connected to the negative phase output end of the first-stage integration unit, the other end of R8 is connected to one end of R7 and the negative phase output end of DAC2 and serves as the negative phase output end of the loop delay compensation unit, and the other end of R7 is connected to the negative phase output end of the second-stage integration unit.

8. The high linearity multi-bit continuous-time Σ-Δ analog-to-digital converter according to claim 1, characterized in that: The sub-analog-to-digital conversion unit adopts a multi-level flash memory type analog-to-digital converter, and the digital code output by the sub-analog-to-digital conversion unit is a multi-bit unary code word.

9. The high linearity multi-bit continuous-time Σ-Δ analog-to-digital converter according to claim 4, characterized in that: The switch control logic unit includes a delay module and an encoding module; the delay module delays the feedback clock to generate two phase-complementary switch clocks Clk1 and Clk2, which are used to control the switch closure in DAC1 and DAC2 at a high level. The feedback clock is phase-complementary to the quantization clock of the sub-analog-to-digital conversion unit. The duty cycle of these four clocks is 50%, and the rising edge of Clk1 is delayed by 1 / 4 of the quantization clock cycle compared to the rising edge of the feedback clock.

10. The high linearity multi-bit continuous-time Σ-Δ analog-to-digital converter according to claim 9, characterized in that: When the number of stages of the sub-ADC is 5, it outputs a 4-bit binary codeword corresponding to 5 values, namely -2, -1, 0, 1, and 2. The encoding module encodes according to the switch clocks Clk1 and Clk2 to generate 5 sets of feedback switch signals to control the switches in DAC1 respectively. Specifically: When the value output by the sub-ADC is -2, S2, S3 and S4 are disconnected, and S1 and S5 are closed; When the value output by the sub-ADC is -1, S2 and S4 are disconnected, S1 and S5 are closed only when Clk1 is at a high level, and S3 is closed only when Clk2 is at a high level; When the value output by the sub-analog-to-digital conversion unit is 0, S1, S2, S4 and S5 are disconnected, and S3 is closed; When the value output by the sub-ADC is 1, S1 and S5 are disconnected, S2 and S4 are closed only when Clk1 is at a high level, and S3 is closed only when Clk2 is at a high level; When the value output by the sub-analog-to-digital conversion unit is 2, S1, S3 and S5 are disconnected, and S2 and S4 are closed.

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