A multi-bit continuous-time Σ-Δ analog-to-digital converter with high linearity

Abstract

The present invention discloses a multi-bit continuous-time Σ-Δ analog-to-digital converter with high linearity. It adopts a resistive digital-to-analog converter, and through the way of time-domain segmentation, uses multiple switches to achieve the feedback of multi-bit digital output; since the accuracy of the feedback analog value is determined by the duty cycle of the clock, it ensures good linearity of the digital-to-analog converter. Therefore, the present invention can solve the mismatch problem between unit resistors while realizing multi-bit feedback, can effectively improve the accuracy and energy efficiency of the continuous-time Σ-Δ analog-to-digital converter, and avoids the use of techniques such as data weighted averaging to improve linearity, reducing the complexity of circuit design.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog-to-digital conversion, and particularly relates to a multi-bit continuous-time Σ-Δ analog-to-digital converter with high linearity. Background Art

[0002] Signals generated in nature and recognizable by humans are analog signals. However, most current high-performance signal processing is performed by computers in the digital domain. Therefore, analog-to-digital converters that convert analog signals with continuous amplitude and time into digital signals with discrete amplitude and time have been widely used. As an important part of the signal chain, the accuracy, speed, and power consumption of analog-to-digital converters determine the accuracy, speed, and power consumption of signal processing. With the rapid development of fields such as mobile communication, automotive electronics, biomedical, and the Internet of Things, the requirements for accurate and high-quality data information are also increasing, so the demand for analog-to-digital converters has also increased significantly.

[0003] Modern automobiles rely on a variety of sensors to monitor and control various functions of the vehicle to ensure safety and efficiency, including sensors for temperature, pressure, humidity, light, etc. Continuous-time Σ-Δ analog-to-digital converters are one of the optimal choices for implementing automotive sensors due to their noise shaping and built-in anti-aliasing characteristics. However, most current continuous-time Σ-Δ analog-to-digital converters used for such sensors use single-bit quantizers such as the literature [M. Jang, C. Lee, and Y. Chae. Analysis and design of a low-power continuous-time Delta-Sigma modulator using a negative-resistance-assisted integrator, IEEE Journal of Solid-State Circuits, January 2019, Vol. 54, No. 1, pp. 277-287], or 1.5-bit quantizers such as the literature [M. Jang, C. Lee, and Y. Chae. A 134-μW 99.4-dB signal-to-noise-and-distortion-ratio audio continuous-time Delta-Sigma modulator using a chopped negative resistance and a three-level finite impulse response digital-to-analog converter, IEEE Journal of Solid-State Circuits, June 2021, Vol. 56, No. 6, pp. 1761-1771]. Although they have good linearity, they have problems of low accuracy and high loop filter power consumption. Using a multi-bit quantizer can increase the number of stages of the feedback digital-to-analog converter, reduce the difference between the input signal and the output of the feedback digital-to-analog converter, and can effectively improve the accuracy and reduce the power consumption of the loop filter, but the mismatch problem of the feedback digital-to-analog converter needs to be solved. Summary of the Invention

[0004] In view of the above, the present invention provides a multi-bit continuous-time Σ-Δ analog-to-digital converter with high linearity. The resistor-type feedback digital-to-analog converter structure used therein solves the mismatch problem between unit resistors while realizing multi-bit feedback, and can effectively improve the accuracy and energy efficiency of the continuous-time Σ-Δ analog-to-digital converter.

[0005] A high-linearity multi-bit continuous-time Σ-Δ analog-to-digital converter, comprising a first-stage integration unit, a second-stage integration unit, a loop delay compensation unit, a sub-analog-to-digital conversion unit, and a switch control logic unit connected in series in sequence, wherein: the two-stage integration unit is used to integrate after taking the difference between the differential input signal and the output of the internal digital-to-analog converter DAC1; the loop delay compensation unit is used to sum the output of the first-stage integration unit, the output of the second-stage integration unit, and the output of the internal digital-to-analog converter DAC2; the sub-analog-to-digital conversion unit is used to quantize the output after summation by the loop delay compensation unit to generate a digital code as the final output result; the switch control logic unit is used to encode the digital code generated by the sub-analog-to-digital conversion unit to generate a feedback switch signal for controlling DAC1 and DAC2.

[0006] Further, the switch control logic unit is connected to the first-stage integration unit and the loop delay compensation unit to form a feedback loop, so as to provide a feedback switch signal for the first-stage integration unit and the loop delay compensation unit.

[0007] Further, the first-stage integration unit includes two resistors R1 and R2, two capacitors C1 and C2, a digital-to-analog converter DAC1, and an operational amplifier OTA1. One end of R1 is the non-inverting input terminal of the first-stage integration unit, the other end of R1 is connected to the non-inverting input terminal of OTA1, the non-inverting output terminal of DAC1, and one end of C1. The other end of C1 is connected to the inverting output terminal of OTA1 and serves as the inverting output terminal of the first-stage integration unit. One end of R2 is the inverting input terminal of the first-stage integration unit, the other end of R2 is connected to the inverting input terminal of OTA1, the inverting output terminal of DAC1, and one end of C2. The other end of C2 is connected to the non-inverting output terminal of OTA1 and serves as the non-inverting output terminal of the first-stage integration unit.

[0008] Further, the digital-to-analog converter DAC1 includes five switches S1~S5 and two resistors R9 and R 10 , wherein one end of S1 is connected to one end of S2 and connected to the power supply voltage. The other end of S1 is connected to one end of S3, one end of S4, and one end of R9. One end of S5 is connected to the other end of S4 and grounded. The other end of S5 is connected to the other end of S2, the other end of S3, and one end of R 10 . The other end of R9 serves as the non-inverting output terminal of DAC1, and the other end of R 10 serves as the inverting output terminal of DAC1.

[0009] Further, when switches S1, S3, and S5 are open, and S2 and S4 are closed, the output value of DAC1 is -1; when switches S1, S2, S4, and S5 are open, and S3 is closed, the output value of DAC1 is 0; when switches S2, S3, and S4 are open, and S1 and S5 are closed, the output value of DAC1 is 1.

[0010] Further, the second-stage integration unit includes two resistors R3 and R4, two capacitors C3 and C4, and an operational amplifier OTA2. One end of R3 is the non-inverting input terminal of the second-stage integration unit, the other end of R3 is connected to the non-inverting input terminal of OTA2 and one end of C3. The other end of C3 is connected to the inverting output terminal of OTA2 and serves as the inverting output terminal of the second-stage integration unit. One end of R4 is the inverting input terminal of the second-stage integration unit, the other end of R4 is connected to the inverting input terminal of OTA2 and one end of C4. The other end of C4 is connected to the non-inverting output terminal of OTA2 and serves as the non-inverting output terminal of the second-stage integration unit.

[0011] Further, the loop delay compensation unit includes four resistors R5~R8 and a digital-to-analog converter DAC2. One end of R5 is connected to the non-inverting output terminal of the first-stage integration unit, the other end of R5 is connected to one end of R6 and the non-inverting output terminal of DAC2 and serves as the non-inverting output terminal of the loop delay compensation unit. The other end of R6 is connected to the non-inverting output terminal of the second-stage integration unit. One end of R8 is connected to the inverting output terminal of the first-stage integration unit, the other end of R8 is connected to one end of R7 and the inverting output terminal of DAC2 and serves as the inverting output terminal of the loop delay compensation unit. The other end of R7 is connected to the inverting output terminal of the second-stage integration unit.

[0012] Further, the sub-analog-to-digital conversion unit uses a multi-stage flash analog-to-digital converter, and the digital code output by it is a multi-bit binary codeword.

[0013] Further, the switch control logic unit includes a delay module and an encoding module; the delay module delays the feedback clock to generate two complementary-phase switch clocks Clk1 and Clk2, which are used to control the closing of the switches in DAC1 and DAC2 at high levels. The feedback clock is complementary in phase to the quantization clock of the sub-analog-to-digital conversion unit. The duty cycles of these four clocks are all 50%. The rising edge of Clk1 is delayed by 1 / 4 of a quantization clock period compared to the rising edge of the feedback clock.

[0014] Further, when the number of stages of the sub-analog-to-digital conversion unit is 5, it outputs a 4-bit binary codeword, corresponding to 5 values, namely -2, -1, 0, 1, 2. The encoding module encodes according to the switch clocks Clk1 and Clk2 to generate 5 groups of feedback switch signals to control the switches in DAC1 respectively. Specifically:

[0015] When the value output by the sub-analog-to-digital conversion unit is -2, S2, S3, and S4 are disconnected, and S1 and S5 are closed;

[0016] When the value output by the sub-analog-to-digital conversion unit is -1, S2 and S4 are disconnected, S1 and S5 are closed only when Clk1 is at a high level, and S3 is closed only when Clk2 is at a high level;

[0017] When the value output by the sub-analog-to-digital conversion unit is 0, S1, S2, S4, and S5 are disconnected, and S3 is closed;

[0018] When the value output by the sub-analog-to-digital conversion unit is 1, S1 and S5 are disconnected, S2 and S4 are closed only when Clk1 is at a high level, and S3 is closed only when Clk2 is at a high level;

[0019] When the value output by the sub-analog-to-digital conversion unit is 2, S1, S3, and S5 are disconnected, and S2 and S4 are closed.

[0020] Compared with the prior art, the present invention adopts a resistive multi-bit digital-to-analog converter structure. By reducing the number of unit resistors in the digital-to-analog converter, the linearity problem caused by the mismatch between unit resistors is avoided. Compared with a single-bit digital-to-analog converter, the present invention realizes a loop filter with higher precision and higher energy efficiency; compared with a traditional multi-bit digital-to-analog converter, the present invention avoids the use of data weighted averaging technology and reduces the circuit complexity. Brief Description of the Drawings

[0021] Figure 1 It is a structural block diagram of the multi-bit continuous-time Σ-Δ analog-to-digital converter of the present invention.

[0022] Figure 2 It is a schematic diagram of the overall circuit structure of the digital-to-analog converter in the present invention.

[0023] Figure 3 It is a schematic diagram of the circuit connection of the digital-to-analog converter in the present invention under different switch states, where (a) corresponds to the switch state when the analog output value is -1, (b) corresponds to the switch state when the analog output value is 0, and (c) corresponds to the switch state when the analog output value is 1.

[0024] Figure 4 It is a schematic diagram of the clock signal used in the present invention.

[0025] Figure 5 It is a logic truth table of the switch control logic unit in the present invention.

[0026] Figure 6 It is a schematic diagram of the analog output waveform of the digital-to-analog converter in the present invention.

[0027] Figure 7This is a schematic diagram of the spectrum of the output digital code of the multi-bit continuous-time Σ-Δ analog-to-digital converter of the present invention. Specific Embodiment

[0028] To describe the present invention more specifically, the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0029] In the application scenario of vehicle sensors, high-precision analog-to-digital converters are often required. To meet the above requirements, this embodiment provides a multi-bit continuous-time Σ-Δ analog-to-digital converter, which is combined with a resistive digital-to-analog converter structure to achieve high precision while avoiding the low linearity problem caused by unit resistor mismatch.

[0030] As Figure 1 shown, the second-order continuous-time Σ-Δ analog-to-digital converter of this embodiment includes a first-stage integration unit, a second-stage integration unit, a loop delay compensation unit, a sub-analog-to-digital conversion unit, and a switch control logic unit connected in series in sequence. The switch control logic unit is respectively connected to the first-stage integration unit and the loop delay compensation unit to form a feedback loop for providing multi-bit feedback to the first-stage integration unit and the loop delay compensation unit.

[0031] In this embodiment, the first-stage integration unit includes a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a first digital-to-analog converter DAC1, and a first operational amplifier OTA1; wherein, the non-inverting input terminal of the first operational amplifier OTA1 is connected to the positive terminal V of the input voltage after being connected in series with the first resistor R1 inp , and the non-inverting input terminal of the first operational amplifier OTA1 is also connected to the inverting output terminal of the first operational amplifier OTA1 after being connected in series with the first capacitor C1; the inverting input terminal of the first operational amplifier OTA1 is connected to the negative terminal V of the input voltage after being connected in series with the second resistor R2 inn , and the inverting input terminal of the first operational amplifier OTA1 is also connected to the non-inverting output terminal of the first operational amplifier OTA1 after being connected in series with the second capacitor C2; the input terminal of the first digital-to-analog converter DAC1 is connected to the output terminal of the switch control logic unit L, the non-inverting output terminal of the first digital-to-analog converter DAC1 is connected to the non-inverting input terminal of the first operational amplifier OTA1, and the inverting output terminal of the first digital-to-analog converter DAC1 is connected to the inverting input terminal of the first operational amplifier OTA1.

[0032] In this embodiment, the second-stage integration unit includes a third resistor R3, a fourth resistor R4, a third capacitor C3, a fourth capacitor C4, and a second operational transconductance amplifier OTA2. The non-inverting input terminal of the second operational transconductance amplifier OTA2 is connected to the non-inverting output terminal of the first operational transconductance amplifier OTA1 after being serially connected with the third resistor R3, and the non-inverting input terminal of the second operational transconductance amplifier OTA2 is also connected to the inverting output terminal of the second operational transconductance amplifier OTA2 after being serially connected with the third capacitor C3. The inverting input terminal of the second operational transconductance amplifier OTA2 is connected to the inverting output terminal of the first operational transconductance amplifier OTA1 after being serially connected with the fourth resistor R4, and the inverting input terminal of the second operational transconductance amplifier OTA2 is also connected to the non-inverting output terminal of the second operational transconductance amplifier OTA2 after being serially connected with the fourth capacitor C4.

[0033] In this embodiment, the loop delay compensation unit includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a second digital-to-analog converter DAC2. One end of the fifth resistor R5 is connected to the non-inverting output terminal of the first operational transconductance amplifier OTA1, and the other end of the fifth resistor R5 is connected to the non-inverting input terminal of the sub-analog-to-digital conversion unit. One end of the sixth resistor R6 is connected to the non-inverting output terminal of the second operational transconductance amplifier OTA2, and the other end of the sixth resistor R6 is connected to the non-inverting input terminal of the sub-analog-to-digital conversion unit. One end of the seventh resistor R7 is connected to the inverting output terminal of the second operational transconductance amplifier OTA2, and the other end of the seventh resistor R7 is connected to the inverting input terminal of the sub-analog-to-digital conversion unit. One end of the eighth resistor R8 is connected to the inverting output terminal of the first operational transconductance amplifier OTA1, and the other end of the eighth resistor R8 is connected to the inverting input terminal of the sub-analog-to-digital conversion unit. The non-inverting output terminal of the second digital-to-analog converter DAC2 is connected to the non-inverting input terminal of the sub-analog-to-digital conversion unit, and the inverting output terminal of the second digital-to-analog converter DAC2 is connected to the inverting input terminal of the sub-analog-to-digital conversion unit.

[0034] In this embodiment, the second digital-to-analog converter DAC2 is implemented by a common multi-bit digital-to-analog converter, which includes 4 unit resistors. The sub-analog-to-digital conversion unit uses a 5-stage flash analog-to-digital converter, and its output is a 4-bit binary codeword D out . The switch control logic unit L includes a delay module and an encoding module, which receives the 4-bit binary codeword output by the sub-analog-to-digital conversion unit and provides 5 groups of feedback switch signals for the first-stage integration unit and the loop delay compensation unit.

[0035] As Figure 2 shown, in this embodiment, the first digital-to-analog converter DAC1 includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a ninth resistor R9, and a tenth resistor R 10 ; One end of the first switch S1 and one end of the second switch S2 are connected to the power supply voltage V DD ; One end of the fourth switch S4 and one end of the fifth switch S5 are grounded at V SSThe other end of the first switch S1, the other end of the fourth switch S4 and one end of the third switch S3 are connected in series with the ninth resistor R9 to the positive phase output terminal I of the first digital-to-analog converter DAC1. OP The other end of the second switch S2, the other end of the fifth switch S5 and the other end of the third switch S3 are connected in series with a tenth resistor R 10 Connected to the inverting output terminal I of the first digital-to-analog converter ON .

[0036] like Figure 3 As shown, when S2 and S4 are closed, the positive phase output terminal I of the first digital-to-analog converter DAC1 OP The series connected R9 is grounded, and its inverting output terminal I ON R 10 Connect to power supply voltage V DD , the realized analog output value is -1, corresponding to Figure 3 (a); when S3 is closed, the positive phase output terminal I of the first digital-to-analog converter DAC1 OP The series connection of R9 and R 10 Connected to its inverting output terminal I ON , the realized analog output value is 0, corresponding to Figure 3 (b); when S1 and S5 are closed, the positive phase output terminal I of the first digital-to-analog converter DAC1 OP The series connected R9 is connected to the power supply voltage V DD , and its inverting output terminal I ON R 10 Grounded, the analog output value achieved is 1, corresponding to Figure 3 (c).

[0037] like Figure 4 As shown, the sub-analog-to-digital conversion unit is quantized by the clock Clk Q The first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 are controlled by the feedback clock Clk DAC Control. For one cycle of the feedback clock, it is divided into two divided clocks Clk1 and Clk2 with the same duty cycle but delayed by half a cycle. For different 4-bit unary code words, Clk1 and Clk2 control the closing of the switch in the digital-to-analog converter when they are at a high level.

[0038] like Figure 5 As shown, when the output of the sub-ADC unit is -2, S1 and S5 are in the entire Clk DAC When the output of the sub-ADC is -1, S1 and S5 are closed only when Clk1 is high, and S3 is closed when Clk2 is high; when the output of the sub-ADC is 0, S3 is closed during the entire Clk DACClosed during the period; when the output of the sub-analog-to-digital conversion unit is 1, S2 and S4 are closed when Clk1 is at a high level, while S3 is closed when Clk2 is at a high level; when the output of the sub-analog-to-digital conversion unit is 2, S2 and S4 are closed during the entire Clk DAC Closed during the period; thus, the 4-bit unary codeword input is converted into a 5-level analog output, realizing the function of a 5-level digital-to-analog converter.

[0039] It can be understood that since there is only one unit resistor in the resistive digital-to-analog converter of the present invention, there is no mismatch problem between the unit resistors. In addition, since Figure 4 The three states of -2, 0, and 2 in DAC last for a complete Clk

[0040] As Figure 6 shown, when the output D of the sub-analog-to-digital conversion unit out is -2, during the entire Clk DAC period, the output DAC of the first digital-to-analog converter DAC1 out is always 1; when the output D of the sub-analog-to-digital conversion unit out is -1, when Clk1 is at a high level, the output DAC of the first digital-to-analog converter DAC1 out is 1, while when Clk2 is at a high level, the output DAC of the first digital-to-analog converter DAC1 out is 0; when the output D of the sub-analog-to-digital conversion unit out is 0, during the entire Clk DAC period, the output DAC of the first digital-to-analog converter DAC1 out is always 0; when the output D of the sub-analog-to-digital conversion unit out is 1, when Clk1 is at a high level, the output DAC of the first digital-to-analog converter DAC1 out is -1, while when Clk2 is at a high level, the output DAC of the first digital-to-analog converter DAC1 out is 0; when the output D of the sub-analog-to-digital conversion unit out is 2, during the entire Clk DAC period, the output DAC of the first digital-to-analog converter DAC1 out is always -1. The second digital-to-analog converter DAC2 is directly controlled by the output 4-bit unary codeword.

[0041] As Figure 7As shown, compared with the conventional continuous-time Σ-Δ analog-to-digital converter using a 1.5-bit quantizer, the continuous-time Σ-Δ analog-to-digital converter of the present invention achieves higher precision. It can be understood that since the basic structure of the digital-to-analog converter is the same as that of the 1.5-bit quantizer, the continuous-time Σ-Δ analog-to-digital converter of the present invention does not have the problem of unit resistor mismatch.

[0042] This embodiment is an improvement made to a 5-stage digital-to-analog converter; it can be understood that similarly, in other embodiments of the present invention, the same structural improvement can also be made to digital-to-analog converters with higher bit numbers, which will not be elaborated here.

[0043] The above description of the embodiments is for the convenience of those of ordinary skill in the art to understand and apply the present invention. It is obvious that those skilled in the art can easily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative labor. Therefore, the present invention is not limited to the above embodiments, and any improvements and modifications made by those skilled in the art based on the disclosure of the present invention should be within the protection scope of the present invention.

Claims

1. A multi-bit continuous-time Σ-Δ analog-to-digital converter with high linearity, characterized in that, It includes a first-stage integration unit, a second-stage integration unit, a loop delay compensation unit, a sub-analog-to-digital conversion unit, and a switch control logic unit connected in series in sequence, where: the two-stage integration unit is used to perform integration after subtracting the differential input signal from the output of the internal digital-to-analog converter DAC1; the loop delay compensation unit is used to sum the output of the first-stage integration unit, the output of the second-stage integration unit, and the output of the internal digital-to-analog converter DAC2; the sub-analog-to-digital conversion unit is used to quantize the output after summation by the loop delay compensation unit to generate a digital code as the final output result; the switch control logic unit is used to encode the digital code generated by the sub-analog-to-digital conversion unit to generate a feedback switch signal for controlling DAC1 and DAC2. The first-stage integration unit includes two resistors R1 and R2, two capacitors C1 and C2, a digital-to-analog converter DAC1, and an operational amplifier OTA1. One end of R1 is the non-inverting input terminal of the first-stage integration unit, and the other end of R1 is connected to the non-inverting input terminal of OTA1, the non-inverting output terminal of DAC1, and one end of C1. The other end of C1 is connected to the inverting output terminal of OTA1 and serves as the inverting output terminal of the first-stage integration unit. One end of R2 is the inverting input terminal of the first-stage integration unit, and the other end of R2 is connected to the inverting input terminal of OTA1, the inverting output terminal of DAC1, and one end of C2. The other end of C2 is connected to the non-inverting output terminal of OTA1 and serves as the non-inverting output terminal of the first-stage integration unit. The digital-to-analog converter DAC1 includes five switches S1 to S5 and two resistors R9 and R 10 , where one end of S1 is connected to one end of S2 and connected to the power supply voltage, the other end of S1 is connected to one end of S3, one end of S4, and one end of R9, one end of S5 is connected to the other end of S4 and grounded, and the other end of S5 is connected to the other end of S2, the other end of S3, and one end of R 10 , the other end of R9 serves as the non-inverting output terminal of DAC1, and the other end of R 10 serves as the inverting output terminal of DAC1; When switches S1, S3, and S5 are open and S2 and S4 are closed, the output value of DAC1 is -1; when switches S1, S2, S4, and S5 are open and S3 is closed, the output value of DAC1 is 0; when switches S2, S3, and S4 are open and S1 and S5 are closed, the output value of DAC1 is 1.

2. A high linearity multi-bit continuous time Σ-Δ analog-to-digital converter according to claim 1, characterized in that: The switch control logic unit is connected to the first-stage integration unit and the loop delay compensation unit to form a feedback loop, thereby providing a feedback switch signal for the first-stage integration unit and the loop delay compensation unit.

3. A high linearity multi-bit continuous time Σ-Δ analog-to-digital converter according to claim 1, characterized in that: The second-stage integration unit includes two resistors R3 and R4, two capacitors C3 and C4, and an operational amplifier OTA2. One end of R3 is the non-inverting input terminal of the second-stage integration unit, and the other end of R3 is connected to the non-inverting input terminal of OTA2 and one end of C3. The other end of C3 is connected to the inverting output terminal of OTA2 and serves as the inverting output terminal of the second-stage integration unit. One end of R4 is the inverting input terminal of the second-stage integration unit, and the other end of R4 is connected to the inverting input terminal of OTA2 and one end of C4. The other end of C4 is connected to the non-inverting output terminal of OTA2 and serves as the non-inverting output terminal of the second-stage integration unit.

4. A high-linearity multi-bit continuous-time Σ-Δ analog-to-digital converter according to claim 1, characterized in that: The loop delay compensation unit includes four resistors R5 to R8 and a digital-to-analog converter DAC2. One end of R5 is connected to the non-inverting output terminal of the first-stage integration unit. The other end of R5 is connected to one end of R6 and the non-inverting output terminal of DAC2 and serves as the non-inverting output terminal of the loop delay compensation unit. The other end of R6 is connected to the non-inverting output terminal of the second-stage integration unit. One end of R8 is connected to the inverting output terminal of the first-stage integration unit. The other end of R8 is connected to one end of R7 and the inverting output terminal of DAC2 and serves as the inverting output terminal of the loop delay compensation unit. The other end of R7 is connected to the inverting output terminal of the second-stage integration unit.

5. A high linearity multi-bit continuous time Σ-Δ analog-to-digital converter according to claim 1, characterized in that: The sub-analog-to-digital conversion unit uses a multi-stage flash analog-to-digital converter, and the digital code output by it is a multi-bit binary codeword.

6. A high linearity multi-bit continuous time Σ-Δ analog-to-digital converter according to claim 1, characterized in that: The switch control logic unit includes a delay module and an encoding module. The delay module delays the feedback clock to generate two complementary-phase switch clocks Clk1 and Clk2, which are used to control the switches in DAC1 and DAC2 to close at high levels. The feedback clock is complementary in phase to the quantization clock of the sub-analog-to-digital conversion unit. The duty cycles of these four clocks are all 50%. The rising edge of Clk1 is delayed by 1 / 4 of a quantization clock cycle compared to the rising edge of the feedback clock.

7. A high linearity multi-bit continuous time Σ-Δ analog-to-digital converter according to claim 6, characterized in that: When the number of stages of the sub-analog-to-digital conversion unit is 5, it outputs a 4-bit binary codeword, corresponding to 5 values, namely -2, -1, 0, 1, 2. The encoding module encodes according to the switch clocks Clk1 and Clk2 to generate 5 groups of feedback switch signals to control the switches in DAC1 respectively. Specifically: When the value output by the sub-analog-to-digital conversion unit is -2, S2, S3, and S4 are disconnected, and S1 and S5 are closed. When the value output by the sub-analog-to-digital conversion unit is -1, S2 and S4 are disconnected, S1 and S5 are closed only at the high level of Clk1, and S3 is closed only at the high level of Clk2. When the value output by the sub-analog-to-digital conversion unit is 0, S1, S2, S4, and S5 are disconnected, and S3 is closed. When the value output by the sub-analog-to-digital conversion unit is 1, S1 and S5 are disconnected, S2 and S4 are closed only at the high level of Clk1, and S3 is closed only at the high level of Clk2. When the value output by the sub-analog-to-digital conversion unit is 2, S1, S3, and S5 are disconnected, and S2 and S4 are closed.

Images