Infrared signal reading unit based on double sampling structure

Abstract

The invention provides an infrared signal readout unit based on a double-sampling structure. The infrared signal readout unit comprises an integrating circuit, a state switching circuit and a double-sampling circuit which are sequentially connected, the integrating circuit converts an input signal into an integral voltage and transmits the integral voltage to the state switching circuit; the state switching circuit charges the charging capacitor in a sampling state, controls the channel charge injection amount of the field effect transistor connected with the sampling capacitor in a holding state, and reduces charge injection into the sampling capacitor; the double-sampling circuit uses a single capacitor to complete twice sampling. The virtual switch is arranged to reduce the situation of channel charge injection in the double-sampling process, good injection efficiency and output linearity are guaranteed, the signal reading precision of the circuit is improved, meanwhile, the single-capacitor double-sampling circuit is used for sampling the integral voltage, the area occupied by one large capacitor can be saved during board arrangement, and the pixel size can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to an infrared signal readout unit based on a dual-sampling structure. Background Art

[0002] An infrared detector array and a readout circuit together form an infrared focal plane array. A well-performing readout circuit plays a crucial role in the quality of the infrared focal plane array. The detector array converts the detected infrared signal into a weak signal and outputs it to the readout circuit, and the readout circuit is responsible for reading out the electrical signal generated by the detector induction.

[0003] With the in-depth research on infrared focal planes, while the scale of the detector array is continuously expanding, the pixel center distance shows a decreasing trend, which puts forward higher requirements for aspects such as low power consumption, small area, and high speed in the design of the readout circuit. In the prior art, the conventional design of the readout circuit usually includes unit modules such as integration amplification, sample and hold, and buffer output. It is not easy to simultaneously meet the requirements of a small area and a high read speed using this framework design. Summary of the Invention

[0004] Aiming at the deficiencies existing in the prior art, the present invention proposes an infrared signal readout unit based on a dual-sampling structure to solve the deficiencies existing in the prior art.

[0005] The technical solution adopted by the present invention is as follows:

[0006] In a first aspect, there is provided an infrared signal readout unit based on a dual-sampling structure, including: an integration circuit, a state switching circuit, and a dual-sampling circuit connected in sequence;

[0007] The integration circuit converts the input signal into an integration voltage and transmits it to the state switching circuit;

[0008] The state switching circuit charges the charging capacitor in the sampling state and controls the channel charge injection amount of the field effect transistor connected to the sampling capacitor in the holding state to reduce the charge injection into the sampling capacitor;

[0009] The dual-sampling circuit uses a single capacitor to complete two samplings.

[0010] Further, the integration circuit includes an operational amplifier, an integration capacitor C1, and a reset switch;

[0011] The negative input terminal of the operational amplifier is connected to the infrared detector to provide a bias voltage for the infrared detector, and the positive input terminal of the operational amplifier is connected to a reference voltage;

[0012] The integration capacitor C1 is connected across the negative input terminal and the output terminal V of the operational amplifier OUT1between, transfer the integral voltage to the state switching circuit;

[0013] The reset switch is connected across the negative input terminal and the output terminal of the operational amplifier.

[0014] Furthermore, the integration circuit controls the integration-reset process of the integration circuit through the reset switch. When the reset switch is closed, the operational amplifier is connected in the form of a unity-gain buffer, and the input and output terminal voltages are equal; when the reset switch is open, the integration capacitor C1 integrates the detector output current I D and controls the working state of the CMOS reset switch by using the first control signal RST and the second control signal RST1.

[0015] Furthermore, the state switching circuit includes PMOS transistor M0, NMOS transistor M1, NMOS transistor M2, PMOS transistor M3, PMOS transistor M4, PMOS transistor M5, NMOS transistor M6, NMOS transistor M7, PMOS transistor M8, NMOS transistor M9, NMOS transistor M10, PMOS transistor M11, NMOS transistor M12, PMOS transistor M13, NMOS transistor M14, PMOS transistor M15, PMOS transistor M16, NMOS transistor M17, and a charging capacitor Cs and a holding capacitor C H .

[0016] Furthermore, when the state switching circuit is in the sampling state, the third control signal CLKS is at a low level, the fourth control signal CLKSB is at a high level, the NMOS transistor M9 is turned on, and the potential at point B is GND; the NMOS transistor M1 is turned on, the potential at point G is GND, and the PMOS transistor M3 is turned on, and the potential at point A is VDD.

[0017] Furthermore, when the state switching circuit is in the holding state, the third control signal CLKS is at a high level, the fourth control signal CLKSB is at a low level, the NMOS transistor M6 is turned on, and the potential GND at point B is transferred to the gates of the PMOS transistor M4 and the PMOS transistor M8. The PMOS transistor M4 and the PMOS transistor M8 are turned on, and the potential VDD at point A is transferred to point G and point D. When the output voltage VOUT1 of the integration signal is input to point C, the CMOS switch composed of the NMOS transistor M10 and the PMOS transistor M11 is turned on. At this time, the potential at point B is VOUT1, the potential at point A is VDD + VOUT1, the potential at point D is VDD + VOUT1, then the potential at point G is also VDD + VOUT1, and the gate-source voltage of the NMOS transistor M12 is constantly VOUT1;

[0018] When the NMOS transistor M12 is turned on, the third control signal controls the NMOS transistor M17 to be turned on, transmitting GND to the gate of the PMOS transistor M15. When the PMOS transistor M15 is turned on, it transmits the potential at point D to the gate of the virtual switch NMOS transistor M14, and the virtual switch NMOS transistor M14 is used to reduce the channel charge injection of the NMOS transistor M12.

[0019] Further, the double-sampling circuit includes an NMOS transistor M18, an NMOS transistor M19, and a sampling capacitor Cc.

[0020] The drain of the NMOS transistor M18 is connected to the lower plate of the sampling capacitor Cc, the gate is connected to the fifth control signal CLK1, and the source is grounded; the drain of the NMOS transistor M19 is connected to the upper plate of the sampling capacitor, the gate is connected to the sixth control signal CKL2, and the source is grounded.

[0021] Further, the state switching circuit includes an NMOS switch M12.

[0022] When the NMOS switch M12 is turned on for the first time, the fifth control signal CLK1 is at a low level, the NMOS transistor M18 is in the off state, the sixth control signal CLK2 is at a high level, the NMOS transistor M19 is in the on state, the upper plate of the sampling capacitor Cc is grounded, and the lower plate is connected to the first sampling potential, completing the first sampling.

[0023] When the NMOS switch M12 is turned on for the second time, the fifth control signal CLK1 is at a low level, the NMOS transistor M18 is in the off state, the sixth control signal CLK2 is at a low level, the NMOS transistor M19 is in the off state, the upper plate of the sampling capacitor Cc is the second sampling potential minus the first sampling potential, and the lower plate is the second sampling potential.

[0024] In a second aspect, an infrared focal plane array is provided, which uses the infrared signal reading unit based on the double-sampling structure described in the first aspect to read the electrical signal generated by the infrared detector.

[0025] As can be seen from the above technical solutions, the beneficial technical effects of the present invention are as follows:

[0026] 1. The integral output voltage is connected to the state switching circuit. The state switching circuit reduces the on-resistance of the sampling switch M12, and a virtual switch M14 is set to reduce the channel charge injection during the double-sampling process, ensuring good injection efficiency and output linearity, and improving the signal reading accuracy of the circuit.

[0027] 2. The integral voltage is sampled by the single-capacitor double-sampling circuit, and the area occupied by one large capacitor can be saved during layout, reducing the pixel size.

[0028] 3. The CMOS switch controlled by the third control signal CLKS and the fourth control signal CLKSB can further improve the charging speed of the charging capacitor C S and improve the readout speed of the circuit, realizing a high-speed and high-precision readout process. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0030] Figure 1 is the circuit structure diagram of the infrared signal readout unit based on the double-sampling structure according to the embodiment of the present invention;

[0031] Figure 2 is the waveform diagram of the output signal of the integration circuit according to the embodiment of the present invention;

[0032] Figure 3 is the circuit structure diagram of the operational amplifier according to the embodiment of the present invention;

[0033] Figure 4 is the timing diagram of the control signal according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] The following will describe in detail the embodiments of the technical solutions of the present invention with reference to the drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and thus are only examples and cannot be used to limit the protection scope of the present invention.

[0035] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should have the ordinary meanings understood by those skilled in the art to which the present invention belongs.

[0036] Embodiment

[0037] The inventors of this application have found through research that: for the existing infrared signal readout circuit, in the sample and hold unit module, a traditional double-sampling structure is usually adopted; the double-sampling structure requires two sampling capacitors, and the area of the capacitors is relatively large, which is not conducive to the miniaturization of the area design of the readout circuit. At the same time, in terms of the read speed, the on-resistance and channel charge injection effect of the sampling unit will always affect the speed and accuracy of the circuit. Specifically, generally, the sampling switch is a CMOS switch composed of a single MOS transistor or a parallel combination of NMOS and PMOS. For different input voltages, the on-resistance of the switch will change, thus affecting the linearity of the sampling circuit. The sampling switch has a channel charge injection effect, and the charge in the channel will be injected into the sampling capacitor Cc, affecting the signal readout accuracy of the circuit.

[0038] Combined with the above research results, this embodiment provides an infrared signal readout unit based on a dual-sampling structure, and its circuit unit structure is as Figure 1 shown, including:

[0039] An integration circuit, a state switching circuit, and a dual-sampling circuit connected in sequence. The following is an explanation of each part of the circuit and its working principle:

[0040] 1. Integration circuit

[0041] The integration circuit includes an operational amplifier, an integration capacitor C1, and a reset switch, which converts the input signal into an integration voltage and transmits it to the state switching circuit.

[0042] The negative input terminal of the operational amplifier is connected to the infrared detector and provides a bias voltage for the infrared detector. The positive input terminal of the operational amplifier is connected to the reference voltage;

[0043] The integration capacitor C1 is connected across the negative input terminal and the output terminal V OUT1 between them, and transmits the integration voltage to the state switching circuit.

[0044] The reset switch is a CMOS reset switch composed of an NMOS transistor M20 and a PMOS transistor M21. The reset switch is connected across the negative input terminal and the output terminal of the operational amplifier. The integration-reset process of the integration circuit is controlled by the reset switch. When the reset switch is closed, the operational amplifier is connected in the form of a unity-gain buffer, and the input and output terminal voltages are equal; when the reset switch is open, the integration capacitor C1 integrates the detector output current I D and controls the working state of the CMOS reset switch by using the first control signal RST and the second control signal RST1.

[0045] Reference Figure 2 , which is the waveform diagram of the integration circuit output signal. The high level of the first control signal RST is the integration state, and the low level of the first control signal RST is the reset state; preferably, the integration time and the reset time are each 2 μS, and the output voltage during the integration process is 2.5 - 3.5 V.

[0046] Reference Figure 3 , which is the schematic circuit diagram of the integration operational amplifier. A common-source amplifier with a cascode structure as the load is used as the integration operational amplifier to increase the output resistance and improve the gain of the amplifier. The gate of the PMOS transistor MP0 is connected to the bias voltage Vb, the gate of the PMOS transistor MP1 is the positive input terminal, and the gate of the PMOS transistor MP2 is the negative input terminal.

[0047] 2. State switching circuit

[0048] The state switching circuit includes PMOS transistor M0, NMOS transistor M1, NMOS transistor M2, PMOS transistor M3, PMOS transistor M4, PMOS transistor M5, NMOS transistor M6, NMOS transistor M7, PMOS transistor M8, NMOS transistor M9, NMOS transistor M10, PMOS transistor M11, NMOS transistor M12, PMOS transistor M13, NMOS transistor M14, PMOS transistor M15, PMOS transistor M16, NMOS transistor M17, charging capacitor Cs and holding capacitor C H ; wherein:

[0049] The gates of PMOS transistor M0 and NMOS transistor M1 are connected to the fourth control signal CLKSB. The drains of PMOS transistor M0 and NMOS transistor M1 are connected to the source of NMOS transistor M2. The source of NMOS transistor M1 is grounded. The source of NMOS transistor M2 is connected to point G. The source of PMOS transistor M0 is connected to VDD;

[0050] The gate of PMOS transistor M3 is connected to the drain of PMOS transistor M4. The source of PMOS transistor M3 is connected to VDD, and the drain is connected to charging capacitor Cs. The gates of PMOS transistor M5 and NMOS transistor M6 are connected to the third control signal CLKS. The drains of PMOS transistor M5, NMOS transistor M6 and NMOS transistor M7 are connected to the gates of PMOS transistor M4 and PMOS transistor M8. The source of PMOS transistor M5 is connected to VDD. The sources of NMOS transistor M6 and NMOS transistor M7 are connected to potential B. The gate of NMOS transistor M7 is connected to potential G;

[0051] The source of NMOS transistor M8 is connected to potential A, and the drain is connected to the upper plate potential D of holding capacitor C H The gate of NMOS transistor M9 is connected to the fourth control signal CLKSB, the source is connected to GND, and the drain is connected to potential B;

[0052] NMOS transistor M10 and PMOS transistor M11 are connected in parallel to form a CMOS switch. The source is connected to potential B, and the drain is connected to potential C. The gate of NMOS transistor M10 is connected to the third control signal CLKS, and the gate of PMOS transistor M11 is connected to the fourth control signal CLKSB. The gate of NMOS transistor M12 is connected to potential G, the source is connected to potential C, the substrate is connected to potential B, and the drain is connected to the sampling capacitor Cc of the single-capacitor double-sampling circuit;

[0053] holding capacitor C HThe upper plate of it is connected to potential D, and the lower plate is connected to GND; the gate of PMOS transistor M13 is connected to the third control signal CLKS, the drain is connected to GND, and the source is connected to potential D; the source and drain of NMOS transistor M14 are connected to the sampling capacitor Cc, the gate is connected to the drain of PMOS transistor M15, the source of PMOS transistor M15 is connected to potential D, and the gate is connected to the drains of PMOS transistor M16 and NMOS transistor M17; the gates of PMOS transistor M16 and NMOS transistor M17 are connected to the fourth control signal CLKSB, the drains are connected to the gate of PMOS transistor M15, the source of PMOS transistor M16 is connected to VDD, and the source of NMOS transistor M17 is connected to GND.

[0054] The state switching circuit is divided into two working states: the sampling state and the holding state. Specifically:

[0055] Sampling state: When the third control signal CLKS is at a low level and the fourth control signal CLKSB is at a high level, it is in the holding state. NMOS transistor M9 is turned on, and the potential at point B is GND; NMOS transistor M1 is turned on, and the potential at point G is GND, then PMOS transistor M3 is turned on, and the potential at point A is VDD, completing the charging process of the charging capacitor C S of.

[0056] Holding state: When the third control signal CLKS is at a high level and the fourth control signal CLKSB is at a low level, it is in the sampling state. NMOS transistor M6 is turned on, transmitting the potential GND at point B to the gates of PMOS transistor M4 and PMOS transistor M8. PMOS transistor M4 and PMOS transistor M8 are turned on, transmitting the potential VDD at point A to point G and point D. When the output voltage VOUT1 of the integration signal is input to point C, the CMOS switch composed of NMOS transistor M10 and PMOS transistor M11 is turned on. At this time, the potential at point B is VOUT1, the potential at point A is VDD + VOUT1, the potential at point D is VDD + VOUT1, then the potential at point G is also VDD + VOUT1, and the gate-source voltage of NMOS transistor M12 is constantly VOUT1. At the same time, when NMOS transistor M12 is turned on, the third control signal controls NMOS transistor M17 to be turned on, transmitting GND to the gate of PMOS transistor M15. PMOS transistor M15 is turned on to transmit the potential at point D to the gate of the virtual switch NMOS transistor M14, and the channel charge injection of NMOS transistor M12 is reduced through the virtual switch NMOS transistor M14. In the holding state, by controlling the channel charge injection amount of the field effect transistor connected to the sampling capacitor, the charge injection into the sampling capacitor can be reduced.

[0057] 3. Dual-sampling circuit

[0058] The dual-sampling circuit of this embodiment is a single-capacitor dual-sampling circuit, including NMOS transistor M18, NMOS transistor M19, and sampling capacitor Cc. Among them:

[0059] The drain of NMOS transistor M18 is connected to the lower plate of the sampling capacitor Cc, the gate is connected to the fifth control signal CLK1, and the source is grounded; the drain of NMOS transistor M19 is connected to the upper plate of the sampling capacitor, the gate is connected to the sixth control signal CKL2, and the source is grounded.

[0060] The working principle of the single-capacitor dual-sampling circuit is as follows: When NMOS switch M12 conducts for the first time, the fifth control signal CLK1 is at a low level, NMOS transistor M18 is in the off state, the sixth control signal CLK2 is at a high level, NMOS transistor M19 is in the on state, the upper plate of the sampling capacitor Cc is grounded, and the lower plate is connected to the first sampling potential, completing the first sampling.

[0061] When NMOS switch M12 conducts for the second time, the fifth control signal CLK1 is at a low level, NMOS transistor M18 is in the off state, the sixth control signal CLK2 is at a low level, NMOS transistor M19 is in the off state, the upper plate of the sampling capacitor Cc is the second sampling potential minus the first sampling potential, and the lower plate is the second sampling potential.

[0062] The single-capacitor dual-sampling circuit of this embodiment is different from the prior art. It can achieve the function of dual sampling with only a single capacitor, and the area occupied by one sampling capacitor can be saved during layout; in this embodiment, saving one sampling capacitor can reduce the size of the entire chip by nearly 20% of the area, which is beneficial to the miniaturization of the area design of the readout circuit.

[0063] 4. Working timing of the readout unit

[0064] Reference Figure 4 , which is the timing diagram of the control signals. RST is the first control signal, and RST1 is the second control signal; CLKS is the third control signal, and CLKSB is the fourth control signal; CLK1 is the fifth control signal, and CLK2 is the sixth control signal; When the first control signal RST is at a high level and the second control signal RST1 is at a low level, integration starts. When the third control signal CLKS is at a high level, the fourth control signal CLKSB is at a low level, the fifth control signal CLK1 is at a low level, and the sixth control signal CLK2 is at a high level, it is the first sampling; When the third control signal CLKS is at a high level, the fourth control signal CLKSB is at a low level, the fifth control signal CLK1 is at a low level, and the sixth control signal CLK2 is at a low level, it is the second sampling. When the first control signal RST is at a low level and the second control signal RST1 is at a high level, the integration is reset. When the output signal is at a high level, the sampling signal is output. When the fifth control signal CLK1 is at a high level and the sixth control signal CLK2 is at a high level, the sampling capacitor Cc is reset.

[0065] Combined with the figures and the above analysis, it shows that an infrared signal readout unit based on a dual-sampling structure according to the present invention uses an integrating circuit composed of a small-area and high-gain operational amplifier to integrate the input current. The integrated output voltage is connected to a state switching circuit. The on-resistance of the sampling switch M12 is reduced through the state switching circuit, and a virtual switch M14 is set to reduce the channel charge injection during the dual-sampling process, which is beneficial to ensuring good injection efficiency and output linearity, and improving the signal reading accuracy of the circuit. Finally, the integrated voltage is sampled by a single-capacitor dual-sampling circuit, and the area occupied by one large capacitor can be saved during layout, which helps to reduce the pixel size. At the same time, the CMOS switch controlled by the third control signal CLKS and the fourth control signal CLKSB can further improve the charging speed of the charging capacitor C S and improve the readout speed of the circuit, realizing a high-speed and high-precision readout process.

[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features. And these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered by the scope of the claims and the description of the present invention.

Claims

1. An infrared signal readout unit based on a double sampling structure, characterized in that: include: An integration circuit, a state switching circuit, and a double sampling circuit are connected in sequence; The integration circuit converts the input signal into an integration voltage and transmits it to the state switching circuit; The state switching circuit charges the charging capacitor in the sampling state, and controls the channel charge injection amount of the field effect transistor connected to the sampling capacitor in the holding state to reduce the charge injection into the sampling capacitor; The double sampling circuit uses a single capacitor to complete two samplings.

2. The infrared signal readout unit based on the double sampling structure according to claim 1, characterized in that: The integration circuit includes an operational amplifier, an integration capacitor C1 and a reset switch; The negative input terminal of the operational amplifier is connected to the infrared detector to provide a bias voltage for the infrared detector, and the positive input terminal of the operational amplifier is connected to a reference voltage; The integrating capacitor C1 is connected across the negative input terminal and output terminal V of the operational amplifier. OUT1 The integrated voltage is transmitted to the state switching circuit; The reset switch is connected between the negative input terminal and the output terminal of the operational amplifier.

3. The infrared signal readout unit based on the double sampling structure according to claim 2, characterized in that: The integration circuit controls the integration-reset process of the integration circuit through the reset switch. When the reset switch is closed, the operational amplifier is connected in the form of a unity gain buffer, and the input and output voltages are equal; when the reset switch is opened, the integration capacitor C1 has an effect on the detector output current I D Integration is performed, and the working state of the CMOS reset switch is controlled by using the first control signal RST and the second control signal RST1.

4. The infrared signal readout unit based on the double sampling structure according to claim 1, characterized in that: The state switching circuit includes a PMOS tube M0, an NMOS tube M1, an NMOS tube M2, a PMOS tube M3, a PMOS tube M4, a PMOS tube M5, an NMOS tube M6, an NMOS tube M7, a PMOS tube M8, an NMOS tube M9, an NMOS tube M10, a PMOS tube M11, an NMOS tube M12, a PMOS tube M13, an NMOS tube M14, a PMOS tube M15, a PMOS tube M16, an NMOS tube M17, a capacitor Cs and a holding capacitor Cs H .

5. The infrared signal readout unit based on the double sampling structure according to claim 4 is characterized in that: When the state switching circuit is in the sampling state, the third control signal CLKS is at a low level, the fourth control signal CLKSB is at a high level, the NMOS tube M9 is turned on, and the potential at point B is GND; the NMOS tube M1 is turned on, the potential at point G is GND, the PMOS tube M3 is turned on, and the potential at point A is VDD.

6. The infrared signal readout unit based on the double sampling structure according to claim 4, characterized in that: When the state switching circuit is in the hold state, the third control signal CLKS is at a high level, the fourth control signal CLKSB is at a low level, the NMOS tube M6 is turned on, and the potential GND at point B is transmitted to the gates of the PMOS tubes M4 and M8, the PMOS tubes M4 and M8 are turned on, and the potential VDD at point A is transmitted to points G and D, when the output voltage VOUT1 of the integrated signal is input to point C, the CMOS switch composed of the NMOS tube M10 and the PMOS tube M11 is turned on, at this time the potential at point B is VOUT1, the potential at point A is VDD+VOUT1, the potential at point D is VDD+VOUT1, then the potential at point G is also VDD+VOUT1, and the gate-source voltage of the NMOS tube M12 is constant at VOUT1; When the NMOS tube M12 is turned on, the third control signal controls the NMOS tube M17 to be turned on, and transmits GND to the gate of the PMOS tube M15. The PMOS tube M15 is turned on to transmit the potential at point D to the gate of the virtual switch NMOS tube M14, and the channel charge injection of the NMOS tube M12 is reduced through the virtual switch NMOS tube M14.

7. The infrared signal readout unit based on the double sampling structure according to claim 1, characterized in that: The double sampling circuit includes an NMOS tube M18, an NMOS tube M19, and a sampling capacitor Cc; The drain of the NMOS tube M18 is connected to the lower plate of the sampling capacitor Cc, the gate is connected to the fifth control signal CLK1, and the source is grounded; the drain of the NMOS tube M19 is connected to the upper plate of the sampling capacitor, the gate is connected to the sixth control signal CKL2, and the source is grounded.

8. The infrared signal readout unit based on the double sampling structure according to claim 7, characterized in that: The state switching circuit includes an NMOS switch M12; When the NMOS switch M12 is turned on for the first time, the fifth control signal CLK1 is at a low level, the NMOS tube M18 is in a closed state, the sixth control signal CLK2 is at a high level, the NMOS tube M19 is in a conducting state, the upper plate of the sampling capacitor Cc is grounded, and the lower plate is connected to the first sampling potential, completing the first sampling; When the NMOS switch M12 is turned on for the second time, the fifth control signal CLK1 is at a low level, the NMOS tube M18 is in a closed state, the sixth control signal CLK2 is at a low level, the NMOS tube M19 is in a closed state, the upper plate of the sampling capacitor Cc is the second sampling potential minus the first sampling potential, and the lower plate is the second sampling potential.

9. An infrared focal plane array, characterized in that: The infrared signal readout unit based on the double sampling structure described in any one of claims 1 to 8 is used to read out the electrical signal induced by the infrared detector.

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