Method for producing semiconductor structure element and semiconductor structure element

Abstract

The invention relates to a method for producing a semiconductor structure element, comprising the following steps: providing a substrate layer and / or a drain layer, a first type doped drift layer and / or diffusion layer applied to the substrate layer and / or the drain layer, a channel layer applied to the drift layer and / or diffusion layer, and a first type doped source layer introduced into and / or applied to the channel layer; constructing a gate channel, wherein the gate channel extends into the drift layer and / or the diffusion layer from the source layer in the vertical direction; in the case of using self-alignment, in particular by means of implantation, a shielding region of a second type of doping is formed, which extends in the vertical direction into the drift layer and / or the diffusion layer, the shielding region is formed such that the shielding region has a predetermined lateral distance from the gate channel, and in the case of self-alignment, in particular by means of implantation, the shielding region extends in the vertical direction into the drift layer and / or the diffusion layer. A channel region corresponding to a predetermined lateral distance remains in the channel layer, and a shielding region is formed such that at least a part of the shielding region extends in the vertical direction up to the underneath of the gate channel.

Description

Field of the Invention

[0001] The present invention relates to a method for manufacturing a semiconductor structural element and such a semiconductor structural element, in particular a transistor, in particular a so-called trench MOSFET. Background Art

[0002] Field effect transistors, in particular so-called MOSFETs or MISFETs, are used in different fields. One variant is the so-called trench MOSFET or T-MOSFET, in which the channel is constructed vertically. Here, for example, an n-doped source layer and a channel layer located between the n-doped source layer and an n-doped drift layer are interrupted by channels (English "Trenches"); in such channels, a gate is subsequently arranged. Summary of the Invention

[0003] According to the present invention, a method for manufacturing a semiconductor structural element and a semiconductor structural element are provided. Advantageous configurations are the subject of the following description.

[0004] The present invention studies semiconductor structural elements, such as in particular field effect transistors, more precisely semiconductor structural elements having channels or trenches, and their manufacture. In terms of semiconductor materials, different types of doping are used, namely n-doping and p-doping, where different components can be doped in different ways. Below, for better understanding, field effect transistors will be described with a certain type of doping, with n-doping being the first type of doping and p-doping being the second type of doping. However, it should be understood that n-doping and p-doping can also be interchanged, i.e., n-doping can be the second type of doping and p-doping can be the first type of doping.

[0005] Typically, such a field effect transistor has a substrate layer and / or a drain layer, an n-doped drift layer and / or a diffusion layer (e.g., but can also have only a drift layer) applied to the substrate layer and / or the drain layer, a channel layer (usually p-doped) applied to the drift layer and / or the diffusion layer, and an n-doped source layer introduced into and / or applied to the channel layer. The substrate layer and / or the drain layer can also have a so-called buffer layer between the substrate layer and the drain layer. In addition, a gate channel, a so-called trench, is provided, which extends in the vertical direction from the source layer into the drift layer and / or the diffusion layer. Then, a gate with a gate electrode is introduced therein, where the gate electrode is usually surrounded by a gate dielectric or a gate oxide.

[0006] In addition, such a field-effect transistor typically has a source contact material layer that is adjacent to the source layer. The gate or gate electrode is insulated from the source contact material layer. Similarly, such a field-effect transistor has a drain contact material layer that is adjacent to the substrate layer and / or the drain layer. Here, the source contact material layer serves as the source electrode or as an attachment end, and correspondingly, the drain contact material layer serves as the drain electrode or as an attachment end.

[0007] It should be mentioned that this type of field-effect transistor can have multiple such gate regions or gate channels and gate electrodes. Then, so-called fins or mesa structures are formed between the gate regions, and the layers mentioned are constructed in the fins or mesa structures. Here, there are special advantages of the trench MOSFET in that, due to the vertical arrangement, multiple gate electrodes can be arranged side by side with respect to each other.

[0008] Such a field-effect transistor can be used alone or together with other field-effect transistors in the field-effect transistors as a power switch. Preferred application areas are, for example, in the electric drive system of a vehicle (where, for example, in a current converter (DC / DC converter, inverter)), in a charging device for an electric drive vehicle, or also in a solar inverter.

[0009] A special advantage of the trench MOSFET, for example, is that due to the vertical arrangement, multiple gate electrodes can be arranged side by side with respect to each other per unit area. The field-effect transistor can be constructed in particular as a SiC field-effect transistor or a GaN field-effect transistor, that is, the substrate and / or the semiconductor material commonly used can be silicon carbide (SiC) or gallium nitride (GaN) because these semiconductor materials have a wide bandgap. However, similarly, semiconductor materials with an ultra-wide bandgap, such as gallium oxide, can also be considered. Generally speaking, however, the present invention can also be used in the case of other semiconductor materials, such as gallium nitride (GaN), silicon (Si), or germanium (Ge).

[0010] One challenge in such a field-effect transistor, such as a silicon carbide (SiC) trench gate power MISFET, is to achieve good on-state performance (i.e., low area-specific resistance) in the case of good short-circuit strength and, in addition, to limit the maximum field strength in the insulator of the trench to an acceptable value, for example, on the order of 3 MV / cm, for reliability reasons at a high cut-off voltage.

[0011] One possibility for achieving good short-circuit strength lies in limiting the current density to the smallest possible value in the event of a short circuit, since this limits the power loss density and the heating rate of the field-effect transistor or of a structural element containing a field-effect transistor and enables timely switching off of the structural element to prevent damage or destruction of the structural element. Ideally, this is achieved while maintaining a low area-specific resistance in the conducting state.

[0012] An important measure for increasing the short-circuit strength can be to reduce the current flowing in the short circuit by reducing channel-length modulation. For this purpose, the pn transition between the body region (channel layer) and the drift layer and / or the diffusion layer must be shielded from the influence of high electric fields. For this purpose, in a SiC trench MISFET, for example, it can be a vertically deep p or p+-doped shielding region that extends vertically into the drift layer and / or the diffusion layer, that is laterally spaced from the gate channel, and that extends vertically down to below the gate channel.

[0013] However, some problems arise here. To achieve a large vertical depth of the shielding region, so-called high-energy implants in the MeV range are usually required, which result in the p or p+ profile (i.e., the profile of the shielding region) not being very abrupt in the lateral and vertical directions, but rather its doping concentration decaying with a moderate steepness due to tails and lateral spreading (Unterstreuung) under the mask necessary for structuring it; furthermore, these MeV processes are cost-intensive and damage the crystal, such as a 4H-SiC crystal.

[0014] Due to alignment tolerances, the nominal spacing of the shielding region from the gate channel or trench in the lateral direction must not be less than a certain minimum spacing, because otherwise, in the case of imperfect alignment, the threshold voltage increases and the specific on-resistance increases in the conducting state.

[0015] Such alignment tolerances result in an asymmetric distribution of the current in the event of a short circuit, since the JFET resistance is different in size or width between the shielding region and the regions to the left and right of the gate channel. As a result, the current always flows through the JFET region (channel layer) with the smaller resistance.

[0016] Against this background, it is proposed to construct a p-doped shielding region in the case of using self-alignment, in particular by means of implantation. By means of self-alignment, a pre-given lateral spacing of the shielding region from the gate channel is achieved, such that a channel region corresponding to the pre-given lateral spacing remains in the channel layer. That is, a part of the channel layer becomes the shielding region. Here, the shielding region is constructed such that at least a part of the shielding region extends vertically down to below the gate channel.

[0017] Here, the use of a mask and / or a filling material can be set, and by means of this filling material, a mask is also formed, for example. This will be discussed in more detail below and within the framework of the description of the drawings.

[0018] This self-alignment allows the lateral spacing between the shielding region and the gate channel to be constructed as accurately as desired.

[0019] In one embodiment, the construction of the shielding region includes, in particular by means of implantation, and in the case of using a first mask for self-alignment, constructing a first sub-shielding region of the shielding region, and in particular by means of implantation, and in the case of using a second mask for self-alignment, constructing a second sub-shielding region of the shielding region. Here, the lateral width of the first mask is selected according to a predefined lateral spacing of the shielding region relative to the gate channel. The second sub-shielding region extends vertically until below the gate channel and is deeper than the first sub-shielding region, and the second sub-shielding region is arranged in the lateral direction at most as close to the gate channel as the first sub-shielding region.

[0020] Here, the second sub-shielding region can in particular correspond to the shielding region mentioned at the beginning. That is, in this case, an additional (here the first) shielding region is additionally provided, which does not extend as deeply in the vertical direction, but this allows a more accurate adjustment of the lateral spacing from the gate channel. Similarly, the first sub-shielding region can be introduced with a lower implantation energy than the second sub-shielding region, so that the first sub-shielding region is more abrupt and thus results in a smaller channel length modulation. The implantation profile can be reverse.

[0021] By constructing the shielding region self-aligned with respect to the gate channel, the shielding region can be arranged particularly close to the surface of the channel layer on the gate-channel side, which again reduces the channel length modulation.

[0022] In one embodiment, the second sub-shielding region can also be implemented deeper, so that the electric field strength on the rounding of the gate channel is reduced, which is advantageous in terms of reliability.

[0023] In one embodiment, before constructing the gate region, a first shielding channel is constructed, which extends vertically into the channel layer and has a greater spacing from the gate channel in the lateral direction than the spacing between the (yet to be constructed) shielding region and the gate channel. Preferably, the first shielding channel can be generated self-aligned with respect to the gate channel. Thereby, the first sub-shielding region is also self-aligned with respect to the gate channel and can be implemented particularly abruptly with a further reduced implantation energy.

[0024] In one embodiment, after constructing the first sub-shielding region and before constructing the second sub-shielding region, a second shielding channel is constructed, which extends into the channel layer in the vertical direction and has a spacing from the gate channel in the lateral direction greater than the spacing between the first shielding channel and the gate channel.

[0025] Preferably, the second shielding channel is implemented self-aligned with respect to the gate channel. Thus, the second shielding channel is also self-aligned with respect to the gate channel and can be fabricated more abruptly and at less cost with a further reduced implantation energy, since the required implantation energy can be reduced.

[0026] As previously mentioned, the second sub-shielding region - or generally this shielding region - is implemented self-aligned with respect to the gate channel. Thus, the nominal spacing between the second sub-shielding region and the gate channel can be reduced compared to the case without self-alignment. This results in an improved shielding effect with respect to field penetration not only to the channel layer but also to the gate channel with its corners / roundings. Additionally, the current distribution in the case of a short circuit is homogenized.

[0027] In one embodiment, the construction of the shielding region includes, in particular by means of implantation and using a mask for self-alignment, constructing the first sub-shielding region and the channel region of the shielding region, and in particular by means of implantation and using a (second) mask for self-alignment, constructing the second sub-shielding region of the shielding region.

[0028] Here, the first sub-shielding region and the channel region of the shielding region are constructed such that the channel layer is doped according to the first sub-shielding region and the channel region is constructed by means of counter-doping. The second sub-shielding region extends in the vertical direction until below the gate channel and is deeper than the first sub-shielding region, and the second sub-shielding region is arranged in the lateral direction at most as close to the gate channel as the first sub-shielding region. That is, the construction of the second sub-shielding region can be carried out in particular as previously described.

[0029] In one embodiment, before constructing the gate channel, the first sub-shielding region and the channel region are constructed, wherein the construction of the gate channel includes removing a part of the channel layer, more precisely, removing a part of the channel layer such that the channel region remains.

[0030] In one embodiment, before constructing the gate channel, the first sub-shielding region is constructed, and after constructing the gate channel, more precisely, in particular by means of inclined implantation, the channel region is constructed above the gate channel.

[0031] It should be understood that for the final field-effect transistor, additional steps may be required, such as the introduction of the gate, the construction of the contact material layer, edge termination, and contact path derivation, etc.; here, common methods according to the current state of micrometer technology and nanometer technology can be adopted.

[0032] In the following, specific variants and combinations of different embodiments and their different advantages will be explained in more detail with reference to the drawings.

[0033] Other advantages and configuration options of the present invention can be derived from the description and the attached drawings.

[0034] The present invention is schematically illustrated in the drawings according to embodiments, and the present invention will be described below with reference to the drawings. Description of the Drawings

[0035] Brief Description of the Drawings

[0036] Figure 1 A field-effect transistor for schematically illustrating the background of the present invention is shown.

[0037] Figure 2a 、 2b Figures 2, 3 and 4 show field-effect transistors in different embodiments.

[0038] Figures 5 to 9 The flow of a method for manufacturing a field-effect transistor in different embodiments is shown. Detailed Description of the Embodiments

[0039] In Figure 1 a field-effect transistor 100 is schematically shown, or generally a semiconductor element, for explaining the present invention, in particular showing the active unit in a larger field-effect transistor. Here, the field-effect transistor is configured as a so-called trench MISFET. Here, a cross-sectional view of the field-effect transistor is shown, where the z-direction is the vertical direction; the field-effect transistor has a relatively large extension scale in the xy-plane (the y-direction extends into the drawing plane here).

[0040] In the following, a field-effect transistor with n-doping as the first type of doping and p-doping as the second type of doping will be described. As mentioned before, the types of doping can also be interchanged.

[0041] According to Figure 1The field effect transistor 100 has a substrate layer and / or a drain layer, and in particular has a substrate layer 115, which has an optional buffer layer 114 (e.g., n+ doped) applied thereon. In addition, the field effect transistor 100 has an n-doped drift layer and / or diffusion layer applied thereon, and in particular has an n-doped drift layer 113 (e.g., as an epitaxial layer) and an optional diffusion layer 111. If the diffusion layer 111 is not provided, instead of the diffusion layer 111, the drift layer 113 extends further upward.

[0042] In addition, the field effect transistor 100 has a channel layer 108 (also referred to as the body region, typically p-doped) and an n-doped source layer 109 (e.g., also n+ doped) applied on the drift layer and / or diffusion layer. The source layer 109 is introduced into the channel layer and / or applied on the channel layer.

[0043] Furthermore, the field effect transistor 100 has a gate channel 105, a so-called trench, which extends in the vertical direction from the source layer 109 into the drift layer and / or diffusion layer 113, 111. Typically, as shown here, the gate channel 105 is configured to have a rounded portion at the corner.

[0044] In addition, the field effect transistor 100 has a p-doped shielding region 110, which extends in the vertical direction into the offset layer and / or diffusion layer 113, 111, is laterally spaced from the gate channel 105, and extends in the vertical direction until below the gate channel 105.

[0045] The shielding region 110 can be formed, in particular, by implantation into the channel layer such that the shown channel region 108 in the channel layer is retained.

[0046] Furthermore, the field effect transistor 100 has a gate, which has a gate electrode 104. The gate electrode 104 is surrounded by a gate dielectric 106 at the bottom of the gate and by a gate dielectric 107 on the side (the thicknesses of 106 and 107 can be different). In addition, an intermediate dielectric 112 is provided.

[0047] For example, the intermediate dielectric 112 is made of SiO2, but it can also be other insulating dielectrics. For example, the gate dielectric 107 at the bottom of the gate channel is made of SiO2, but it can also be other insulating dielectrics. For example, the gate dielectric 106 is made of SiO2, but it can also be other insulating dielectrics, for example, it can also be a high-k dielectric, or it can be composed of a multi-layer system of these same dielectrics or alternative dielectrics (such as Si3N4, Al2O3, etc.).

[0048] In addition, the field effect transistor 100 has a drain contact material layer 103, such as a drain electrode, which is adjacent to or in contact with the substrate layer 115 here. In addition, the field effect transistor 100 has a source contact material layer 102, such as a source electrode, which is adjacent to or in contact with the source layer 109 here. However, the gate electrode 104 is separated from the source contact material layer 102 by an intermediate dielectric 112.

[0049] In the following, the principle of operation of the field effect transistor 100 will be explained. Regions or layers of the same doping type (n or p) that are adjacent to each other or even penetrate are conductively connected to each other. Similarly, in particular, the contact between a metal and a semiconductor can be understood as a low-ohmic ohmic contact, for example, between the source contact metal layer 102 and the source region 109 and the shielding region 110 or between the drain contact metal layer 103 and the substrate layer 115.

[0050] Based on the doping concentrations n, p without additional symbols, n−, p− represent doping concentrations that are significantly lower, for example, by at least a factor of 10, compared to the concentration without additional symbols, and n+ and p+ represent doping concentrations that are significantly higher, for example, by at least a factor of 10, compared to the concentration without additional symbols. In the following explanation of the principle of operation, the source potential is used as the reference potential.

[0051] In the conducting state, the source contact material layer 102 is at the source potential, the gate or gate electrode 104 is at a positive gate potential, and the drain contact material layer 103 is at a small drain potential of a few volts. If the gate potential is less than the so-called threshold voltage Vth, only a small cutoff current flows from the drain to the source, that is, from the drain contact material layer 103 to the source contact material layer 102. If the gate voltage of the gate is increased above Vth, due to the induction effect, so many electrons are attracted to the surface on the gate insulator side of the body region 108 (channel region) that is laterally adjacent to the gate channel 105 that a conducting inversion channel is formed there (here, the charge polarity is inverted with respect to the body region 108).

[0052] Therefore, a low-ohmic current path from the drain contact material layer 103 through the substrate layer 115, the optional buffer layer 114, the drift layer and / or diffusion layer 111, 113, the channel formed on the surface on the gate insulator side of the body region 108, and the source layer 109 to the source contact material layer 102 is opened, and this structural element can conduct a high current density and has a small specific on-resistance Ron*A (where A is the active area of the MISFET). For Figure 1In this operating situation, the boundaries of the space charge regions are drawn by the dashed lines 190, 191. The optional diffusion layer 111 causes an increased conduction capacity and thus contributes to a small on-resistance.

[0053] In the cut-off situation, the gate voltage is less than Vth, and the drain voltage is a positive voltage. As the drain voltage increases, the space charge region of the pn transition section, which receives the cut-off voltage, between the p-doped or p+-doped regions (screening region 110, channel region 108) and the respectively adjacent lower n-doped regions (drift layer and / or diffusion layer 111, 113) extends substantially into the low n-doped region; in the case of an increasing cut-off voltage, it also extends further into the drift layer 113, while the p-doped regions (screening region 110, channel region 108) are not completely depleted. The screening region 110 serves to limit the electric field strength especially at the corners / roundings of the gate channel 105 and also at its bottom, where the rounding is preferably constructed such that the peak of the electric field constructed there enables a defined reliability of the structural element. In addition, this screening region limits the electric field at the pn transition between the body region or channel layer 108 and the drift region (drift layer and / or diffusion layer 111, 113).

[0054] The deeper the screening region 110 extends into the drift region (drift layer and / or diffusion layer 111, 113) in the vertical direction, the higher and more abruptly the screening region is doped, and the smaller the lateral spacing of the screening region from the gate channel 105, the stronger the effect in limiting the electric field strength. However, based on the alignment tolerance between the screening region 110 and the gate channel 105, the nominal spacing of the screening region 110 must not be less than a certain minimum spacing from the gate channel 105 without tolerance, because otherwise, in the case of imperfect alignment, the threshold voltage increases in the on-state and the specific on-resistance Ron*A increases.

[0055] In the short-circuit situation, if a high voltage is applied to the drain contact material layer 103 and a voltage higher than the threshold voltage Vth is applied to the gate, a high current flows through the structural element. For Figure 1 this operating situation in, the boundaries of the space charge region (RLZ) are drawn by the dotted line 192. It can be seen that, compared to the on-state situation, the space charge region extends significantly further into the body region 108 due to the high voltage. This shortens the effective channel length, which, in addition to the common current increase according to the MISFET characteristic curve, is an additional reason for the high current in this operating situation. In addition, the structural element is vulnerable to short-channel effects such as DIBL and premature breakdown (punch-through) in the short-circuit situation.

[0056] The shielding region 110 serves to limit the electric field strength especially at the corners / roundings of the gate channel 105 and also at its bottom. Furthermore, this shielding region limits the electric field at the pn transition between the body region or channel region 108 and the drift region (drift layer and / or diffusion layer 111, 113), and thus helps to counteract the shortening of the effective channel length. The deeper the shielding region 110 extends vertically into the drift region, the higher and more abruptly the shielding region is doped, and the smaller the lateral spacing of the shielding region from the gate channel 105, the stronger the effect in limiting the electric field strength. However, based on the alignment tolerance between the shielding region 110 and the gate channel 105, the nominal spacing of the shielding region 110 must not be lower than a certain minimum spacing from the gate channel 105 without tolerance, because otherwise, in the case of imperfect alignment, the threshold voltage increases and the specific on-resistance increases in the conducting state.

[0057] Now, in Figure 2a , 2b , 3, and 4, field-effect transistors in different embodiments are schematically shown. Here, the same reference numerals are applied to the same or functionally identical elements and components as in Figure 1 . However, the differences shall be explicitly discussed.

[0058] According to Figure 2a , the field-effect transistor 200a has a p-doped shielding region, which includes a first sub-shielding region 116 and a second sub-shielding region 110. Here, the second sub-shielding region 110 roughly corresponds to the shielding region of the field-effect transistor 100 according to Figure 1 , i.e., here additionally there is a first sub-shielding region 116, which is especially p-doped.

[0059] Here, the first sub-shielding region 116 is flatter in the vertical direction than the second sub-shielding region 110, and in the lateral direction (here in the x direction) is at least as close to the gate channel 105 as, preferably even closer than, the second sub-shielding region. Since the first sub-shielding region 116 can be introduced with a lower implantation energy than the second sub-shielding region 110, this first sub-shielding region is more abrupt and thus results in a smaller channel length modulation. The implantation profile of 116 can be locally non-constant, for example, retrograde; the implantation profile of 110 can be locally non-constant, for example, retrograde.

[0060] Here, due to the first sub-shielding region 116, the channel region 108 is narrower in the lateral direction than in the case of the field-effect transistor 100 according to Figure 1 .

[0061] As described above, the first sub-screening region 116 can be implemented self-aligned with respect to the gate channel 105 and can thus be arranged particularly close to the channel that can be generated on the surface on the trench side of the channel layer or in the channel region 108, which again reduces channel length modulation.

[0062] The field-effect transistor 200b according to Figure 2b has a p or p+ implanted region that is compensated to some extent in terms of net doping by masking an n implanted (counter-doped or counter-implanted) region. Thereby, a p body region or channel region (denoted herein as 108b) and a laterally adjacent first screening region 116 are generated by different process guides, but substantially have the same net doping and functionality as in the embodiment according to Figure 2a

[0063] In addition to the field-effect transistor 200a according to Figure 2a , the field-effect transistor 300 according to Figure 3 has a first screening channel 117 that extends into the channel layer in the vertical direction and has a greater spacing from the gate channel 105 in the lateral direction than the spacing between the screening region and the gate channel. In this way, the second sub-screening region 110 can be implemented deeper, and thus, the electric field strength on the rounded portion of the gate channel 105 is reduced, which is advantageous in terms of reliability. In addition, the first sub-screening region 116 can be implemented deeper with a smaller implantation energy, whereby the doping profile of the first sub-screening region is more abrupt and the screening effect for the channel region 108 is more effective.

[0064] In addition to the field-effect transistor 300 according to Figure 3 , the field-effect transistor 400 according to Figure 4 has a second screening channel 118 that extends into the channel layer in the vertical direction and has a greater spacing from the gate channel 105 in the lateral direction than the spacing between the first screening channel 117 and the gate channel. In this way, the second sub-screening region 110 can also be implemented deeper, and thus, the electric field strength on the rounded portion of the gate channel 105 is reduced, which is advantageous in terms of reliability.

[0065] Now, the flow of a method for manufacturing a field-effect transistor in different embodiments is schematically shown in Figures 5 to 9 . The same elements, components, or layers are denoted herein with the same reference numerals as in Figures 1 to 4 .

[0066] In Figure 5 , an embodiment of the manufacturing method is shown, by means of which a field-effect transistor 200a according to, for example, Figure 2a can be manufactured.

[0067] First, in step 500, a substrate layer 115 is provided, which has an optional buffer layer 114 applied thereon, a drift layer 113 (e.g., as an epitaxial layer) applied thereon, an optional diffusion layer 111, a channel layer applied thereon (here, the entire channel layer is again denoted by 108, and later only a part of the entire channel layer is retained as the channel region), and a source layer 109. Specifically, for example, the buffer layer 114 and the drift region (111, 113) can be generated on the substrate layer 115 first by means of epitaxy in a conventional manner. Subsequently, the diffusion layer 111 is doped, for example, by implantation. Subsequently, the implant region or the channel layer 108 and the source layer 109 are implanted.

[0068] In addition, in step 510, a gate channel 105 is constructed, for example, by etching with a mask 512 (e.g., a hard mask, also referred to as the "structurable zero region" hereinafter), such that a structure as shown for step 500 is produced. Here, a mask made of a structurable material can be used for lateral structuring in a conventional manner.

[0069] In step 520, a structurable first material 522 is applied, and thereby the gate channel 105 is also filled.

[0070] In step 530, after back-etching the structurable first material 522 (recess etching) and removing the remaining part from the structurable zero region or the mask 512, a structurable second material 532 is applied.

[0071] In step 540, after back-etching the structurable second material 532 (recess etching), a first sub-shielding region 116 is constructed in a self-aligned manner with respect to the gate channel 105 by means of the remaining parts of the structurable first and second materials, which are referred to here as the first mask 542, more precisely, especially by implantation 544. It should be mentioned here that although the first sub-shielding region 116 already has the desired lateral spacing from the gate channel 105 and the desired vertical depth, it also still (further to the left of the gate channel) extends into a region where the second sub-shielding region is later constructed. Here, therefore, only the final channel region of the channel layer with the desired lateral width remains.

[0072] In step 550, a structurable third material 552 is applied.

[0073] In step 560, after back-etching the structurable third material 552, the remaining portions of the structurable first, second, and third materials are used as a mask, herein referred to as the second mask 562, to construct the second sub-screening region 110 in a self-aligned manner with respect to the gate channel 105, more precisely by implantation 564 in particular. The second sub-screening region 110 extends in the vertical direction until below the gate channel 105 and is deeper than the first sub-screening region 116.

[0074] Next, in step 570, the remaining portions of the structurable first, second, and third materials can be removed and the field-effect transistor can be completed in a conventional manner by additional steps. These steps include, for example, trench degradation, thermal activation of doping, application and structuring of the intermediate dielectric as well as the source contact material layer and the passivation (not shown), back-grinding of the substrate layer 115, and application of the drain contact material layer.

[0075] The structurable zero-th, first, second, and third materials are, for example, silicon dioxide, silicon nitride, polysilicon (doped or undoped), or photosensitive lacquer or a combination of these materials. However, in particular, the zero-th and first materials, the first and second materials, and the second and third materials are each different. The zero-th and second materials, the zero-th and third materials, and the first and third materials can optionally be composed of the same or different materials.

[0076] In Figure 6 an embodiment of the manufacturing method is shown by means of which a field-effect transistor 300 can be manufactured, for example, according to Figure 3 . Here, steps 600 to 700 correspond to steps 500 to 570 according to Figure 5 , but with the following differences. Therefore, the same elements or components as in Figure 5 are denoted by the same reference numerals.

[0077] In step 640, in addition to step 540, before implanting 544 the first sub-screening region 116, a first screening channel 117 is constructed (this applies in particular to each cell of the field-effect transistor). For this purpose, for example, the structurable second material is used as a mask (here the mask 542), such that the first screening channel 117 is self-aligned with respect to the gate channel 105. The implantation of the first sub-screening region 116 into the first screening channel 117 is achieved in a self-aligned manner with respect to the gate channel 105 by means of the structurable second material as a mask (here the mask 542).

[0078] In step 660, the construction or implantation 564 of the second sub-screening region 110 into the first screening channel 117 is achieved in a self-aligned manner with respect to the gate channel 105 by means of the structurable third material as a mask.

[0079] In Figure 7 an embodiment of a manufacturing method is shown, by means of which a field effect transistor 400 can be manufactured, for example, according to Figure 4 . Here, steps 700 to 770 correspond to steps 600 to 670 according to Figure 6 (or most of these steps correspond to steps 500 to 570 according to Figure 5 ), but with the following differences. Therefore, the same elements or components as in Figure 5 or 6 are denoted by the same reference numerals.

[0080] In step 760, in addition to step 660, before implanting the second shielding region 110, a second shielding channel 118 is constructed (this especially applies to each cell of the field effect transistor). For this purpose, a structurable third material is used as a mask (here mask 562), such that the second shielding channel 118 is self-aligned with respect to the gate channel 105. By means of the structurable third material as a mask (here mask 562), the implantation of the second sub-shielding region 110 into the second shielding channel 118 is realized in a self-aligned manner with respect to the gate channel 105.

[0081] In Figure 8 an embodiment of a manufacturing method is shown, by means of which a field effect transistor 200b can be manufactured, for example, according to Figure 2b . Here, steps 800 to 700 correspond to steps 500 to 570 according to Figure 5 , but with the following differences. Therefore, the same elements or components as in Figure 5 are denoted by the same reference numerals.

[0082] In step 800, here, additionally a p or p+ implantation 816 is realized, more precisely, in the regions of the future channel region 108b and the first sub-shielding region 116 (these two regions are not yet distinguishable from each other at this time point). For example, then the source layer 109 is implanted.

[0083] Therefore, in step 810, a masked (by using material 512 as a mask) n implantation (for counter-doping) is realized, which partially compensates for the already existing p doping in the channel layer or at the site where the channel region 108b should be retained and reduces the net doping concentration. Thus, the channel region 108b and the laterally adjacent first sub-shielding region 116 are produced. Here, the gate channel is constructed later.

[0084] In step 820, a structurable material 822 (“spacer concept”) is applied, for example by at least locally conformal deposition, widening the existing mask, and the gate channel 105 is constructed or etched such that the structure shown in step 820 is produced. Thus, the channel region 108b attains its final lateral width.

[0085] In step 830, a new structurable material 832 is applied and thereby also fills the gate channel 105. In step 840, after etching the structurable material from the back, the filled gate channel 105 is exposed. In step 850, an additional structurable material 852 is applied. Here, the material 832 can essentially correspond to the material 522.

[0086] In step 840, unlike in step 540, no implantation is carried out (which has already been done in step 800), instead, material is removed.

[0087] In step 860, after etching the additional structurable material from the back, the unmasked area is exposed and there the second sub-screening region 110 is constructed in a self-aligned manner with respect to the gate channel 105, more precisely by means of implantation 564 (as in step 560). However, the material that remains is used as the mask 562 here.

[0088] In Figure 9 is shown an embodiment of a manufacturing method by means of which a field-effect transistor 200b can be manufactured, for example, according to Figure 2b ; this relates to an alternative according to a variant of Figure 8 . Here, steps 900 to 970 correspond to steps 800 to 870 according to Figure 8 or thus also correspond to steps 500 to 570 according to Figure 5 , but with the following differences. Thus, the same elements or components as in Figure 5 are denoted by the same reference numerals.

[0089] In step 900, supplementing step 500 and as in step 800, a p or p+ implantation is effected, more precisely in the region of the future channel region 108b and the first sub-screening region 116 (these two regions are not yet distinguishable from each other at this point in time). For example, then the source layer 109 is implanted.

[0090] In step 910, as in step 510, the gate channel 105 is constructed, for example by etching with the aid of the mask 512, such that the structure shown for step 910 is produced.

[0091] In step 920, using mask 512, masked n-implantation 926 is achieved by means of tilted implantation and / or tilted, rotated implantation into gate channel 105, thereby partially compensating for the p-doping already present in the channel layer and reducing the net doping concentration. Thereby, channel region 108b and laterally adjacent first sub-screening region 116 are generated.

[0092] Supplementally to the cross-section according to Figure 2b here, for example, implantation into the bottom of gate channel 105 is also achieved additionally, if not prevented by other measures in the process (such as a structurable, masking material).

[0093] Then, steps 930 to 970 correspond to steps 830 to 870.

[0094] In another embodiment, for example, first sub-screening region 116 is omitted and only self-aligned second sub-screening region 110 relative to gate channel 105 is used. The corresponding process steps for generating first sub-screening region 116 can be omitted. Here, the body region can be implemented with a reverse profile.

[0095] In another embodiment, first sub-screening region 116 is omitted and only self-aligned second screening channel 118 and self-aligned second sub-screening region 110 relative to gate channel 105 are used. The corresponding process steps for generating first sub-screening region 116 can be omitted.

[0096] By using self-alignment in the described production method, the sample variation (Exemplarstreuung) between different structural elements is small. This results in increased productivity and / or smaller guaranteed tolerances in production.

[0097] The present invention can be applied not only to structural elements with uniform epitaxial doping, but also in the case of locally variable, for example stepped or gradually varying epitaxial doping and as in the case of the superjunction concept.

[0098] The implantation profile of 116 can be locally non-constant, for example reverse; the implantation profile of 110 can be locally non-constant, for example reverse.

[0099] Furthermore, the described self-alignment for the screening regions can be applied not only to the shown cross-section of a field effect transistor (or MOS / MIS control head), but also in the case of different cross-sections; especially in the case where an additional p-doped screening region is provided below the gate channel, where the additional screening region can be connected to the source potential and can contact gate channel 105.

Claims

1. A method for producing a semiconductor component (200a, 200b, 300, 400), in particular a transistor, comprising the following steps: - providing (500) a substrate layer and / or a drain layer (115, 114), a drift layer and / or a diffusion layer (113, 111) of a first type of doping applied on the substrate layer and / or the drain layer, a channel layer applied on the drift layer and / or the diffusion layer, and a source layer (109) of a first type of doping introduced into the channel layer and / or applied on the channel layer, - constructing (510) a gate channel, the gate channel extending in a vertical direction from the source layer (109) into the drift layer and / or diffusion layer (113, 111), and - using self-alignment, in particular by implantation, forming a shielding region (116, 110) of a second type of doping, which extends in a vertical direction into the drift layer and / or the diffusion layer (113, 111), wherein The shielding region is constructed in such a way that it has a predetermined lateral distance from the gate trench (105), so that a channel region (108, 108b) corresponding to the predetermined lateral distance remains in the channel layer, wherein the shielding region is constructed in such a way that at least a portion of the shielding region extends in a vertical direction to below the gate trench.

2. The method according to claim 1, wherein: The structure of the shielding area includes: - forming (540) a first sub-shielding region (116) of the shielding region, in particular by means of implantation and using a first mask (542) for the self-alignment, wherein a lateral width of the first mask (542) is selected as a function of a predetermined lateral distance of the shielding region from the gate trench (105), - In particular, by means of implantation and using a second mask (562) for the self-alignment, constructing (560) a second sub-shielding region (110) of the shielding region, wherein the second sub-shielding region extends in a vertical direction to below the gate channel and is deeper than the first sub-shielding region (116), and wherein the second sub-shielding region is arranged in a lateral direction at most as close to the gate channel as the first sub-shielding region.

3. The method according to claim 1 or 2, further comprising, before constructing the shielding area: - constructing (640) a first shielding trench extending into the channel layer in a vertical direction and having a spacing from the gate trench in a lateral direction greater than a spacing from the shielding region to the gate trench.

4. The method according to claim 2 and 3, the method further comprising, after constructing the first sub-shielding area and before constructing the second sub-shielding area: - forming a second shielding trench which extends into the channel layer in a vertical direction and is spaced apart from the gate trench in a lateral direction greater than the spacing of the first shielding trench from the gate trench.

5. The method according to claim 1, wherein: The structure of the shielding area includes: - structuring (540) a first sub-shielding region (116) of the shielding region and the channel region, in particular by implantation, such that the channel layer is doped according to the first sub-shielding region and such that the channel region is structured by counter-doping, - In particular by means of implantation and using a mask (562) for the self-alignment, constructing (560) a second sub-shielding region (110) of the shielding region, wherein the second sub-shielding region extends in a vertical direction to below the gate channel and is deeper than the first sub-shielding region (116), and wherein the second sub-shielding region is arranged in a lateral direction at most as close to the gate channel as the first sub-shielding region.

6. The method according to claim 5, wherein: Before constructing the gate channel, the first sub-shielding region (116) and the channel region (108b) are constructed, wherein the construction of the gate channel includes removing a portion of the channel layer so that the channel region remains.

7. The method according to claim 5, wherein: The first shielding sub-region (116) is formed before forming the gate trench, wherein after forming the gate trench, the channel region (108b) is formed above the gate trench, in particular by means of an inclined implantation.

8. The method according to any one of the preceding claims, further comprising: - introducing a gate having a gate electrode into the gate trench such that the gate adjoins the source layer and the channel layer.

9. A semiconductor component (100), in particular a transistor, comprising: - a substrate layer and / or a drain layer (115, 114), - a drift layer and / or a diffusion layer (113, 111) of a first type of doping applied on said substrate layer and / or drain layer, - a channel layer applied on said drift layer and / or diffusion layer, and a source layer (109) of a first type of doping introduced into the channel layer and / or applied onto the channel layer, - a gate channel extending in a vertical direction from the source layer (109) into the drift layer and / or diffusion layer (113, 111), and - a second type doped shielding region, the shielding region extending in the vertical direction into the drift layer and / or the diffusion layer (113, 111), wherein The shielding region is constructed in a self-aligned manner with a predetermined lateral spacing from the gate trench, so that a channel region (108, 108b) corresponding to the predetermined lateral spacing remains in the channel layer, wherein at least a portion of the shielding region extends in a vertical direction to below the gate trench. 10 . The semiconductor component according to claim 9 , produced according to the method according to claim 1 .

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