Semiconductor structure

Abstract

The invention provides a semiconductor structure. The semiconductor structure comprises a substrate, a semiconductor barrier layer and a gate electrode. The semiconductor barrier layer is arranged above the substrate, and the gate electrode is arranged above the semiconductor barrier layer and is provided with a first gate barrier layer and a second gate barrier layer. Wherein the first gate barrier layer is arranged between the semiconductor barrier layer and the second gate barrier layer, the work function of the first gate barrier layer is larger than that of the semiconductor barrier layer, and the work function of the second gate barrier layer is larger than that of the first gate barrier layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, and more particularly to a high electron mobility transistor. Background Art

[0002] In recent years, due to the increasing demand for high-frequency and high-power products, semiconductor power devices made of gallium nitride, taking aluminum gallium nitride / gallium nitride (AlGaN / GaN) as an example, have a wide bandgap and high-speed moving electrons, enabling very fast switching speeds and can operate in high-frequency, high-power, and high-temperature working environments. Therefore, they are widely used in high-power semiconductor structures, especially in radio frequency and power applications. Traditionally, high electron mobility transistors utilize a III-V semiconductor stack to form a heterojunction at their interface. Due to the band bending at the heterojunction, a potential well is formed deep in the bent conduction band, and a two-dimensional electron gas (2DEG) is formed in the potential well.

[0003] Generally speaking, a high electron mobility transistor is a normally-on (D-mode) device, or a depletion mode device, which requires an additional negative bias voltage to turn off the device. Besides being relatively inconvenient to use, it also limits the scope of use of the device. On the other hand, there is currently another type of enhancement-mode high electron mobility transistor proposed. It uses fluorine ion bombardment to damage the lattice structure of the aluminum gallium nitride layer before forming the metal gate, or forms a recess in the aluminum gallium nitride layer by etching, or uses a gate stack structure with a p-type doped gallium nitride layer to achieve a normally-off (E-mode) device that can turn off the two-dimensional electron gas without applying an additional bias voltage.

[0004] However, in currently common E-mode gallium nitride high electron mobility transistor devices, the gate-source drive voltage (Vgs) ranges from 7V to 10V, and there is a situation of gate hard breakdown due to too high gate leakage current, so its operating range can only be limited to between 0V and 6V. On the other hand, in common D-mode gallium nitride high electron mobility transistor devices, the gate leakage is relatively high, even reaching the milliampere level. When operating the above devices, the gate leakage current will also increase during the process of increasing the gate voltage. However, the increase in the gate leakage current may lead to the failure of the device. Therefore, it is necessary to effectively control the gate leakage current of the device. To overcome the above problems, the industry urgently needs an innovative semiconductor structure to improve the problem that the gate leakage current may cause the failure of the device. Summary of the Invention

[0005] The main object of the present invention is to provide an innovative semiconductor structure, which can increase the voltage operating range of the device by increasing the gate breakdown voltage, and can improve the problem of device failure caused by too high gate leakage current in existing high electron mobility transistor devices.

[0006] To achieve the above object, the present invention provides a semiconductor structure, including a substrate, a semiconductor barrier layer, and a gate electrode. The semiconductor barrier layer is disposed above the substrate, and the gate electrode is disposed above the semiconductor barrier layer and has a first gate barrier layer and a second gate barrier layer. Among them, the first gate barrier layer is disposed between the semiconductor barrier layer and the second gate barrier layer, and the work function of the first gate barrier layer is greater than the work function of the semiconductor barrier layer, and the work function of the second gate barrier layer is greater than the work function of the first gate barrier layer.

[0007] In an embodiment of the semiconductor structure of the present invention, the first gate barrier layer is a conductive metal compound, and the work function of the conductive metal compound is not less than 4eV.

[0008] In an embodiment of the semiconductor structure of the present invention, the conductive metal compound is selected from one of the group consisting of titanium nitride, tantalum nitride, and tungsten nitride.

[0009] In an embodiment of the semiconductor structure of the present invention, the second gate barrier layer is a conductive material, and the work function of the conductive material is not less than 5eV.

[0010] In an embodiment of the semiconductor structure of the present invention, the conductive material is selected from one of the group consisting of nickel, platinum, tungsten, and tungsten nitride.

[0011] In an embodiment of the semiconductor structure of the present invention, the semiconductor structure further includes a source electrode and a drain electrode, which are respectively disposed above the semiconductor barrier layer.

[0012] In an embodiment of the semiconductor structure of the present invention, the source electrode and the drain electrode are selected from one of the group consisting of titanium, aluminum, nickel, molybdenum, titanium nitride, gold, or a mixed element of two or more of them.

[0013] In an embodiment of the semiconductor structure of the present invention, the semiconductor barrier layer is a gallium aluminum nitride layer.

[0014] In an embodiment of the semiconductor structure of the present invention, the semiconductor structure further includes a gallium nitride layer, wherein the gallium aluminum nitride layer is disposed above the gallium nitride layer.

[0015] In an embodiment of the semiconductor structure of the present invention, the semiconductor structure further includes a P-type doped gallium nitride layer, wherein the P-type doped gallium nitride layer is disposed between the gallium aluminum nitride layer and the first gate barrier layer, and the work function of the first gate barrier layer is greater than the work function of the P-type doped gallium nitride layer.

[0016] In an embodiment of the semiconductor structure of the present invention, the semiconductor barrier layer under the gate electrode further includes a recess structure, and the first gate barrier layer fills the recess structure.

[0017] In an embodiment of the semiconductor structure of the present invention, a part of the gallium aluminum nitride layer under the gate electrode has fluoride ion doping.

[0018] In an embodiment of the semiconductor structure of the present invention, the gate electrode further includes a low-resistance metal layer disposed above the second gate barrier layer.

[0019] In an embodiment of the semiconductor structure of the present invention, the low-resistance metal layer is selected from one of the group consisting of aluminum, platinum, titanium, nickel, tungsten, copper, palladium, gold, or a mixed element of two or more of them.

[0020] To achieve the above object, the present invention provides a semiconductor structure, including a substrate, a semiconductor barrier layer, an anode electrode, and a cathode electrode. The semiconductor barrier layer is disposed above the substrate, and the anode electrode and a cathode electrode are respectively disposed at two opposite ends above the semiconductor barrier layer, wherein the anode electrode has a first anode barrier layer and a second anode barrier layer, the first anode barrier layer is disposed between the semiconductor barrier layer and the second anode barrier layer, and the work function of the first anode barrier layer is greater than the work function of the semiconductor barrier layer, and the work function of the second anode barrier layer is greater than the work function of the first anode barrier layer.

[0021] In an embodiment of the semiconductor structure of the present invention, the first anode barrier layer is a conductive metal compound, and the work function of the conductive metal compound is not less than 4 eV.

[0022] In an embodiment of the semiconductor structure of the present invention, the conductive metal compound is selected from one of the group consisting of titanium nitride, tantalum nitride, and tungsten nitride.

[0023] In an embodiment of the semiconductor structure of the present invention, the second anode barrier layer is a conductive material, and the work function of the conductive material is not less than 5 eV.

[0024] In an embodiment of the semiconductor structure of the present invention, the conductive material is selected from the group consisting of nickel, platinum, tungsten, and tungsten nitride.

[0025] In an embodiment of the semiconductor structure of the present invention, the semiconductor barrier layer is a gallium aluminum nitride layer, and the semiconductor structure further includes a p-type doped gallium nitride layer disposed between the gallium aluminum nitride layer and the first anode barrier layer, and the work function of the first anode barrier layer is greater than the work function of the p-type doped gallium nitride layer.

[0026] After referring to the accompanying drawings and the embodiments described hereinafter, those skilled in the art can understand the other objects of the present invention, as well as the technical means and embodiments of the present invention. Description of the Drawings

[0027] Figures 1 to 5 Schematic diagram of the manufacturing process steps of a normally-on high electron mobility transistor in an embodiment of the present invention;

[0028] Figure 6 Comparison curve of the gate current and voltage relationships between the normally-on high electron mobility transistor of the present invention and the existing normally-on high electron mobility transistor;

[0029] Figures 7 to 12 Schematic diagram of the manufacturing process steps of a normally-off high electron mobility transistor in an embodiment of the present invention;

[0030] Figure 13 Comparison curve of the gate current and voltage relationships between the normally-off high electron mobility transistor of the present invention and the existing normally-off high electron mobility transistor;

[0031] Figure 14 Schematic diagram of a normally-off high electron mobility transistor with a recessed gate structure in an embodiment of the present invention;

[0032] Figure 15 Schematic diagram of a normally-off high electron mobility transistor with fluoride ion doping in an embodiment of the present invention;

[0033] Figure 16 Schematic diagram of a normally-on Schottky barrier diode in an embodiment of the present invention; and

[0034] Figure 17 Schematic diagram of a normally-off Schottky barrier diode in an embodiment of the present invention.

[0035] Description of the Reference Numerals

[0036] 100 Substrate

[0037] 110 Nucleation layer

[0038] 120 Buffer layer

[0039] 130 Channel layer

[0040] 140 Semiconductor barrier layer

[0041] 142 Concave structure

[0042] 150 Insulating protective layer

[0043] 160 Source electrode

[0044] 170 Drain electrode

[0045] 180 Gate electrode

[0046] 182 First gate barrier layer

[0047] 184 Second gate barrier layer

[0048] 186 Low-resistance metal layer

[0049] 190 p-type doped gallium nitride layer

[0050] 200 Anode electrode

[0051] 202 First anode barrier layer

[0052] 204 Second anode barrier layer

[0053] 210 Cathode electrode

[0054] 220 P-type doped gallium nitride layer. Detailed implementation manners

[0055] The content of the present invention will be explained below through embodiments. The embodiments of the present invention are not used to limit that the present invention must be implemented in any specific environment, application or special manner as described in the embodiments. Therefore, the description of the embodiments is only for the purpose of explaining the present invention, rather than for limiting the present invention. It should be noted that in the following embodiments and drawings, elements not directly related to the present invention have been omitted and not shown, and the dimensional relationships between the elements in the drawings are only for easy understanding and are not used to limit the actual ratio.

[0056] Please refer to Figure 1, which shows a semiconductor structure and a manufacturing method thereof in an embodiment of the present invention, especially a normally-on or depletion-mode high electron mobility transistor and a manufacturing method thereof. Among them, a nucleation layer 110, a buffer layer 120, a channel layer 130 and a semiconductor barrier layer 140 are sequentially formed on a substrate 100. Among them, the material of the substrate 100 may include silicon, sapphire, diamond, gallium nitride, silicon carbide, gallium arsenide, etc. The nucleation layer 110 is located above the substrate 100 and has a thickness of about dozens of nanometers or hundreds of nanometers, which is used to reduce the lattice difference between the substrate 100 and the semiconductor barrier layer 140. The nucleation layer 110 is, for example, a III-V material, including materials such as aluminum nitride, gallium nitride, or aluminum gallium nitride. The buffer layer 120 is located above the nucleation layer 110 and has a thickness of about several micrometers or dozens of micrometers. Its material can be a III-V material, which is also used to reduce the lattice difference between the substrate 100 and the semiconductor barrier layer 140 and reduce lattice defects. In this embodiment, the buffer layer 120 may include a single-layer structure or a multi-layer structure. For example, it may be a multi-layer super lattice multilayer or a single-layer III-V semiconductor material, such as aluminum nitride, gallium nitride, or aluminum gallium nitride.

[0057] The channel layer 130 is formed on the buffer layer 120 and has a first energy gap. The semiconductor barrier layer 140 is formed on the channel layer 130 and has a second energy gap, and the second energy gap is higher than the first energy gap. The lattice constant of the semiconductor barrier layer 140 is smaller than that of the channel layer 130. In this embodiment, the materials of the channel layer 130 and the semiconductor barrier layer 140 include aluminum indium gallium nitride (AlxInyGa(1-x-y)N), where 0≦x<1 and 0≦x + y≦1. In this embodiment, the channel layer 130 may be a gallium nitride layer, and the semiconductor barrier layer 140 may be an aluminum gallium nitride layer or an indium gallium nitride layer. Since the channel layer 130 and the semiconductor barrier layer 140 form spontaneous polarization by themselves, and the piezoelectric polarization between the channel layer 130 and the semiconductor barrier layer 140, a two-dimensional electron gas 2DEG is generated at the heterojunction between the channel layer 130 and the semiconductor barrier layer 140.

[0058] Please refer to Figure 2 , to perform an isolation insulation manufacturing process between the active area and the non-active area of the device. For example, a MESA etching manufacturing process can be implemented or an ion implantation manufacturing process can be performed. In this embodiment, ion implantation of nitrogen, argon, boron, oxygen, arsenic, etc. can be performed to achieve the effect of device isolation. Please refer to Figure 3, an insulating protective layer 150 is then covered on the substrate and defines source and drain regions. This insulating protective layer 150 can be made of materials such as silicon nitride, aluminum nitride, aluminum oxide, silicon dioxide, silicon oxynitride, silicon carbide, etc. Please refer to Figure 4 , source electrode 160 and drain electrode 170 that are in ohmic contact with the semiconductor barrier layer 140 are formed on the source and drain regions above the semiconductor barrier layer 140. Specifically, the source electrode and the drain electrode can be manufactured by a metal evaporation process on the aluminum gallium nitride layer to form an alloy material for ohmic contact at high temperature. The alloy material can be selected from one or a mixture of two or more of the elements consisting of titanium, aluminum, nickel, molybdenum, titanium nitride, and gold. Specifically, the source electrode and the drain electrode can be metal alloy systems such as titanium / aluminum / nickel / gold, titanium / aluminum / titanium / gold, titanium / aluminum / molybdenum / gold, titanium / aluminum / titanium / titanium nitride, etc.

[0059] Please refer to Figure 5 , then a gate electrode region is defined in the insulating protective layer 150 to expose a part of the semiconductor barrier layer 140, and a metal evaporation manufacturing process is performed in this gate electrode region to form a gate electrode 180 above the exposed part of the semiconductor barrier layer 140. To solve the problem in the prior art that the gate hard breakdown occurs in high electron mobility transistor elements due to too high gate leakage current, the present invention discloses an innovative gate structure with a dual barrier layer to suppress the gate leakage current. Specifically, the gate electrode 180 of the present invention has a first gate barrier layer 182 and a second gate barrier layer 184. Among them, the first gate barrier layer 182 is disposed above the exposed part of the semiconductor barrier layer 140, and the second gate barrier layer 184 is disposed above the first gate barrier layer 182. In particular, the work function of the first gate barrier layer 182 is greater than the work function of the semiconductor barrier layer 140, and the work function of the second gate barrier layer 184 is greater than the work function of the first gate barrier layer 182. In a specific embodiment, the first gate barrier layer 182 can be a conductive metal compound or a conductive ceramic, and the work function of the conductive metal compound is not less than 4 eV, but it is not limited thereto. The conductive metal compound is selected from one of the group consisting of titanium nitride, tantalum nitride, and tungsten nitride. The second gate barrier layer 184 can be a conductive substance such as a metal with a higher work function, and the work function of the conductive substance is not less than 5 eV, but it is not limited thereto. The conductive substance is selected from one of the group consisting of nickel, platinum, tungsten, and tungsten nitride. In addition, the gate electrode 180 further includes a low-resistance metal layer 186 disposed above the second gate barrier layer 184. This low-resistance metal layer is selected from one or a mixture of two or more of the elements consisting of aluminum, platinum, titanium, nickel, tungsten, copper, palladium, and gold.

[0060] Please refer to Figure 6, which shows a comparative graph of the gate current - voltage relationship between the normally - on high - electron - mobility transistor (D - mode HEMT) of the present invention and existing D - mode HEMT components. Among them, Figure 6 Curve I in it represents the current - voltage curve of the existing D - mode HEMT component; on the other hand, Curve II represents the current - voltage curve of the D - mode HEMT component of the present invention. Comparing Figure 6 the current - voltage curves I and II in, it can be seen that the gate leakage current of the existing D - mode HEMT component is relatively high, approximately in the range of 1.00E - 02 to 1.00E - 03 amperes. In contrast, the present invention can greatly suppress the gate leakage current by using the work - function difference of the double - layer gate barrier layer, so that the gate leakage current of the D - mode HEMT component of the present invention can be reduced by about 1000 times, reduced to 1.00E - 05 to 1.00E - 07 amperes.

[0061] It should be noted that the above content only takes the normally - on or depletion - type high - electron - mobility transistor as one of the implementation schemes of several embodiments of the present invention. In fact, those skilled in the art can use the technical features of the double - barrier - layer gate structure disclosed in the present invention and expand its application to normally - off high - electron - mobility transistors. Please refer to Figure 1 、 Figure 7 and the foregoing related content. Similar to the fabrication of D - mode HEMT components, when fabricating E - mode HEMT components, a nucleation layer 110, a buffer layer 120, a channel layer 130, and a semiconductor barrier layer 140 are sequentially formed on a substrate 100. The material compositions and manufacturing processes of the substrate 100, nucleation layer 110, buffer layer 120, channel layer 130, and semiconductor barrier layer 140 in this embodiment can all refer to the foregoing disclosed content and will not be elaborated here. Then, a p - type doped semiconductor layer is formed on the semiconductor barrier layer 140. In this embodiment, this p - type doped semiconductor layer is a p - type doped gallium nitride layer 190. Further, doping is carried out on the gallium nitride layer with p - type dopants, such as magnesium, calcium, zinc, beryllium, carbon, or a combination of the foregoing. In a specific embodiment, the thickness range of the p - type doped gallium nitride layer 190 is between about 1 nm and 100 nm.

[0062] Please refer to Figure 8 , for the isolation insulation manufacturing process between the active area and the non - active area of the component. Similar to the foregoing embodiment, in this embodiment, the ion implantation manufacturing process is used, and element isolation treatment is carried out by implanting nitrogen, argon, boron, oxygen, arsenic and other ions. Then, please refer to Figure 9 , for the etching manufacturing process to define the p - type doped gallium nitride layer 190 of the gate structure. Please refer to Figure 10, similar to the foregoing embodiments, an insulating protective layer 150 is formed above the semiconductor barrier layer 140, and source and drain regions are defined. In this embodiment, the material composition and manufacturing process of the insulating protective layer 150 can refer to the foregoing disclosure, which will not be elaborated here. Next, please refer to Figure 11 , and then a source electrode 160 and a drain electrode 170 that are ohmic - contacted with the semiconductor barrier layer 140 are formed on the source and drain regions above the semiconductor barrier layer 140. The material composition and manufacturing process for specifically forming the source electrode and the drain electrode can refer to the foregoing disclosure, which will not be elaborated here.

[0063] Please refer to Figure 12 , then a gate - electrode region is defined in the insulating protective layer 150 to expose a part of the p - type doped gallium nitride layer 190, and a metal evaporation manufacturing process is performed in this gate - electrode region to form a gate electrode 180 above the exposed part of the p - type doped gallium nitride layer 190. To solve the problem in the prior art that the gate hard breakdown occurs in high - electron - mobility transistor devices due to too high gate leakage current, this embodiment also applies an innovative gate structure with a dual - barrier layer to suppress the gate leakage current. Specifically, the same as the foregoing embodiments, the gate electrode 180 of the present invention has a first gate barrier layer 182 and a second gate barrier layer 184. Among them, the first gate barrier layer 182 is disposed above the exposed part of the p - type doped gallium nitride layer 190, and the second gate barrier layer 184 is disposed above the first gate barrier layer 182. In particular, the work function of the first gate barrier layer 182 is greater than the work function of the p - type doped gallium nitride layer 190, and the work function of the second gate barrier layer 184 is greater than the work function of the first gate barrier layer 182. In a specific embodiment, the first gate barrier layer 182 can be a conductive metal compound or a conductive ceramic, and the work function of the conductive metal compound is not less than 4 eV, but is not limited thereto. The conductive metal compound is selected from the group consisting of titanium nitride, tantalum nitride, and tungsten nitride. The second gate barrier layer 184 can be a conductive material such as a metal with a higher work function, and the work function of the conductive material is not less than 5 eV, but is not limited thereto. The conductive material is selected from the group consisting of nickel, platinum, tungsten, and tungsten nitride. In addition, the gate electrode 180 further includes a low - resistance metal layer 186 disposed above the second gate barrier layer 184. This low - resistance metal layer is selected from the group consisting of aluminum, platinum, titanium, nickel, tungsten, copper, palladium, gold, or a mixture of two or more of them.

[0064] Please refer to Figure 13 , which shows a comparison curve graph of the gate current and voltage relationships of both the p - type doped gallium nitride enhancement - mode high - electron - mobility transistor (pGaN E - mode HEMT) of the present invention and the existing pGaN E - mode HEMT device. Among them, Figure 13The curve formed by connecting each square marked point represents the current-voltage curve I of the existing pGaN E-mode HEMT device; on the other hand, Figure 13 the curve formed by connecting each diamond marked point represents the current-voltage curve II of the pGaN E-mode HEMT device of the present invention. Comparing Figure 13 the current-voltage curves I and II, it can be seen that in the existing pGaN E-mode HEMT device, when the gate voltage is between 7V and 10V, gate hard breakdown occurs due to too high gate leakage current, so its operating range is only limited to between 0V and 6V. In contrast, the present invention uses the work function difference of different materials in the double barrier layer of the gate structure to suppress the gate leakage current, so that the gate voltage of the pGaN E-mode HEMT device of the present invention can be increased from 7V to about 19V, greatly increasing the operable voltage range of the high electron mobility transistor device.

[0065] It should be noted that the above is only one embodiment of the normally-off high electron mobility transistor of the present invention. The technical features of the double barrier layer gate structure disclosed in the present invention can also be applied to other normally-off HEMT devices. Please refer to Figure 14 , which shows the recess gate structure of a normally-off HEMT device. Specifically, this gate electrode 180 is also a double barrier layer gate structure having a first gate barrier layer 182 and a second gate barrier layer 184. However, different from the foregoing embodiment, there is no p-type doped gallium nitride layer 190 under the gate electrode 180. Instead, the semiconductor barrier layer 140 under the gate electrode 180 has a recess structure 142, and the first gate barrier layer 182 fills the recess structure 142 to improve the gate's control ability over the electron channel. In this embodiment, the double barrier layer gate with a recess structure can also utilize the work function difference of different materials in the double barrier layer of the gate structure to achieve the effect of suppressing the gate leakage current.

[0066] On the other hand, please refer to Figure 15 , which shows another normally-off HEMT device applying the present invention. Specifically, similar to the embodiment shown above, Figure 15 in the HEMT device of the embodiment shown, the gate electrode 180 is also a double barrier layer gate structure having a first gate barrier layer 182 and a second gate barrier layer 184, and there is fluoride ion doping in a part of the semiconductor barrier layer (i.e., aluminum gallium nitride layer) 140 under the gate electrode 180 to change the energy band bending between the semiconductor barrier layer and the channel layer, thereby affecting and adjusting the gate voltage required to turn on the electron channel, and using the work function difference of different materials in the double barrier layer of the gate to achieve the effect of suppressing the gate leakage current as desired by the present invention.

[0067] The technical feature of the present invention with a multi-stage barrier layer to suppress leakage current can also be widely applied to Schottky Barrier Diode (SBD) devices, as described below. Please refer to Figure 16 , which shows one embodiment of the D-mode SBD device applying the dual-barrier layer structure of the present invention. Its structure has a substrate 100, a nucleation layer 110, a buffer layer 120, a channel layer 130, and a semiconductor barrier layer 140 from bottom to top. The material compositions and manufacturing processes of the substrate 100, nucleation layer 110, buffer layer 120, channel layer 130, and semiconductor barrier layer 140 in this embodiment can refer to the foregoing disclosure content and will not be elaborated here. Taking the gallium aluminum nitride layer as the semiconductor barrier layer 140 as an example, an anode electrode 200 and a cathode electrode 210 are respectively disposed at two opposite ends above the semiconductor barrier layer 140. The anode electrode 200 has a first anode barrier layer 202 and a second anode barrier layer 204. Among them, the first anode barrier layer 202 is disposed between the semiconductor barrier layer 140 and the second anode barrier layer 204, and the work function of the first anode barrier layer 202 is greater than the work function of the semiconductor barrier layer 140, and the work function of the second anode barrier layer 204 is greater than the work function of the first anode barrier layer 202. In a specific embodiment, the first anode barrier layer 202 is a conductive metal compound, and the work function of the conductive metal compound is not less than 4 eV. The conductive metal compound is selected from one of the group consisting of titanium nitride, tantalum nitride, and tungsten nitride. In addition, the second anode barrier layer 204 is a conductive material, and the work function of the conductive material is not less than 5 eV. The conductive material is selected from one of the group consisting of nickel, platinum, tungsten, and tungsten nitride. The material of the cathode electrode 210 can be selected from one of the group consisting of titanium, aluminum, nickel, molybdenum, titanium nitride, and gold, or a mixed element of two or more of them.

[0068] Please refer to Figure 17 , which shows one embodiment of the E-mode SBD device applying the dual-barrier layer structure of the present invention. This embodiment is Figure 16 substantially similar. This E-mode SBD device further includes a P-type doped gallium nitride layer 220 disposed between the semiconductor barrier layer 140 (i.e., the gallium aluminum nitride layer) and the first anode barrier layer 202, and the work function of the first anode barrier layer 202 is greater than the work function of the P-type doped gallium nitride layer 220.

[0069] The above embodiments are only used to illustrate the embodiments of the present invention and to explain the technical features of the present invention, and are not used to limit the protection scope of the present invention. Any change or equivalent arrangement that can be easily completed by any person skilled in the art belongs to the scope claimed by the present invention. The scope of the protection of the present invention shall be subject to the claims.

Claims

1. A semiconductor structure comprising: a substrate; a semiconductor barrier layer disposed above the substrate; and a gate electrode disposed above the semiconductor barrier layer, having a first gate barrier layer and a second gate barrier layer, in, The first gate barrier layer is disposed between the semiconductor barrier layer and the second gate barrier layer, and the work function of the first gate barrier layer is greater than the work function of the semiconductor barrier layer, and the work function of the second gate barrier layer is greater than the work function of the first gate barrier layer. 2 . The semiconductor structure as claimed in claim 1 , wherein the first gate barrier layer is a conductive metal compound, and a work function of the conductive metal compound is not less than 4 eV.

3. The semiconductor structure of claim 2, wherein the conductive metal compound is selected from the group consisting of titanium nitride, tantalum nitride, and tungsten nitride. 4 . The semiconductor structure as claimed in claim 2 , wherein the second gate barrier layer is a conductive material, and a work function of the conductive material is not less than 5 eV. 5 . The semiconductor structure as claimed in claim 4 , wherein the conductive material is selected from the group consisting of nickel, platinum, tungsten, and tungsten nitride. 6 . The semiconductor structure as claimed in claim 1 , further comprising a source electrode and a drain electrode, respectively disposed on the semiconductor barrier layer. 7 . The semiconductor structure as claimed in claim 6 , wherein the source electrode and the drain electrode are selected from one of the group consisting of titanium, aluminum, nickel, molybdenum, titanium nitride, and gold, or a mixture of two or more thereof.

8. The semiconductor structure as claimed in claim 1, wherein the semiconductor barrier layer is an aluminum gallium nitride layer. 9 . The semiconductor structure of claim 8 , further comprising a gallium nitride layer, wherein the aluminum gallium nitride layer is disposed above the gallium nitride layer.

10. The semiconductor structure of claim 8, further comprising a P-type doped gallium nitride layer, wherein the P-type doped gallium nitride layer is disposed between the aluminum gallium nitride layer and the first gate barrier layer, and a work function of the first gate barrier layer is greater than a work function of the P-type doped gallium nitride layer. 11 . The semiconductor structure as claimed in claim 1 , wherein the semiconductor barrier layer below the gate electrode further comprises a recessed structure, and the first gate barrier layer is filled into the recessed structure. 12 . The semiconductor structure as claimed in claim 8 , wherein a portion of the aluminum gallium nitride layer below the gate electrode is doped with fluorine ions. 13 . The semiconductor structure as claimed in claim 1 , wherein the gate electrode further comprises a low resistance metal layer disposed above the second gate barrier layer.

14. The semiconductor structure as claimed in claim 13, wherein the low resistance metal layer is selected from the group consisting of aluminum, platinum, titanium, nickel, tungsten, copper, palladium, gold or a mixture of two or more thereof.

15. A semiconductor structure comprising: a substrate; a semiconductor barrier layer disposed above the substrate; and An anode electrode and a cathode electrode are respectively disposed at two opposite ends above the semiconductor barrier layer, wherein the anode electrode has a first anode barrier layer and a second anode barrier layer, in, The first anode barrier layer is disposed between the semiconductor barrier layer and the second anode barrier layer, and the work function of the first anode barrier layer is greater than the work function of the semiconductor barrier layer, and the work function of the second anode barrier layer is greater than the work function of the first anode barrier layer. 16 . The semiconductor structure as claimed in claim 15 , wherein the first anode barrier layer is a conductive metal compound, and a work function of the conductive metal compound is not less than 4 eV.

17. The semiconductor structure of claim 16, wherein the conductive metal compound is selected from the group consisting of titanium nitride, tantalum nitride, and tungsten nitride. 18 . The semiconductor structure as claimed in claim 16 , wherein the second anode barrier layer is a conductive material, and a work function of the conductive material is not less than 5 eV.

19. The semiconductor structure of claim 18, wherein the conductive material is selected from the group consisting of nickel, platinum, tungsten, and tungsten nitride.

20. The semiconductor structure of claim 18, wherein the semiconductor barrier layer is an aluminum gallium nitride layer, and the semiconductor structure further comprises a P-type doped gallium nitride layer disposed between the aluminum gallium nitride layer and the first anode barrier layer, and a work function of the first anode barrier layer is greater than a work function of the P-type doped gallium nitride layer.

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