A power MOS device and its fabrication method

Abstract

This application discloses a power MOS device and its fabrication method, relating to the field of semiconductor technology. The power MOS device includes: a drift layer; a first substrate layer and a second substrate layer using highly thermally conductive materials, respectively disposed on opposite sides of the drift layer; a drain layer disposed on the back side of the drift layer; a first channel layer and a second channel layer, respectively disposed on the front sides of the first substrate layer and the second substrate layer; a P-type well disposed between the first channel layer and the second channel layer, wherein an N-type doped region is formed inside the P-type well, and a P-type doped region is formed inside the N-type doped region; a gate structure disposed on the front side of the first channel layer and the second channel layer; a dielectric layer disposed on the front side of the gate structure and covering the gate structure; a connection via provided in the dielectric layer; and a source layer disposed on the front side of the dielectric layer and contacting the N-type doped region and the P-type doped region through the connection via. This application effectively improves the heat dissipation capability of the power MOS device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a power MOS device and its fabrication method. Background Technology

[0002] In modern power electronics, power MOS (Metal-Oxide-Semiconductor) devices are widely used due to their high efficiency, fast switching speed, and ease of driving. These characteristics make power MOS devices an indispensable part of applications ranging from consumer electronics to industrial applications. However, with technological advancements and changing market demands, the need for higher power density and smaller size is constantly growing, posing new challenges to traditional power MOS structures.

[0003] One of the main problems focuses on thermal management. Conventional power MOSFET structures struggle to dissipate heat quickly during high-power operation, causing device temperatures to rise. This not only affects performance but also threatens the reliability and lifespan of the equipment. Summary of the Invention

[0004] The main objective of this application is to provide a power MOS device and its fabrication method, which aims to effectively improve the heat dissipation capability of the power MOS device.

[0005] To achieve the above objectives, embodiments of this application provide a power MOS device, comprising:

[0006] Drift layer;

[0007] A first substrate layer and a second substrate layer are respectively disposed on both sides of the drift layer, wherein the first substrate layer and / or the second substrate layer are made of a high thermal conductivity material;

[0008] A drain layer is disposed on the back side of the drift layer;

[0009] The first trench layer and the second trench layer are respectively disposed on the front side of the first substrate layer and the second substrate layer;

[0010] A P-type well is disposed between the first channel layer and the second channel layer. An N-type doped region is formed inside the P-type well, and a P-type doped region is formed inside the N-type doped region.

[0011] A gate structure is disposed on the front side of the first channel layer and the second channel layer;

[0012] A dielectric layer is disposed on the front side of the gate structure and covers the gate structure; the dielectric layer is provided with connection holes;

[0013] The source layer is disposed on the front side of the dielectric layer and contacts the N-type doped region and the P-type doped region through the connection hole.

[0014] In one embodiment, the material of the first substrate layer and / or the second substrate layer includes diamond.

[0015] In one embodiment, the power MOS device further includes: a gate dielectric disposed between the gate structure and the channel layer, wherein the channel layer includes a first channel layer and / or a second channel layer.

[0016] In one embodiment, the thickness of the drift layer is 10–15 μm;

[0017] And / or, the thickness of the first trench layer and the second trench layer is 3 to 7 μm;

[0018] And / or, the thickness of the gate structure is 0.1–0.5 μm;

[0019] And / or, the thickness of the dielectric layer is 0.4–0.8 μm;

[0020] And / or, the thickness of the source layer is 1–3 μm;

[0021] And / or, the thickness of the drain layer is 1 to 3 μm.

[0022] In one embodiment, the material of the drift layer includes at least one of N-type silicon carbide, N-type gallium nitride, N-type gallium arsenide, N-type gallium oxide, N-type aluminum gallium nitride, and N-type aluminum nitride;

[0023] And / or, the material of the gate structure includes at least one of polycrystalline silicon, titanium nitride, tantalum nitride, tungsten, and cobalt;

[0024] And / or, the material of the source layer includes at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium and cobalt;

[0025] And / or, the material of the drain layer includes at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium and cobalt.

[0026] To achieve the above objectives, this application provides a method for fabricating a power MOS device, which includes the following steps:

[0027] The substrate layer is etched to form trenches, wherein the substrate layer is made of a material with high thermal conductivity;

[0028] A drift layer is prepared within the trench;

[0029] A channel layer is fabricated on the front side of the substrate layer and the drift layer;

[0030] A portion of the channel layer is P-type doped to obtain a P-type well.

[0031] A portion of the P-type well is N-type doped to obtain an N-type doped region.

[0032] A portion of the N-type doped region is p-type doped to obtain a p-type doped region.

[0033] A gate structure and a dielectric layer are sequentially fabricated on the front side of the channel layer, wherein the dielectric layer covers the gate structure;

[0034] The dielectric layer is etched to obtain the connection hole;

[0035] A source layer is prepared, wherein the source layer is in contact with the N-type doped region and the P-type doped region through the connecting hole;

[0036] Remove the substrate layer located on the back side of the drift layer to expose the drift layer;

[0037] A drain layer is fabricated on the back side of the drift layer to obtain a power MOS device.

[0038] In one embodiment, the step of P-type doping a portion of the channel layer to obtain a P-type well includes:

[0039] A first oxide layer is prepared on the front side of the channel layer;

[0040] A first photoresist pattern is defined on the front side of the first oxide layer;

[0041] The first oxide layer is etched based on the first photoresist pattern to form a P-type well injection window;

[0042] The channel layer exposed to the P-type well implantation window is P-type doped to obtain the P-type well.

[0043] In one embodiment, prior to the step of N-type doping a portion of the P-type well, the method further includes:

[0044] A second oxide layer of a first thickness is prepared on the front side of the first oxide layer;

[0045] The second oxide layer of a first thickness is etched to form sidewalls located on both sides of the P-type trap injection window.

[0046] In one embodiment, the step of sequentially fabricating a gate structure and a dielectric layer on the front side of the channel layer includes:

[0047] A gate layer is fabricated on the front side of the channel layer;

[0048] The gate layer is etched to obtain the gate structure;

[0049] The dielectric layer is prepared on the front side of the gate structure.

[0050] In one embodiment, the p-type doping concentration of a portion of the channel layer is 1e17 to 5e17 cm⁻¹. -3 ;

[0051] And / or, the N-type doping concentration of the portion of the P-type well is 1e18 to 1e19 cm⁻¹. -3 ;

[0052] And / or, the doping concentration for P-type doping of a portion of the N-type doped region is 1e18 to 1e19 cm⁻¹. -3 .

[0053] This application provides a power MOS device, comprising: a drift layer; a first substrate layer and a second substrate layer, respectively disposed on opposite sides of the drift layer, wherein the first substrate layer and / or the second substrate layer are made of a high thermal conductivity material; a drain layer, disposed on the back side of the drift layer; a first channel layer and a second channel layer, respectively disposed on the front side of the first substrate layer and the second substrate layer; a P-type well, disposed between the first channel layer and the second channel layer, wherein an N-type doped region is formed inside the P-type well, and a P-type doped region is formed inside the N-type doped region; a gate structure, disposed on the front side of the first channel layer and the second channel layer; a dielectric layer, disposed on the front side of the gate structure and covering the gate structure; a connection via provided in the dielectric layer; and a source layer, disposed on the front side of the dielectric layer and contacting the N-type doped region and the P-type doped region through the connection via. In power MOS devices, although the JFET (Junction Field-Effect Transistor) region is not the primary current path, its inherent on-resistance still leads to heat accumulation, thus affecting the overall thermal performance of the device. To effectively address this issue, embodiments of this application incorporate a first substrate layer and a second substrate layer made of highly thermally conductive materials in the JFET region of the power MOS device. This allows for rapid heat dissipation during device operation, significantly reducing thermal stress caused by localized overheating and effectively lowering the device's operating temperature. Through optimized thermal management, the long-term reliability of the device is significantly improved, providing strong assurance for performance stability under high-power operation. Attached Figure Description

[0054] Figure 1This is a schematic diagram of the power MOS device involved in the embodiments of this application;

[0055] Figure 2 This is a flowchart illustrating the fabrication method of the power MOS device involved in the embodiments of this application;

[0056] Figure 3 The process flow of the power MOS device fabrication method involved in the embodiments of this application is as follows. Figure 1 ;

[0057] Figure 4 The process flow of the power MOS device fabrication method involved in the embodiments of this application is as follows. Figure 2 ;

[0058] Figure 5 The process flow of the power MOS device fabrication method involved in the embodiments of this application is as follows. Figure 3 ;

[0059] Figure 6 The process flow of the power MOS device fabrication method involved in the embodiments of this application is as follows. Figure 4 ;

[0060] Figure 7 The process flow of the power MOS device fabrication method involved in the embodiments of this application is as follows. Figure 5 ;

[0061] Figure 8 The process flow of the power MOS device fabrication method involved in the embodiments of this application is as follows. Figure 6 ;

[0062] Figure 9 The process flow of the power MOS device fabrication method involved in the embodiments of this application is as follows. Figure 7 ;

[0063] Figure 10 The process flow of the power MOS device fabrication method involved in the embodiments of this application is as follows. Figure 8 ;

[0064] Figure 11 The process flow of the power MOS device fabrication method involved in the embodiments of this application is as follows. Figure 9 ;

[0065] Figure 12 The process flow of the power MOS device fabrication method involved in the embodiments of this application is as follows. Figure 10 ;

[0066] Figure 13 The process flow of the power MOS device fabrication method involved in the embodiments of this application is as follows. Figure 10 one;

[0067] Figure 14 The process flow of the power MOS device fabrication method involved in the embodiments of this application is as follows. Figure 10 two;

[0068] Figure 15 The process flow of the power MOS device fabrication method involved in the embodiments of this application is as follows. Figure 10 three.

[0069] Explanation of reference numerals in the attached figures:

[0070] 110. Drift layer; 120. Substrate layer;

[0071] 121. First substrate layer; 122. Second substrate layer; 123. Trench;

[0072] 130. Drain layer; 140. Channel layer; 141. First channel layer; 142. Second channel layer;

[0073] 143. First oxide layer; 144. First photoresist pattern; 145. Sidewall;

[0074] 151. P-type well; 152. N-type doped region; 153. P-type doped region;

[0075] 160. Gate structure; 161. Gate dielectric;

[0076] 170, dielectric layer; 171, connection hole; 180, source layer.

[0077] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0078] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments whose manufacturers are not specified are all conventional products that can be purchased commercially.

[0079] The following detailed description, with appropriate reference to the accompanying drawings, discloses embodiments of the power MOS device and its fabrication method of this application. However, unnecessary detailed descriptions may be omitted. For example, detailed descriptions of well-known matters and repetitive descriptions of practically identical structures may be omitted. This is to avoid unnecessarily lengthy descriptions and to facilitate understanding by those skilled in the art. Furthermore, the accompanying drawings and the following description are provided for the purpose of enabling those skilled in the art to fully understand this application and are not intended to limit the subject matter of the claims.

[0080] The "range" disclosed in this application is defined by a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, which define the boundaries of a particular range. Ranges defined in this way can include or exclude endpoints and can be arbitrarily combined; that is, any lower limit can be combined with any upper limit to form a range. For example, if ranges of 60–120 and 80–110 are listed for a specific parameter, it is understood that ranges of 60–110 and 80–120 are also expected. Furthermore, if minimum range values ​​of 1 and 2 are listed, and if maximum range values ​​of 3, 4, and 5 are listed, then the following ranges are all expected: 1–3, 1–4, 1–5, 2–3, 2–4, and 2–5. In this application, unless otherwise stated, the numerical range "a–b" represents a shortened representation of any combination of real numbers between a and b, where a and b are real numbers. For example, the numerical range "0~5" indicates that all real numbers between "0~5" have been listed in this article; "0~5" is simply a shortened representation of these numerical combinations. Furthermore, when a parameter is stated as an integer ≥2, it is equivalent to disclosing that the parameter is, for example, an integer such as 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0081] Unless otherwise specified, all embodiments and optional embodiments of this application can be combined to form new technical solutions.

[0082] Unless otherwise specified, all steps of this application may be performed sequentially or randomly, preferably sequentially. For example, if the method includes steps (a) and (b), it means that the method may include steps (a) and (b) performed sequentially, or it may include steps (b) and (a) performed sequentially. For example, if the method may also include step (c), it means that step (c) may be added to the method in any order. For example, the method may include steps (a), (b), and (c), or it may include steps (a), (c), and (b), or it may include steps (c), (a), and (b), etc.

[0083] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the technical solution of this application is further described below in conjunction with the accompanying drawings and embodiments. However, this application is not limited to the listed embodiments, but should also include any other well-known modifications within the scope of the claims made in this application.

[0084] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0085] In conventional technologies, power MOSFETs struggle to dissipate internal heat quickly during high-power operation, leading to a significant temperature rise. This not only impacts device performance but also threatens reliability and lifespan. Furthermore, the structure of traditional power MOSFETs is limited by their breakdown voltage, restricting their application in high-voltage scenarios. Simultaneously, due to their weak heat dissipation capabilities, performance often degrades as device dimensions shrink to the micro-nano scale due to heat accumulation.

[0086] This application provides a power MOS device. By setting a first substrate layer and a second substrate layer made of a high thermal conductivity material in the JFET region of the power MOS device, the heat generated during device operation can be rapidly dissipated, significantly reducing thermal stress caused by local overheating, thereby effectively lowering the device's operating temperature. Through optimized thermal management, the long-term reliability of the device is significantly improved, providing a strong guarantee for performance stability under high power operation.

[0087] The first embodiment of this application provides a power MOS device, as shown in the reference. Figure 1 ,include:

[0088] Drift layer 110.

[0089] In one embodiment, the drift layer 110 is a critical region in the power MOS device used to withstand high voltages, and is typically composed of a lightly doped semiconductor material. The main function of the drift layer 110 is to withstand the high voltage across the device. By controlling the doping concentration and thickness of the drift layer 110, the breakdown voltage (BV) of the device can be adjusted. A lightly doped drift layer 110 can increase the device's breakdown voltage capability, but it also increases the on-resistance. When the device is turned on, the drift layer 110 is one of the main channels for current to flow from the drain to the source. Its resistance characteristics directly affect the device's conduction losses.

[0090] The first substrate layer 121 and the second substrate layer 122 are respectively disposed on both sides of the drift layer 110, wherein the material of the first substrate layer 121 and / or the second substrate layer 122 is a high thermal conductivity material.

[0091] In one embodiment, the substrate layer (including the first substrate layer 121 and the second substrate layer 122) is the basic structure of the device, typically composed of highly doped semiconductor materials (such as silicon). It provides physical support for the device, ensuring its stability during manufacturing and use; simultaneously, it provides good electrical isolation, preventing leakage and parasitic effects. In this embodiment, by placing the substrate layer on both sides of the drift layer 110 of the main current channel and using a highly thermally conductive material, the heat generated during device operation can be rapidly dissipated, significantly reducing thermal stress caused by localized overheating and effectively lowering the device's operating temperature, thus optimizing device thermal management.

[0092] Drain layer 130 is disposed on the back side of drift layer 110.

[0093] In one embodiment, the drain layer 130 is the negative electrode region of the power MOS device, typically made of highly doped semiconductor material. Its main function is to collect the current transferred from the drift layer 110 and lead it to the external circuit. The drain layer 130 is typically connected to the drift layer 110, and together they withstand the high voltage across the device.

[0094] Optionally, the front and back sides mentioned in the embodiments of this application are two opposite directions, used to indicate the physical orientation of the device and the relative position of the functional layers.

[0095] Optionally, the front side can be the surface corresponding to the first direction of the MOS device, while the back side can be the opposite of the front side, that is, the surface away from the first direction.

[0096] Alternatively, the front side can be the surface that is first processed during the manufacturing process of the device, while the back side can be the surface opposite to the front side.

[0097] The first channel layer 141 and the second channel layer 142 are respectively disposed on the front side of the first substrate layer 121 and the second substrate layer 122.

[0098] In one embodiment, the channel layer (including a first channel layer 141 and a second channel layer 142) is a thin layer region in a MOS device used for conducting current, typically located below the gate layer. In an N-channel MOS device, the channel layer is formed by an inversion layer (i.e., an N-type conductive channel) of a P-type semiconductor material under the action of a gate voltage, thereby allowing current to flow from the source to the drain. In a P-channel MOS device, the channel layer is formed by an inversion layer (i.e., a P-type conductive channel) of an N-type semiconductor material under the action of a gate voltage.

[0099] A P-type well 151 is disposed between the first channel layer 141 and the second channel layer 142. An N-type doped region 152 is formed inside the P-type well 151, and a P-type doped region 153 is formed inside the N-type doped region 152.

[0100] In one embodiment, in an N-channel MOS device, a P-type well 151 is used to isolate different device cells and prevent parasitic effects. It provides a substrate for the N-type source and drain. Simultaneously, under the influence of the gate voltage, an inversion layer, i.e., an N-type conductive channel, forms on the surface of the P-type well 151. The highly doped N-type regions formed inside the P-type well 151 through diffusion or ion implantation processes can form PN junctions with the P-type well 151. When the gate voltage is sufficiently high, the inversion layer on the surface of the P-type well 151 connects these N-type doped regions 152, forming a conductive channel. The P-type doped regions 153 formed inside the N-type doped regions 152 can form a body diode junction with the N-type substrate. When the power MOS device is subjected to reverse voltage or the current needs to flow in reverse, the body diode can conduct, acting as a freewheeling current and protecting the power MOS device from damage by reverse voltage and current.

[0101] A gate structure 160 is disposed on the front side of the first channel layer 141 and the second channel layer 142.

[0102] In one embodiment, the gate structure 160 is the core control component of the power MOS device, capable of controlling the device's on and off states by applying a voltage. For example, when the gate voltage reaches a threshold voltage, a conductive channel is formed on the semiconductor surface beneath the gate, allowing current to flow from the source to the drain. The change in gate voltage determines the device's switching speed and dynamic characteristics.

[0103] For example, the gate structure 160 includes a first gate structure 160 (not shown in the figure) and a second gate structure 160 (not shown in the figure), which are respectively disposed on the front side of the first channel layer 141 and the second channel layer 142.

[0104] A dielectric layer 170 is disposed on the front side of the gate structure 160 and covers the gate structure 160; the dielectric layer 170 is provided with a connection hole 171.

[0105] In one embodiment, the primary function of the dielectric layer 170 is to isolate the gate structure 160, prevent current leakage, and ensure that the gate voltage can effectively regulate the formation of the channel. A high-quality dielectric layer 170 can withstand high voltages, preventing breakdown and thus improving the device's withstand voltage capability.

[0106] Optionally, the dielectric layer 170 is provided with a connection hole 171, and the N-type doped region 152 and the P-type doped region 153 are exposed through the connection hole 171.

[0107] For example, the dielectric layer 170 includes a first dielectric layer 170 (not shown in the figure) and a second dielectric layer 170 (not shown in the figure), which are respectively disposed on the front side of the first gate structure 160 and the second gate structure 160, and respectively cover the first gate structure 160 and the second gate structure 160.

[0108] The source layer 180 is disposed on the front side of the dielectric layer 170 and contacts the N-type doped region 152 and the P-type doped region 153 through the connection hole 171.

[0109] In one embodiment, the source layer 180 is the current-out terminal of the power MOS device, typically composed of highly doped N-type or P-type semiconductor material. In an N-channel MOS device, the source serves as the electron injection terminal; in a P-channel MOS device, the source serves as the hole injection terminal.

[0110] In one feasible embodiment, the material of the first substrate layer 121 and / or the second substrate layer 122 includes diamond. As an emerging semiconductor material, diamond exhibits significant advantages in thermal conductivity and high breakdown field strength when used as a substrate material in MOS devices. First, diamond has extremely high thermal conductivity; single-crystal diamond has a thermal conductivity as high as 2400 W / (m·K) at room temperature, and polycrystalline diamond also has a thermal conductivity close to 2000 W / (m·K), making it an ideal heat dissipation substrate. In power devices, diamond can rapidly conduct heat away from the active region, effectively reducing the device operating temperature and thus improving device performance and reliability. Furthermore, diamond has an extremely high breakdown field strength, reaching 10 MV / cm, which is 17 times that of gallium arsenide, 2 times that of gallium nitride, and 2.5 times that of silicon carbide. This high breakdown field strength characteristic enables diamond to perform exceptionally well in high-voltage, high-power applications, significantly improving the device's withstand voltage and power capacity. Meanwhile, diamond has a wide bandgap (5.47 eV) and high carrier mobility (electron mobility up to 4500 cm⁻¹). 2 The V·s ratio further enhances its application potential in high-frequency, high-power semiconductor devices. Meanwhile, through the selection of high thermal conductivity materials and the positioning of the substrate structure, MOS devices can maintain good performance even when their size is reduced to the micro-nano scale.

[0111] In one feasible embodiment, the power MOS device further includes a gate dielectric 161 disposed between the gate structure 160 and the channel layer, wherein the channel layer includes a first channel layer 141 and / or a second channel layer 142. The most basic function of the gate dielectric 161 is to act as an insulating layer, isolating the gate from the channel layer. This insulation prevents gate current from flowing directly into the semiconductor substrate, thereby ensuring the voltage control characteristics of the device.

[0112] In one feasible embodiment, the thickness of the drift layer 110 is 10 to 15 μm; for example, the thickness of the drift layer 110 is 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, etc.

[0113] In one feasible embodiment, the thickness of the first channel layer 141 and the second channel layer 142 is 3 to 7 μm; for example, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, etc.

[0114] In one feasible embodiment, the thickness of the gate structure 160 is 0.1 to 0.5 μm; for example, the thickness of the gate structure 160 is 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, etc.

[0115] In one feasible embodiment, the thickness of the dielectric layer 170 is 0.4 to 0.8 μm; for example, the thickness of the dielectric layer 170 is 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, etc.

[0116] In one feasible embodiment, the thickness of the source layer 180 is 1 to 3 μm; for example, the thickness of the source layer 180 is 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, etc.

[0117] In one feasible embodiment, the thickness of the drain layer 130 is 1 to 3 μm; for example, the thickness of the drain layer 130 is 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, etc.

[0118] In one feasible embodiment, the thickness of the first substrate layer 121 and / or the second substrate layer 122 is 30 to 70 μm; for example, the thickness of the first substrate layer 121 and / or the second substrate layer 122 is 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, etc.

[0119] In one feasible embodiment, the material of the drift layer 110 includes at least one of N-type silicon carbide, N-type gallium nitride, N-type gallium arsenide, N-type gallium oxide, N-type aluminum gallium nitride, and N-type aluminum nitride.

[0120] In one feasible embodiment, the material of the gate structure 160 includes at least one of polysilicon, titanium nitride, tantalum nitride, tungsten, and cobalt.

[0121] In one feasible embodiment, the material of the source layer 180 includes at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium and cobalt.

[0122] In one feasible embodiment, the material of the drain layer 130 includes at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium and cobalt.

[0123] In this embodiment, although the JFET region of the power MOS device is not the main current flow path, its inherent on-resistance still leads to heat accumulation, thus affecting the overall thermal performance of the device. To effectively solve this problem, this embodiment of the application provides a first substrate layer 121 and a second substrate layer 122 made of a high thermal conductivity material in the JFET region of the power MOS device. This allows for rapid heat dissipation during device operation, significantly reducing thermal stress caused by local overheating and effectively lowering the device's operating temperature. Through optimized thermal management, the long-term reliability of the device is significantly improved, providing strong assurance for performance stability under high-power operation.

[0124] The second embodiment of this application provides a method for fabricating a power MOS device, referring to... Figure 2 This includes the following steps:

[0125] Step S10: Etch substrate 120 to form trench 123, wherein the substrate 120 is made of a high thermal conductivity material.

[0126] In one feasible embodiment, reference is made to Figure 3 A substrate layer 120 of 80-120 μm is provided, and the substrate layer 120 is etched to form trenches 123.

[0127] Optionally, the substrate can be patterned using photolithography to form the trenches 123; for example, using photolithography techniques such as EBL (electron beam lithography) and DUV (deep ultraviolet lithography). Exemplarily, the patterning steps may include: cleaning, spin coating, exposure, development, and etching the substrate layer 120 using photolithography to form the trenches 123 and the columnar structure of the substrate layer 120.

[0128] Optionally, the material of the substrate 120 includes diamond.

[0129] Step S20: Prepare a drift layer 110 in the trench 123.

[0130] In one feasible embodiment, reference is made to Figure 4 A drift layer 110 is prepared within the trench 123.

[0131] For example, an epitaxial layer is grown within the trench 123 and on the front side of the substrate layer 120 as a drift layer 110, wherein the N-type doping concentration of the drift layer 110 is 1e15 to 1e17 cm⁻¹. -3 The material of the drift layer 110 includes at least one of N-type silicon carbide, N-type gallium nitride, N-type gallium arsenide, N-type gallium oxide, N-type aluminum gallium nitride, and N-type aluminum nitride.

[0132] Optionally, the thickness of the drift layer 110 is 10–15 μm.

[0133] Step S30: A channel layer 140 is prepared on the front side of the substrate layer 120 and the drift layer 110.

[0134] In one feasible embodiment, reference is made to Figure 5 A channel layer 140 is fabricated on the front side of the substrate layer 120 and the drift layer 110.

[0135] For example, the surface drift layer 110 located on the front side of the substrate layer 120 is formed into a channel layer 140 by ion implantation and high-temperature activation.

[0136] Step S40: P-type doping is performed on a portion of the channel layer 140 to obtain a P-type well 151.

[0137] In one feasible embodiment, a portion of the channel layer 140 is p-type doped to obtain a p-type well 151, wherein the doping concentration of the p-type well 151 is 1e17 to 5e17 cm⁻¹. -3 .

[0138] In one feasible embodiment, step S40, which involves P-type doping a portion of the channel layer 140 to obtain a P-type well 151, includes:

[0139] Step S41: Prepare a first oxide layer 143 on the front side of the channel layer 140;

[0140] Step S42: Define the first photoresist pattern 144 on the front side of the first oxide layer 143;

[0141] Step S43: Etch the first oxide layer 143 based on the first photoresist pattern 144 to form a P-type well 151 injection window;

[0142] Step S44: P-type doping is performed on the channel layer 140 exposed to the implantation window of the P-type well 151 to obtain the P-type well 151.

[0143] In one feasible embodiment, reference is made to Figure 6 Deposition on the front side of channel layer 140 The first oxide layer 143 is used to define a first photoresist pattern 144 on its front side. Using the first photoresist pattern 144 as an etch resist layer, the first oxide layer 143 is etched to form a P-type well 151 injection window (not shown in the attached figure). Then, the channel layer 140 exposed to the P-type well 151 injection window is subjected to a etching process of 1e17~5e17 / cm. -3 P-type doping concentration was increased to obtain P-type well 151.

[0144] Step S50: N-type doping is performed on a portion of the P-type well 151 to obtain the N-type doped region 152.

[0145] In one feasible embodiment, a portion of the P-type trap 151 is subjected to a 1e18–1e19 cm sizing. -3 The concentration of N-type doping was increased to obtain N-type doped region 152.

[0146] In one feasible embodiment, prior to step S50, which involves N-type doping of a portion of the P-type well 151, the method further includes:

[0147] Step S51: A second oxide layer of a first thickness is prepared on the front side of the first oxide layer 143;

[0148] Step S52: Etch a second oxide layer of first thickness to form sidewalls 145 located on both sides of the injection window of the P-type trap 151.

[0149] In one feasible embodiment, reference is made to Figure 7 Remove the first photoresist pattern 144, and prepare a first thickness (e.g., on the front side of the first oxide layer 143) A second oxide layer (not shown in the figures) of a first thickness is formed by etching the second oxide layer, thereby forming sidewalls 145 on both sides of the injection window of the P-type well 151. Further, referring to... Figure 8 By shielding the area through the sidewall 145, N-type doping is performed on a portion of the P-type well 151 exposed to the injection window of the P-type well 151 to obtain the N-type doped region 152.

[0150] Step S60: P-type doping is performed on a portion of the N-type doped region 152 to obtain the P-type doped region 153.

[0151] In one feasible embodiment, reference is made to Figure 9 Photolithography was used to implant 1e18–1e19 cm⁻¹ into a portion of the N-type doped region 152. -3 P-type impurities of varying concentrations are used to achieve P-type doping and obtain the P-type doped region 153.

[0152] In one feasible embodiment, prior to step S70, which involves sequentially fabricating the gate structure 160 and the dielectric layer 170 on the front side of the channel layer 140, the method further includes: referring to Figure 10 Remove the first oxide layer 143 and sidewall 145, and thermally grow a layer on the front side of the trench layer 140. Thermo-oxidized metal is used as the gate dielectric 161.

[0153] In step S70, a gate structure 160 and a dielectric layer 170 are sequentially fabricated on the front side of the channel layer 140, wherein the dielectric layer 170 covers the gate structure 160.

[0154] In one feasible embodiment, a gate structure 160 and a dielectric layer 170 covering the gate structure 160 are sequentially fabricated on the front side of the channel layer 140.

[0155] In one feasible embodiment, step S70, which involves sequentially fabricating a gate structure 160 and a dielectric layer 170 on the front side of the channel layer 140, includes:

[0156] Step S71: A gate layer is fabricated on the front side of the channel layer 140;

[0157] Step S72: Etch the gate layer to obtain gate structure 160;

[0158] In one feasible embodiment, reference is made to Figure 11 A gate layer is deposited on the front side of the channel layer 140, and the gate structure 160 is obtained by etching.

[0159] Step S73: Prepare a dielectric layer 170 on the front side of the gate structure 160.

[0160] In one feasible embodiment, reference is made to Figure 12 A dielectric layer 170 is deposited on the front side of the gate structure 160 to cover the gate structure 160.

[0161] Step S80: Etch dielectric layer 170 to obtain connection hole 171.

[0162] In one feasible embodiment, reference is made to Figure 13 The dielectric layer 170 is etched to obtain a connection hole 171, wherein the N-type doped region 152 and the P-type doped region 153 are exposed through the connection hole 171.

[0163] Step S90: Prepare source layer 180, wherein source layer 180 is in contact with N-type doped region 152 and P-type doped region 153 through connection hole 171.

[0164] In one feasible embodiment, reference is made to Figure 14 A source layer 180 is prepared, and the source layer 180 is made to contact the N-type doped region 152 and the P-type doped region 153 through the connecting hole 171.

[0165] Step S100: Remove the substrate layer 120 located on the back side of the drift layer 110 to expose the drift layer 110.

[0166] In one feasible embodiment, reference is made to Figure 15 Remove the substrate layer 120 located on the back side of the drift layer 110 to expose the drift layer 110.

[0167] In step S110, a drain layer 130 is fabricated on the back side of the drift layer 110 to obtain a power MOS device.

[0168] In one feasible embodiment, reference is made to Figure 1 A drain layer 130 is fabricated on the back side of the drift layer 110 to obtain a power MOS device.

[0169] In this embodiment, by setting a first substrate layer and a second substrate layer made of a high thermal conductivity material in the JFET region of the power MOS device, the heat generated during device operation can be rapidly dissipated, significantly reducing thermal stress caused by local overheating and thus effectively lowering the device's operating temperature. Through optimized thermal management, the long-term reliability of the device is significantly improved, providing strong assurance for performance stability under high-power operation.

[0170] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the patent protection scope of this application.

Claims

1. A power MOS device, characterized in that, The power MOS device includes: Drift layer; A first substrate layer and a second substrate layer are respectively disposed on both sides of the drift layer, wherein the material of the first substrate layer and / or the second substrate layer is a high thermal conductivity material, including diamond; A drain layer is disposed on the back side of the drift layer; The first trench layer and the second trench layer are respectively disposed on the front side of the first substrate layer and the second substrate layer; A P-type well is disposed between the first channel layer and the second channel layer. An N-type doped region is formed inside the P-type well, and a P-type doped region is formed inside the N-type doped region. The steps for fabricating the P-type well include: fabricating a first oxide layer on the front side of the channel layer; defining a first photoresist pattern on the front side of the first oxide layer; etching the first oxide layer based on the first photoresist pattern to form a P-type well implantation window; and performing P-type doping on the channel layer exposed to the P-type well implantation window to obtain the P-type well. A gate structure is disposed on the front side of the first channel layer and the second channel layer; A dielectric layer is disposed on the front side of the gate structure and covers the gate structure; the dielectric layer is provided with connection holes; The source layer is disposed on the front side of the dielectric layer and contacts the N-type doped region and the P-type doped region through the connection hole.

2. The power MOS device as described in claim 1, characterized in that, The power MOS device further includes: a gate dielectric disposed between the gate structure and the channel layer, wherein the channel layer includes a first channel layer and / or a second channel layer.

3. The power MOS device as described in claim 1, characterized in that, The thickness of the drift layer is 10~15 μm; And / or, the thickness of the first trench layer and the second trench layer is 3~7 μm; And / or, the thickness of the gate structure is 0.1~0.5 μm; And / or, the thickness of the dielectric layer is 0.4~0.8 μm; And / or, the thickness of the source layer is 1~3 μm; And / or, the thickness of the drain layer is 1~3 μm.

4. The power MOS device as described in claim 1, characterized in that, The material of the drift layer includes at least one of N-type silicon carbide, N-type gallium nitride, N-type gallium arsenide, N-type gallium oxide, N-type aluminum gallium nitride, and N-type aluminum nitride; And / or, the material of the gate structure includes at least one of polycrystalline silicon, titanium nitride, tantalum nitride, tungsten, and cobalt; And / or, the material of the source layer includes at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium and cobalt; And / or, the material of the drain layer includes at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium and cobalt.

5. A method for fabricating a power MOS device, characterized in that, The method for fabricating the power MOS device is used to fabricate the power MOS device as described in any one of claims 1 to 4, and includes the following steps: The substrate layer is etched to form trenches, wherein the substrate layer is made of a material with high thermal conductivity; A drift layer is prepared within the trench; A channel layer is fabricated on the front side of the substrate layer and the drift layer; A first oxide layer is prepared on the front side of the channel layer; A first photoresist pattern is defined on the front side of the first oxide layer; The first oxide layer is etched based on the first photoresist pattern to form a P-type well injection window; The channel layer exposed to the P-type well implantation window is P-type doped to obtain the P-type well; A portion of the P-type well is N-type doped to obtain an N-type doped region. A portion of the N-type doped region is p-type doped to obtain a p-type doped region. A gate structure and a dielectric layer are sequentially fabricated on the front side of the channel layer, wherein the dielectric layer covers the gate structure; The dielectric layer is etched to obtain the connection hole; A source layer is prepared, wherein the source layer is in contact with the N-type doped region and the P-type doped region through the connecting hole; Remove the substrate layer located on the back side of the drift layer to expose the drift layer; A drain layer is fabricated on the back side of the drift layer to obtain a power MOS device.

6. The method for fabricating a power MOS device as described in claim 5, characterized in that, Prior to the step of performing N-type doping on a portion of the P-type well, the method further includes: A second oxide layer of a first thickness is prepared on the front side of the first oxide layer; The second oxide layer of a first thickness is etched to form sidewalls located on both sides of the P-type trap injection window.

7. The method for fabricating a power MOS device as described in claim 5, characterized in that, The step of sequentially fabricating the gate structure and the dielectric layer on the front side of the channel layer includes: A gate layer is fabricated on the front side of the channel layer; The gate layer is etched to obtain the gate structure; The dielectric layer is prepared on the front side of the gate structure.

8. The method for fabricating a power MOS device as described in claim 5, characterized in that, The p-type doping concentration of a portion of the channel layer is 1e17~5e17 cm⁻¹. -3 ; And / or, the N-type doping concentration of the portion of the P-type well is 1e18~1e19 cm⁻¹. -3 ; And / or, the doping concentration for p-type doping of a portion of the N-type doped region is 1e18~1e19 cm⁻¹. -3 .

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