A MOSFET semiconductor structure with optimized source-drain contact and a method for preparing the same

Abstract

The present invention relates to the field of MOS semiconductor technology and discloses a MOSFET semiconductor structure with optimized source-drain contacts, comprising a drain, a semiconductor epitaxial layer, a source, and a gate. The semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P well layer, an N well layer, and a P layer. Source polysilicon is provided within the P layer, and the top of the source polysilicon is in ohmic contact with the source. Three metal oxide layers are provided within the N well layer, and the tops of the three metal oxide layers are in ohmic contact with the source. The drain also includes several semicircular metal layers within the drain, and the semicircular metal layers are in ohmic contact with the N substrate layer. The present invention forms a low-resistance channel through a heavily doped gate doped with high-concentration phosphorus, reducing the charge and discharge time of the gate charge. The doped gate provides an additional conductive path, reducing switching time, improving power conversion efficiency, and reducing heat loss.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a MOSFET semiconductor structure with optimized source-drain contact and a preparation method thereof. Background Art

[0002] With the rapid development of power electronics technology, metal-oxide-semiconductor field-effect transistors (MOSFETs), as core power switching devices, have been widely used in new energy conversion, motor drive, high-frequency power supply and other fields.

[0003] However, conventional MOSFETs typically employ an ohmic contact structure between planar polysilicon and metal. However, this can lead to high contact resistance due to uneven interface impurity diffusion or limited contact area. For example, an inadequately designed polysilicon doping concentration gradient in the source region results in a tortuous carrier transport path, further increasing conduction losses (Rds(on)). While existing technologies attempt to reduce contact resistance through metal silicide, the poor interface stability of silicide in high-temperature processes can easily lead to contact degradation, compromising the long-term reliability of the device.

[0004] An existing patent discloses a hybrid-gate SiC MOSFET cell structure, device, and fabrication method (publication number CN116053316A), belonging to the field of semiconductor device technology. The cell structure comprises an N++-type SiC substrate and an N-type SiC drift layer disposed above the substrate. The technology disclosed in this patent addresses the problem of concentrated current density in the drain region, which can lead to localized hot spots in high-current applications. This can exacerbate hot carrier injection and even cause thermal breakdown. Existing solutions often rely on increasing the thermal conductivity of heat sinks or packaging materials, but such methods fail to fundamentally optimize the internal thermal distribution of the device. Furthermore, conventional drain structures have limited ability to regulate the electric field. Under high-voltage conditions, electric field edge concentration (e.g., inadequately optimized RESURF effect) can reduce the breakdown voltage (BVDSS), limiting the device's high-voltage applications. Summary of the Invention

[0005] In order to solve the existing technical problems, the present invention provides a MOSFET semiconductor structure with optimized source-drain contacts and a preparation method thereof, which solves the problems in the above-mentioned background technology.

[0006] To solve the above technical problems, according to one aspect of the present invention, more specifically, a MOSFET semiconductor structure with optimized source-drain contacts includes a drain, a semiconductor epitaxial layer, a source, and a gate. The semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a P well layer, an N well layer, and a P-layer. Source polysilicon is provided inside the P-layer, and the top of the source polysilicon is in ohmic contact with the source.

[0007] Three metal oxide layers are provided inside the N-well layer, and the tops of the three metal oxide layers are connected to the source electrode;

[0008] The drain electrode further includes a plurality of semicircular metal layers inside, and the semicircular metal layers are in ohmic contact with the N substrate layer.

[0009] Furthermore, the cross-sectional profile of the P-layer is in an "L" shape.

[0010] Furthermore, drain polysilicon is provided on both the left and right sides of the bottom end of the semiconductor epitaxial layer, and the bottom end of the drain polysilicon is in contact with the drain electrode.

[0011] Furthermore, the N substrate layer further includes a substrate layer 1, wherein the top of the drain polysilicon is in ohmic contact with the N drift layer.

[0012] Furthermore, the N substrate layer also includes a second substrate layer, wherein the N substrate layer is completely wrapped by the second substrate layer.

[0013] Furthermore, the N substrate layer further includes a substrate layer three, wherein the cross-sectional profile of the substrate layer three is in a shape with convex sides and concave in the middle.

[0014] Furthermore, four heavily doped gates are formed in the middle recess of the substrate layer three by ion implantation.

[0015] A method for preparing a MOSFET semiconductor structure with optimized source-drain contacts, comprising the following steps:

[0016] S1. Growing an N drift layer, a P well layer, an N well layer, and a P- layer in sequence by chemical vapor deposition;

[0017] S2, depositing source polysilicon on the surface of the P- layer, and forming N+ doping by phosphorus ion implantation to achieve ohmic contact with the source;

[0018] S3, depositing drain polysilicon layers on the left and right sides of the N substrate layer, and defining the drain polysilicon region by photolithography and etching, followed by annealing to optimize contact resistance;

[0019] S4, depositing tungsten oxide inside the N-well layer, forming three metal oxide layers by photolithography and dry etching, and connecting them to the source;

[0020] S5. Depositing aluminum metal in the drain region or forming a semicircular metal layer by patterned etching;

[0021] S6. Forming a third substrate layer in the N substrate layer by photolithography and ion implantation, wherein the cross section thereof has a shape of convex sides and concave middle;

[0022] S7, implanting high-concentration phosphorus into the recessed area of the substrate layer 3 to form four heavily doped gates;

[0023] S8. Conduct electrical performance testing on a MOSFET semiconductor structure containing four heavily doped gates.

[0024] Furthermore, in step S8, the performance of the MOSFET semiconductor structure is determined based on the changes in on-resistance, threshold voltage, and switching time when the MOSFET semiconductor structure is heated from 25° C. to 100° C., and thus:

[0025] ;

[0026] Where, Indicates the performance stability coefficient of the MOSFET semiconductor structure; Indicates the change in on-resistance of the MOSFET semiconductor structure when the temperature changes from 25°C to 100°C; It indicates the change in switching time of the MOSFET semiconductor structure when the temperature changes from 25°C to 100°C.

[0027] The present invention provides a MOSFET semiconductor structure with optimized source-drain contacts and a method for preparing the same. Compared with the prior art, the present method achieves the following effects:

[0028] 1. The present invention adopts the ohmic contact design between the semicircular metal layer and the N substrate layer, utilizes the semicircular structure to disperse the current density, avoid local hot spots, enhance the heat dissipation capacity of the drain, and improve the high current carrying stability of the device.

[0029] 2. The present invention forms a low-resistance contact directly with the N drift layer through the drain polysilicon, shortening the carrier transmission path from the drain to the drift layer, reducing the total resistance of the drain region, and improving the efficiency of the device in high-voltage applications.

[0030] 3. The present invention uses high thermal conductivity materials in the substrate layer 2 to quickly conduct heat from the N substrate layer to the package base, thereby reducing the operating temperature of the device, extending its life and improving its stability in high temperature environments.

[0031] 4. The present invention disperses the electric field line density through the recessed area of the substrate layer 3, thereby avoiding edge electric field concentration, increasing the breakdown voltage, and enhancing the withstand voltage capability of the device.

[0032] 5. The present invention forms a low-resistance channel through a heavily doped gate doped with high-concentration phosphorus, reducing the charging and discharging time of the gate charge, and the doped gate provides an additional conductive path, reducing the switching time, improving the power conversion efficiency, and reducing heat loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a schematic structural diagram of Example 1 of the present invention;

[0034] Figure 2 This is a schematic structural diagram of Example 2 of the present invention;

[0035] Figure 3 This is a schematic structural diagram of Example 3 of the present invention;

[0036] Figure 4 This is a schematic structural diagram of Embodiment 4 of the present invention;

[0037] Figure 5 This is a structural diagram of Example 5 of the present invention.

[0038] In the figure: 1. Drain; 2. N substrate layer; 3. N drift layer; 4. Source; 5. Gate; 6. P well layer; 7. N well layer; 8. P-layer; 9. Source polysilicon; 10. Oxide metal layer; 11. Semicircular metal layer; 12. Drain polysilicon; 13. Heavily doped gate; 21. Substrate layer 1; 22. Substrate layer 2; 23. Substrate layer 3. DETAILED DESCRIPTION

[0039] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0040] like Figure 1-5 As shown, a method for preparing a MOSFET semiconductor structure with optimized source-drain contacts comprises the following specific steps:

[0041] Step 1: growing an N drift layer 3, a P well layer 6, an N well layer 7, and a P- layer 8 in sequence by chemical vapor deposition;

[0042] Step 2: deposit source polysilicon 9 on the surface of the P-layer 8, and form N+ doping by phosphorus ion implantation to achieve ohmic contact with the source 4;

[0043] Step 3: depositing drain polysilicon layers 12 on the left and right sides of the N substrate layer 2, and defining the drain polysilicon 12 region by photolithography and etching, followed by annealing to optimize contact resistance;

[0044] Step 4: Deposit tungsten oxide inside the N-well layer 7, and form three metal oxide layers 10 by photolithography and dry etching, and connect them to the source electrode 4;

[0045] Step 5: depositing aluminum metal in the drain region 1 or forming a semicircular metal layer 11 by pattern etching;

[0046] Step 6: forming a third substrate layer 23 in the N substrate layer 2 by photolithography and ion implantation, wherein the cross section thereof is convex at both sides and concave in the middle;

[0047] Step 7: implant high-concentration phosphorus into the recessed area of the substrate layer 3 23 to form four heavily doped gates 13;

[0048] Step 8: Conduct electrical performance testing on the MOSFET semiconductor structure containing four heavily doped gates 13. The performance of the MOSFET semiconductor structure is determined based on the changes in on-resistance, threshold voltage, and switching time when the MOSFET semiconductor structure is heated from 25°C to 100°C. The following are the results:

[0049] ;

[0050] Where, Indicates the performance stability coefficient of the MOSFET semiconductor structure; Indicates the change in on-resistance of the MOSFET semiconductor structure when the temperature changes from 25°C to 100°C; It indicates the change in switching time of the MOSFET semiconductor structure when the temperature changes from 25°C to 100°C.

[0051] The performance temperature coefficient of any power device is calculated. The change in on-resistance of the MOSFET semiconductor structure from 25°C to 100°C is taken as (On-resistance change = |On-resistance at 100°C - On-resistance at 25°C| ÷ On-resistance at 20°C × 100%). The change in switching time of this MOSFET semiconductor structure from 25°C to 100°C is (The change in switching time = |switching time at 100°C - switching time at 25°C| ÷ switching time at 20°C × 100%). Then we have:

[0052]

[0053] From the above calculation, we can know that the performance stability coefficient of the MOSFET semiconductor structure is .

[0054] The performance temperature coefficient of the traditional device with the same power is calculated again. The change in on-resistance of the traditional MOSFET semiconductor structure from 25℃ to 100℃ is taken as The change in switching time of the conventional MOSFET semiconductor structure from 25°C to 100°C is , then we have:

[0055]

[0056] From the above calculations, it can be seen that the performance stability coefficient of the MOSFET semiconductor structure in this application is improved by 36.3% compared with the traditional MOSFET semiconductor structure.

[0057] Example 1

[0058] like Figure 1As shown, according to one aspect of the present invention, a MOSFET semiconductor structure with optimized source-drain contact is provided, comprising a drain 1, a semiconductor epitaxial layer, a source 4, and a gate 5. The semiconductor epitaxial layer comprises an N substrate layer 2, an N drift layer 3, a P well layer 6, an N well layer 7, and a P-layer. A source polysilicon 9 is provided within the P-layer 8, and the top of the source polysilicon 9 is in ohmic contact with the source 4. Three metal oxide layers 10 are provided within the N well layer 7, and the tops of the three metal oxide layers 10 are in ohmic contact with the source 4. The drain 1 also comprises several semicircular metal layers 11 within, and the semicircular metal layers 11 are in ohmic contact with the N substrate layer 2. The ohmic contact design between the semicircular metal layers 11 and the N substrate layer 2 utilizes the semicircular structure to disperse current density, avoid local hot spots, enhance the heat dissipation capability of the drain, and improve the high current carrying stability of the device.

[0059] The cross-sectional profile of the P-layer 8 is L-shaped. The L-shaped P-layer 8 reduces the tortuosity of the carrier transmission path by increasing the contact area between the source electrode 4 and the P-layer 8. Furthermore, the source polysilicon 9 establishes direct ohmic contact with the source electrode 4, significantly reducing contact resistance, improving current conduction efficiency, and reducing conduction losses.

[0060] Example 2

[0061] like Figure 2 As shown, drain polysilicon 12 is provided on both sides of the bottom of the semiconductor epitaxial layer. The bottom of drain polysilicon 12 contacts the drain 1. The N substrate layer 2 also includes substrate layer 1 21, where the top of drain polysilicon 12 makes ohmic contact with the N drift layer 3. The drain polysilicon 12 forms a direct low-resistance contact with the N drift layer 3, shortening the carrier transmission path from the drain to the drift layer, reducing the total resistance of the drain region, and improving the efficiency of the device in high-voltage applications.

[0062] Furthermore, the substrate layer 1 21 serves as a buffer layer to reduce the lattice mismatch between the N substrate layer 2 and the N drift layer 3 , lower the interface defect density, suppress leakage current, and improve device reliability.

[0063] Example 3

[0064] like Figure 3 As shown, drain polysilicon 12 is provided on both sides of the bottom of the semiconductor epitaxial layer. The bottom of the drain polysilicon 12 contacts the drain electrode 1. The N substrate layer 2 also includes a second substrate layer 22, wherein the N substrate layer 2 is completely enclosed by the second substrate layer 22. The second substrate layer 22 is made of a high thermal conductivity material to quickly conduct heat from the N substrate layer 2 to the package substrate, reducing the operating temperature of the device, extending the life, and improving stability in high-temperature environments.

[0065] Example 4

[0066] like Figure 4As shown, drain polysilicon 12 is provided on both sides of the bottom of the semiconductor epitaxial layer. The bottom of drain polysilicon 12 contacts drain electrode 1. N substrate layer 2 also includes substrate layer 3 23. The cross-sectional profile of substrate layer 3 23 is convex on both sides and concave in the middle. The concave region disperses the electric field line density, avoiding edge electric field concentration (such as the RESURF effect), and increases the breakdown voltage (BVDSS), enhancing the device's withstand voltage capability.

[0067] The raised structures on both sides guide the carriers to concentrate in the central recessed area, reducing the on-resistance, increasing the current density and improving the dynamic response speed.

[0068] Example 5

[0069] like Figure 5 As shown, drain polysilicon 12 is provided on both sides of the bottom of the semiconductor epitaxial layer. The bottom end of the drain polysilicon 12 contacts the drain 1. The N substrate layer 2 also includes a third substrate layer 23. The cross-sectional profile of the third substrate layer 23 is convex on both sides and concave in the middle. Four heavily doped gates 13 are formed in the middle concave portion of the third substrate layer 23 through ion implantation. The heavily doped gates 13, with a high concentration of phosphorus doping, form low-resistance channels, reducing the charge and discharge time of the gate charge. The doped gates 13 also provide additional conductive paths, reducing switching time, improving power conversion efficiency, and reducing heat loss.

[0070] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A MOSFET semiconductor structure with optimized source-drain contact, comprising a drain (1), a semiconductor epitaxial layer, a source (4), and a gate (5), wherein the semiconductor epitaxial layer comprises an N substrate layer (2), an N drift layer (3), a P well layer (6), an N well layer (7), and a P-layer, characterized in that: A source polysilicon (9) is provided inside the P-layer (8), and the top of the source polysilicon (9) is in ohmic contact with the source electrode (4); Three metal oxide layers (10) are provided inside the N-well layer (7), and the top ends of the three metal oxide layers (10) are in contact with the source electrode (4); The drain electrode (1) further comprises a plurality of semicircular metal layers (11) inside, and the semicircular metal layers (11) are in ohmic contact with the N substrate layer (2); Drain polysilicon (12) is provided on both the left and right sides of the bottom end of the semiconductor epitaxial layer, and the bottom end of the drain polysilicon (12) is in contact with the drain electrode (1); The N substrate layer (2) further includes a substrate layer three (23), wherein the cross-sectional profile of the substrate layer three (23) is in the shape of convex on both sides and concave in the middle; Four heavily doped gates (13) are formed in the middle recess of the substrate layer three (23) by ion implantation.

2. The MOSFET semiconductor structure with optimized source-drain contacts according to claim 1, wherein: The cross-sectional profile of the P-layer (8) is in an "L" shape.

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