Gate structure and floating gate memory

Abstract

The invention discloses a gate structure and a floating gate memory. The gate structure comprises at least one floating gate, a control gate and a dielectric layer. The floating gate has a first region and a second region. The dielectric layer is located between the floating gate and the control gate. The first region is located between the second region and the dielectric layer, and the energy band gap of the first region is smaller than the energy band gap of the second region.

Description

Technical Field

[0001] The present invention relates to an electrode structure, and more particularly to a gate structure and a floating gate memory including the same. Background Art

[0002] Since non-volatile memory has the advantage that the stored data does not disappear even after power-off, such memory must be provided in many electrical products to maintain the normal operation of the electrical products when powered on. In a non-volatile memory that stores charge using a floating gate, the material and / or design of the floating gate may affect the electrical performance of the memory element. Therefore, how to improve the quality of the memory element by improving the floating gate is an ongoing goal. Summary of the Invention

[0003] The present invention provides a gate structure and a corresponding floating gate memory with better quality.

[0004] The gate structure of the present invention includes at least one floating gate, a control gate, and a second dielectric layer. The floating gate has a first region and a second region. The second dielectric layer is located between the floating gate and the control gate. The first region is located between the second region and the second dielectric layer, and the energy band gap of the first region is smaller than that of the second region.

[0005] In an embodiment of the present invention, the gate structure further includes a substrate and a first dielectric layer. The first dielectric layer, the floating gate, the second dielectric layer, and the control gate are located on the substrate, and the first dielectric layer is located between the substrate and the floating gate.

[0006] In an embodiment of the present invention, the number of floating gates is multiple, and part of the control gate is located between two adjacent floating gates.

[0007] In an embodiment of the present invention, the first region is a doped portion formed by an epitaxial growth process.

[0008] In an embodiment of the present invention, the first region covers the upper region of the second region.

[0009] In an embodiment of the present invention, the maximum width of the floating gate corresponds to the first region.

[0010] In an embodiment of the present invention, the first region is a quantum well layer.

[0011] In an embodiment of the present invention, the first region is located on the upper region of the second region.

[0012] The floating gate memory of the present invention includes the aforementioned gate structure.

[0013] In an embodiment of the present invention, the number of floating gates is multiple. The control gate corresponds to the multiple floating gates. The control gate is electrically connected to a word line.

[0014] Based on the above, the gate structure of the present invention can enable corresponding components (such as floating gate memories) to have better quality. Description of the Drawings

[0015] Figures 1A to 1D is a partial cross-sectional schematic diagram of a method for manufacturing a gate structure according to a first embodiment of the present invention;

[0016] Figure 2 is a partial cross-sectional schematic diagram of a gate structure according to a second embodiment of the present invention;

[0017] Figures 3A to 3C is a partial cross-sectional schematic diagram of a method for manufacturing a gate structure according to a third embodiment of the present invention.

[0018] Symbol Description

[0019] 100, 200, 300: Gate structure

[0020] 110: Substrate

[0021] 121: First dielectric layer

[0022] 122: Second dielectric layer

[0023] 123: Isolation structure

[0024] 130: First conductive layer, conductive part

[0025] 134: Upper region

[0026] 141, 241: Doped part

[0027] 150: Second conductive layer

[0028] 180: Hard mask layer

[0029] 342: Quantum well layer

[0030] 342a: Well layer

[0031] 342b: Barrier layer

[0032] CG: Control gate

[0033] FG1, FG2, FG3: Conductor, floating gate

[0034] T: Trench

[0035] Wx: Maximum width Detailed Description of the Invention

[0036] Examples are listed below and described in detail in conjunction with the accompanying drawings. However, the provided examples are not intended to limit the scope covered by the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to the original size. For ease of understanding, the same elements will be denoted by the same reference numerals in the following description.

[0037] In addition, terms such as "comprising", "having", etc. used herein are open-ended terms, that is, they mean "including but not limited to".

[0038] It should be understood that although terms such as "first", "second", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, the "first element", "component", "region", "layer", or "part" discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings herein.

[0039] Figures 1A to 1D is a partial cross-sectional schematic view of a method for fabricating a gate structure according to a first embodiment of the present invention.

[0040] Please refer to Figure 1A , a substrate 110 is provided. The substrate 110 may include a semiconductor substrate 110 (such as a silicon substrate). It should be noted that the substrate 110 in Figure 1A is only schematically illustrated. In one embodiment, the substrate 110 may have corresponding patterned or unpatterned film layers (such as a dielectric layer, a semiconductor layer, or a conductive layer), or corresponding doped regions (such as a source region or a drain region). For example, the aforementioned semiconductor substrate and the patterned and / or unpatterned film layer thereon or the corresponding doped region therein may be collectively referred to as the substrate 110.

[0041] Please continue to refer to Figure 1A , corresponding film layers may be formed on the substrate 110 by appropriate semiconductor fabrication processes. For example, a first dielectric layer 121, a first conductive layer 130, and a hard mask (HM) layer 180 may be formed.

[0042] In one embodiment, the material of the first dielectric layer 121 includes silicon oxide, silicon oxynitride, silicon nitride, other suitable dielectric materials, or a stack or combination of the above. The forming method thereof includes chemical vapor deposition, atomic layer deposition, or oxidation methods (such as furnace tube oxidation, n-situ steam generation (ISSG) method, etc.). The thickness of the first dielectric layer 121 can be about 5 nanometers (nm) to 20 nm, but the present invention is not limited thereto.

[0043] In one embodiment, the material of the first conductive layer 130 includes doped amorphous silicon or polycrystalline silicon, undoped amorphous silicon or polycrystalline silicon, or a combination of the above. The forming method can be chemical vapor deposition. For example, the first conductive layer 130 can be a P-type polycrystalline silicon layer, and its dopant can be boron (for example, BF 2 ). The thickness of the first conductive layer 130 can be about 50 nm to 150 nm, but the present invention is not limited thereto. For example, the thickness of the first conductive layer 130 can be about 70 nm to 75 nm; or, about 100 nm; or, about 70 nm.

[0044] In one embodiment, the material of the hard mask layer 180 includes undoped silicon nitride, and the forming method includes chemical vapor deposition. The thickness of the hard mask layer 180 can be 30 nm to 100 nm, but the present invention is not limited thereto.

[0045] In one embodiment, there may be a corresponding conductive seed layer (not shown) between the hard mask layer 180 and the first conductive layer 130 (such as the first conductive layer 130), but the present invention is not limited thereto. The aforementioned conductive seed layer is suitable for the formation of subsequent doping sites 141 (marked in Figure 1C ).

[0046] Please refer to Figures 1A to 1B , and appropriate semiconductor manufacturing processes (such as lithography and etching manufacturing processes, but not limited thereto) can be used to form the trench T. It should be noted that the trenches T that appear separated in a cross-sectional view (such as Figure 1B ) may be substantially connected elsewhere or in other cross-sectional views not shown. The trench T can penetrate the film layers on the substrate 110 (such as the first dielectric layer 121, the first conductive layer 130, and the hard mask layer 180) to at least form multiple fin-shaped conductive portions 130 of the first conductive layer 130. For the sake of simplicity, the conductive portions 130 formed by the first conductive layer 130 still use the same marking symbols. Moreover, the trench T can extend downward to form corresponding depressions on the surface of the substrate 110, so that the substrate 110 has multiple fin-shaped protrusions corresponding to the first conductive layer 130.

[0047] Please continue to refer to Figure 1B, an isolation structure 123 can be formed in the trench T through appropriate semiconductor manufacturing processes (such as, but not limited to, deposition, grinding, etching). The isolation structure 123 basically does not cover the upper region 134 of the first conductive layer 130 (i.e., the region of the first conductive layer 130 farther from the substrate 110). During the process of forming the isolation structure 123 (such as the corresponding grinding or etching step), the hard mask layer 180 (shown in Figure 1A ) can be correspondingly removed.

[0048] In one embodiment, the isolation structure 123 can include a corresponding liner layer and an isolation material layer. The liner layer can be conformally formed in the trench T to cover a part of the sidewalls and the bottom surface of the trench T. The isolation material layer can be formed on the inner surface of the liner layer to fill a part of the trench T covered by the liner layer. That is, the liner layer can cover the isolation material layer, such that the liner layer is located between the substrate 110 and the isolation material layer. In one embodiment, the material of the liner layer includes high-temperature oxide (HTO), such as hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), lanthanum oxide (LaO), aluminum oxide (Al 2 O 3 ) or tantalum oxide (Ta 2 O 5 ), but the present invention is not limited thereto. In one embodiment, the material of the isolation material layer includes spin-on glass (SOG), but the present invention is not limited thereto. In one embodiment, the isolation structure 123 can be referred to as a shallow trench isolation (STI) structure.

[0049] Please refer to Figures 1B to 1C, an appropriate semiconductor manufacturing process (such as, but not limited to, an epitaxial growth process) can be used to form a corresponding doped region 141. The energy band gap (Eg) of the material of the doped region 141 is substantially smaller than the energy band gap of the material of the corresponding first conductive layer 130. Specifically, the energy band gap of the material of the doped region 141 is substantially smaller than the energy band gap of the material of the upper region 134. For example, the energy band gap of the upper region 134 can be about 1.12 ± 0.05 eV, and the energy band gap of the doped region 141 is smaller than that of the upper region 134 and greater than 0.66 eV; or, the energy band gap of the doped region 141 is smaller than that of the upper region 134 and even greater than about 0.9 eV. As another example, the material of the first conductive layer 130 is silicon, and the material of the doped region 141 is silicon-germanium. By adjusting the doping concentration in the doped region 141, the value of the energy band gap can be correspondingly adjusted. Taking silicon-germanium material as an example, the value of the energy band gap can decrease with the increase of germanium concentration within a certain range.

[0050] Please refer to Figure 1C , in a cross-section (such as: Figure 1C the plane shown), the contour of the doped region 141 can be the same as or similar to a rhombus. For example, the contour of the doped region 141 can be similar to a rhombus with rounded or arced corners; and / or, the bottom of the rhombus (i.e., corresponding to the part covering the upper region 134) is replaced by a corresponding virtual contour. The contour and / or size of the doped region 141 may change due to materials (such as doping concentration and / or type) and manufacturing process conditions (such as time and / or temperature). In addition, different doped regions 141 corresponding to different upper regions 134 are substantially not connected or in contact with each other.

[0051] Each fin-shaped conductive part 130 and the doped region 141 covering its upper region 134 can form a corresponding conductor FG1. That is to say, the conductor FG1 can include the conductive part 130 and the doped region 141. The conductive part 130 has an upper region 134 away from the substrate 110. The doped region 141 covers the upper region 134. The energy band gap of the doped region 141 is smaller than the energy band gap of the conductive part 130.

[0052] Please refer to Figures 1C to 1D , an appropriate semiconductor manufacturing process (such as, but not limited to, deposition) can be used to form a corresponding film layer on the substrate 110. For example, a second dielectric layer 122 and a second conductive layer 150 can be formed.

[0053] The second dielectric layer 122 can conformally cover the partially conductive body FG1 not covered by the isolation structure 123. For example, the second dielectric layer 122 can conformally cover the doped region 141. The material of the second dielectric layer 122 can be the same as or similar to that of the first dielectric layer 121 or the isolation structure 123. The second dielectric layer 122 can be a single-layer or multi-layer composite dielectric layer.

[0054] The second conductive layer 150 is covered on the second dielectric layer 122, and at least a part of the second conductive layer 150 overlaps with the conductive body FG1. In one embodiment, a part of the second conductive layer 150 can be further located between two adjacent conductive bodies FG1. In this way, in subsequent applications, the effective gate coupling ratio (GCR) can be improved. The material of the second conductive layer 150 can be the same as or similar to that of the first conductive layer 130, but the present invention is not limited thereto.

[0055] In one embodiment, the conductive body FG1 can be used as an electrode. In one embodiment, the conductive body FG1 can be referred to as a charge trap layer. For example, the conductive body FG1 can be used as a floating gate. Additionally, taking the embodiment where the conductive body FG1 is used as a floating gate as an example, a part of the second conductive layer 150 corresponding to the conductive body FG1 can be used as a control gate CG. The control gate can be electrically connected to the corresponding word line (WL). Additionally, for the sake of simplicity, the conductive body FG1 used as a floating gate and the floating gate may use the same marking symbol.

[0056] After the above manufacturing process, the manufacturing of the gate structure 100 of this embodiment can be generally completed.

[0057] Please refer to Figure 1D , the gate structure 100 can include at least one floating gate FG1, a second dielectric layer 122, and a control gate CG. The second dielectric layer 122 is located between the floating gate FG1 and the control gate CG. The floating gate FG1 has a first region (i.e., the doped region 141) and a second region (i.e., the conductive region 130). The first region is located between the second region and the second dielectric layer 122. The energy band gap of the first region (i.e., the doped region 141) is smaller than the energy band gap of the second region (i.e., the conductive region 130). In one embodiment, the second dielectric layer 122 can be referred to as an inter-electrode dielectric layer (IPD layer), a blocking layer, or an IPD blocking layer.

[0058] In one embodiment, the gate structure 100 may further include a substrate 110 and a first dielectric layer 121. The first dielectric layer 121, the floating gate FG1, the second dielectric layer 122, and the control gate CG are located on the substrate 110. The first dielectric layer 121 is located between the substrate 110 and the floating gate FG1. In one embodiment, the first dielectric layer 121 may be referred to as a tunneling layer.

[0059] In one embodiment, the number of the floating gates FG1 may be multiple, and a part of the control gate CG may be located between two adjacent floating gates FG1.

[0060] In one embodiment, the first region (i.e., the doped portion 141) covers the upper region 134 of the second region (i.e., the conductive portion 130). In one embodiment, the isolation structure 123 may laterally cover the lower region (i.e., the portion corresponding to the upper region 134) of the second region (i.e., the conductive portion 130).

[0061] In one embodiment, the first region (i.e., the doped portion 141) covers the upper region 134 of the second region (i.e., the conductive portion 130), and a part of the control gate CG may be located between two adjacent floating gates FG1. In this way, in subsequent applications, the gate coupling ratio (GCR) can be more effectively improved. In one embodiment, the position of the maximum width (e.g., the maximum width Wx) of the floating gate FG1 corresponds to the first region (i.e., the doped portion 141).

[0062] Figure 2 It is a partial cross-sectional schematic diagram of a gate structure according to the second embodiment of the present invention.

[0063] Please refer to Figure 2 , the gate structure 200 may include at least one floating gate FG2, a second dielectric layer 122, and a control gate CG. The second dielectric layer 122 is located between the floating gate FG2 and the control gate CG. The floating gate FG2 has a first region (i.e., the doped portion 241) and a second region (i.e., the conductive portion 130). The first region is located between the second region and the second dielectric layer 122. The energy band gap of the first region (i.e., the doped portion 241) is smaller than the energy band gap of the second region (i.e., the conductive portion 130).

[0064] The material or formation method of the doped portion 241 may be the same as or similar to that of the aforementioned doped portion 141 (e.g., Figure 1C or Figure 1D ), with the difference being the topography. In a cross-section (e.g., Figure 2On the plane shown, the contour of the doped region 241 can be the same as or similar to a pentagon or a hexagon. For example, the contour of the doped region 241 can be similar to a pentagon or a hexagon with rounded or arc-shaped corners; and / or, the bottom of the pentagon or hexagon (i.e., corresponding to the upper covering region 134) is replaced by a corresponding virtual contour.

[0065] In other possible or unshown embodiments, the cross-sectional contour of the doped region can be the same as or similar to other polygons.

[0066] Figures 3A to 3C FIG. is a partial cross-sectional schematic view of a method for manufacturing a gate structure according to a third embodiment of the present invention. The manufacturing method of the gate structure 300 in this embodiment is similar to the manufacturing method of the gate structure 100 in the foregoing embodiment. Similar components are denoted by the same reference numerals, and have similar functions, materials, or formation methods, and the description thereof is omitted.

[0067] Please refer to Figure 3A , corresponding film layers can be formed on the substrate 110 through appropriate semiconductor manufacturing processes. For example, a first dielectric layer 121, a first conductive layer 130, a quantum well layer 342, and a hard mask layer 180 can be formed.

[0068] The quantum well layer can be formed through appropriate semiconductor manufacturing processes (such as, but not limited to, deposition). The quantum well layer includes a plurality of well layers 342a and a plurality of barrier layers 342b that are alternately arranged in a repeating manner, and the well layer 342a and the barrier layer 342b are basically thin layers with a thickness of less than 10 nm. For example, the material of the quantum well layer 342 is, for example, a multi-layer structure including alternately stacked silicon layers and silicon germanium layers (Si / SiGe). By designing the element ratio, the number of thin layers, and the thickness of the thin layers in the quantum well layer 342, the quantum well layer 342 can have a corresponding energy band gap. It should be noted that the thin layers of the quantum well layer 342 exemplified above are only examples, and the thin layers of the quantum well layer 342 in the embodiments of the present invention are not limited to the combination of silicon layers and silicon germanium layers. The overall energy band gap of the quantum well layer 342 is basically smaller than the energy band gap of the first conductive layer 130.

[0069] Please refer to Figures 3A to 3B , it can be the same as or similar to Figures 1A to 1BThe trench T is formed in the following manner. The trench T can penetrate through the film layers on the substrate 110 (such as the first dielectric layer 121, the first conductive layer 130, the quantum well layer 342, and the hard mask layer 180). Moreover, the trench T can extend downward further so that there are corresponding depressions on the surface of the substrate 110. Then, an isolation structure 123 is formed in the trench T. During the formation of the isolation structure 123, the hard mask layer 180 (illustrated in Figure 1A ) can be removed correspondingly. The isolation structure 123 basically does not cover the quantum well layer 342.

[0070] Each fin-shaped conductive part 130 and the quantum well layer 342 located thereon can form a corresponding conductor FG3. That is to say, the conductor FG3 can include the conductive part 130 and the quantum well layer 342. The quantum well layer 342 is located on the conductive part 130. The overall energy band gap of the quantum well layer 342 is smaller than the energy band gap of the conductive part 130.

[0071] Please refer to Figures 3B to 3C , and corresponding film layers can be formed on the substrate 110 in a manner the same as or similar to Figures 1C to 1D . For example, a second dielectric layer 122 and a second conductive layer 150 can be formed.

[0072] In one embodiment, the conductor FG3 can be used as an electrode. Additionally, taking the embodiment where the conductor FG3 is used as a floating gate as an example, a part of the second conductive layer 150 corresponding to the conductor FG3 can be used as the control gate CG. For example, the conductor FG3 can be the floating gate of a floating gate transistor. Additionally, for the sake of simplicity, the conductor FG3 serving as the floating gate and the floating gate may use the same marking symbol.

[0073] After the above manufacturing process, the manufacturing of the gate structure 300 of this embodiment can be substantially completed.

[0074] Please refer to Figure 3C , the gate structure 300 can include at least one floating gate FG3, a second dielectric layer 122, and a control gate CG. The second dielectric layer 122 is located between the floating gate FG3 and the control gate CG. The floating gate FG3 has a first region (i.e., the quantum well layer 342) and a second region (i.e., the conductive part 130). The first region is located between the second region and the second dielectric layer 122. The energy band gap of the first region (i.e., the quantum well layer 342) is smaller than the energy band gap of the second region (i.e., the conductive part 130).

[0075] In one embodiment, the gate structure 300 can further include a substrate 110 and a first dielectric layer 121. The first dielectric layer 121, the floating gate FG3, the second dielectric layer 122, and the control gate CG are located on the substrate 110. The first dielectric layer 121 is located between the substrate 110 and the floating gate FG3.

[0076] In one embodiment, the number of floating gates FG3 can be multiple, and a part of the control gate CG can be located between two adjacent floating gates FG3.

[0077] In one embodiment, the first region (i.e., the quantum well layer 342) is located on the upper region 134 of the second region (i.e., the conductive portion 130).

[0078] In one embodiment, the thickness of the first region (i.e., the quantum well layer 342) accounts for about 10% to 30% of the overall thickness of the floating gate FG3, but the present invention is not limited thereto.

[0079] In one embodiment, the foregoing gate structure 100, gate structure 200, or gate structure 300 can be a part of a floating gate transistor (FGT). For example, the foregoing floating gates FG1, FG2, or FG3 can be the floating gates of the floating gate transistor, and the control gate CG can be the control gate of the floating gate transistor. The types of the foregoing floating gate transistors can include, for example, floating gate metal oxide semiconductor field effect transistors (FGMOS). In application, the floating gate can be used in a floating gate memory (FGM), which can include but is not limited to: Erasable Programmable Read Only Memory or Flash Memory. And, since in the corresponding gate structure (such as: gate structure 100, gate structure 200, or gate structure 300), the energy band gap of the first region (i.e., the doped portion 141, doped portion 241, or quantum well layer 342) is smaller than the energy band gap of the second region (i.e., the conductive portion 130). In this way, for the application of the floating gate memory, the corresponding data retention ability may be improved. For example, the first region (i.e., the doped portion 141, doped portion 241, or quantum well layer 342) may be more capable of constraining the corresponding charges (such as electrons) therein.

[0080] In addition, in the foregoing embodiment, the described film layer can be a single-layer structure or a multi-layer structure. And if it is a stack of multi-layer structures, there may be no other materials with other properties between the foregoing multi-layer structures. For example, the conductive layer can be a single layer or a multi-layer structure; and if it is a multi-layer conductive layer, there may be no insulating or dielectric materials between the foregoing multi-layer structures. Another example is that the dielectric layer can be a single layer or a multi-layer structure; and if it is a multi-layer dielectric layer, there may be no conductive materials between the foregoing multi-layer structures.

[0081] In addition, the structures in the foregoing embodiments may be combined or integrated according to requirements. For example, in a structure (such as a floating gate memory), a certain cross-section may have the same or similar structure as that Figure 1D shown; another cross-section may have the same or similar structure as that Figure 2 shown; and / or, still another cross-section may have the same or similar structure as that Figure 3C shown.

[0082] In summary, through the first region with a smaller band gap (compared with the second region), the gate structure of the present invention can enable the corresponding device (such as a floating gate memory) to have better quality.

Claims

1. A gate structure, comprising: at least one floating gate having a first region and a second region; a control gate; and a second dielectric layer located between the floating gate and the control gate, wherein: the first region is located between the second region and the second dielectric layer; and the energy band gap of the first region is smaller than that of the second region.

2. The gate structure according to claim 1, further comprising: a substrate; and a first dielectric layer, the first dielectric layer, the floating gate, the second dielectric layer, and the control gate are located on the substrate, and the first dielectric layer is located between the substrate and the floating gate.

3. The gate structure according to claim 1, wherein the number of the floating gates is multiple, and a part of the control gate is located between two adjacent floating gates.

4. The gate structure according to claim 1, wherein the first region is a doped portion formed by an epitaxial growth manufacturing process.

5. The gate structure according to claim 1 or 4, wherein the first region covers an upper region of the second region.

6. The gate structure according to claim 5, wherein the maximum width of the floating gate corresponds to the first region.

7. The gate structure according to claim 1, wherein the first region is a quantum well layer.

8. The gate structure according to claim 1 or 7, wherein the first region is located on an upper region of the second region.

9. A floating gate memory, comprising: the gate structure according to claim 1.

10. The floating gate memory according to claim 9, wherein the number of the floating gates is multiple, the control gate corresponds to the multiple floating gates, and the control gate is electrically connected to a word line.

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