Packaging structure of H-bridge circuit and motor control system

Abstract

The invention discloses a packaging structure of an H-bridge circuit and a motor control system. The packaging structure comprises a first base island, a second base island, a third base island, a fourth base island, a fifth base island, a first pin, a second pin, a third pin, a fourth pin, a first field effect transistor, a second field effect transistor, a third field effect transistor and a fourth field effect transistor. The first field effect transistor, the second field effect transistor, the third field effect transistor and the fourth field effect transistor are arranged into a rectangle, the third field effect transistor and the fourth field effect transistor are inversely arranged when the first field effect transistor and the second field effect transistor are positively arranged, or the third field effect transistor and the fourth field effect transistor are positively arranged when the first field effect transistor and the second field effect transistor are inversely arranged; therefore, the purpose of packaging the H-bridge circuit in a compact space can be achieved, the H-bridge circuit packaging structure has the advantages of being simple in wire arrangement and reasonable in layout, and the requirements for high integration and high density of an integrated circuit are met.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, and particularly to a packaging structure of an H-bridge circuit and a motor control system. Background Art

[0002] Brushed motors are widely used in the electronic field and the mechanical field. For example, a brushed motor can be used to realize the lifting of a car window or the movement of an electric seat. In industrial design, a brushed motor that realizes periodic forward and reverse rotation needs to be implemented through an H-bridge circuit. Specifically, the brushed motor is connected between two bridge arms of the H-bridge circuit. By controlling the four switching tubes in the H-bridge circuit, the periodic change of the current in the brushed motor can be controlled, thereby realizing the periodic forward and reverse rotation of the brushed motor.

[0003] In the prior art, when packaging the H-bridge circuit, four MOS single tubes or two half-bridges are usually used for packaging. However, both of the above two packaging methods have the problems of low integration and complex wire arrangement, and cannot adapt to the development trend of high density and high integration of existing integrated circuits. Therefore, how to design a packaging structure of an H-bridge circuit with simple wire arrangement and high integration has become one of the problems that need to be solved urgently by those skilled in the art.

[0004] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solution of the present invention and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present invention. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a packaging structure of an H-bridge circuit and a motor control system, which are used to solve the problems of large size, complex wiring and low integration of the packaging structure of the H-bridge circuit in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a packaging structure for an H-bridge circuit. The packaging structure of the H-bridge circuit at least includes: first, second, third, fourth, and fifth base islands, first, second, third, and fourth pins, and first, second, third, and fourth field-effect transistors; the first field-effect transistor and the second field-effect transistor are arranged in a first direction, and the third field-effect transistor and the fourth field-effect transistor are arranged in the first direction; the first field-effect transistor and the third field-effect transistor are arranged in a second direction, and the second field-effect transistor and the fourth field-effect transistor are arranged in the second direction, and the first direction and the second direction are perpendicular to each other; each field-effect transistor is an NMOS transistor, and the drain of each field-effect transistor is provided on the first surface of each field-effect transistor, and the gate and the source are provided on the second surface opposite to the first surface; the drain of the first field-effect transistor is welded to the first base island and electrically connected to the first base island, the gate is led out to the first pin, and the source is led out to the second pin; the drain of the second field-effect transistor is welded to the first base island and electrically connected to the first base island, the gate is led out to the third pin, and the source is led out to the fourth pin; the drain of the third field-effect transistor is led out to the second pin, the gate is welded to the second base island and electrically connected to the second base island, and the source is welded to the third base island and electrically connected to the third base island; the drain of the fourth field-effect transistor is led out to the fourth pin, the gate is welded to the fourth base island and electrically connected to the fourth base island, and the source is welded to the fifth base island and electrically connected to the fifth base island.

[0007] Optionally, the third base island and the fifth base island are connected by a wire; or the third base island and the fifth base island are combined into the same base island.

[0008] Optionally, the first pin, the second pin, the third pin, and the fourth pin are located on the first side of the first base island; the second base island, the third base island, the fourth base island, and the fifth base island are located on the second side of the first base island; the first side and the second side are opposite to each other.

[0009] More optionally, the first pin, the second pin, the third pin, and the fourth pin are arranged in the first direction, and the second base island, the third base island, the fourth base island, and the fifth base island are arranged in the first direction.

[0010] To achieve the above and other related objectives, the present invention also provides a packaging structure for an H-bridge circuit. The packaging structure of the H-bridge circuit at least includes: first, second, third, fourth, and fifth base islands, first, second, third, and fourth pins, and first, second, third, and fourth field effect transistors; the first field effect transistor and the second field effect transistor are arranged in a first direction, and the third field effect transistor and the fourth field effect transistor are arranged in the first direction; the first field effect transistor and the third field effect transistor are arranged in a second direction, and the second field effect transistor and the fourth field effect transistor are arranged in the second direction, and the first direction and the second direction are perpendicular to each other; each field effect transistor is a PMOS transistor, and the drain of each field effect transistor is arranged on the first surface of the first field effect transistor, and the gate and the source are arranged on the second surface opposite to the first surface; the drain of the first field effect transistor is led out to the first pin, the gate is welded on the second base island and electrically connected to the second base island, and the source is welded on the first base island and electrically connected to the first base island; the drain of the second field effect transistor is led out to the second pin, the gate is welded on the third base island and electrically connected to the third base island, and the source is welded on the first base island and electrically connected to the first base island; the drain of the third field effect transistor is welded on the fourth base island and electrically connected to the fourth base island, the gate is led out to the third pin, and the source is led out to the first pin; the drain of the fourth field effect transistor is welded on the fifth base island and electrically connected to the fifth base island, the gate is led out to the fourth pin, and the source is led out to the second pin.

[0011] Optionally, the fourth base island and the fifth base island are connected by a wire; or the fourth base island and the fifth base island are combined into the same base island.

[0012] Optionally, the second base island, the first pin, the third base island, and the second pin are located on the first side of the first base island; the third pin, the fourth base island, the fourth pin, and the fifth base island are located on the second side of the first base island; the first side and the second side are opposite to each other.

[0013] More optionally, the second base island, the first pin, the third base island, and the second pin are arranged in the first direction, and the third pin, the fourth base island, the fourth pin, and the fifth base island are arranged in the first direction.

[0014] To achieve the above and other related objectives, the present invention also provides a motor control system. The motor control system includes: a control module and the packaging structure of the H-bridge circuit; the control module provides control signals for the first field effect transistor, the second field effect transistor, the third field effect transistor, and the fourth field effect transistor.

[0015] As described above, the packaging structure of the H-bridge circuit and the motor control system of the present invention have the following beneficial effects:

[0016] 1. By arranging the first field-effect transistor, the second field-effect transistor, the third field-effect transistor, and the fourth field-effect transistor in a rectangle, and when the first field-effect transistor and the second field-effect transistor are mounted upright, the third field-effect transistor and the fourth field-effect transistor are mounted upside down, or when the first field-effect transistor and the second field-effect transistor are mounted upside down, the third field-effect transistor and the fourth field-effect transistor are mounted upright, the present invention achieves the purpose of packaging the H-bridge circuit in a compact space and has simple wire arrangement.

[0017] 2. According to the different types of field-effect transistors, the second base island, the third base island, the fourth base island, the fifth base island, the first pin, the second pin, the third pin, and the fourth pin are grouped, and the grouped above-mentioned base islands and / or pins are arranged on both sides of the first base island. The present invention can make the layout of the packaging structure of the H-bridge circuit more compact and improve the integration degree of the packaging structure of the H-bridge circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It shows the first structural schematic diagram of the packaging structure of the H-bridge circuit of the present invention.

[0019] Figure 2 It shows the first installation schematic diagram of the first and second field-effect transistors of the present invention.

[0020] Figure 3 It shows the first structural schematic diagram of each base island and each pin of the present invention.

[0021] Figure 4 It shows the first circuit schematic diagram of the packaging structure of the H-bridge circuit of the present invention.

[0022] Figure 5 It shows the first installation schematic diagram of the third and fourth field-effect transistors of the present invention.

[0023] Figure 6 It shows the second circuit schematic diagram of the packaging structure of the H-bridge circuit of the present invention.

[0024] Figure 7 It shows the second structural schematic diagram of the packaging structure of the H-bridge circuit of the present invention.

[0025] Figure 8 It shows the third structural schematic diagram of the packaging structure of the H-bridge circuit of the present invention.

[0026] Figure 9 It shows the fourth structural schematic diagram of the packaging structure of the H-bridge circuit of the present invention.

[0027] Figure 10Shown is the second installation schematic diagram of the first and second field effect transistors of the present invention.

[0028] Figure 11 Shown is the second structural schematic diagram of each base island and each pin of the present invention.

[0029] Figure 12 Shown is the third circuit schematic diagram of the package structure of the H-bridge circuit of the present invention.

[0030] Figure 13 Shown is the second installation schematic diagram of the third and fourth field effect transistors of the present invention.

[0031] Figure 14 Shown is the fourth circuit schematic diagram of the package structure of the H-bridge circuit of the present invention.

[0032] Figure 15 Shown is the fifth structural schematic diagram of the package structure of the H-bridge circuit of the present invention.

[0033] Figure 16 Shown is the sixth structural schematic diagram of the package structure of the H-bridge circuit of the present invention.

[0034] Figure 17 Shown is the structural schematic diagram of the motor control system of the present invention.

[0035] Element label description

[0036] 1a First base island

[0037] 1b Second base island

[0038] 1c Third base island

[0039] 1d Fourth base island

[0040] 1e Fifth base island

[0041] 2a First pin

[0042] 2b Second pin

[0043] 2c Third pin

[0044] 2d Fourth pin

[0045] 3a First field effect transistor

[0046] 3b Second field effect transistor

[0047] 3c Third field effect transistor

[0048] 3d Fourth field effect transistor Detailed implementation manners

[0049] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0050] Please refer to Figures 1 - 17 . It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0051] The H-bridge circuit is a very important circuit structure. In order to package the H-bridge circuit, there is a method that uses four MOS transistors to build an H-bridge, and there is another method that uses two half-bridge packages to build an H-bridge. However, when both of the above two packaging methods adopt the PDFN5x6 packaging technology (the packaging size adopted by the PDFN5x6 packaging technology is 5mm * 6mm): The building method using four MOS transistors will make the size of the PCB board reach 12mm * 14mm; the building method using two existing half-bridge packages will make the size of the PCB board reach 5mm * 14mm. Thus, the above two packaging methods will bring the following three problems: First, whether the size is 12mm * 14mm or 5mm * 14mm, a large amount of PCB space is required; Second, both of the above two packaging methods need to be connected through complex PCB board traces, resulting in a lot of parasitic parameters (such as parasitic inductance, parasitic capacitance, and parasitic resistance, etc.) being introduced by the PCB circuit traces. These parasitic parameters exist in the circuit and will affect the overall efficiency and overall power consumption of the circuit; Third, the integration degree of the above two packaging methods is relatively low, which does not conform to the development trend of high density and high integration of integrated circuits. Therefore, in order to solve the above problems, the present invention provides a packaging structure of an H-bridge circuit and a motor control system. The specific technical solutions are as follows:

[0052] Embodiment 1

[0053] As Figure 1 shown, this embodiment provides a packaging structure of an H-bridge circuit, including: a first base island 1a, a second base island 1b, a third base island 1c, a fourth base island 1d, a fifth base island 1e, a first pin 2a, a second pin 2b, a third pin 2c, a fourth pin 2d, and a first field-effect transistor 3a, a second field-effect transistor 3b, a third field-effect transistor 3c, a fourth field-effect transistor 3d.

[0054] As Figure 1As shown, the first field effect transistor 3a and the second field effect transistor 3b are arranged in the first direction, and the third field effect transistor 3c and the fourth field effect transistor 3d are arranged in the first direction; the first field effect transistor 3a and the third field effect transistor 3c are arranged in the second direction, and the second field effect transistor 3b and the fourth field effect transistor 3d are arranged in the second direction, and the first direction and the second direction are perpendicular to each other.

[0055] Specifically, in this embodiment, as Figure 1 shown, the first field effect transistor 3a (Q1), the second field effect transistor 3b (Q2), the third field effect transistor 3c (Q3) and the fourth field effect transistor 3d (Q4) can be arranged in a rectangular distribution, aiming to make the first, second, third and fourth field effect transistors as close as possible, saving space on the PCB board, so as to facilitate the subsequent integration of the H-bridge circuit. In practical applications, the specific spatial directions of the first direction and the second direction can be selected according to actual needs, which will not be elaborated here.

[0056] As Figure 1 shown, each field effect transistor is an NMOS transistor, and the drain of each field effect transistor is arranged on the first surface of each field effect transistor, and the gate and the source are arranged on the second surface opposite to the first surface.

[0057] Specifically, in this embodiment, in the existing processing technology of field effect transistors, the drain is usually not processed on the same surface of the device as the source and the gate, because the drain usually requires high-concentration doping or special metallization treatment, and processing the drain separately on one surface of the device can avoid process conflicts with the source and the gate.

[0058] As Figure 1 shown, the drain of the first field effect transistor 3a is welded to and electrically connected to the first base island 1a, the gate is led out to the first pin 2a, and the source is led out to the second pin 2b.

[0059] Specifically, in this embodiment, the first field effect transistor 3a is an NMOS transistor. As Figure 2 shown, the first field effect transistor 3a is mounted in a normal way. Further, as Figure 3 shown, the drain of the first field effect transistor 3a is welded to the first base island 1a, and the gate and the source of the first field effect transistor 3a both face away from the first base island 1a. Therefore, the source and the gate need to be led out to the first pin 2a and the second pin 2b respectively. As an example, the gate and the source of the first field effect transistor 3a can both be led out by wire bonding. In practical applications, the specific leading-out methods of the gate and the source of the first field effect transistor 3a can be selected according to actual needs, not limited to this embodiment.

[0060] As Figure 1As shown, the drain of the second field effect transistor 3b is soldered to the first base island 1a and electrically connected to the first base island 1a. The gate is led out to the third pin 2c, and the source is led out to the fourth pin 2d.

[0061] Specifically, in this embodiment, the second field effect transistor 3b is an NMOS transistor, as Figure 2 shown. The second field effect transistor 3b is mounted right side up. Further, as Figure 3 shown, the drain of the second field effect transistor 3b is soldered to the first base island 1a (as Figure 4 shown, the drain of the first field effect transistor 3a is connected to the drain of the second field effect transistor 3b). Additionally, the gate and source of the second field effect transistor 3b face away from the first base island 1a. Therefore, the gate and source need to be led out to the third pin 2c and the fourth pin 2d respectively. As an example, both the gate and source of the second field effect transistor 3b can be led out by wire bonding. In practical applications, the specific lead-out methods of the gate and source of the second field effect transistor 3b can be selected according to actual needs, not limited to this embodiment.

[0062] As Figure 1 shown, the drain of the third field effect transistor 3c is led out to the second pin 2b. The gate is soldered to the second base island 1b and electrically connected to the second base island 1b. The source is soldered to the third base island 1c and electrically connected to the third base island 1c.

[0063] Specifically, in this embodiment, the third field effect transistor 3c is an NMOS transistor, as Figure 5 shown. The third field effect transistor 3c is mounted upside down. Further, as Figure 3 shown, the gate of the third field effect transistor 3c is soldered to the second base island 1b, and the source is electrically soldered to the third base island 1c. At the same time, the drain of the third field effect transistor 3c faces away from the second base island 1b and the third base island 1c, and the drain needs to be led out to the second pin 2b (as Figure 4 shown, the source of the first field effect transistor 3a is connected to the drain of the third field effect transistor 3c, and one end (point A) of the motor is connected to the second pin 2b). As an example, the drain of the third field effect transistor 3c can be directly wire-bonded to the second pin 2b, or the drain of the third field effect transistor 3c and the source of the first field effect transistor 3a can both be led to the second pin 2b through a copper clip. In practical applications, the specific lead-out method of the drain of the third field effect transistor 3c can be selected according to actual needs, not limited to this embodiment.

[0064] As Figure 1 shown, the drain of the fourth field effect transistor 3d is led out to the fourth pin 2d. The gate is soldered to the fourth base island 1d and electrically connected to the fourth base island 1d. The source is soldered to the fifth base island 1e and electrically connected to the fifth base island 1e.

[0065] Specifically, in this embodiment, the fourth field-effect transistor 3d is an NMOS transistor. As shown in Figure 5 , the fourth field-effect transistor 3d is flip-chip mounted. Further, as shown in Figure 3 , the gate of the fourth field-effect transistor 3d is welded to the fourth base island 1d, and the source is welded to the fifth base island 1e. At the same time, the drain of the fourth field-effect transistor 3d faces away from the fourth base island 1d and the fifth base island 1e, and the drain needs to be led out to the fourth pin 2d (as shown in Figure 4 , the source of the second field-effect transistor 3b is connected to the drain of the fourth field-effect transistor 3d, and the other end (point B) of the motor is connected to the fourth pin 2d). As an example, the drain of the fourth field-effect transistor 3d can be directly wire-bonded to the fourth pin 2d, or the drain of the fourth field-effect transistor 3d and the source of the second field-effect transistor 3b can be led to the fourth pin 2d through a copper clip. In practical applications, the specific way of leading out the drain of the fourth field-effect transistor 3d can be selected according to actual needs, and this embodiment is not limiting.

[0066] Specifically, in this embodiment, to make the use of the H-bridge circuit more convenient, as shown in Figure 6 , the source of the third field-effect transistor 3c and the source of the fourth field-effect transistor 3d can be connected. Therefore, as shown in Figure 7 , in this embodiment, the third base island 1c and the fifth base island 1e can be connected by a wire; as shown in Figure 8 , in this embodiment, the third base island 1c and the fifth base island 1e can also be combined into the same base island. In practical applications, the way of connecting the source of the third field-effect transistor 3c and the source of the fourth field-effect transistor 3d can be selected according to needs, and this embodiment is not limiting.

[0067] Specifically, in this embodiment, as shown in Figure 1 , to make the wire arrangement of the packaging structure of the H-bridge circuit simpler, the first pin 2a, the second pin 2b, the third pin 2c, and the fourth pin 2d are located on the first side of the first base island 1a; the second base island 1b, the third base island 1c, the fourth base island 1d, and the fifth base island 1e are located on the second side of the first base island 1a; the first side of the first base island 1a and the second side of the first base island 1a are arranged opposite to each other. Further, to make the wire arrangement of the H-bridge circuit more concise, the first pin 2a, the second pin 2b, the third pin 2c, and the fourth pin 2d are arranged in the first direction, and the second base island 1b, the third base island 1c, the fourth base island 1d, and the fifth base island 1e are arranged in the first direction. As an example, as shown in Figure 3 , the first pin 2a, the second pin 2b, the third pin 2c, and the fourth pin 2d are arranged in sequence, and the second base island 1b, the third base island 1c, the fourth base island 1d, and the fifth base island 1e are arranged in sequence. In practical applications, the arrangement positions and arrangement orders of each pin and each base island can be designed according to actual needs, and this embodiment is not limiting.

[0068] Embodiment 2

[0069] like Figure 9 As shown, this embodiment provides a packaging structure of an H-bridge circuit, including: a first base island 1a, a second base island 1b, a third base island 1c, a fourth base island 1d, a fifth base island 1e, a first pin 2a, a second pin 2b, a third pin 2c, a fourth pin 2d, and a first field effect transistor 3a, a second field effect transistor 3b, a third field effect transistor 3c, and a fourth field effect transistor 3d.

[0070] like Figure 9 As shown, the first field effect transistor 3a and the second field effect transistor 3b are arranged in the first direction, and the third field effect transistor 3c and the fourth field effect transistor 3d are arranged in the first direction; the first field effect transistor 3a and the third field effect transistor 3c are arranged in the second direction, and the second field effect transistor 3b and the fourth field effect transistor 3d are arranged in the second direction, and the first direction and the second direction are perpendicular to each other.

[0071] Specifically, in this embodiment, the first field effect transistor 3a (Q1), the second field effect transistor 3b (Q2), the third field effect transistor 3c (Q3), and the fourth field effect transistor 3d (Q4) can be arranged in a rectangular shape, such as Figure 9 As shown, the first direction and the second direction are perpendicular to each other. In practical applications, the specific spatial orientations of the first direction and the second direction can be selected according to actual needs, which will not be elaborated here.

[0072] like Figure 9 As shown, each field effect tube is a PMOS tube, and the drain of each field effect tube is arranged on the first surface of the first field effect tube, and the gate and the source are arranged on the second surface arranged opposite to the first surface.

[0073] Specifically, in this embodiment, regardless of whether it is an NMOS tube or a PMOS tube, the drain needs to be processed separately on one side of the field effect tube. The reason for processing the PMOS tube in this way is the same as that of the NMOS tube, which will not be repeated here.

[0074] like Figure 9 As shown, the drain of the first field effect transistor 3a is led to the first pin 2a, the gate is welded on the second base island 1b and electrically connected to the second base island 1b, and the source is welded on the first base island 1a and electrically connected to the first base island 1a.

[0075] Specifically, in this embodiment, the first field effect transistor 3a is a PMOS transistor. Figure 10 As shown, the first field effect transistor 3a is flipped. Figure 11As shown, the source of the first field effect tube 3a is welded on the first base island 1a, the gate is welded on the second base island 1b, and the drain is facing away from the first base island 1a and the second base island 1b, so the drain of the first field effect tube 3a needs to be led out to the first pin 2a. As an example, the drain of the first field effect tube 3a can be led out by wire bonding. In actual applications, the specific lead-out method of the drain of the first field effect tube 3a is selected according to actual needs, and is not limited to this embodiment.

[0076] like Figure 9 As shown, the drain of the second field effect transistor 3b is led to the second pin 2b, the gate is welded on the third base island 1c and electrically connected to the third base island 1c, and the source is welded on the first base island 1a and electrically connected to the first base island 1a.

[0077] Specifically, in this embodiment, the second field effect transistor 3b is a PMOS transistor, such as Figure 10 As shown, the second field effect transistor 3b is flipped. Figure 11 As shown, the source of the second field effect tube 3b is welded on the first base island 1a (as shown in FIG. Figure 12 As shown, the source of the first field effect tube 3a is connected to the source of the second field effect tube 3b, the gate is welded on the third base island 1c, and the drain is facing away from the first base island 1a and the third base island 1c, so the drain of the second field effect tube 3b needs to be led out to the second pin 2b. As an example, the drain of the second field effect tube 3b can be led out by wire bonding. In actual applications, the specific lead-out method of the drain of the second field effect tube 3b is selected according to actual needs, and is not limited to this embodiment.

[0078] like Figure 9 As shown, the drain of the third field effect tube 3c is welded on the fourth base island 1d and electrically connected to the fourth base island 1d, the gate is led to the third pin 2c, and the source is led to the first pin 2a.

[0079] Specifically, in this embodiment, the third field effect transistor 3c is a PMOS transistor. Figure 13 As shown, the third field effect tube 3c is installed in a normal direction. Figure 11 As shown, the drain of the third field effect tube 3c is welded on the fourth base island 1d, and the gate and source are facing away from the fourth base island 1d. Therefore, the gate of the third field effect tube 3c needs to be led to the third pin 2c, and the source is led to the first pin 2a (such as Figure 12As shown, the drain of the first field-effect transistor 3a is connected to the source of the third field-effect transistor 3c, and one end (point A) of the motor is connected to the first pin 2a). As an example, the source of the third field-effect transistor 3c can be directly wire-bonded to the first pin 2a, or the source of the third field-effect transistor 3c and the drain of the first field-effect transistor 3a can be led to the first pin 2a through a copper clip. In practical applications, the specific way of leading out the source of the third field-effect transistor 3c can be selected according to actual needs, and is not limited to this embodiment.

[0080] As Figure 9 shown, the drain of the fourth field-effect transistor 3d is welded to the fifth base island 1e and electrically connected to the fifth base island 1e, the gate is led out to the fourth pin 2d, and the source is led out to the second pin 2b.

[0081] Specifically, in this embodiment, the fourth field-effect transistor 3d is a PMOS transistor. As Figure 13 shown, the fourth field-effect transistor 3d is face-up. Further, as Figure 11 shown, the drain of the fourth field-effect transistor 3d is welded to the fifth base island 1e, and the gate and the source face away from the fifth base island 1e. Therefore, the gate of the fourth field-effect transistor 3d needs to be led out to the fourth pin 2d, and the source is led out to the second pin 2b (as Figure 12 shown, the drain of the second field-effect transistor 3b is connected to the source of the fourth field-effect transistor 3d, and the other end (point B) of the motor is connected to the second pin 2b). As an example, the source of the fourth field-effect transistor 3d can be directly wire-bonded to the second pin 2b, or the source of the fourth field-effect transistor 3d and the drain of the second field-effect transistor 3b can be led to the second pin 2b through a copper clip. In practical applications, the specific way of leading out the source of the fourth field-effect transistor 3d can be selected according to actual needs, and is not limited to this embodiment.

[0082] Specifically, in this embodiment, in order to make the use of the H-bridge circuit more convenient, as Figure 14 shown, the drains of the third field-effect transistor 3c and the fourth field-effect transistor 3d can be connected. Therefore, as Figure 15 shown, in this embodiment, the fourth base island 1d and the fifth base island 1e can be connected by a wire; as Figure 16 shown, in this embodiment, the fourth base island 1d and the fifth base island 1e can also be combined into the same base island. In practical applications, the way of connecting the drains of the third field-effect transistor 3c and the fourth field-effect transistor 3d is selected according to needs, and is not limited to this embodiment.

[0083] Specifically, in this embodiment, as Figure 9As shown, in order to simplify the wire arrangement of the packaging structure of the H-bridge circuit, the second base island 1b, the first pin 2a, the third base island 1c, and the second pin 2b are located on the first side of the first base island 1a; the third pin 2c, the fourth base island 1d, the fourth pin 2d, and the fifth base island 1e are located on the second side of the first base island 1a; the first side and the second side of the first base island 1a are arranged opposite to each other. Further, in order to make the wire arrangement of the packaging structure more concise, the second base island 1b, the first pin 2a, the third base island 1c, and the second pin 2b are arranged in the first direction, and the third pin 2c, the fourth base island 1d, the fourth pin 2d, and the fifth base island 1e are arranged in the first direction. As an example, as Figure 11 shown, the second base island 1b, the first pin 2a, the third base island 1c, and the second pin 2b are arranged in sequence, and the third pin 2c, the fourth base island 1d, the fourth pin 2d, and the fifth base island 1e are arranged in sequence. In practical applications, the arrangement positions and sequences of each pin and each base island are designed according to actual needs, and are not limited to this embodiment.

[0084] Embodiment 3

[0085] As Figure 17 shown, this embodiment provides a motor control system, which includes: a control module and a packaging structure of an H-bridge circuit; the control module provides control signals for the first field effect transistor 3a, the second field effect transistor 3b, the third field effect transistor 3c, and the fourth field effect transistor 3d.

[0086] Specifically, in this embodiment, the packaging structure of the H-bridge circuit can select the packaging structure of the H-bridge circuit in Embodiment 1 according to actual needs, or can also select the packaging structure of the H-bridge circuit in Embodiment 2, which is not limited here. Further, as Figure 4 、 Figure 6 、 Figure 12 、 Figure 14 shown, when the control module controls the first field effect transistor and the fourth field effect transistor to conduct, the current direction in the motor is set as the positive direction; when the control module controls the second field effect transistor and the third field effect transistor to conduct, the current direction in the motor is the reverse direction; therefore, through the control module, this embodiment can make the motor realize periodic forward and reverse rotations. In practical applications, the specific control method of the control module is designed according to actual needs, and is not limited to this embodiment.

[0087] In summary, the packaging structure of the H-bridge circuit and the motor control system of the present invention include the first, second, third, fourth, and fifth base islands, the first, second, third, and fourth pins, and the first, second, third, and fourth field effect transistors; in the present invention, the first, second, third, and fourth field effect transistors are arranged in a rectangle, and when the first and second field effect transistors are mounted upright, the third and fourth field effect transistors are mounted upside down, or when the first and second field effect transistors are mounted upside down, the third and fourth field effect transistors are mounted upright, so that the present invention can achieve the purpose of packaging the H-bridge circuit in a compact space, and the present invention has the advantages of simple wire arrangement and reasonable layout, meeting the requirements of high integration and high density of integrated circuits. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0088] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A packaging structure of an H-bridge circuit, characterized in that: The packaging structure of the H-bridge circuit at least includes: first, second, third, fourth, and fifth base islands, first, second, third, and fourth pins, and first, second, third, and fourth field effect transistors; The first field effect transistor and the second field effect transistor are arranged in a first direction, and the third field effect transistor and the fourth field effect transistor are arranged in the first direction; the first field effect transistor and the third field effect transistor are arranged in a second direction, and the second field effect transistor and the fourth field effect transistor are arranged in the second direction, and the first direction and the second direction are perpendicular to each other; Each field effect tube is an NMOS tube, and the drain of each field effect tube is arranged on the first surface of each field effect tube, and the gate and the source are arranged on the second surface arranged opposite to the first surface; The drain of the first field effect tube is welded on the first base island and electrically connected to the first base island, the gate is led to the first pin, and the source is led to the second pin; The drain of the second field effect tube is welded on the first base island and electrically connected to the first base island, the gate is led to the third pin, and the source is led to the fourth pin; The drain of the third field effect tube is led to the second pin, the gate is welded on the second base island and electrically connected to the second base island, and the source is welded on the third base island and electrically connected to the third base island; The drain of the fourth field effect transistor is led out to the fourth pin, the gate is welded on the fourth base island and electrically connected to the fourth base island, and the source is welded on the fifth base island and electrically connected to the fifth base island.

2. The packaging structure of the H-bridge circuit according to claim 1, characterized in that: The third base island is connected to the fifth base island through a wire; or the third base island is combined with the fifth base island into the same base island.

3. The packaging structure of the H-bridge circuit according to claim 1 or 2, characterized in that: The first pin, the second pin, the third pin and the fourth pin are located on a first side of the first base island; The second base island, the third base island, the fourth base island and the fifth base island are located on a second side of the first base island; the first side is arranged opposite to the second side.

4. The packaging structure of the H-bridge circuit according to claim 3, characterized in that: The first pin, the second pin, the third pin and the fourth pin are arranged in the first direction, and the second base island, the third base island, the fourth base island and the fifth base island are arranged in the first direction.

5. A packaging structure of an H-bridge circuit, characterized in that: The packaging structure of the H-bridge circuit at least includes: first, second, third, fourth, and fifth base islands, first, second, third, and fourth pins, and first, second, third, and fourth field effect transistors; The first field effect transistor and the second field effect transistor are arranged in a first direction, and the third field effect transistor and the fourth field effect transistor are arranged in the first direction; the first field effect transistor and the third field effect transistor are arranged in a second direction, and the second field effect transistor and the fourth field effect transistor are arranged in the second direction, and the first direction and the second direction are perpendicular to each other; Each field effect tube is a PMOS tube, and the drain of each field effect tube is arranged on the first surface of the first field effect tube, and the gate and the source are arranged on the second surface arranged opposite to the first surface; The drain of the first field effect tube is led out to the first pin, the gate is welded on the second base island and electrically connected to the second base island, and the source is welded on the first base island and electrically connected to the first base island; The drain of the second field effect transistor is led to the second pin, the gate is welded on the third base island and electrically connected to the third base island, and the source is welded on the first base island and electrically connected to the first base island; The drain of the third field effect tube is welded on the fourth base island and electrically connected to the fourth base island, the gate is led to the third pin, and the source is led to the first pin; The drain of the fourth field effect transistor is welded on the fifth base island and electrically connected to the fifth base island, the gate is led to the fourth pin, and the source is led to the second pin.

6. The packaging structure of the H-bridge circuit according to claim 4, characterized in that: The fourth base island is connected to the fifth base island through a wire; or the fourth base island is combined with the fifth base island into the same base island.

7. The packaging structure of the H-bridge circuit according to claim 5 or 6, characterized in that: The second base island, the first pin, the third base island and the second pin are located on a first side of the first base island; The third pin, the fourth base island, the fourth pin and the fifth base island are located on the second side of the first base island; the first side is arranged opposite to the second side.

8. The packaging structure of the H-bridge circuit according to claim 7, characterized in that: The second base island, the first pin, the third base island and the second pin are arranged in the first direction, and the third pin, the fourth base island, the fourth pin and the fifth base island are arranged in the first direction.

9. A motor control system, characterized in that: The motor control system comprises: a control module and a packaging structure of an H-bridge circuit as described in any one of claims 1 to 8; the control module provides control signals for the first field effect transistor, the second field effect transistor, the third field effect transistor and the fourth field effect transistor.

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