Semiconductor Devices and Power Equipment

Abstract

The semiconductor device and power device of the present disclosure include an N+ substrate; an N- epitaxial layer located above the N+ substrate; a drive circuit disposed in the N- epitaxial layer, the drive circuit including an inverting amplifier and a level converter, wherein the inverting amplifier is configured to amplify a first level signal and output it to the level converter, and the level converter is configured to convert the amplified first level signal into a second level signal; a vertical junction field effect transistor including a gate and a source disposed in the N- epitaxial layer, and a drain disposed on a side of the N+ substrate away from the N- epitaxial layer; the gate of the vertical junction field effect transistor is connected to the output terminal of the drive circuit, the source of the vertical junction field effect transistor is connected to a reference signal, and the drain of the vertical junction field effect transistor is connected to a load.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor device and a power device. Background Art

[0002] Power devices need to be driven by a drive circuit (also referred to as a drive buffer). However, in a main drive module of a new energy vehicle, for example, the drive circuit and the power device are in a spatially separated positional relationship, and an electrical connection needs to be achieved between the drive circuit and the power device through a relatively long connecting wire, resulting in a relatively large parasitic inductance of the gate-source loop formed by the drive circuit and the power device. Summary of the Invention

[0003] Embodiments of the present disclosure provide a semiconductor device and a power device to reduce the parasitic inductance of the gate-source loop and improve the driving performance.

[0004] The semiconductor device and the power device provided by the embodiments of the present disclosure are specifically as follows:

[0005] On the one hand, embodiments of the present disclosure provide a semiconductor device, including:

[0006] An N+ substrate;

[0007] An N- epitaxial layer, located on the N+ substrate;

[0008] A drive circuit, disposed in the N- epitaxial layer, the drive circuit including an inverting amplifier and a level converter, wherein the inverting amplifier is configured to amplify a first level signal and output it to the level converter, and the level converter is configured to convert the amplified first level signal into a second level signal;

[0009] A vertical junction field effect transistor, including a gate and a source disposed in the N- epitaxial layer, and a drain disposed on a side of the N+ substrate away from the N- epitaxial layer; the gate of the vertical junction field effect transistor is connected to the output end of the drive circuit, the source of the vertical junction field effect transistor accesses a reference signal, and the drain of the vertical junction field effect transistor is connected to a load.

[0010] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the N- epitaxial layer includes a first N- epitaxial layer, the first N- epitaxial layer includes a first part, the first part is provided with a first P+ top gate region and a first N+ source contact region, the first P+ top gate region is the gate of the vertical junction field effect transistor, and the first N+ source contact region is the source of the vertical junction field effect transistor.

[0011] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the inverter amplifier includes a first lateral junction field effect transistor and a first resistor;

[0012] The first N-epitaxial layer further includes a second part and a third part spaced apart from the first part, wherein the second part is provided with a second P+ top gate region, a second N+ source contact region, and a first N+ drain contact region, and the third part is provided with two first N+ resistor contact regions;

[0013] The second P+ top gate region is the gate of the first lateral junction field effect transistor, the second N+ source contact region is the source of the first lateral junction field effect transistor, the first N+ drain contact region is the drain of the first lateral junction field effect transistor, and the two first N+ resistor contact regions are the two ends of the first resistor.

[0014] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the level shifter includes a second lateral junction field effect transistor, a second resistor, and a third resistor;

[0015] The first N-epitaxial layer further includes a fourth part, a fifth part, and a sixth part spaced apart from the first part, the second part, and the third part; wherein the fourth part is provided with a third P+ top gate region, a third N+ source contact region, and a second N+ drain contact region, the fifth part is provided with two second N+ resistor contact regions, and the sixth part is provided with two third N+ resistor contact regions;

[0016] The third P+ top gate region is the gate of the second lateral junction field effect transistor, the third N+ source contact region is the source of the second lateral junction field effect transistor, the second N+ drain contact region is the drain of the second lateral junction field effect transistor, the two second N+ resistor contact regions are the two ends of the second resistor, and the two third N+ resistor contact regions are the two ends of the third resistor.

[0017] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, an interconnection metal layer is further included on the side of the N-epitaxial layer away from the N+ substrate;

[0018] The N-epitaxial layer further includes a second N-epitaxial layer located between the first N-epitaxial layer and the N+ substrate, the second N-epitaxial layer includes a P+ bottom gate region, and the first N-epitaxial layer further includes a first P+ connection region connected to the P+ bottom gate region;

[0019] The second P+ top gate region accesses the first level signal through the interconnecting metal layer. The second N+ source contact region and the first P+ connection region access the reference signal through the interconnecting metal layer. The first N+ drain contact region, the third P+ top gate region, and one of the first N+ resistor contact regions are electrically connected through the interconnecting metal layer. The other first N+ resistor contact region and the second N+ drain contact region are electrically connected to the output terminal of the first voltage power supply through the interconnecting metal layer. The third N+ source contact region and one of the second N+ resistor contact regions are electrically connected through the interconnecting metal layer. The other second N+ resistor contact region, one of the third N+ resistor contact regions, and the first P+ top gate region are electrically connected through the interconnecting metal layer. The other third N+ resistor contact region is electrically connected to the output terminal of the second voltage power supply through the interconnecting metal layer.

[0020] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, a dielectric layer is further included. The first part, the second part, the third part, the fourth part, the fifth part, and the sixth part are isolated from each other through the dielectric layer.

[0021] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the first N-epitaxial layer further includes a second P+ connection region. The first part, the second part, the third part, the fourth part, the fifth part, and the sixth part are isolated from each other through the second P+ connection region.

[0022] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the P+ bottom gate region is provided with an opening overlapping with the first P+ top gate region, and an N-type region is provided at the opening.

[0023] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the reverse breakdown voltages of the first lateral junction field effect transistor and the second lateral junction field effect transistor are greater than 20V. The threshold voltages of the first lateral junction field effect transistor and the second lateral junction field effect transistor are 0V to -20V. The resistance values of the first resistor, the second resistor, and the third resistor are the same.

[0024] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the drive circuit includes at least one sub-drive circuit, and the sub-drive circuit includes one of the inverting amplifiers and one of the level converters.

[0025] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the number of the sub-drive circuits is 1. The sub-drive circuit is connected to the output terminal of the level signal source, and the output terminal of the sub-drive circuit is the output terminal of the drive circuit.

[0026] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, there are n sub-driving circuits. The first sub-driving circuit is connected to the output terminal of a level signal source. The second level signal output by the m-th sub-driving circuit is the first level signal accessed by the (m + 1)-th sub-driving circuit. The output terminal of the n-th sub-driving circuit is the output terminal of the driving circuit, where n is an integer greater than or equal to 2, and m is an integer greater than or equal to 1 and less than n.

[0027] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, there is one vertical junction field effect transistor, and the source electrode of the vertical junction field effect transistor is grounded.

[0028] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, there are two sub-driving circuits. The two sub-driving circuits are connected to the output terminals of different level signal sources, and the output terminals of the two sub-driving circuits are the output terminals of the driving circuit.

[0029] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, there are two vertical junction field effect transistors. The source electrode of one vertical junction field effect transistor is grounded, and the drain electrode is connected to the source electrode of the other vertical junction field effect transistor.

[0030] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, one output terminal of the driving circuit is correspondingly connected to the gate electrode of one vertical junction field effect transistor.

[0031] On the other hand, the embodiments of the present disclosure provide a power device, including the above semiconductor device provided by the embodiments of the present disclosure.

[0032] The beneficial effects of the present disclosure are as follows:

[0033] The semiconductor device and power device provided by the embodiments of the present disclosure include an N+ substrate; an N- epitaxial layer located above the N+ substrate; a driving circuit disposed in the N- epitaxial layer, the driving circuit including an inverting amplifier and a level converter, wherein the inverting amplifier is configured to amplify a first level signal and output it to the level converter, and the level converter is configured to convert the amplified first level signal into a second level signal; a vertical junction field effect transistor including a gate and a source disposed in the N- epitaxial layer, and a drain disposed on a side of the N+ substrate away from the N- epitaxial layer; the gate of the vertical junction field effect transistor is connected to the output end of the driving circuit, the source of the vertical junction field effect transistor is connected to a reference signal, and the drain of the vertical junction field effect transistor is connected to a load. The vertical junction field effect transistor of the present disclosure is integrated on the same chip as the power device, effectively reducing the parasitic inductance of the gate-source loop formed by the driving circuit and the power device. Description of the Drawings

[0034] Figure 1 Schematic diagram of a semiconductor device and a double-pulse test circuit provided by the embodiments of the present disclosure;

[0035] Figure 2 is Figure 1 Curves of the level signal provided by the level signal source, the output signal of the inverting amplifier, and the output signal of the level converter changing with time;

[0036] Figure 3 is Figure 1 Curves of the midpoint voltage of the double-pulse test circuit, the drain current of the vertical junction field effect transistor, and the load current of the first inductor changing with time;

[0037] Figure 4 is Figure 1 Curve of the gate drive current of the vertical junction field effect transistor changing with time;

[0038] Figure 5 Schematic diagram of another semiconductor device and a double-pulse test circuit provided by the embodiments of the present disclosure;

[0039] Figure 6 is Figure 5 Curves of the midpoint voltage of the double-pulse test circuit, the drain current of the vertical junction field effect transistor, and the load current of the first inductor changing with time;

[0040] Figure 7 is Figure 5 Curves of the output currents of three sub-driving circuits changing with time;

[0041] Figure 8 is Figure 5The curves of the output currents of three sub-driving circuits and the drain current of the vertical junction field effect transistor changing with time;

[0042] Figure 9 Schematic diagram of another semiconductor device and double-pulse test circuit provided by an embodiment of the present disclosure;

[0043] Figure 10 is Figure 1 A schematic structural diagram of the semiconductor device shown;

[0044] Figure 11 is Figure 1 A schematic structural diagram of the semiconductor device shown during the manufacturing process;

[0045] Figure 12 is Figure 1 Another schematic structural diagram of the semiconductor device shown during the manufacturing process;

[0046] Figure 13 is Figure 1 Another schematic structural diagram of the semiconductor device shown during the manufacturing process;

[0047] Figure 14 is Figure 1 Another schematic structural diagram of the semiconductor device shown during the manufacturing process;

[0048] Figure 15 is Figure 1 Another schematic structural diagram of the semiconductor device shown. Detailed implementation manners

[0049] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It should be noted that the implementation manners described in the present disclosure should not be construed as limited to the specific shapes of the regions shown in the present disclosure, but include deviations in shape caused by, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or non-linear features; the sharp corners illustrated may be rounded, etc. And the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components are omitted in the present disclosure.

[0050] Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second" and similar words used in the description and claims of this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Words such as "comprising" or "including" mean that the elements or items appearing before the word cover the elements or items listed after the word and their equivalents, without excluding other elements or items. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Words such as "inside", "outside", "above", "below" are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0051] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer can be directly on the other element or layer, directly connected to the other element or layer, or there can be intermediate elements or intermediate layers. When an element or layer is referred to as being "disposed on one side of" another element or layer, the element or layer can be directly on one side of the other element or layer, directly connected to the other element or layer, or there can be intermediate elements or intermediate layers. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0052] Power devices need to be driven by a drive circuit (also called a drive buffer). However, in a main drive module of a new energy vehicle, for example, the drive circuit and the power device are in a spatially separated positional relationship, and an electrical connection needs to be achieved between the drive circuit and the power device through a long connecting wire, resulting in a relatively large parasitic inductance in the gate-source loop formed by the drive circuit and the power device. A relatively high parasitic inductance in the gate-source loop will cause obvious gate drive oscillation. Bringing the drive circuit and the power device as close as possible, or even integrating them monolithically, can effectively reduce the parasitic inductance in the gate-source loop and improve the drive performance.

[0053] Based on this, the embodiments of this disclosure provide a semiconductor device PIC, such as Figure 1 and Figure 10As shown, it includes: an N+ substrate 101, optionally, the N+ substrate 101 is an N-type heavily doped silicon carbide semiconductor substrate. An N-epitaxial layer 102, located above the N+ substrate 101. A drive circuit DB and a vertical junction field effect transistor VJ1. Among them, the drive circuit DB is disposed in the N-epitaxial layer 102. The drive circuit DB includes an inverting amplifier IA and a level shifter LS. Among them, the inverting amplifier IA is configured to amplify a first level signal and output it to the level shifter LS. The level shifter LS is configured to convert the amplified first level signal into a second level signal, so that the drive circuit DB can be used to drive a high-voltage power device (such as a vertical junction field effect transistor VJ1) with a low-voltage signal. The vertical junction field effect transistor VJ1 includes a gate (i.e., Figure 10 the first P+ top gate region PTG1 shown) and a source (i.e., Figure 10 the first N+ source contact region S1 shown) disposed in the N-epitaxial layer 102, and a drain (i.e., Figure 10 the back metal 105 shown) located on the side of the N+ substrate 101 away from the N-epitaxial layer 102. And as Figure 1 shown, the gate ng of the vertical junction field effect transistor VJ1 is connected to the output terminal of the drive circuit DB. The source ns of the vertical junction field effect transistor VJ1 is connected to a reference signal. The drain nd of the vertical junction field effect transistor VJ1 is connected to a load (such as a first inductor L1). Thus, by integrating the vertical junction field effect transistor VJ1 as a power device and the drive circuit DB on the same chip, the parasitic inductance of the gate-source loop formed by the drive circuit DB and the power device is effectively reduced, realizing a low-oscillation gate drive and improving the module stability.

[0054] In addition, related silicon carbide-based power devices (such as silicon carbide MOSFETs) all use silicon-based drive chips. The maximum operating temperature of silicon-based drive chips is generally between 125°C and 150°C, which is significantly lower than the maximum operating temperature of silicon carbide-based power devices (such as silicon carbide MOSFETs), which is between 175°C and 200°C. If a silicon carbide integrated drive circuit and power device on the same chip are used, the overall operating temperature of the semiconductor device can be increased and the cost can be reduced. Based on this, the semiconductor device PIC of the present disclosure can be provided as a silicon carbide-based chip. At the same time, the present disclosure uses a silicon carbide VJ1 device with a higher temperature resistance characteristic than a silicon carbide MOSFET as a power device, which is beneficial to further improving the high-temperature tolerance characteristic.

[0055] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, as Figure 1As shown, the inverting amplifier IA includes a first lateral junction field effect transistor LJ1 and a first resistor R1. Among them, the gate of the first lateral junction field effect transistor LJ1 is connected to a first level signal provided by a level signal source V3, the source of the first lateral junction field effect transistor LJ1 is grounded, and the drain of the first lateral junction field effect transistor LJ1 is connected to the output terminal of a first voltage source V1 through the first resistor R1. The level shifter LS includes a second lateral junction field effect transistor LJ2, a second resistor R2, and a third resistor R3. Among them, the gate of the second lateral junction field effect transistor LJ2 is connected to the amplified first level signal, the source of the second lateral junction field effect transistor LJ2 is connected to one end of the second resistor R2, the drain of the second lateral junction field effect transistor LJ2 is connected to the output terminal of the first voltage source V1, and the other end of the second resistor R2 is connected to the output terminal of a second voltage source V2 through the third resistor R3. The source ns of the vertical junction field effect transistor VJ1, the input terminal of the level signal source V3, the input terminal of the first voltage source V1, and the input terminal of the second voltage source V2 are all grounded. The reverse breakdown voltages of the first lateral junction field effect transistor LJ1 and the second lateral junction field effect transistor LJ2 are greater than 20V, the threshold voltages of the first lateral junction field effect transistor LJ1 and the second lateral junction field effect transistor LJ2 are 0V to -20V, and the resistance values of the first resistor R1, the second resistor R2, and the third resistor R3 can be the same. The junction field effect transistors of the present disclosure can be normally open type to ensure a wider voltage driving window.

[0056] In some embodiments, when the above-mentioned vertical junction field effect transistor VJ1, the first lateral junction field effect transistor LJ1, the second lateral junction field effect transistor LJ2, the first resistor R1, the second resistor R2, and the third resistor R3 are integrated on the same chip, the structures of the first lateral junction field effect transistor LJ1 and the second lateral junction field effect transistor LJ2 can be the same, and the structures of the first resistor R1, the second resistor R2, and the third resistor R3 can be the same. For the convenience of illustration, Figure 10 only shows Figure 1 the cross-sectional structures of the first lateral junction field effect transistor LJ1, the second lateral junction field effect transistor LJ2, and the vertical junction field effect transistor VJ1 in Figure 15 only shows the cross-sectional structures of the vertical junction field effect transistor VJ1, the first lateral junction field effect transistor LJ1, and the first resistor R1.

[0057] Such as Figure 10 and Figure 15As shown, the N-epitaxial layer 102 includes a first N-epitaxial layer 1021. The first N-epitaxial layer 1021 includes a first part VJA for arranging a vertical junction field effect transistor VJ1, a second part LJA1 for arranging a first lateral junction field effect transistor LJ1, a third part RA for arranging a first resistor R1, a fourth part LJA2 for arranging a second lateral junction field effect transistor LJ2, a fifth part for arranging a second resistor R2, and a sixth part for arranging a third resistor R3. Among them, the film layer structures of the fifth part and the sixth part are the same as Figure 15 that of the RA region in Figure 15 . Optionally, as shown in

[0058] , the part for introducing a reference signal (such as ground) in the first N-epitaxial layer 1021 of the present disclosure can be marked as the GNDA region. Figure 10 And Figure 15 . Continuing to refer to

[0059] and Figure 10 and Figure 15 it can be known that the first part VJA of the present disclosure is provided with a first P+ top gate region PTG1 and a first N+ source contact region S1. The first P+ top gate region PTG1 is the gate of the vertical junction field effect transistor VJ1, and the first N+ source contact region S1 is the source of the vertical junction field effect transistor VJ1. The second part LJA1 is provided with a second P+ top gate region PTG2, a second N+ source contact region S2, and a first N+ drain contact region D1. The third part RA is provided with two first N+ resistor contact regions E1. The second P+ top gate region PTG2 is the gate of the first lateral junction field effect transistor LJ1, the second N+ source contact region S2 is the source of the first lateral junction field effect transistor LJ1, the first N+ drain contact region D1 is the drain of the first lateral junction field effect transistor LJ1, and the two first N+ resistor contact regions E1 are the two ends of the first resistor R1. The fourth part LJA2 can be provided with a third P+ top gate region PTG3, a third N+ source contact region S3, and a second N+ drain contact region D2. The third P+ top gate region PTG3 is the gate of the second lateral junction field effect transistor LJ2, the third N+ source contact region S3 is the source of the second lateral junction field effect transistor LJ2, and the second N+ drain contact region D2 is the drain of the second lateral junction field effect transistor LJ2. Referring to the third part, it can be known that the film layer structures of the fifth part and the sixth part. The fifth part can be provided with two second N+ resistor contact regions, and the sixth part is provided with two third N+ resistor contact regions. And the two second N+ resistor contact regions are the two ends of the second resistor R2, and the two third N+ resistor contact regions are the two ends of the third resistor R3.

[0059] Combined with Figure 10 and Figure 15It can be seen that the semiconductor device provided by the embodiments of the present disclosure may further include an interconnect metal layer 104 on the side of the N-epitaxial layer 102 away from the N+ substrate 101; the N-epitaxial layer 102 may further include a second N-epitaxial layer 1022 between the first N-epitaxial layer 1021 and the N+ substrate 101. The second N-epitaxial layer 1022 includes a P+ bottom gate region PBG. The P+ bottom gate region PBG may be provided with an opening overlapping with the first P+ top gate region PTG1, and an N-type region is provided at the opening to reduce the on-resistance of the vertical junction field effect transistor VJ1. The first N-epitaxial layer 1021 further includes a first P+ connection region PL1 connected to the P+ bottom gate region PBG. The first P+ connection region PL1 may be disposed at the edge of the first part VJA and the reference signal region GNDA. Among them, the second P+ top gate region PTG2 accesses the first level signal (for example, the level signal provided by the level signal source V3) through the interconnect metal layer 104. The second N+ source contact region S2 and the first P+ connection region PL1 access the reference signal (for example, ground) through the interconnect metal layer 104. The first N+ drain contact region D1, the third P+ top gate region PTG3, and one first N+ resistor contact region E1 are electrically connected through the interconnect metal layer 104. The other first N+ resistor contact region E1 and the second N+ drain contact region D2 are electrically connected to the output terminal of the first voltage power supply V1 through the interconnect metal layer 104. The third N+ source contact region S3 and one second N+ resistor contact region (i.e., one end of the second resistor R2) are electrically connected through the interconnect metal layer 104. The other second N+ resistor contact region (i.e., the other end of the second resistor R2), one third N+ resistor contact region (i.e., one end of the third resistor R3), and the first P+ top gate region PTG1 are electrically connected through the interconnect metal layer 104. The other third N+ resistor contact region (i.e., the other end of the third resistor R3) is electrically connected to the output terminal of the second voltage power supply V2 through the interconnect metal layer 104.

[0060] In some embodiments, as Figure 10 and Figure 15 shown, the first part VJA, the second part LJA1, the third part RA, the fourth part LJA2, the fifth part (not shown in the figure), and the sixth part (not shown in the figure) of the first N-epitaxial layer 1021 of the present disclosure may be isolated from each other by the dielectric layer 103. Alternatively, as Figure 14 shown, a second P+ connection region PL2 for isolating the first part VJA, the second part LJA1, the third part RA, the fourth part LJA2, the fifth part (not shown in the figure), and the sixth part (not shown in the figure) is further provided in the first N-epitaxial layer 1021.

[0061] In some embodiments, in the above semiconductor device PIC provided by the embodiments of the present disclosure, as Figure 1 , Figure 5 and Figure 9As shown, the drive circuit DB may include at least one sub-drive circuit (such as SDB1, SDB2, SDB3), and a sub-drive circuit includes an inverting amplifier IA and a level converter LS. Exemplarily, Figure 1 the number of sub-drive circuits (such as SDB1) included in the drive circuit DB is 1. The sub-drive circuit (such as SDB1) is connected to the output terminal of the level signal source V3, and the output terminal of the sub-drive circuit (such as SDB1) is the output terminal of the drive circuit DB.

[0062] As Figure 2 shown, curve 1 represents Figure 1 the signal provided by the level signal source V3 in is a pulse input signal of 0V to -2V. After being amplified once by the inverting amplifier IA, the output voltage pulse is a positive voltage level signal of 0.27V to 20V (as shown by curve 2). Further, after being converted twice by the level converter LS, the output signal is a negative voltage level signal of -0.11V to -9.34V (as shown by curve 3). The negative voltage level signal has a small shoulder signal around -6.23V, which corresponds to the Miller plateau of VGS in the gate drive.

[0063] The negative voltage level signal represented by curve 3 enters the Figure 1 dual-pulse test circuit DPT in. The dual-pulse test circuit DPT uses a silicon carbide power diode U as the upper tube, with the anode connected to the midpoint (Midpoint, mp) of the circuit and the cathode connected to the high-voltage bus; the lower tube is the vertical junction field effect transistor VJ1 of the semiconductor device PIC provided by the present disclosure. The gate ng of the vertical junction field effect transistor VJ1 is connected to the negative voltage level signal of the drive circuit DB, the source ns is grounded, and the drain nd is connected to the midpoint mp of the dual-pulse test circuit DPT; the dual-pulse test circuit DPT further includes a fourth resistor R4 connected between the midpoint mp and the cathode of the silicon carbide power diode U, a first inductor L1 connected between the midpoint mp and the cathode of the silicon carbide power diode U, and a second inductor L2 connected between the level signal source V3 and the cathode of the silicon carbide power diode U.

[0064] Figure 3 For Figure 1 the dual-pulse test simulation results of the semiconductor device PIC shown. Figure 3In the figure, curve 4 has dot markers, curve 5 has square markers, and curve 6 has triangle markers. Curve 4 is the voltage at the midpoint mp of the dual-pulse test circuit DPT. Curve 5 is the current value of the first inductor L1 (the illustrated inductance value is 10 mH). As time increases, continuous inductor charging occurs. At 2.3 ms, the load current increases to 54 A. Curve 6 is the drain current of the vertical junction field-effect transistor VJ1. It can be seen that when the output signal of the primary drive circuit reaches -9.34 V, the vertical junction field-effect transistor VJ1 is fully turned off. At this time, the current in the first inductor L1 continues to flow through the forward conduction of the silicon carbide power diode U.

[0065] Figure 4 is Figure 1 the gate drive current signal of the vertical junction field-effect transistor VJ1 in the figure, with a duration of 0.05 ms, which switches the power device of the vertical junction field-effect transistor VJ1. There is a spike in the drive current from 2.5 mA to 3.5 mA, and then it quickly drops to the plateau current of 1.5 mA to 2.5 mA.

[0066] In some embodiments, in the above semiconductor device PIC provided by the embodiments of the present disclosure, not only can the Figure 1 shown primary drive be adopted, but also a multi-stage drive (such as Figure 5 the three-stage drive shown) can be adopted to improve the drive efficiency. In the case of multi-stage drive, the number of sub-drive circuits in the drive circuit DB can be n. The first-stage sub-drive circuit SDB1 is connected to the output terminal of the level signal source V3. The second level signal output by the m-th stage sub-drive circuit SDBm serves as the first level signal for the access of the (m + 1)-th sub-drive circuit SDBm+1. The output terminal of the n-th stage sub-drive circuit SDBn is the output terminal of the drive circuit DB, where n is an integer greater than or equal to 2, and m is an integer greater than or equal to 1 and less than n.

[0067] It should be noted that Figure 5 the structures of the 3 sub-drive circuits SDB1 to SDB3 in the figure are the same. For easy distinction, Figure 5The corresponding components in the three - level sub - drive circuits SDB1 to SDB3 are marked differently. Among them, in the first / second / third - level sub - drive circuits SDB1 / SDB2 / SDB3, R8 / R5 / R1 and LJ5 / LJ3 / LJ1 form an inverting amplifier IA, and LJ6 / LJ4 / LJ2, together with R9 / R6 / R2 and R10 / R7 / R3, form a level shifter LS. In the first - level sub - drive circuit SDB1, V3 inputs a level signal to the gate of LJ5, and the level signal output from the drain of LJ5 is inversely amplified after passing through the level shifter LS composed of LJ6, R8, and R9, and then input to the second - level sub - drive circuit SDB2, and so on until the third - level sub - drive circuit SDB3 outputs a signal to the gate of VJ1. LJ1 to LJ6 are all silicon carbide lateral junction field - effect transistors, whose reverse breakdown voltage > 20V, and at the same time, their threshold voltage ranges from 0V to - 20V. Preferably, it is - 1V to - 2V. In the multi - level drive embodiment, the output pulse current of each level of the sub - drive circuit is reduced in proportion (1:N) (where N is the number of levels of the sub - drive circuit SDB). Combining Figure 5 The parameter - related relationship of the three - level drive can be obtained as , and at the same time, assuming that the rated current of the device LJi is Ii (i = 1, 2,..., 6), then it satisfies , and at the same time, . The equal sign in the above formula is based on the theoretical design. In the actual design, taking the first - level sub - drive circuit SDB1 as an example, since LJ5 has a certain non - zero internal resistance r5 when conducting, the gate voltage signal output to LJ6 at this time is not GND, but a lower positive voltage Vo. Then, the ratio of R9 and R10 can be finely adjusted, with R10 slightly larger than R9, so that the output voltage signal of the first - level sub - drive circuit SDB1 can be strictly equal to .

[0068] Figure 6 is Figure 5 the double - pulse test simulation results of the semiconductor device PIC shown. Figure 6 In, curve 7 has dot marks, curve 8 has square marks, and curve 9 has triangle marks. Curve 7 is the voltage at the mid - point mp of the double - pulse test circuit DPT, curve 8 is the current value of the first inductor L1 (the inductance value shown is 10mH), and as time increases, continuous inductor charging occurs. At 2.3ms, the inductor current increases to 54A. Curve 9 is the drain current of the vertical junction field - effect transistor VJ1. When the output signal of the third - level sub - drive circuit SDB3 reaches - 9.42V, the vertical junction field - effect transistor VJ1 is completely turned off, and at this time, the current in the first inductor L1 completely conducts through the forward conduction of the silicon carbide power diode U for freewheeling.

[0069] Figure 5 The three - level drive design shown andFigure 1 Different from the first-level drive design shown, the drive currents of each level of drive are different. Figure 7 and Figure 8 In [reference], curve 10 has dot marks, curve 11 has square marks, curve 12 has triangle marks, and curve 13 has x marks. Curve 10 is Figure 5 the pulsed current signal input from V3 to LJ5 in [reference], curve 11 is the level signal input from the first-level drive to the gate of LJ3, and curve 12 is the level signal output from the second-level drive to the first lateral junction field-effect transistor LJ1 of the third-level sub-drive circuit SDB3; Figure 8 In [reference], curve 13 is the drive current pulse of VJ1 (inverted with the level signal output from the second-level drive to the first lateral junction field-effect transistor LJ1 of the third-level sub-drive circuit SDB3), and the gate drive charge of its pulse is much larger than that of the aforementioned multi-level drive.

[0070] In some embodiments, the above-mentioned semiconductor device PIC provided by the present disclosure may also be Figure 9 the half-bridge power device shown in [reference]. As Figure 9 shown in [reference], there are 2 sub-drive circuits (such as SDB1 and SDB2). The two sub-drive circuits (such as SDB1 and SDB2) are connected to the output terminals of different level signal sources (such as V3 and V5), and the output terminals of the two sub-drive circuits (such as SDB1 and SDB2) are the output terminals of the drive circuit DB. There may be 2 vertical junction field-effect transistors. The source electrode of one vertical junction field-effect transistor (such as VJ1) is grounded, and the drain electrode is connected to the source electrode of the other vertical junction field-effect transistor (such as VJ2). The gates of the two vertical junction field-effect transistors (such as VJ1 and VJ2) are electrically connected to the output terminals of the two sub-drive circuits (such as SDB1 and SDB2) respectively. In specific implementation, after VJ1 is turned off, VJ2 is turned on after a dead time to conduct freewheeling of the first inductor L1 and reduce freewheeling loss. At the same time, after VJ2 is turned off, VJ1 is turned on to continue charging the load of the first inductor L1 to achieve the synchronous rectification function.

[0071] Based on the same inventive concept, the embodiments of the present disclosure provide a preparation method of the above-mentioned semiconductor device. Since the principle of solving problems by this preparation method is similar to that of the above-mentioned semiconductor device, therefore, the implementation of the preparation method provided by the embodiments of the present disclosure can refer to the implementation of the above-mentioned semiconductor device provided by the embodiments of the present disclosure, and the repeated parts will not be described again.

[0072] To better understand the preparation scheme of the semiconductor device PIC provided by the present disclosure, the following will Figure 1 detail the manufacturing process of the semiconductor device PIC shown in [reference]. It should be noted that for simplicity of illustration, Figure 10 only showsFigure 1 The cross-sectional structures of LJ1, LJ2, and VJ1. In fact, R1, R2, and R3 are also integrated on the same substrate. The following is a specific description.

[0073] The first step is as Figure 11 shown. A second N-epitaxial layer 1022 is epitaxially formed on the N+ substrate 101. Then, P-type impurities are selectively implanted into the second N-epitaxial layer 1022 and annealed to activate the N-type impurities, forming a P+ bottom gate region PBG and a terminal protection structure TER. Among them, the P+ bottom gate region PBG has an opening within the gate region of the vertical junction field effect transistor VJ1, and N-type impurities can be implanted at this opening and annealed to activate the N-type impurities to reduce the on-resistance of the vertical junction field effect transistor VJ1.

[0074] The second step is as Figure 12 shown. A first N-epitaxial layer 1021 is epitaxially formed on the second N-epitaxial layer 1022, and P-type impurities are selectively implanted into the first N-epitaxial layer 1021 through a hard mask and ion implantation process, forming a first P+ top gate region PTG1, a second P+ top gate region PTG2, a third P+ top gate region PTG3 (not shown in the figure), and a first P+ connection region PL1 connected to the P+ bottom gate region PBG. Among them, the first P+ top gate region PTG1 is the gate of the vertical junction field effect transistor VJ1, the second P+ top gate region PTG2 is the gate of the first lateral junction field effect transistor LJ1, and the third P+ top gate region PTG3 is the gate of the second lateral junction field effect transistor LJ2. Optionally, N-type impurities can also be implanted into the channel of the vertical junction field effect transistor VJ1 to modulate the threshold voltage of the vertical junction field effect transistor VJ1.

[0075] The third step is to isolate and form a first resistor region, a second resistor region, a third resistor region, a first lateral junction field effect transistor region, a second lateral junction field effect transistor region, a vertical junction field effect transistor region, and a ground region.

[0076] In some embodiments, as Figure 13 shown, the first N-epitaxial layer 1021 can be selectively etched and stopped at the interface between the second N-epitaxial layer 1022 and the first N-epitaxial layer 1021 to define a first resistor region (i.e., the region shown as RA), a second resistor region (not shown in the figure), a third resistor region (not shown in the figure), a first lateral junction field effect transistor region (i.e., the region shown as LJA1), a second lateral junction field effect transistor region (not shown in the figure), a vertical junction field effect transistor region (i.e., the region shown as VJA), and a ground region (i.e., the region shown as GNDA) arranged at intervals.

[0077] In other embodiments, as Figure 14As shown, P-type impurity selective area implantation can also be performed in the first N-epitaxial layer 1021 to form a second P+ connection area PL2 connected to the P+ bottom gate area PBG, so as to isolate the first resistor area (i.e., the area shown by RA), the second resistor area (not shown in the figure), the third resistor area (not shown in the figure), the first lateral junction field effect transistor area (i.e., the area shown by LJA1), the second lateral junction field effect transistor area (not shown in the figure), the vertical junction field effect transistor area (i.e., the area shown by VJA) and the ground connection area (i.e., the area shown by GNDA) by using the second P+ connection area PL2.

[0078] Optionally, a shallow N-type doping can also be performed in the first resistor area, the second resistor area, the third resistor area, the first lateral junction field effect transistor area, the second lateral junction field effect transistor area, and the vertical junction field effect transistor area to modulate the resistance value, the source-drain contact resistance of the lateral junction field effect transistor, and the source resistance of the vertical junction field effect transistor. The N-type doped area does not overlap with the first P+ top gate area PTG1, the second P+ top gate area PTG2, the third P+ top gate area PTG3, the first P+ connection area PL1, and the second P+ connection area PL2.

[0079] The fourth step, as Figure 13 and Figure 14 shown, through the hard mask and ion implantation process, N-type impurity selective area implantation is performed in the first N-epitaxial layer 1021 and the N-type impurities are annealed and activated, so that two N+ contact areas are respectively formed in the first resistor area (i.e., the area shown by RA), the second resistor area (not shown in the figure), the third resistor area (not shown in the figure), the first lateral junction field effect transistor area (i.e., the area shown by LJA1), the second lateral junction field effect transistor area (not shown in the figure), and the vertical junction field effect transistor area (i.e., the area shown by VJA). Among them, the two N+ contact areas (i.e., the areas shown by S2 and D1) in the first lateral junction field effect transistor area (i.e., the area shown by LJA1) are respectively the source and drain of the first lateral junction field effect transistor LJ1, the two N+ contact areas (i.e., the area shown by S1) in the vertical junction field effect transistor area (i.e., the area shown by VJA) are the source of the vertical junction field effect transistor VJ1, the two N+ contact areas (i.e., the areas shown by E1) in the first resistor area (i.e., the area shown by RA) are respectively the two ends of the first resistor R1, the two N+ contact areas in the second resistor area (not shown in the figure) are respectively the two ends of the second resistor R2, and the two N+ contact areas in the third resistor area (not shown in the figure) are respectively the two ends of the third resistor R3.

[0080] The fifth step, as Figure 15 and Figure 10As shown, a dielectric layer 103 is formed on the first N-epitaxial layer 1021, and vias penetrating the dielectric layer 103 are formed in the first P+ connection region PL1, the first P+ top gate region PTG1, the second P+ top gate region PTG2, the third P+ top gate region PTG3, and each N+ contact region; then an interconnect metal layer 104 can be formed such that the first P+ connection region PL1 and the second N+ source contact region S2 of the first lateral junction field effect transistor LJ1 are respectively connected to a reference signal (such as ground); one first N+ resistor contact region E1 of the first resistor R1 is connected to the first N+ drain contact region D1 of the first lateral junction field effect transistor LJ1, and the other first N+ resistor contact region E1 of the first resistor R1 is connected to the second N+ drain contact region D2 of the second lateral junction field effect transistor LJ2; one second N+ resistor contact region (i.e., one end of the second resistor R2) of the second resistor R2 is connected to the third N+ source contact region S3 of the second lateral junction field effect transistor LJ2, and the other second N+ resistor contact region (i.e., the other end of the second resistor R2) of the second resistor R2 is respectively connected to the first P+ top gate region PTG1 of the vertical junction field effect transistor VJ1 and one third N+ resistor contact region (i.e., one end of the third resistor R3) of the third resistor R3. A backside metal 105 can also be formed on the backside of the N+ substrate 101 by physical vapor deposition (PVD) as the drain of the vertical junction field effect transistor VJ1, and laser annealing is performed to achieve a drain ohmic contact, and finally, a semiconductor device PIC integrated on the same chip as shown in Figure 1 is obtained.

[0081] Based on the same inventive concept, an embodiment of the present disclosure provides a power device including the above semiconductor device provided by the embodiment of the present disclosure. Since the principle of solving problems by this power device is similar to that of the above semiconductor device, therefore, the implementation of this power device provided by the embodiment of the present disclosure can refer to the implementation of the above semiconductor device provided by the embodiment of the present disclosure, and the repeated parts will not be elaborated.

[0082] In some embodiments, the above power device provided by the embodiment of the present disclosure may include, but is not limited to: radio frequency amplifiers, mixers, radars, satellites, power supplies, automotive electronics, energy-saving lamps, household appliances, etc. Of course, in addition to including semiconductor devices, the power device provided by the present disclosure may also include other structures. For example, when the power device is a radar, it further includes: a transmitter, an antenna, a receiver, etc.; when the power device is a mixer, it may further include: an input port and an output port, etc.

[0083] As can be seen from the above, the present disclosure realizes a drive circuit + vertical power device structure integrated on the same chip based on silicon carbide JFET. Since the silicon carbide JFET device has stronger high-temperature resistance characteristics compared to SiC MOSFET, a high-temperature-resistant power supply can be realized based on this on-chip integrated structure. At the same time, since the power supply realizes low parasitic inductance in the gate-source loop, low-oscillation gate drive can be achieved, improving the stability of the module.

[0084] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present disclosure.

[0085] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. A semiconductor device, characterized in that: include: N+ substrate; An N-epitaxial layer, located on the N+ substrate; A driving circuit is provided in the N-epitaxial layer, the driving circuit comprising an inverting amplifier and a level converter, wherein the inverting amplifier is configured to amplify a first level signal and output it to the level converter, and the level converter is configured to convert the amplified first level signal into a second level signal; A vertical junction field effect transistor comprises a gate and a source arranged in the N-epitaxial layer, and a drain arranged on a side of the N+ substrate away from the N-epitaxial layer; the gate of the vertical junction field effect transistor is connected to the output end of the driving circuit, the source of the vertical junction field effect transistor is connected to a reference signal, and the drain of the vertical junction field effect transistor is connected to a load.

2. The semiconductor device according to claim 1, wherein The N-epitaxial layer includes a first N-epitaxial layer, the first N-epitaxial layer includes a first part, the first part is provided with a first P+ top gate region and a first N+ source contact region, the first P+ top gate region is the gate of the vertical junction field effect transistor, and the first N+ source contact region is the source of the vertical junction field effect transistor.

3. The semiconductor device according to claim 2, wherein: The inverting amplifier includes a first lateral junction field effect transistor and a first resistor; The first N-epitaxial layer further includes a second part and a third part spaced apart from the first part, wherein the second part is provided with a second P+ top gate region, a second N+ source contact region and a first N+ drain contact region, and the third part is provided with two first N+ resistor contact regions; The second P+ top gate region is the gate of the first lateral junction field effect transistor, the second N+ source contact region is the source of the first lateral junction field effect transistor, the first N+ drain contact region is the drain of the first lateral junction field effect transistor, and the two first N+ resistor contact regions are the two ends of the first resistor.

4. The semiconductor device according to claim 3, characterized in that The level converter includes a second lateral junction field effect transistor, a second resistor and a third resistor; The first N-epitaxial layer further includes a fourth part, a fifth part and a sixth part which are spaced apart from the first part, the second part and the third part; wherein the fourth part is provided with a third P+ top gate region, a third N+ source contact region and a second N+ drain contact region, the fifth part is provided with two second N+ resistor contact regions, and the sixth part is provided with two third N+ resistor contact regions; The third P+ top gate region is the gate of the second lateral junction field effect transistor, the third N+ source contact region is the source of the second lateral junction field effect transistor, the second N+ drain contact region is the drain of the second lateral junction field effect transistor, the two second N+ resistor contact regions are the two ends of the second resistor, and the two third N+ resistor contact regions are the two ends of the third resistor.

5. The semiconductor device according to claim 4, wherein: Also included is an interconnect metal layer located on a side of the N- epitaxial layer away from the N+ substrate; The N-epitaxial layer further includes a second N-epitaxial layer located between the first N-epitaxial layer and the N+ substrate, the second N-epitaxial layer includes a P+ bottom gate region, and the first N-epitaxial layer further includes a first P+ connection region connected to the P+ bottom gate region; The second P+ top gate region is connected to the first level signal through the interconnection metal layer, the second N+ source contact region and the first P+ connection region are connected to the reference signal through the interconnection metal layer, the first N+ drain contact region, the third P+ top gate region, and one of the first N+ resistor contact regions are electrically connected through the interconnection metal layer, another of the first N+ resistor contact regions, and the second N+ drain contact region are electrically connected to the output end of the first voltage power supply through the interconnection metal layer, the third N+ source contact region is electrically connected to one of the second N+ resistor contact regions through the interconnection metal layer, another of the second N+ resistor contact regions, one of the third N+ resistor contact regions, and the first P+ top gate region are electrically connected through the interconnection metal layer, and another of the third N+ resistor contact regions is electrically connected to the output end of the second voltage power supply through the interconnection metal layer.

6. The semiconductor device according to claim 5, characterized in that It also includes a dielectric layer, and the first part, the second part, the third part, the fourth part, the fifth part, and the sixth part are isolated from each other by the dielectric layer.

7. The semiconductor device according to claim 5, characterized in that The first N-epitaxial layer also includes a second P+ connection region, and the first portion, the second portion, the third portion, the fourth portion, the fifth portion, and the sixth portion are isolated from each other by the second P+ connection region.

8. The semiconductor device according to any one of claims 5 to 7, characterized in that: The P+ bottom gate region is provided with an opening which overlaps with the first P+ top gate region, and an N-type region is provided at the opening.

9. The semiconductor device according to any one of claims 4 to 7, characterized in that: The reverse breakdown voltage of the first lateral junction field effect transistor and the second lateral junction field effect transistor is greater than 20V, the threshold voltage of the first lateral junction field effect transistor and the second lateral junction field effect transistor is 0V~-20V, and the resistance values ​​of the first resistor, the second resistor and the third resistor are the same.

10. The semiconductor device according to any one of claims 1 to 7, characterized in that: The driving circuit includes at least one sub-driving circuit, and the sub-driving circuit includes one of the inverting amplifiers and one of the level converters.

11. The semiconductor device according to claim 10, wherein: There is one sub-driving circuit, which is connected to the output end of the level signal source, and the output end of the sub-driving circuit is the output end of the driving circuit.

12. The semiconductor device according to claim 10, wherein: There are n sub-driving circuits, the first sub-driving circuit is connected to the output end of the level signal source, the second level signal output by the m-th sub-driving circuit is the first level signal connected to the (m+1)-th sub-driving circuit, the output end of the n-th sub-driving circuit is the output end of the driving circuit, n is an integer greater than or equal to 2, and m is an integer greater than or equal to 1 and less than n.

13. The semiconductor device according to claim 11 or 12, characterized in that: There is one vertical junction field effect transistor, and a source of the vertical junction field effect transistor is grounded.

14. The semiconductor device according to claim 10, wherein: There are two sub-driving circuits, and the two sub-driving circuits are connected to the output ends of signal sources with different levels, and the output ends of the two sub-driving circuits are the output ends of the driving circuit.

15. The semiconductor device according to claim 14, wherein: There are two vertical junction field effect transistors, wherein the source of one of the vertical junction field effect transistors is grounded and the drain is connected to the source of the other vertical junction field effect transistor.

16. The semiconductor device according to any one of claims 1 to 7, 11, 12, 14 and 15, characterized in that: An output terminal of the driving circuit is correspondingly connected to a gate of the vertical junction field effect transistor.

17. A power device, characterized in that: Comprising a semiconductor device as described in any one of claims 1 to 16.

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