Display panel, manufacturing method thereof and display device

Abstract

The invention belongs to the field of display, and particularly relates to a display panel, a manufacturing method of the display panel and a display device.The display panel comprises a substrate, a first metal layer, a gate insulation layer, an active layer, a second metal layer, an insulation protection layer and a transparent conductive layer, and the first metal layer, the gate insulation layer, the active layer, the second metal layer, the insulation protection layer and the transparent conductive layer are sequentially formed on the substrate. The gate insulation layer at least covers the first metal layer, the active layer comprises a first semiconductor part and a second semiconductor part, the second metal layer comprises a source and a drain, the insulation protection layer covers the active layer and the second metal layer, the transparent conductive layer comprises a pixel electrode and a third gate, and the third gate is connected with the second gate. The second thin film transistor comprises a second grid electrode, a third grid electrode, a second semiconductor part and a second source drain electrode, the second thin film transistor is a double-grid thin film transistor, the reliability of the ambient light sensor is improved, and the situation that the display brightness cannot be accurately adjusted due to inaccurate light sensing current detection can be avoided.

Description

Technical Field

[0001] This application belongs to the field of displays, and particularly relates to a display panel, a manufacturing method thereof, and a display device. Background Art

[0002] With the development of display technologies, thin film transistor liquid crystal displays (TFT-LCDs) have been widely used in various consumer electronic products such as mobile phones, TVs, computer monitors, and laptop computers due to their advantages of high picture quality, power saving, thin body, and mature and stable manufacturing processes, becoming the mainstream in display devices.

[0003] The user's perception of the display effects presented by a display in terms of brightness, contrast, color gamut, etc. will vary due to the brightness difference of the surrounding environment. For example, in an outdoor location with direct sunlight, if the brightness of the display is insufficient, the picture will appear very dim and the colors will not be vivid, making it difficult to see the picture details and colors. On the contrary, in a darker environment, the brightness of the display can be appropriately reduced. Excessive brightness will cause discomfort to the human eye, and in a dark environment, a screen with a lower brightness can also present good contrast and color saturation.

[0004] To achieve automatic brightness adjustment, some displays are provided with ambient light sensors (ALS) inside the panel. When the ambient brightness increases, the current measured by the ambient light sensor increases, and the driving module controls the backlight brightness of the back module to increase. Ambient light sensors made of amorphous silicon (a-Si) thin film transistors are widely used in displays because of their advantages of low manufacturing cost and relatively mature technology. However, when the display is used for a long time, the amorphous silicon thin film transistor ambient light sensor continuously outputs a photosensitive current under light irradiation, which will be under the pressure of a DC signal, resulting in poor reliability, and then the input photosensitive current is inaccurate, and finally the display brightness cannot be accurately adjusted. Summary of the Invention

[0005] The purpose of this application is to provide a display panel, a manufacturing method thereof, and a display device to improve the reliability of the ambient light sensor and avoid inaccurate detection of the photosensitive current, resulting in the inability to accurately adjust the display brightness.

[0006] To achieve the above purpose, this application provides a display panel, including a substrate, and the display panel further includes:

[0007] A first metal layer formed on one side of the substrate, the first metal layer including a first gate and a second gate;

[0008] A gate insulating layer is formed on one side of the substrate and covers the first metal layer;

[0009] An active layer is formed on the side of the gate insulating layer away from the substrate. The active layer includes a first semiconductor portion and a second semiconductor portion. The first semiconductor portion is located on the side of the first gate away from the substrate, and the second semiconductor portion is located on the side of the second gate away from the substrate;

[0010] A second metal layer includes source and drain electrodes, and the source and drain electrodes are at least formed on the side of the first semiconductor portion away from the substrate and on the side of the second semiconductor portion away from the substrate;

[0011] An insulating protection layer is formed on the side of the gate insulating layer away from the substrate and covers the active layer and the second metal layer;

[0012] A transparent conductive layer is formed on the side of the insulating protection layer away from the substrate. The transparent conductive layer includes a pixel electrode and a third gate. The pixel electrode is connected to the source and drain electrodes corresponding to a part of the first semiconductor portion. The orthographic projection of the third gate on the active layer overlaps with the second semiconductor portion, and the third gate is connected to the second gate.

[0013] Optionally, the source and drain electrodes include a second source electrode and a second drain electrode spaced apart in a first direction. The second source electrode and the second drain electrode are at least located on the side of the second semiconductor portion away from the substrate. The third gate is connected to the second gate through a first communication hole penetrating through the insulating protection layer and the gate insulating layer. The first communication hole is located on one side of the second semiconductor portion in a second direction, and the second direction is perpendicular to the first direction.

[0014] Optionally, the source and drain electrodes include a second source electrode and a second drain electrode spaced apart in a first direction. The second source electrode and the second drain electrode are at least located on the side of the second semiconductor portion away from the substrate. In the first direction, the second gate forms a gap with at least one of the second source electrode and the second drain electrode.

[0015] Optionally, the second gate forms a first gap with the second source electrode or the second drain electrode. The first gap is greater than or equal to 2 micrometers and less than or equal to 15 micrometers.

[0016] Optionally, the second gate forms a first gap with the second source electrode and a second gap with the second drain electrode. The first gap is greater than or equal to 1 micrometer, the second gap is greater than or equal to 1 micrometer, and the sum of the first gap and the second gap is less than or equal to 15 micrometers.

[0017] Optionally, the source-drain includes a second source and a second drain spaced apart in a first direction. The second source and the second drain are at least located on a side of the second semiconductor portion away from the substrate. At least in the first direction, the edges of the second source and the second drain extend outside the second semiconductor portion, and the distance between the edge of the second gate and the corresponding source-drain is greater than or equal to 3 micrometers.

[0018] Optionally, the display panel further includes a planarization layer formed on a side of the insulating protection layer away from the substrate. The pixel electrode is formed on a side of the planarization layer away from the substrate. A groove extending to the insulating protection layer is formed on the planarization layer, and the third gate is located in the groove; or

[0019] The display panel further includes a planarization layer located between the transparent conductive layer and the insulating protection layer. The pixel electrode passes through the planarization layer and the insulating protection layer to be connected to the source-drain.

[0020] Optionally, the material for making the gate insulating layer includes silicon dioxide, aluminum oxide, silicon oxynitride, and hafnium oxide, and the material for making the insulating protection layer includes silicon dioxide and aluminum oxide.

[0021] This application also provides a method for manufacturing a display panel, including:

[0022] Forming a first metal material layer on the substrate, and patterning the first metal material layer to form a first gate and a second gate;

[0023] Forming a gate insulating layer covering the first gate and the second gate on the substrate;

[0024] Forming a semiconductor material layer on a side of the gate insulating layer away from the substrate, and patterning the semiconductor material layer to form an active layer. The active layer includes a first semiconductor portion and a second semiconductor portion. The first semiconductor portion is located on a side of the first gate away from the substrate, and the second semiconductor portion is located on a side of the second gate away from the substrate;

[0025] Forming a second metal material layer on a side of the gate insulating layer away from the substrate, and patterning the second metal material layer to form a source-drain. The source-drain is at least located on a side of the first semiconductor portion away from the substrate and a side of the second semiconductor portion away from the substrate;

[0026] Forming an insulating protection layer covering the source-drain and the active layer;

[0027] A transparent conductive material layer is formed on a side of the insulating protective layer away from the substrate. The transparent conductive material layer is patterned to form a pixel electrode and a third gate. The pixel electrode is connected to source / drain electrodes corresponding to a part of the first semiconductor portion. A positive projection of the third gate on the active layer overlaps with the second semiconductor portion, and the third gate is connected to the second gate.

[0028] The present application also provides a display device, including:

[0029] A backlight module;

[0030] The display panel, disposed on a light-emitting side of the backlight module.

[0031] The display panel, manufacturing method thereof, and display device disclosed in the present application have the following beneficial effects:

[0032] In the present application, the display panel includes a substrate and a first metal layer, a gate insulating layer, an active layer, a second metal layer, an insulating protective layer, and a transparent conductive layer sequentially formed on the substrate. The first metal layer includes a first gate and a second gate. The gate insulating layer covers at least the first metal layer. The active layer includes a first semiconductor portion and a second semiconductor portion. The second metal layer includes source / drain electrodes, and the source / drain electrodes are at least formed on a side of the first semiconductor portion and the second semiconductor portion away from the substrate. The insulating protective layer covers the active layer and the second metal layer. The transparent conductive layer includes a pixel electrode and a third gate. The pixel electrode is connected to source / drain electrodes corresponding to a part of the first semiconductor portion. A positive projection of the third gate on the active layer overlaps with the second semiconductor portion, and the third gate is connected to the second gate. The second thin-film transistor includes a second gate, a third gate, a second semiconductor portion, and a second source / drain electrode. The second thin-film transistor is a double-gate thin-film transistor, which improves the reliability of the ambient light sensor and can avoid inaccurate detection of the photosensitive current, resulting in inaccurate adjustment of the display brightness.

[0033] Other features and advantages of the present application will become apparent from the following detailed description, or can be learned in part through the practice of the present application.

[0034] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0036] Figure 1 It is a schematic structural diagram of an array substrate in Embodiment 1 of the present application.

[0037] Figure 2 It is a schematic structural diagram of a display panel in Embodiment 1 of the present application.

[0038] Figure 3 It is a top view schematic diagram of the second thin film transistor of the array substrate in Embodiment 1 of the present application.

[0039] Figure 4 It is a schematic diagram of the photosensitive current of an amorphous silicon metal bottom gate silicon thin film transistor environmental light sensor.

[0040] Figure 5 It is a schematic diagram of the gate centered of the environmental light sensor of the array substrate in Embodiment 1 of the present application.

[0041] Figure 6 It is a schematic diagram of an array substrate with a gate located on an insulating protective layer in Embodiment 2 of the present application.

[0042] Figure 7 It is a schematic diagram of an array substrate with a gate located on a planarization layer in Embodiment 2 of the present application.

[0043] Figure 8 It is a flowchart of the manufacturing method of the display panel in Embodiment 3 of the present application.

[0044] Figure 9 It is a schematic diagram of forming a first metal layer in Embodiment 3 of the present application.

[0045] Figure 10 It is a schematic diagram of forming an active layer in Embodiment 3 of the present application.

[0046] Figure 11 It is a schematic diagram of forming a second metal layer in Embodiment 3 of the present application.

[0047] Figure 12 It is a schematic diagram of forming an insulating protective layer in Embodiment 3 of the present application.

[0048] Figure 13 It is a schematic structural diagram of a display device in Embodiment 4 of the present application.

[0049] Explanation of reference numerals:

[0050] 100, Array Substrate; 110, Substrate; 120, First Metal Layer; 121, First Gate; 122, Second Gate; 130, Gate Insulating Layer; 140, Active Layer; 141, First Semiconductor Portion; 142, Second Semiconductor Portion; 150, Second Metal Layer; 151, First Source; 152, First Drain; 153, Second Source; 154, Second Source; 160, Insulating Protection Layer; 161, First Connecting Hole; 162, Second Connecting Hole; 170, Transparent Conductive Layer; 171, Pixel Electrode; 172, Third Gate; 180, Ohmic Contact Layer; 190, Planarization Layer; 191, Groove

[0051] 200, Counter Substrate; 210, Color Resist Layer; 220, Black Matrix; 230, Light Transmitting Region

[0052] 300, Liquid Crystal Layer

[0053] 10, Display Panel; 20, Backlight Module Detailed Embodiments

[0054] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art.

[0055] In addition, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of this application. However, those skilled in the art will realize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of this application.

[0056] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted here that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present application and should not be construed as limiting the present application.

[0057] Embodiment 1

[0058] Refer to Figures 1 to 3As shown, in this embodiment, the display panel 10 includes an array substrate 100, and the array substrate 100 includes a substrate 110, a first metal layer 120, a gate insulating layer 130, an active layer 140, a second metal layer 150, an insulating protective layer 160, and a transparent conductive layer 170. The first metal layer 120 is formed on one side of the substrate 110. The first metal layer 120 includes a first gate 121 and a second gate 122, and a gap is formed between the first gate 121 and the second gate 122. The first metal layer 120 further includes scan lines (not shown). The gate insulating layer 130 is formed on one side of the substrate 110 and at least covers the first metal layer 120.

[0059] The active layer 140 is formed on the side of the gate insulating layer 130 away from the substrate 110. The active layer 140 includes a first semiconductor portion 141 and a second semiconductor portion 142. The first semiconductor portion 141 is located on the side of the first gate 121 away from the substrate 110, and the second semiconductor portion 142 is located on the side of the second gate 122 away from the substrate 110. That is to say, the first gate 121 can block the light irradiated from the side of the substrate 110 to the first semiconductor portion 141, and the second gate 122 can block the light irradiated from the side of the substrate 110 to the second semiconductor portion 142. The material for making the active layer 140 includes amorphous silicon.

[0060] The second metal layer 150 includes source-drain electrodes, and the source-drain electrodes are at least formed on the side of the first semiconductor portion 141 away from the substrate 110 and on the side of the second semiconductor portion 142 away from the substrate 110. The source-drain electrodes include a first source-drain electrode and a second source-drain electrode. The insulating protective layer 160 is formed on the side of the gate insulating layer 130 away from the substrate 110 and covers the active layer 140 and the second metal layer 150.

[0061] The transparent conductive layer 170 is formed on the side of the insulating protective layer 160 away from the substrate 110. The transparent conductive layer 170 includes a pixel electrode 171 and a third gate 172. The pixel electrode 171 is connected to the source-drain electrode corresponding to a part of the first semiconductor portion 141. The third gate 172 overlaps with the second semiconductor portion 142 in the orthographic projection on the active layer 140, and the third gate 172 is connected to the second gate 122. The material for making the transparent conductive layer 170 includes indium tin oxide (ITO).

[0062] The array substrate 100 includes a first thin film transistor and a second thin film transistor. The first thin film transistor includes a first gate 121, a first semiconductor portion 141, and a first source-drain electrode. The second thin film transistor includes a second gate 122, a third gate 172, a second semiconductor portion 142, and a second source-drain electrode. The third gate 172 is connected to the second gate 122, and the second thin film transistor is a double-gate thin film transistor. The second thin film transistor serves as an ambient light sensor for generating a photosensitive current. The first thin film transistor serves as a switching transistor. Some of the first thin film transistors are connected to the second thin film transistor and a driving module for reading the photosensitive current, and some of the first thin film transistors are connected to a pixel electrode 171 for controlling the writing of a data voltage to the pixel electrode 171.

[0063] It should be understood that the display panel 10 further includes a counter substrate 200 and a liquid crystal layer 300. The liquid crystal layer 300 is disposed between the array substrate 100 and the counter substrate 200. The counter substrate 200 includes a color filter substrate. The counter substrate 200 may include a color resist layer 210, a black matrix 220, and a light-transmitting region 230. The color resist layer 210 is disposed on a side of the pixel electrode 171 away from the substrate 110. The light-transmitting region 230 is located on a side of the second semiconductor portion 142 away from the substrate 110. The black matrix 220 is disposed around the color resist layer 210 and the light-transmitting region 230. The black matrix 220 can block light on a side of the first semiconductor portion 141 away from the substrate 110. The display panel 10 may further include a sealant (not shown) disposed between the array substrate 100 and the counter substrate 200. The liquid crystal layer 300 is located within the sealant, and the first thin film transistor and the second thin film transistor are located within the region surrounded by the sealant.

[0064] When the display is used for a long time, the amorphous silicon thin film transistor ambient light sensor continuously outputs a photosensitive current under light irradiation, which will be under the pressure of a DC signal, resulting in poor reliability, and further causing the input photosensitive current to be inaccurate, and ultimately unable to accurately adjust the display brightness.

[0065] In this embodiment, the display panel 10 includes a substrate 110, and a first metal layer 120, a gate insulating layer 130, an active layer 140, a second metal layer 150, an insulating protection layer 160, and a transparent conductive layer 170 formed in sequence on the substrate 110. The first metal layer 120 includes a first gate 121 and a second gate 122. The gate insulating layer 130 covers at least the first metal layer 120. The active layer 140 includes a first semiconductor portion 141 and a second semiconductor portion 142. The second metal layer 150 includes source / drain electrodes, and the source / drain electrodes are formed at least on the sides of the first semiconductor portion 141 and the second semiconductor portion 142 away from the substrate 110. The insulating protection layer 160 covers the active layer 140 and the second metal layer 150. The transparent conductive layer 170 includes a pixel electrode 171 and a third gate 172. The pixel electrode 171 is connected to the source / drain electrode corresponding to a part of the first semiconductor portion 141. The orthographic projection of the third gate 172 on the active layer 140 overlaps with the second semiconductor portion 142, and the third gate 172 is connected to the second gate 122. The second thin film transistor includes the second gate 122, the third gate 172, the second semiconductor portion 142, and a second source / drain electrode. The second thin film transistor is a double-gate thin film transistor, which improves the reliability of the ambient light sensor and can avoid inaccurate detection of the photosensitive current, resulting in inaccurate adjustment of the display brightness.

[0066] In addition, for an ambient light sensor fabricated using amorphous silicon thin film transistors, the gate is usually disposed on the first metal layer, as Figure 4 shown. For an ambient light sensor with such a structure, the current ratio between the bright state and the dark state is small, resulting in low sensitivity for adjusting the backlight brightness according to the ambient brightness and fewer adjustable levels.

[0067] In this embodiment, the third gate 172 of the second thin film transistor is disposed in the transparent conductive layer 170, and the second thin film transistor is used as an ambient light sensor. The current ratio between the bright state and the dark state of the second thin film transistor increases, improving the sensitivity for adjusting the backlight brightness according to the ambient brightness and increasing the number of adjustable levels. The third gate 172 of the ambient light sensor is disposed on the same layer as the pixel electrode 171, without adding an extra film layer structure to the array substrate 100 and the display panel 10, which is beneficial to reducing the manufacturing cost of the array substrate 100 and the display panel 10. The second gate 122 is disposed on the first metal layer 120, and the second gate 122 can block the light irradiated from the side of the substrate 110 to the second semiconductor portion 142, reducing or eliminating the influence of backlight irradiation on the photosensitive current of the ambient light sensor.

[0068] In some embodiments, the first source-drain includes a first source 151 and a first drain 152. The first source 151 and the first drain 152 are spaced apart along a first direction. The first source 151 and the first drain 152 are at least located on a side of the first semiconductor portion 141 away from the substrate 110. That is to say, the first source 151 and the first drain 152 can extend along the first direction to the outside of the first semiconductor portion 141 and contact the gate insulating layer 130. The insulating protective layer 160 is provided with a second communication hole 162 communicating with the first source 151, and the pixel electrode 171 is connected to the first source 151 through the second communication hole 162.

[0069] The second source-drain includes a second source 153 and a second drain 154. The second source 153 and the second drain 154 are spaced apart along the first direction. The second source 153 and the second drain 154 are at least located on a side of the second semiconductor portion 142 away from the substrate 110. That is to say, the second source 153 and the second drain 154 can extend along the first direction to the outside of the second semiconductor portion 142 and contact the gate insulating layer 130. In the first direction, the third gate 172 forms a gap with at least one of the second source 153 and the second drain 154. That is to say, the second thin film transistor is a gap type thin film transistor (Gap Type TFT).

[0070] The second thin film transistor is a gap type thin film transistor. The second thin film transistor is used as an ambient light sensor, and the current ratio between the bright state and the dark state is increased, improving the sensitivity of adjusting the backlight brightness according to the ambient brightness and increasing the number of adjustable levels.

[0071] In some embodiments, the third gate 172 forms a first gap Gap1 with the second source 153 or the second drain 154. The first gap is greater than or equal to 2 microns and less than or equal to 15 microns.

[0072] The third gate 172 does not overlap with the second source 153 or the second drain 154 in the first direction, which can reduce the parasitic capacitance and increase the photosensitive current. Defining the first gap to be greater than or equal to 2 microns can avoid the situation that the gap is too small to increase the photosensitive current; defining the first gap to be less than or equal to 15 microns can avoid the situation that the gap is too large resulting in a significant decline in the electrical characteristics of the second thin film transistor in the dark state.

[0073] In some embodiments, the third gate 172 forms a first gap Gap1 with the second source 153, and the third gate 172 forms a second gap Gap2 with the second drain 154. As Figure 5 shown, the first gap is greater than or equal to 1 micron, the second gap is greater than or equal to 1 micron, and the sum of the first gap and the second gap is less than or equal to 15 microns.

[0074] It is specified that both the first gap and the second gap are greater than or equal to 2 micrometers to avoid the situation where the gap is too small to increase the photosensitive current; it is specified that the sum of the first gap and the second gap is less than or equal to 15 micrometers to avoid the situation where the gap is too large, resulting in a significant decline in the electrical characteristics of the second thin-film transistor in the dark state.

[0075] In some embodiments, the array substrate 100 further includes an ohmic contact layer 180 formed between the active layer 140 and the second metal layer 150. The material for making the ohmic contact layer 180 includes doped semiconductor materials or metal silicides.

[0076] An ohmic contact layer 180 is provided between the active layer 140 and the second metal layer 150 to form an ohmic contact between the active layer 140 and the second metal layer 150, which can reduce the interface resistance between the active layer 140 and the second metal layer 150 and improve the electrical characteristics of the thin-film transistor.

[0077] In some embodiments, the distance between the edge of the second gate 122 and the corresponding source-drain electrode (i.e., the second source-drain electrode) is greater than or equal to 3 micrometers.

[0078] By defining the distance between the edge of the second gate 122 and the corresponding source-drain electrode, it is ensured that the second gate 122 can reliably shield the second semiconductor portion 142, which can reduce or eliminate the influence of backlight irradiation on the photosensitive current of the ambient light sensor.

[0079] In some embodiments, the insulating protection layer 160 and the gate insulating layer 130 are provided with a first communication hole 161 communicating with the second gate 122. The third gate 172 is connected to the second gate 122 through the first communication hole 161. The first communication hole 161 is located on one side of the second semiconductor portion 142 in the second direction, and the second direction is perpendicular to the first direction. In the first direction, the second source electrode 153 and the second drain electrode 154 are arranged on the same straight line, and the position of the first communication hole 161 can be centered and aligned with respect to the second source electrode 153 and the second drain electrode 154.

[0080] The first communication hole 161 is located on one side of the second semiconductor portion 142 in the second direction, which can reduce the area of the second thin-film transistor occupying the array substrate 100. In addition, the second source electrode 153 and the second drain electrode 154 are arranged on the same straight line, which can increase the photosensitive current of the second thin-film transistor.

[0081] In some embodiments, the material for making the gate insulating layer 130 includes silicon dioxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), silicon oxynitride (SiON), and hafnium oxide (HfO), and the material for making the insulating protection layer 160 includes silicon dioxide and aluminum oxide.

[0082] The gate insulating layer 130 is used to isolate the gate from the semiconductor portion to effectively control the channel carriers. The gate insulating layer 130 needs to ensure a high capacitance between the gate and the semiconductor portion while ensuring a low leakage current. The insulating protective layer 160 is mainly used to protect the thin film transistor from the external environment, such as preventing the erosion and contamination of the thin film transistor by water vapor, oxygen, impurity ions, etc. In the prior art, the manufacturing materials of the gate insulating layer 130 and the insulating protective layer 160 are not completely the same.

[0083] In this embodiment, the insulating protective layer 160 serves both as the gate insulating film layer of the second thin film transistor and as the passivation layer of the first thin film transistor and the second thin film transistor. The insulating protective layer 160 selects an insulating material that can be used for both the gate insulating layer 130 and the passivation layer.

[0084] Embodiment 2

[0085] The main difference between Embodiment 2 and Embodiment 1 is that in Embodiment 2, the array substrate 100 further includes a planarization layer 190.

[0086] See Figure 6 As shown, in this embodiment, the display panel 10 includes an array substrate 100. The array substrate 100 further includes a planarization layer 190. The planarization layer 190 is formed on the side of the insulating protective layer 160 away from the substrate 110. The pixel electrode 171 is formed on the side of the planarization layer 190 away from the substrate 110. A groove 191 extending to the insulating protective layer 160 is formed on the planarization layer 190, and the third gate 172 is located in the groove 191.

[0087] By providing the planarization layer 190 on the side of the insulating protective layer 160 away from the substrate 110, the planarization layer 190 can planarize the area under the pixel electrode 171, improve the film layer uniformity of the pixel electrode 171, and avoid inconsistent alignment of liquid crystal molecules caused by an uneven surface, thereby affecting the display effect.

[0088] In some embodiments, the planarization layer 190 is located between the transparent conductive layer 170 and the insulating protective layer 160. As Figure 7 shown, the pixel electrode 171 passes through the planarization layer 190 and the insulating protective layer 160 to be connected to the source-drain electrodes. That is to say, both the pixel electrode 171 and the third gate 172 can be provided on the side of the planarization layer 190 away from the substrate 110. The planarization layer 190 can be made of an organic insulating material.

[0089] The third gate 172 is located on the side of the planarization layer 190 away from the substrate 110. The distance between the third gate 172 and the second semiconductor portion 142 is increased, which can improve the electrical characteristics of the second thin film transistor.

[0090] It should be noted that whether the third gate 172 is specifically disposed on the side of the insulating protection layer 160 away from the substrate 110 or on the side of the planar layer 190 away from the substrate 110 can be determined according to the materials and thicknesses of the insulating protection layer 160 and the planar layer 190 as the case may be.

[0091] Embodiment 3

[0092] The present application also provides a method for manufacturing a display panel for manufacturing the display panel 10 disclosed in Embodiment 1 and Embodiment 2. Refer to Figures 8 to 12 As shown, the method for manufacturing a display panel includes:

[0093] S100: Form a first metal material layer on the substrate 110, pattern the first metal material layer to form a first metal layer 120, and the first metal layer 120 includes a first gate 121 and a second gate 122 arranged at intervals;

[0094] S200: Form a gate insulating layer 130 covering the first gate 121 and the second gate 122 on the substrate 110;

[0095] S300: Form a semiconductor material layer on the side of the gate insulating layer 130 away from the substrate 110, pattern the semiconductor material layer to form an active layer 140, and the active layer 140 includes a first semiconductor portion 141 and a second semiconductor portion 142. The first semiconductor portion 141 is located on the side of the first gate 121 away from the substrate 110, and the second semiconductor portion 142 is located on the side of the second gate 122 away from the substrate 110;

[0096] S400: Form a second metal material layer on the side of the gate insulating layer 130 away from the substrate 110, pattern the second metal material layer to form a second metal layer 150, and the second metal layer 150 includes source / drain electrodes, and the source / drain electrodes are at least located on the side of the first semiconductor portion 141 away from the substrate 110 and on the side of the second semiconductor portion 142 away from the substrate 110;

[0097] S500: Form an insulating protection layer 160 covering the source / drain electrodes and the active layer 140, pattern the insulating protection layer 160 and the gate insulating layer 130 to form a first communication hole 161 and a second communication hole 162. The first communication hole 161 communicates with the second gate 122, and the second communication hole 162 communicates with the source / drain electrode corresponding to a part of the first semiconductor portion 141;

[0098] S600: A transparent conductive material layer is formed on the side of the insulating protective layer 160 away from the substrate 110, and the transparent conductive material layer is patterned to form a transparent conductive layer 170. The transparent conductive layer 170 includes a pixel electrode 171 and a third gate 172. The pixel electrode 171 is connected to the source-drain electrodes corresponding to a part of the first semiconductor portion 141 through a second communication hole 161. The orthographic projection of the third gate 172 on the active layer 140 overlaps with the second semiconductor portion 142, and the third gate 172 is connected to the third gate 172 through a first communication hole 161.

[0099] It should be understood that when the array substrate 100 further includes an ohmic contact layer 180 and a planarization layer 190, the ohmic contact layer 180 can be formed before the second metal layer 150, and the planarization layer 190 can be formed before the transparent conductive layer 170. In addition, the manufacturing method of the display panel may further include the steps of manufacturing a counter substrate 200 and setting the array substrate 100 and the counter substrate 200 in a cell and injecting liquid crystal to form a liquid crystal layer 300.

[0100] The second thin film transistor of the display panel 10 includes a second gate 122, a third gate 172, a second semiconductor portion 142, and a second source-drain electrode. The second thin film transistor is a double-gate thin film transistor, which improves the reliability of the ambient light sensor and can avoid inaccurate detection of the photosensitive current resulting in inaccurate adjustment of the display brightness.

[0101] Embodiment 4

[0102] See Figure 13 As shown, in this embodiment, the display device includes a backlight module 20 and the display panel 10 disclosed in Embodiment 1 or Embodiment 2. The display panel 10 is disposed on the light-emitting side of the backlight module 20. The display device may further include a driving module. Both the backlight module 20 and the display panel 10 are connected to the driving module. The display panel 10 may include at least one second thin film transistor. The second thin film transistor is connected to the driving module through a first thin film transistor. The second thin film transistor is used to generate a photosensitive current, and the first thin film transistor is used to read the photosensitive current and output it to the driving module. The driving module adjusts the backlight brightness of the backlight module 20 according to the magnitude of the read photosensitive current.

[0103] In this embodiment, the display device includes a display panel 10, and the display panel 10 includes a substrate 110 and a first metal layer 120, a gate insulating layer 130, an active layer 140, a second metal layer 150, an insulating protection layer 160, and a transparent conductive layer 170 formed in sequence on the substrate 110. The first metal layer 120 includes a first gate 121 and a second gate 122. The gate insulating layer 130 covers at least the first metal layer 120. The active layer 140 includes a first semiconductor portion 141 and a second semiconductor portion 142. The second metal layer 150 includes source-drain electrodes, and the source-drain electrodes are formed at least on the side of the first semiconductor portion 141 and the second semiconductor portion 142 away from the substrate 110. The insulating protection layer 160 covers the active layer 140 and the second metal layer 150. The transparent conductive layer 170 includes a pixel electrode 171 and a third gate 172. The pixel electrode 171 is connected to the source-drain electrodes corresponding to a part of the first semiconductor portion 141. The third gate 172 overlaps with the second semiconductor portion 142 in the orthographic projection on the active layer 140, and the third gate 172 is connected to the second gate 122. The second thin film transistor includes a second gate 122, a third gate 172, a second semiconductor portion 142, and a second source-drain electrode. The second thin film transistor is a double-gate thin film transistor, which improves the reliability of the ambient light sensor and can avoid inaccurate detection of the photosensitive current resulting in inaccurate adjustment of the display brightness.

[0104] The terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of this application, the meaning of "a plurality" is two or more, unless otherwise specifically defined.

[0105] In this application, unless otherwise clearly specified and limited, the terms "assembly", "connection", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0106] In the description of this specification, the descriptions referring to the terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0107] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and the description of the present application shall fall within the scope covered by the patent of the present application.

Claims

1. A display panel, comprising a base substrate, characterized in that: The display panel further includes: A first metal layer is formed on one side of the substrate, the first metal layer comprising a first gate and a second gate; A gate insulating layer, formed on one side of the base substrate and covering the first metal layer; An active layer is formed on a side of the gate insulating layer away from the base substrate, the active layer comprising a first semiconductor portion and a second semiconductor portion, the first semiconductor portion is located on a side of the first gate away from the base substrate, and the second semiconductor portion is located on a side of the second gate away from the base substrate; A second metal layer includes a source and a drain, wherein the source and the drain are formed at least on a side of the first semiconductor portion away from the substrate and a side of the second semiconductor portion away from the substrate; An insulating protection layer, formed on a side of the gate insulating layer away from the base substrate and covering the active layer and the second metal layer; A transparent conductive layer is formed on a side of the insulating protective layer away from the base substrate, the transparent conductive layer includes a pixel electrode and a third gate, the pixel electrode is connected to the source and drain corresponding to a portion of the first semiconductor portion, the third gate has an orthographic projection on the active layer that overlaps with the second semiconductor portion, and the third gate is connected to the second gate.

2. The display panel according to claim 1, characterized in that: The source and drain include a second source and a second drain spaced apart along a first direction, the second source and the second drain are at least located on a side of the second semiconductor portion away from the base substrate, the third gate is connected to the second gate via a first connecting hole penetrating the insulating protection layer and the gate insulating layer, the first connecting hole is located on one side of the second direction of the second semiconductor portion, and the second direction is perpendicular to the first direction.

3. The display panel according to claim 1, characterized in that: The source and drain include a second source and a second drain spaced apart along a first direction, the second source and the second drain are at least located on a side of the second semiconductor portion away from the base substrate, and in the first direction, the second gate forms a gap with at least one of the second source and the second drain.

4. The display panel according to claim 3, characterized in that: The second gate and the second source or the second drain form a first gap, and the first gap is greater than or equal to 2 micrometers, and the first gap is less than or equal to 15 micrometers.

5. The display panel according to claim 3, characterized in that: The second gate and the second source form a first gap, the second gate and the second drain form a second gap, the first gap is greater than or equal to 1 micron, the second gap is greater than or equal to 1 micron, and the sum of the first gap and the second gap is less than or equal to 15 microns.

6. The display panel according to claim 1, characterized in that: The source and drain include a second source and a second drain spaced apart along a first direction, the second source and the second drain are located at least on a side of the second semiconductor portion away from the substrate, at least in the first direction, the edges of the second source and the second drain extend to the outside of the second semiconductor portion, and the distance between the edge of the second gate and the corresponding source and drain is greater than or equal to 3 microns.

7. The display panel according to any one of claims 1 to 5, characterized in that: The display panel further comprises a flat layer, the flat layer is formed on a side of the insulating protection layer away from the base substrate, the pixel electrode is formed on a side of the flat layer away from the base substrate, a groove extending to the insulating protection layer is formed on the flat layer, and the third gate is located in the groove; or The display panel further includes a planar layer, which is located between the transparent conductive layer and the insulating protective layer, and the pixel electrode is connected to the source and drain electrodes through the planar layer and the insulating protective layer.

8. The display panel according to claim 1, characterized in that: The gate insulating layer is made of materials including silicon dioxide, aluminum oxide, silicon oxynitride and hafnium oxide, and the insulating protection layer is made of materials including silicon dioxide and aluminum oxide.

9. A method for manufacturing a display panel, characterized in that: include: Forming a first metal material layer on the base substrate, and patterning the first metal material layer to form a first gate and a second gate; forming a gate insulating layer covering the first gate and the second gate on the base substrate; Forming a semiconductor material layer on a side of the gate insulating layer away from the substrate, patterning the semiconductor material layer to form an active layer, wherein the active layer includes a first semiconductor portion and a second semiconductor portion, wherein the first semiconductor portion is located on a side of the first gate away from the substrate, and the second semiconductor portion is located on a side of the second gate away from the substrate; Forming a second metal material layer on a side of the gate insulating layer away from the base substrate, patterning the second metal material layer to form source and drain electrodes, wherein the source and drain electrodes are at least located on a side of the first semiconductor portion away from the base substrate and a side of the second semiconductor portion away from the base substrate; forming an insulating protection layer covering the source and drain electrodes and the active layer; A transparent conductive material layer is formed on the side of the insulating protection layer away from the base substrate, and the transparent conductive material layer is patterned to form a pixel electrode and a third gate. The pixel electrode is connected to the source and drain corresponding to a portion of the first semiconductor portion. The orthographic projection of the third gate on the active layer overlaps with the second semiconductor portion, and the third gate is connected to the second gate.

10. A display device, characterized in that: include: Backlight module; The display panel according to any one of claims 1 to 8 is arranged on the light output side of the backlight module.

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