Display panel
By introducing a pseudo-electrode into the sub-pixel transistor of the display panel, increasing the channel length and masking the semiconductor layer, the problem of leakage in the high-pixel density display panel is solved, and better display quality and sufficient storage capacitance are achieved.
Patent Information
- Application Number
- CN202311617679.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-30
- Publication Date
- 2025-06-03
AI Technical Summary
In a display panel with high pixel density, how to effectively suppress leakage under limited transistor sizes and ensure display quality.
A dummy electrode is introduced into the transistor of the subpixel of the display panel, which is arranged between the source and the drain, and the channel length of the transistor is increased, and a partial semiconductor layer is masked by the dummy electrode to reduce leakage current.
Effectively suppress leakage, improve the display quality of the display panel, and at the same time, the area of the transistor is not greatly increased, thereby retaining enough area to set the pixel electrodes, and avoiding the image quality affected by insufficient capacitance during low-frequency driving.
Smart Images
Figure CN120091628A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a display panel, and particularly to a display panel having a transistor with low leakage current. Background Art
[0002] In a display panel with a high pixel density (pixels per inch, PPI), the area of each sub-pixel is small, which limits the size of the transistor. Therefore, one of the objectives of the present invention is to effectively suppress leakage current under the limited size of the transistor and enable the display panel to have better display quality. Summary of the Invention
[0003] Therefore, the objective of the present invention is to provide a display panel, and the technical problem to be solved is how to effectively suppress leakage current under the limited size of the transistor and enable the display panel to have better display quality.
[0004] To solve the above technical problem, the present invention provides a display panel, which includes a substrate and a sub-pixel. The sub-pixel is disposed on the substrate. The sub-pixel includes a transistor, and the transistor includes a gate, a semiconductor layer, a source electrode, a drain electrode, and a dummy electrode. The gate is disposed on the substrate. The semiconductor layer is disposed on the gate. The source electrode and the drain electrode are disposed on the semiconductor layer, wherein the source electrode is disposed at one end of the semiconductor layer, and the drain electrode is disposed at the other end of the semiconductor layer. The dummy electrode is disposed on the semiconductor layer and between the source electrode and the drain electrode, wherein the dummy electrode is separated from the source electrode, the dummy electrode is separated from the drain electrode, and the dummy electrode is electrically floating.
[0005] In the display panel of the present invention, the transistor of the sub-pixel has a dummy electrode disposed between the source electrode and the drain electrode, which can increase the channel length of the transistor and thus suppress leakage current. In addition, a part of the semiconductor layer can be shielded by the dummy electrode, and the semiconductor layer receiving light to generate leakage current is reduced. In addition, although the transistor further includes a dummy electrode, the area of the transistor is not significantly increased, so that there is still enough area in the sub-pixel to dispose a pixel electrode, and thus there can be enough storage capacitance and the image quality can be prevented from being affected due to insufficient capacitance during low-frequency driving. Brief Description of the Drawings
[0006] Figure 1 A top view schematic diagram of a sub-pixel of a display panel according to a first embodiment of the present invention.
[0007] Figure 2 An enlarged schematic diagram of a transistor of a display panel according to a first embodiment of the present invention.
[0008] Figure 3 A cross-sectional schematic diagram of a transistor of a display panel according to a first embodiment of the present invention.
[0009] Figure 4 An enlarged schematic diagram of a transistor of a display panel according to a second embodiment of the present invention.
[0010] Description of reference numerals: 10 - display panel; 100 - substrate; 202, 206 - conductive layer; 204 - gate insulating layer; 301, 305 - first part; 303, 307 - second part; 309 - connecting part; CH - semiconductor layer; CHa - first region; CHb - second region; CHc - third region; CL - common signal line; CO1, CO2 - contact hole; D - drain; D1, D2 - distance; DL - data line; DM - dummy electrode; DR1, DR2, DR3 - direction; FE, CE - electrode; G - gate; GL - scan line; PR1, PR2 - protrusion; RE - reflective electrode; S - source; SP - sub - pixel; SW - transistor; TE - transparent electrode; W - channel width. Detailed implementation manners
[0011] To enable those of ordinary skill in the art to further understand the present invention, the following preferably enumerate the embodiments of the present invention and, in conjunction with the accompanying drawings, detail the composition and the achieved effects of the present invention. It should be noted that the accompanying drawings are all simplified schematic diagrams. Therefore, only the elements and the combination relationships related to the present invention are shown to provide a clearer description of the basic structure or implementation method of the present invention, while the actual elements and layouts may be more complex. Additionally, for the convenience of description, the elements shown in the accompanying drawings of the present invention are not drawn in an equal proportion according to the actual number, shape, and size of the implementation. The detailed ratio can be adjusted according to the design requirements.
[0012] In the following accompanying drawings, a direction DR1, a direction DR2, and a direction DR3 are marked. The direction DR3 can be the normal direction or the top - view direction. For example, Figure 3 , the direction DR3 can be perpendicular to an upper surface of a substrate 100. For example, Figure 1 , the direction DR1 and the direction DR2 can be horizontal directions and can be perpendicular to the direction DR3, and the direction DR1 and the direction DR2 are different. For example, the direction DR1 can be perpendicular to the direction DR2. The following accompanying drawings can describe the spatial relationship of the structure according to the direction DR1, the direction DR2, and the direction DR3.
[0013] Please refer to Figures 1 to 3 , Figure 1 A top - view schematic diagram of a sub - pixel of a display panel according to a first embodiment of the present invention, Figure 2 An enlarged schematic diagram of a transistor of a display panel according to a first embodiment of the present invention, and Figure 3Schematic cross-sectional view of a transistor of a display panel according to a first embodiment of the present invention. The display panel of this embodiment is taken as an example of a reflective type or a transflective type display panel, but the present invention is not limited thereto. As Figure 1 shown, the display panel 10 includes a substrate 100, a scan line GL, and a data line DL. The substrate 100 may include a rigid substrate such as a glass substrate, a plastic substrate, a quartz substrate, or a sapphire substrate, but is not limited thereto. The substrate 100 may also include a flexible substrate such as a polyimide (PI) substrate or a polyethylene terephthalate (PET) substrate, but is not limited thereto.
[0014] The scan line GL and the data line DL are disposed on the substrate 100. The scan line GL extends along the direction DR1, and the data line DL extends along the direction DR2. A sub-pixel SP is disposed on the substrate 100 and may correspond to the scan line GL and the data line DL. In addition, the display panel 10 may include a plurality of scan lines GL and a plurality of data lines DL, and the scan lines GL and the data lines DL may intersect to form a plurality of sub-pixels SP.
[0015] The sub-pixel SP includes a transistor SW, and the transistor SW is disposed on the substrate 100. The transistor SW may be, for example, a bottom-gate thin film transistor, but is not limited thereto. The design concept of the present invention can also be applied to a top-gate thin film transistor. In addition, the transistor SW may be a low temperature poly-silicon (LTPS) thin film transistor, an indium gallium zinc oxide (IGZO) thin film transistor, or an amorphous silicon (a-Si) thin film transistor, but is not limited thereto.
[0016] The transistor SW includes a gate G, a source S, a drain D, a semiconductor layer CH, and a gate insulating layer 204. The scan line GL is electrically connected to the gate G of the transistor SW, and a switching signal for controlling the transistor SW may be provided to the gate G of the transistor SW through the scan line GL, thereby controlling the update of the display screen. The data line DL is electrically connected to the source S of the transistor SW, and a grayscale signal of the screen may be provided to the source S of the transistor SW through the data line DL.
[0017] As Figure 3, the gate G is disposed on the substrate 100, the semiconductor layer CH is disposed on the gate G, and the gate insulating layer 204 is disposed between the gate G and the semiconductor layer CH. The source S and the drain D are disposed on the semiconductor layer CH, and as Figure 2 and Figure 3 shown, the source S is disposed at one end of the semiconductor layer CH, and the drain D is disposed at the other end of the semiconductor layer CH. As Figure 2 , the source S overlaps with a first region CHa of the semiconductor layer CH in the direction DR3, and the drain D overlaps with a second region CHb of the semiconductor layer CH in the direction DR3.
[0018] The transistor SW further includes a dummy electrode DM. As Figure 3 , the dummy electrode DM is disposed on the semiconductor layer CH, and the dummy electrode DM can be in direct contact with the semiconductor layer CH. As Figure 2 , the dummy electrode DM is disposed between the source S and the drain D, the dummy electrode DM and the source S are separated, and the dummy electrode DM and the drain D are also separated. In this embodiment (as Figure 2 ), the dummy electrode DM has a rectangular structure, and the dummy electrode DM overlaps with a part of the semiconductor layer CH (such as a third region CHc) in the direction DR3, but is not limited thereto. In addition, the dummy electrode DM is electrically floating.
[0019] In existing transistors, when the gate is turned off, the current cannot be completely turned off, and there is still a partial leakage path in the semiconductor layer, resulting in transistor leakage. According to the following equation (1), the amount of leakage is inversely proportional to the channel length of the transistor.
[0020]
[0021] In equation (1), I off is the leakage current (unit: nanoampere, nA), W is the channel width, L is the channel length, Vt is the threshold voltage, and S is the subthreshold swing.
[0022] In the present invention, the dummy electrode DM disposed between the source S and the drain D can increase the channel length of the transistor SW. When the channel length of the transistor SW increases, the path of electron leakage increases, making it difficult for electrons to reach the electrode at the other end, thereby suppressing leakage. As Figure 2 , there is a distance D1 between the dummy electrode DM disposed on the semiconductor layer CH and the source S, and there is a distance D2 between the dummy electrode DM disposed on the semiconductor layer CH and the drain D, and the sum of the distance D1 and the distance D2 is the channel length of the transistor SW.
[0023] In this embodiment, the distance D1 and the distance D2 can each be 4 micrometers, the channel length of the transistor SW can be 8 micrometers, and a channel width W of the transistor SW can be 17 micrometers, but not limited thereto. The distance D1 and the distance D2 can be measured, for example, in the direction DR1, and the channel width W can be measured, for example, in the direction DR2.
[0024] As Figure 2 and Figure 3 shown, the dummy electrode DM overlaps with a part of the semiconductor layer CH (such as the third region CHc) in the direction DR3. Therefore, the third region CHc of the semiconductor layer CH can be shielded by the dummy electrode DM, reducing the exposed area of the upper surface of the semiconductor layer CH and reducing the leakage current generated by the upper surface of the semiconductor layer CH receiving light. On the other hand, the semiconductor layer CH overlaps with the gate G in the direction DR3. Therefore, the light from the backlight module can be shielded by the gate G, reducing the leakage current generated by the lower surface of the semiconductor layer CH receiving light.
[0025] As Figure 1 shown, the sub-pixel SP includes an electrode FE, and the electrode FE can be disposed on one side of the transistor SW and electrically connected to the drain D of the transistor SW. The sub-pixel SP includes a transparent electrode TE (represented by a thick black line), and the transparent electrode TE is disposed on the electrode FE and electrically connected to the electrode FE. For example, an insulating layer can be disposed between the transparent electrode TE and the electrode FE. The insulating layer can have a contact hole CO1, and the transparent electrode TE can be electrically connected to the electrode FE through the contact hole CO1, but not limited thereto.
[0026] The sub-pixel SP includes a reflective electrode RE (represented by a semi-thick black line) disposed on the transparent electrode TE and electrically connected to the transparent electrode TE. For example, an insulating layer can be disposed between the reflective electrode RE and the transparent electrode TE. The insulating layer can have a contact hole CO2, and the reflective electrode RE can be electrically connected to the transparent electrode TE through the contact hole CO2, but not limited thereto. The reflective electrode RE, the transparent electrode TE, and the electrode FE are electrically connected to each other and are collectively electrically connected to the drain D of the transistor SW. Therefore, the reflective electrode RE, the transparent electrode TE, and the electrode FE can together serve as a pixel electrode.
[0027] In other words, the sub-pixel SP includes a pixel electrode. The pixel electrode is disposed on the substrate 100 and electrically connected to the drain D of the transistor SW, and the pixel electrode includes the electrode FE, the transparent electrode TE, and the reflective electrode RE.
[0028] The sub-pixel SP includes an electrode CE, and the electrode CE is disposed between the electrode FE and the substrate 100. The display panel 10 includes a common signal line CL. The common signal line CL extends along the direction DR1. The electrode CE is electrically connected to the common signal line CL, and the common signal line CL can provide a common voltage to the electrode CE.
[0029] In the present invention, although the transistor SW further includes a dummy electrode DM, the area of the transistor SW is not significantly increased, so that there is still enough area in the sub-pixel SP to set the pixel electrode (such as the electrode FE, the transparent electrode TE, and the reflective electrode RE) and the common electrode (such as the electrode CE), and thus a sufficient storage capacitor can be provided. Therefore, it is possible to avoid affecting the image quality due to insufficient capacitance during low-frequency driving.
[0030] On the other hand, as Figure 3 , the display panel 10 includes a conductive layer 202 and a conductive layer 206. The conductive layer 202 is disposed on the substrate 100, and the conductive layer 202 may include Figure 1 the scanning line GL, the gate G of the transistor SW, the electrode CE, and the common signal line CL in Figure 1 , but is not limited thereto. The gate insulating layer 204 is disposed on the conductive layer 202, and the semiconductor layer CH is disposed on the gate insulating layer 204. The conductive layer 206 is disposed on the semiconductor layer CH and the gate insulating layer 204, and the conductive layer 206 may include
[0031] the data line DL, the electrode FE, and the source S, drain D, and dummy electrode DM of the transistor SW in
[0032] , but is not limited thereto. Therefore, the dummy electrode DM, the source S, and the drain D are formed by the same conductive layer, and the materials of the dummy electrode DM, the source S, and the drain D are the same, but are not limited thereto. In some embodiments, another conductive layer may also be disposed on the conductive layer 206 and between the conductive layer 206 and the transparent electrode TE, but is not limited thereto.
[0033] Please refer to Figure 4 , Figure 4An enlarged schematic diagram of a transistor of a display panel according to a second embodiment of the present invention. In this embodiment, the gate G includes a protrusion PR1 and a protrusion PR2, and the protrusion PR1 and the protrusion PR2 are arranged adjacent to each other and electrically connected to each other. The semiconductor layer CH includes a first portion 301 and a second portion 303. The first portion 301 is disposed on the protrusion PR1 of the gate G, and the second portion 303 is disposed on the protrusion PR2 of the gate G, and the first portion 301 and the second portion 303 are separated.
[0034] The dummy electrode DM includes a first portion 305, a second portion 307, and a connection portion 309. The first portion 305 of the dummy electrode DM is located at one end of the dummy electrode DM and is disposed close to the drain D, and the first portion 305 is disposed on the first portion 301 of the semiconductor layer CH. Therefore, the first portion 301 of the semiconductor layer CH is disposed between the protrusion PR1 of the gate G and the first portion 305 of the dummy electrode DM.
[0035] The second portion 307 of the dummy electrode DM is located at the other end of the dummy electrode DM and is disposed close to the source S, and the second portion 307 is disposed on the second portion 303 of the semiconductor layer CH. Therefore, the second portion 303 of the semiconductor layer CH is disposed between the protrusion PR2 of the gate G and the second portion 307 of the dummy electrode DM.
[0036] The first portion 305 and the second portion 307 of the dummy electrode DM have a U-shaped structure, and the U-shaped openings of the first portion 305 and the second portion 307 face opposite directions. At least a part of the drain D can be disposed within the U-shaped opening of the first portion 305, and at least a part of the source S can be disposed within the U-shaped opening of the second portion 307. In addition, the connection portion 309 is disposed between the first portion 305 and the second portion 307 and is connected to the first portion 305 and the second portion 307.
[0037] The dummy electrode DM of this embodiment can also provide the same effects as those described in the first embodiment. In addition, when the first portion 305 and the second portion 307 of the dummy electrode DM have a U-shaped structure, the channel width of the transistor SW can be increased, and the charging efficiency of the transistor SW can be optimized. In this embodiment, the source S and a part of the data line DL connected thereto can have a smaller size (such as area), which can reduce the parasitic capacitance between the data line DL and the scan line GL and can improve the charging efficiency of the transistor SW. In addition, the drain D and a part of the pixel electrode's electrode FE connected thereto can have a smaller size (such as area), which can reduce the leakage of the storage capacitance.
[0038] In summary, in the display panel of the present invention, the transistor of the sub-pixel has a pseudo-electrode, which is disposed between the source and the drain, can increase the channel length of the transistor, and thus can suppress leakage current. In addition, a part of the semiconductor layer can be shielded by the pseudo-electrode, and the leakage current generated by the semiconductor layer receiving light can be reduced. In some embodiments, when the pseudo-electrode has a U-shaped structure, the charging efficiency of the transistor can be optimized. In addition, although the transistor further includes a pseudo-electrode, the area of the transistor is not significantly increased, so that there is still enough area in the sub-pixel to set the pixel electrode, and thus there can be enough storage capacitance and the image quality can be prevented from being affected by insufficient capacitance during low-frequency driving.
[0039] The foregoing are only the preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention for those of ordinary skill in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.
Claims
1. A display panel, characterized in that, comprising: a substrate; and a sub-pixel, disposed on the substrate, wherein the sub-pixel includes a transistor, and the transistor includes: a gate, disposed on the substrate; a semiconductor layer, disposed on the gate; a source electrode and a drain electrode, disposed on the semiconductor layer, wherein the source electrode is disposed at one end of the semiconductor layer, and the drain electrode is disposed at the other end of the semiconductor layer; and a pseudo electrode, disposed on the semiconductor layer and between the source electrode and the drain electrode, wherein the pseudo electrode is separated from the source electrode, the pseudo electrode is separated from the drain electrode, and the pseudo electrode is electrically floating.
2. The display panel according to claim 1, characterized in that, the materials of the pseudo electrode, the source electrode and the drain electrode are the same.
3. The display panel according to claim 1, characterized in that, the pseudo electrode overlaps with a part of the semiconductor layer.
4. The display panel according to claim 1, characterized in that, the pseudo electrode directly contacts the semiconductor layer.
5. The display panel according to claim 1, characterized in that, the pseudo electrode has a rectangular structure.
6. The display panel according to claim 1, characterized in that, the pseudo electrode includes: a first part, located at one end of the pseudo electrode and close to the drain electrode; a second part, located at the other end of the pseudo electrode and close to the source electrode, and the first part and the second part have a U-shaped structure; and a connecting part, disposed between the first part and the second part.
7. The display panel according to claim 6, characterized in that, the semiconductor layer includes: a first part, disposed between the gate and the first part of the pseudo electrode; and a second part, disposed between the gate and the second part of the pseudo electrode, and the first part of the semiconductor layer and the second part of the semiconductor layer are separated.
8. The display panel according to claim 1, characterized in that, the sub-pixel further includes: a scanning line, disposed on the substrate and electrically connected to the gate of the transistor; a data line, disposed on the substrate and electrically connected to the source electrode of the transistor; and a pixel electrode, disposed on the substrate and electrically connected to the drain electrode of the transistor.
9. The display panel according to claim 8, characterized in that, the pixel electrode includes: an electrode, disposed on one side of the transistor and electrically connected to the drain electrode of the transistor; a transparent electrode, disposed on the electrode and electrically connected to the electrode; and a reflective electrode, disposed on the transparent electrode and electrically connected to the transparent electrode.
10. The display panel according to claim 1, characterized in that, the transistor further includes a gate insulating layer, and the gate insulating layer is disposed between the gate and the semiconductor layer.