Vertical charge transfer imaging sensing device and manufacturing method thereof

Abstract

The invention relates to a vertical charge transfer imaging sensing device and a manufacturing method thereof. In the vertical charge transfer imaging sensing device, a deep trench isolation medium isolates a pixel region and a common substrate region in a substrate, the pixel region and a gate structure above the pixel region form an MOS (Metal Oxide Semiconductor) capacitor, and a substrate end voltage of the MOS capacitor is applied to the common substrate region from one side of the front surface of the substrate; the deep trench isolation medium is formed on the back surface of the substrate and is transmitted to each pixel region through the polycrystalline silicon layer formed on the back surface of the substrate, so that the problems that interface defects are difficult to control and the contact resistance is large when a metal electrode is formed on the back surface of the substrate can be avoided; the third isolation dielectric layer covers the deep trench electrode from one side of the back surface of the substrate, and the top surface of the third isolation dielectric layer is flush with the back surface of the substrate, so that effective isolation is formed between pixels, the manufacturing difficulty of other structures formed on the polycrystalline silicon layer can be reduced, and the quality and reliability of the vertical charge transfer imaging sensor can be improved.

Description

Technical Field

[0001] The present invention relates to the field of photosensitive technology, and in particular, to a vertically charge-transferring imaging sensor device and a manufacturing method thereof. Background Art

[0002] A vertically charge-transferring imaging sensor device (Vertically charge transferring Pixel Sensors) is an image sensor that uses a substrate and a floating-gate transistor structure to achieve imaging. Figure 1 It is a planar schematic diagram of a vertically charge-transferring imaging sensor device. Figure 2 It is along Figure 1 a cross-sectional schematic diagram of the vertically charge-transferring imaging sensor device in the XX' direction in Figure 1 and Figure 2 Referring to

[0003] Compared with traditional photodiode-based sensor devices (such as CMOS image sensors), the vertically charge-transferring imaging sensor device can achieve a higher full-well charge at the same pixel size, thus having a higher signal-to-noise ratio and having an obvious advantage in pixel scaling.

[0004] To avoid crosstalk of photoelectrons between different pixels, such as Figure 2As shown, currently, a deep trench isolation structure (DTI) is formed through the substrate 10 to physically isolate adjacent pixels. To facilitate applying a voltage to the substrate 10 which serves as the MOS capacitor electrode, a metal electrode 15 is embedded in the area between the pixels on the back surface of the substrate 10. Part of the surface of the metal electrode 15 is in direct contact with the substrate 10, and the other part of the surface is covered with a high-k dielectric layer 16 at an interval to cover the deep trench isolation structure. The high-k dielectric layer 16 is also formed on the back surface of the substrate 10 around the metal electrode 15.

[0005] However, the above-mentioned metal electrode 15 disposed on the back surface of the substrate 10 is embedded in the substrate 10 to connect the substrate 10, making it difficult to control the interface defects and having the problem of large contact resistance. Moreover, forming the above-mentioned back surface structure of the substrate requires multiple processes such as exposure, etching, and PVD. The process flow is long and difficult, which will increase the manufacturing cost of the vertical charge transfer imaging sensor device. Summary of the Invention

[0006] In order to form effective isolation between pixels while avoiding the above-mentioned problems existing when forming a metal electrode on the back surface of the substrate, the present invention provides a manufacturing method of a vertical charge transfer imaging sensor device and a vertical charge transfer imaging sensor device.

[0007] On the one hand, the present invention provides a manufacturing method of a vertical charge transfer imaging sensor device, and the forming method includes:

[0008] Providing a substrate, the substrate having a first doping type and including opposite front and back surfaces;

[0009] Forming a deep trench, a shallow trench, a deep trench isolation medium filling the deep trench, and a shallow trench isolation medium filling the shallow trench on the front side, the deep trench isolation medium isolating a first number of pixel regions and a second number of common substrate regions located between the pixel regions in the substrate, and the shallow trench isolation medium isolating a photosensitive region and a charge reading region within the pixel region. Wherein, the deep trench isolation medium includes a first isolation medium layer covering the side wall and the bottom wall of the deep trench, a deep trench electrode filled in the deep trench, and a second isolation medium layer covering the deep trench electrode from the front side;

[0010] Forming a gate structure on the surface of the pixel region;

[0011] Thinning the substrate from the back side, exposing the deep trench isolation medium from the back side, and removing part of the deep trench isolation medium from the exposed area to form a groove at one end of the deep trench facing the back side;

[0012] Filling a third isolation medium layer in the groove and making the top surface of the third isolation medium layer flush with the back surface of the substrate; and

[0013] A polysilicon layer is formed on the back side, covering the substrate and the third isolation dielectric layer. The polysilicon layer is electrically connected to the substrates of each pixel region and the common substrate region. Among them, the gate structure and the pixel region thereunder form a MOS capacitor, and the substrate terminal voltage of the MOS capacitor is applied to the common substrate region from the front side of the substrate.

[0014] Optionally, the cross-section of the deep trench is in a grid structure. After thinning the substrate from the back side, the deep trench portions in each region of the grid structure penetrate through the substrate.

[0015] Optionally, when thinning the substrate from the back side, a CMP process is performed to make the top surface of the exposed deep trench isolation dielectric flush with the back surface of the substrate.

[0016] Optionally, before removing part of the deep trench isolation dielectric from the exposed region after thinning the substrate from the back side, at least part of the first isolation dielectric layer covering the bottom wall of the deep trench is exposed, or at least part of the deep trench electrode is exposed.

[0017] Optionally, removing part of the deep trench isolation dielectric from the exposed region is performed by self-aligned wet etching.

[0018] Optionally, the bottom surface of the groove exposes the deep trench electrode.

[0019] Optionally, filling the groove with a third isolation dielectric layer and making the top surface of the third isolation dielectric layer flush with the back surface of the substrate includes: depositing a dielectric material in the groove and on the back surface of the substrate; and performing a CMP process to expose the back surface of the substrate, and the remaining dielectric material fills the groove to form the third isolation dielectric layer, and the top surface of the third isolation dielectric layer is flush with the back surface of the substrate.

[0020] Optionally, before depositing the dielectric material, the manufacturing method further includes: forming a linear oxide layer along the back surface of the substrate and the inner surface of the groove.

[0021] Optionally, forming the polysilicon layer includes: depositing an amorphous silicon layer on the back side of the substrate; and performing a laser crystallization process to convert the amorphous silicon layer into the polysilicon layer.

[0022] On the other hand, the present invention provides a vertical charge transfer imaging sensor device, which includes:

[0023] A substrate, having a first doping type and including opposite front and back surfaces, in which deep trenches, shallow trenches, deep trench isolation media filling the deep trenches, and shallow trench isolation media filling the shallow trenches are formed. Wherein, the deep trenches penetrate through the substrate, and the deep trench isolation media isolate a first number of pixel regions and a second number of common substrate regions located between the pixel regions in the substrate. The shallow trench isolation media isolate a photosensitive region and a charge reading region within the pixel regions. The deep trench isolation media includes a first isolation media layer covering the sidewalls of the deep trenches, a deep trench electrode filled in the deep trenches, a second isolation media layer covering the deep trench electrode from the front side, and a third isolation media layer covering the deep trench electrode from the back side. The top surface of the third isolation media layer is flush with the back surface of the substrate;

[0024] A polysilicon layer, covering the substrate and the deep trench isolation media from the back side of the substrate, and the polysilicon layer is electrically connected to the substrate of each of the pixel regions and the common substrate regions; and

[0025] A gate structure, formed on the surface of the pixel region, and the gate structure and the pixel region thereunder form a MOS capacitor. Wherein, the substrate terminal voltage of the MOS capacitor is applied to the common substrate region from the front side of the substrate.

[0026] Optionally, the gate structure includes a gate dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate stacked on the surfaces of the photosensitive region and the charge reading region. Wherein, the floating gate, the inter-gate dielectric layer, and the control gate extend from the photosensitive region to the charge reading region; the vertical charge transfer imaging sensor device further includes a source region and a drain region formed in the charge reading region and located on both sides of the gate structure, and the gate structure, the source region, and the drain region form a reading transistor.

[0027] Optionally, the vertical charge transfer imaging sensor device further includes:

[0028] An interlayer dielectric layer, covering the substrate and the gate structure from the front side of the substrate;

[0029] A substrate contact plug, penetrating through the interlayer dielectric layer and electrically connected to the common substrate region; and

[0030] A metal wiring layer, formed on the surface of the interlayer dielectric layer, and the metal wiring layer is electrically connected to the substrate contact plug.

[0031] Optionally, the substrate further includes a peripheral region formed around the first number of pixel regions and the second number of common substrate regions, and the metal wiring layer extends to the peripheral region; the vertical charge transfer imaging sensor device further includes:

[0032] A via hole, located in the peripheral region and penetrating the substrate, is electrically connected to the metal wiring layer; and

[0033] A back metal pad, formed in the peripheral region and located on the back side of the substrate, is electrically connected to the corresponding via hole. Wherein, the back metal pad is electrically connected to the common substrate region through the via hole, the metal wiring layer and the substrate contact plug, and the back metal pad is an input port for the substrate terminal voltage of the MOS capacitor.

[0034] Optionally, the vertical charge transfer imaging sensor further includes a high dielectric constant layer covering the polysilicon layer from the back side.

[0035] In the manufacturing method of the vertical charge transfer imaging sensor provided by the present invention, the deep trench isolation dielectric forms an effective isolation between the pixel regions in the substrate. The gate structure is formed on the surface of the pixel region and forms a MOS capacitor with the pixel region. In order to apply a voltage to the pixel region substrate that serves as an electrode in the MOS capacitor, a polysilicon layer electrically connected to the substrates of each pixel region and the common substrate region is formed on the back side of the substrate. The substrate terminal voltage of the MOS capacitor is applied to the common substrate region from the front side of the substrate, and this substrate terminal voltage is transmitted to the substrates of each pixel region through the common substrate region and the polysilicon layer, so that it is not necessary to form a metal electrode on the back side of the substrate, and problems such as difficult control of interface defects and large contact resistance existing when forming a metal electrode on the back side of the substrate can be avoided; in addition, before forming the polysilicon layer, the substrate is thinned from the back side, so that the deep trench isolation dielectric is exposed from the back side, and a part of the deep trench isolation dielectric is removed from the exposed area, a groove is formed at one end of the deep trench facing the back side, a third isolation dielectric layer is filled in the groove, and the top surface of the third isolation dielectric layer is flush with the back surface of the substrate. On the one hand, it can avoid the deep trench electrode in the deep trench isolation dielectric from contacting the polysilicon layer and causing a short circuit. On the other hand, it makes the surface of the polysilicon layer flat, which helps to reduce the difficulty of subsequent backside processes and improve the quality of subsequent backside processes.

[0036] In the vertical charge transfer imaging sensor device provided by the present invention, a deep trench isolation medium formed in a deep trench isolates the pixel region and the common substrate region in the substrate, which helps to avoid the crosstalk of photoelectrons between different pixel regions. Moreover, the substrate terminal voltage of the MOS capacitor formed by the gate structure and the pixel region thereunder is applied to the common substrate region from the front side of the substrate, and this substrate terminal voltage is transmitted to the substrates of each pixel region through the common substrate region and the polysilicon layer, so that it is not necessary to form a metal electrode on the back side of the substrate, and problems such as difficult control of interface defects and large contact resistance when forming a metal electrode on the back side of the substrate can be avoided. Further, in the deep trench isolation medium, a third isolation medium layer covers the deep trench electrode from the back side of the substrate, and the top surface of the third isolation medium layer is flush with the back side of the substrate. On the one hand, it can avoid the short circuit caused by the contact between the deep trench electrode and the polysilicon layer, and on the other hand, it makes the surface of the polysilicon layer flat, which helps to reduce the manufacturing difficulty of other structures formed on the polysilicon layer and improve the quality and reliability of the vertical charge transfer imaging sensor device. Description of the Drawings

[0037] Figure 1 is a plan view of the vertical charge transfer imaging sensor device.

[0038] Figure 2 is along Figure 1 in the XX' direction of the vertical charge transfer imaging sensor device is a cross-sectional view.

[0039] Figure 3 is a flowchart of the manufacturing method of the vertical charge transfer imaging sensor device according to an embodiment of the present invention.

[0040] Figures 4A to 4O is a cross-sectional view of the manufacturing method of the vertical charge transfer imaging sensor device according to an embodiment of the present invention.

[0041] Figure 5 is a cross-sectional view of the vertical charge transfer imaging sensor device according to an embodiment of the present invention. Detailed Description of the Embodiment

[0042] The following further details the vertical charge transfer imaging sensor device and its manufacturing method of the present invention in conjunction with the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the convenience and clarity of assisting in explaining the embodiments of the present invention. The embodiments of the present invention should not be considered limited to the specific shapes shown in the figures, but may include the actually obtained shapes, such as manufacturing-induced deviations.

[0043] Embodiments of the present invention relate to a manufacturing method of a vertical charge transfer imaging sensor device and a vertical charge transfer imaging sensor device that can be formed by using this manufacturing method. First, the following is referred to Figure 3 and Figures 4A to 4O to introduce the manufacturing method.

[0044] Referring to Figure 3 and Figure 4A , perform step S1 to provide a substrate 10, where the substrate 10 has a first doping type and includes opposite front surface 10a and back surface 10b.

[0045] The substrate 10 can adopt various suitable semiconductor substrates in the art, and its materials can include silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide, etc. The substrate 10 has a first doping type, such as p-type or n-type. In this embodiment, taking the first doping type as p-type as an example, the substrate 10 is, for example, a silicon substrate doped with boron or boron difluoride.

[0046] Then perform step S2 to form a shallow trench ST, a deep trench DT, a shallow trench isolation medium 110 filling the shallow trench ST, and a deep trench isolation medium 120 filling the deep trench DT on one side of the front surface 10a of the substrate 10 (refer to Figure 4F ).

[0047] When performing step S2, the shallow trench ST can be formed first and the shallow trench isolation medium 110 can be filled in the shallow trench ST, and then the deep trench DT and the deep trench isolation medium 120 filling the deep trench DT can be formed; but it is not limited thereto. For example, the deep trench DT can be formed first before filling the shallow trench isolation medium 110 in the shallow trench ST, and when filling the shallow trench isolation medium 110 in the shallow trench ST, the isolation medium can be filled in the deep trench DT at the same time. The present application does not particularly limit the formation order of the shallow trench ST, the deep trench DT, the shallow trench isolation medium 110, and the deep trench isolation medium 120.

[0048] As an example, step S2 includes the following process, for example:

[0049] First, referring to Figure 4A , stack a pad oxide layer 101 (such as silicon oxide) and a first hard mask layer 103 (such as silicon nitride) on the front surface 10a of the substrate 10, and use photolithography and etching processes to form a deep trench DT that penetrates the first hard mask layer 103, the pad oxide layer 101, and part of the substrate 10. The deep trench DT extends from the front surface 10a to a depth of about 1.5 μm - 2.5 μm inside the substrate 10;

[0050] After that, referring to Figure 4B, a first isolation dielectric layer 105 (such as silicon oxide) is formed on the inner surface of the deep trench. Annealing can be performed thereafter to repair the lattice defects generated by the etching process. In this embodiment, the first isolation dielectric layer 105 is formed on the sidewalls and the bottom wall of the deep trench DT in the substrate 10. Then, a conductive material is deposited to fill the deep trench DT and cover the first hard mask layer 103. Then, the upper surface of the conductive material is planarized to expose the first hard mask layer 103, and a trench conductive layer 104 is formed in the deep trench DT. Optionally, the trench conductive layer 104 is, for example, doped polysilicon;

[0051] Next, referring to Figure 4C , the first hard mask layer 103, the pad oxide layer 101, and the semiconductor substrate 100 are etched to form a shallow trench ST that penetrates the first hard mask layer 103, the pad oxide layer 101, and a part of the semiconductor substrate 100. The shallow trench extends from the front surface 10a to a depth of about 100 nm to 400 nm in the substrate 10;

[0052] After that, referring to Figure 4D , the trench conductive layer 104 in the deep trench DT is etched back so that the trench conductive layer 104 is lower than the front surface of the semiconductor substrate 100, and the remaining trench conductive layer 104 forms a deep trench electrode 106, and an unfilled space is formed in the upper part of the deep trench DT;

[0053] Next, referring to Figure 4E , a dielectric material is deposited so that the dielectric material fills the deep trench DT and the shallow trench ST and covers the surface of the first hard mask layer 103. Then, through planarization, the first hard mask layer 103 is exposed. The remaining dielectric material is respectively located in the shallow trench ST and the deep trench DT. A shallow trench isolation dielectric 110 is formed in the shallow trench ST, and a second isolation dielectric layer 107 covering the deep trench electrode 106 is formed in the deep trench DT. The first isolation dielectric layer 105, the deep trench electrode 106, and the second isolation dielectric layer 107 filled in the deep trench DT constitute a deep trench isolation dielectric 120;

[0054] After that, referring to Figure 4F , the first hard mask layer 103 is removed.

[0055] In this embodiment, the cross-section of the deep trench DT is a grid structure (the "cross-section" is parallel to the front surface 10a of the substrate 10), which defines a first number of pixel regions A1 in the substrate 10 and a second number of common substrate regions A2 located between the pixel regions A1. The deep trench isolation medium 120 forms an isolation between the first number of pixel regions A1 and the second number of common substrate regions A2 located between the pixel regions A1. The shallow trench ST is formed in each pixel region A1 to define a photosensitive region 11 and a charge reading region 12 of the pixel region A1. The shallow trench isolation medium 110 isolates the photosensitive region 11 and the charge reading region 12 within the pixel region A1.

[0056] In this embodiment, in addition to the first isolation medium layer 105 and the second isolation medium layer 107, the deep trench isolation medium 120 further includes a deep trench electrode 106. The deep trench electrode 106 provides an operable electrode terminal for the vertical charge transfer imaging sensor device. Cooperating with other electrode terminals in the sensor, diverse operation modes can be achieved. For example, by applying a positive bias voltage between the substrate 10 and the deep trench electrode 106, the potential barrier at the interface between the deep trench isolation medium 120 and the substrate 10 can be increased, reducing the probability of photoelectrons being captured at this interface, which helps to improve the photoelectric conversion efficiency and improve the dark current and white pixel problems.

[0057] Refer to Figure 3 and Figure 4G , perform step S3 to form a gate structure on the surface of the pixel region A1.

[0058] The gate structure includes a gate dielectric layer 108, a floating gate FG, an inter-gate dielectric layer 109, and a control gate CG stacked on the surfaces of the photosensitive region 11 and the charge reading region 12, and may further include sidewalls covering the sides of the floating gate FG, the inter-gate dielectric layer 109, and the control gate CG. Among them, the floating gate FG, the inter-gate dielectric layer 109, the control gate CG, and the sidewalls extend, for example, from the photosensitive region 11 of the pixel region A1 to the charge reading region 12. After forming the gate structure, a source region (S) and a drain region (D) can then be formed in the charge reading region 12 of the pixel region A1. The source region (S) and the drain region (D) are respectively located on both sides of the gate structure. The positional relationship between the source region (S) and the drain region (D) and the control gate CG can refer to Figure 1 . The formation of the gate structure and the source region (S) and the drain region (D) can adopt processes known in the art.

[0059] In this embodiment, the common substrate region A2 is not used to form pixels, and no gate structure needs to be formed above it. Therefore, during the process of forming the gate structure on the surface of the pixel region A1, the gate dielectric layer 108 material, floating gate FG material, inter-gate dielectric layer 109 material, and control gate CG material deposited on the common substrate region A2 can be removed. The present invention is not limited thereto. In another embodiment, a gate structure that is not used to form pixels can also be formed above the common substrate region A2, and the substrate contact plug formed on the common substrate region A2 later passes through the gate structure and is electrically isolated from the gate structure.

[0060] After forming the gate structure, referring to Figure 4H , the following process can be further performed: An interlayer dielectric layer 111 is formed on the front surface 10a of the substrate 10, and the interlayer dielectric layer 111 covers the substrate 10 after forming the above-mentioned gate structure from the side of the front surface 10a; then, a substrate contact plug CT1, a control gate contact plug CT2, a source region contact plug (not shown in the figure), and a drain region contact plug (not shown in the figure) are formed in the interlayer dielectric layer 111. The substrate contact plug CT1 is electrically connected to the substrate of the common substrate region A2, the control gate contact plug CT2 is electrically connected to the control gate CG, the source region contact plug is electrically connected to the source region, and the drain region contact plug is electrically connected to the drain region; then, a patterned metal wiring layer 112 is formed on the surface of the interlayer dielectric layer 111, and the metal wiring layer 112 is electrically connected to the substrate contact plug CT1, the control gate contact plug CT2, the source region contact plug, and the drain region contact plug respectively, so as to electrically lead out the substrate contact plug CT1, the control gate contact plug CT2, the source region contact plug, and the drain region contact plug respectively. According to needs, other dielectric materials and / or metal wiring layers can also be formed on the metal wiring layer 112.

[0061] After completing the process on the side of the front surface 10a of the substrate 10, referring to Figure 3 , step S4 is performed to thin the substrate 10 from the side of the back surface 10b, so that the deep trench isolation dielectric 120 is exposed from the side of the back surface 10b of the substrate 10, and a part of the deep trench isolation dielectric 120 is removed from the exposed area, and a groove is formed at one end of the deep trench DT facing the back surface 10b of the substrate 10.

[0062] Before thinning the substrate 10, a carrier plate can be bonded to the side of the front surface 10a of the substrate 10 as a support. Various methods can be used to thin the substrate 10, such as at least one of chemical etching, laser irradiation, CMP and other processes can be used to thin the substrate 10. Exemplarily, the CMP process is used to thin the substrate 10.

[0063] In this embodiment, the cross-section of the deep trench DT has a grid structure to define each of the above-mentioned pixel regions A1 and the common substrate region A2. The depth of the part of the deep trench DT corresponding to each region on the grid structure in the substrate 10 can be equal, or can vary within a range. For example, in one embodiment, the part of the deep trench DT corresponding to the intersection of the grid lines is located at a deeper position in the substrate 10 than the part of the deep trench DT corresponding to the non-intersection. By thinning the substrate 10, the deep trench DT corresponding to a part of the regions on the grid structure can be exposed, or the deep trench DT corresponding to each region on the grid structure can be exposed. In order to improve the isolation effect between the substrates 10 of each pixel region A1 and to ensure the isolation between the deep trench electrode 106 and the polysilicon layer formed on the back side 10b of the substrate 10 subsequently, in this embodiment, after thinning the substrate 10 from the back side 10b, the part of the deep trench DT in each region of the grid structure penetrates through the substrate 10. Moreover, in this way, all the substrate 10 between the lower end of the deep trench DT and the back side 10b of the substrate 10 is removed, which can reduce the influence of the depth difference of the deep trench isolation medium 120 in the substrate 10 on the thickness of the substrate 10 of each pixel region A1, and helps to improve the uniformity of each pixel region A1.

[0064] When thinning the substrate 10 by the CMP process, the top surface of the exposed deep trench isolation medium 120 is flush with the new back side 10b formed after thinning the substrate 10. After thinning the substrate 10 from the back side 10b of the substrate 10, at least a part of the first isolation medium layer 105 covering the bottom wall of the deep trench DT is exposed, or at least a part of the deep trench electrode 106 is exposed. As Figure 4I shown, in this embodiment, after thinning the substrate 10 such that the deep trench isolation medium 120 is exposed from the back side 10b of the substrate 10, the first isolation medium layer 105 covering the bottom wall of the deep trench DT is ground and removed, and the deep trench electrode 106 is exposed.

[0065] As Figure 4J shown, a part of the deep trench isolation medium 120 is removed from the exposed region, and a groove 120a is formed at one end of the deep trench DT facing the back side 10. Specifically, removing a part of the deep trench isolation medium 120 can be achieved by re-etching, such as wet etching or dry etching. Since the deep trench isolation medium 120 and the substrate 10 have etching selectivity, this re-etching does not require a mask to be made and can be performed by self-aligned etching. In this embodiment, in order to protect the deep trench electrode 106 and prevent it from contacting the polysilicon layer formed subsequently, when re-etching the deep trench isolation medium 120, a self-aligned wet etching process is used to make the surface of the deep trench electrode 106 facing the back side 10b of the substrate 10 lower than the back side 10b, and at the same time, a part of the first isolation medium layer 105 covering the side wall of the deep trench DT is also etched, and a groove 120a is formed at one end of the deep trench DT facing the back side 10.

[0066] Referring to Figure 3 , Figure 4K and Figure 4L , step S5 is performed to fill the third isolation dielectric layer 113 in the groove 120a and make the top surface of the third isolation dielectric layer 113 flush with the back surface 10b of the substrate 10.

[0067] Specifically, as Figure 4K shown, step S5 may include the following process:

[0068] First, a dielectric material 113a (such as silicon oxide) is deposited in the groove 120a and on the back surface 10b of the substrate 10. The deposition of the dielectric material 113a is performed by, for example, a chemical vapor deposition (CVD) process. In order to better protect the deep trench electrode 106 and ensure isolation between the deep trench electrode 106, the substrate 10, and the polysilicon layer, a linear oxide layer (not shown in the figure) may be formed along the back surface 10b of the substrate 10 and the inner surface of the groove 120a before depositing the dielectric material 113a, and then the dielectric material 113a is deposited;

[0069] Next, as Figure 4L shown, a CMP process is performed to expose the back surface 10b of the substrate 10. The remaining dielectric material 113a fills the groove 120a to form the third isolation dielectric layer 113, and the top surface of the third isolation dielectric layer 113 is flush with the back surface 10b of the substrate 10.

[0070] The third isolation dielectric layer 113 is used to fill the deep trench DT as an isolation dielectric to isolate adjacent pixel regions A1, and is also used to protect the deep trench electrode 106 to prevent the deep trench electrode 106 from being electrically connected to the polysilicon layer formed on the back surface 10b of the substrate 10 subsequently. In this embodiment, the third isolation dielectric layer 113 fills the groove 120a, so that as an isolation dielectric in the deep trench DT, it can isolate adjacent pixel regions A1. The first isolation dielectric layer 105, the deep trench electrode 106, the second isolation dielectric layer 107, and the third isolation dielectric layer 113 filled in the deep trench DT form a new deep trench isolation dielectric, denoted as 121.

[0071] Referring to Figure 3 , step S6 is performed to form a polysilicon layer on one side of the back surface 10b of the substrate 10. The polysilicon layer covers the substrate 10 and the third isolation dielectric layer 113, and the polysilicon layer is electrically connected to the substrate 10 of each pixel region A1 and the common substrate region A2. The gate structure and the pixel region A1 thereunder form a MOS capacitor, and the substrate terminal voltage of the MOS capacitor is applied to the common substrate region A2 from the front surface 10a side of the substrate 10.

[0072] In order to protect the formed structure on the front surface 10a of the substrate 10, the process of forming the polysilicon layer preferably adopts a low-temperature process to avoid high temperatures. Since the temperature for forming polysilicon by chemical vapor deposition or epitaxial processes is generally higher than that for forming amorphous silicon, in this embodiment, a method of first forming an amorphous silicon layer and then converting it into a polysilicon layer is adopted.

[0073] Specifically, first, referring to Figure 4M , an amorphous silicon layer 114 is formed on the back surface 10b of the substrate 10. The amorphous silicon layer 114 covers the back surface 10b of the substrate 10 and the third isolation dielectric layer 113. The growth temperature of the amorphous silicon layer 114 is controlled below 450 degrees, for example. Before forming the amorphous silicon layer 114, the native oxide layer on the back surface 10b of the substrate 10 can be removed as needed.

[0074] Next, referring to Figure 4N , a laser crystallization process is performed to convert the amorphous silicon layer 114 into a polysilicon layer 114a. In other embodiments, other techniques can also be used to convert the amorphous silicon layer 114 into a polysilicon layer 114a.

[0075] In this embodiment, the polysilicon layer 114a covers the back surface 10b of the substrate 10 and the surface of the third isolation dielectric layer 113 formed in the groove 120a corresponding to the deep trench DT. Since the back surface 10b of the substrate 10 is subjected to CMP treatment, the top surface of the third isolation dielectric layer 113 is flush with the back surface 10b of the substrate 10, so that the surface of the polysilicon layer 114a is flat.

[0076] Since the polysilicon layer 114a is formed from the amorphous silicon layer 114 deposited on the substrate 10, the thickness of the polysilicon layer 114a in contact with each pixel region A1 and the common substrate region A2 is substantially the same. The polysilicon layer 114a contacts the substrate 10 of each pixel region A1 and the common substrate region A2, and thus is electrically connected to the substrate 10 of each pixel region A1 and the common substrate region A2. When the substrate terminal voltage of the MOS capacitor is applied from the side of the front surface 10a of the substrate 10 to the common substrate region A2, the substrate terminal voltage is transmitted to the substrate 10 of each pixel region A1 through the common substrate region A2 and the polysilicon layer 114a. Since the thickness uniformity of the polysilicon layer 114a is good, it is convenient to control the voltage loss on the voltage transmission path and balance the voltage applied to the substrate 10 of each pixel region A1.

[0077] Referring to Figure 4O , optionally, after completing the above step S6, a high-k dielectric layer 115 can be further formed on the surface of the polysilicon layer 114a. The high-k dielectric layer 115 is made of a material with a high dielectric constant (for example, the dielectric constant k is greater than 3.9) such as Al 2 O 3 , Ta 2 O5 , ZrO 2 , LaO, BaZrO, AlO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO 3 (BST) or TiO 2 and so on. By using the high dielectric constant layer 115, the barrier of the back surface 10b of the substrate 10 can be increased, and the probability of photoelectrons being trapped near the back surface 10b of the substrate 10 can be reduced, which helps to improve the photoelectric conversion efficiency.

[0078] Adopting the manufacturing method of the vertical charge transfer imaging sensor device described in the above embodiments, the deep trench isolation medium helps to avoid the crosstalk of photoelectrons between different pixel regions A1. The gate structure formed on the surface of the pixel region A1 and the corresponding pixel region A1 form a MOS capacitor. The substrate end voltage applied to the substrate 10 as an electrode in the MOS capacitor can be applied to the common substrate region A2 from the front surface 10a side of the substrate 10. By forming a polysilicon layer 114a on the back surface 10b of the substrate 10 to electrically connect each pixel region A1 and the common substrate region A2, the substrate end voltage can be transmitted to the substrate 10 of each pixel region A1 through the common substrate region A2 and the polysilicon layer 114a. Compared with the method of forming a metal electrode in contact with the substrate 10 on the back surface 10b of the substrate 10 to apply the substrate end voltage, the problems of difficult control of interface defects and large contact resistance existing when forming such a metal electrode can be avoided. Moreover, by applying the substrate end voltage through the common substrate region A2 formed between the pixel regions A1, the voltage loss can be reduced, which helps to make the voltages applied to the substrates 10 of each pixel region A1 balanced.

[0079] In addition, in the above embodiments, before forming the polysilicon layer 114a, the deep trench isolation medium 120 is etched back from the back surface 10b side of the substrate 10, and a groove 120a is formed at one end of the deep trench DT facing the back surface 10b. Then, a third isolation medium layer 113 is filled in the groove 120a and the top surface of the third isolation medium layer 113 is flush with the back surface 10b of the substrate 10. On the one hand, it can avoid the short circuit of the deep trench electrode 106 in the deep trench isolation medium 120 contacting the polysilicon layer 114a. On the other hand, it makes the surface of the polysilicon layer 114a flat, which helps to reduce the difficulty of subsequent back processes and improve the quality of subsequent back processes.

[0080] The embodiment of the present invention also relates to a vertical charge transfer imaging sensor device, and the vertical charge transfer imaging sensor device can be formed by using the manufacturing method of the vertical charge transfer imaging sensor device described in the above embodiments. Refer to Figure 5, the vertical charge transfer imaging sensor device includes a substrate 10, a gate structure formed on one side of the front surface 10a of the substrate 10, and a polysilicon layer 114a formed on one side of the back surface 10b of the substrate 10.

[0081] The substrate 10 may adopt various suitable semiconductor substrates in the art. The substrate 10 has a first doping type. In this embodiment, the first doping type is, for example, p-type. The substrate 10 has opposite front surface 10a and back surface 10b. In this embodiment, the front surface 10a refers to the side where the read transistor is formed.

[0082] Specifically, as Figure 5 shown, a deep trench DT, a shallow trench ST, a deep trench isolation dielectric 121 filling the deep trench DT, and a shallow trench isolation dielectric 110 filling the shallow trench ST are formed in the substrate 10. The deep trench DT penetrates the substrate 10. The deep trench isolation dielectric 121 isolates a first number of pixel regions A1 and a second number of common substrate regions A2 located between the pixel regions A1 in the substrate 10. The shallow trench isolation dielectric 110 isolates a photosensitive region 11 and a charge read region 12 within the pixel region A1. The deep trench isolation dielectric 121 includes a first isolation dielectric layer 105 covering the sidewalls of the deep trench DT, a deep trench electrode 106 filled in the deep trench DT, a second isolation dielectric layer 107 covering the deep trench electrode 106 from the front surface 10a side, and a third isolation dielectric layer 113 covering the deep trench electrode 106 from the back surface 10b side. The top surface of the third isolation dielectric layer 113 is flush with the back surface 10b of the substrate 10. The first isolation dielectric layer 105, the second isolation dielectric layer 107, and the third isolation dielectric layer 113 wrap the deep trench electrode 106 to isolate the deep trench electrode 106 from the substrate 10 and the polysilicon layer 114a. The shallow trench isolation STI is formed on the front surface 10a of the substrate 10 in each pixel region A1 to define the photosensitive region 11 and the charge read region 12 in the pixels of the vertical charge transfer imaging sensor device.

[0083] The gate structure is located on one side of the front surface 10a of the substrate 10 and is formed on the surface of each pixel region A1. As Figure 5 shown, the gate structure includes a gate dielectric layer 108, a floating gate FG, an inter-gate dielectric layer 109, and a control gate CG stacked on the surfaces of the photosensitive region 11 and the charge read region 12 of the corresponding pixel region A1. In this embodiment, the floating gate FG, the inter-gate dielectric layer 109, and the control gate CG in the gate structure extend from the photosensitive region 11 of the corresponding pixel region A1 to the charge read region 12. Since the common substrate region A2 is not used as a pixel and the gate structure does not need to be formed thereon, but it is not limited thereto. In some embodiments, for example, in order to facilitate the connection of the control gates CG on different pixel regions A1, a gate structure may also be formed on the common substrate region A2.

[0084] The gate structure and the pixel region A1 thereunder (i.e., the pixel region A1 where the gate structure is formed on the surface) form a MOS capacitor. In the MOS capacitor, the control gate CG forms one electrode, and the substrate 10 of the pixel region A1 forms the other electrode.

[0085] The gate structure formed on the surface of the pixel region A1 exposes partial charge read regions 12 in the corresponding pixel regions A1 on both sides in the extending direction. The vertical charge transfer imaging sensor further includes a source region (S) and a drain region (D) formed in the charge read regions 12 and located on both sides of the gate structure respectively (the positional relationship between the source region (S) and the drain region (D) and the control gate CG in the gate structure can be referred to Figure 1 ). The gate structure, the source region (S), and the drain region (D) form a read transistor, and the read transistor is used for charge reading. When the vertical charge transfer imaging sensor is exposed to light, voltages are applied to the two electrodes of the MOS capacitor, so that the control gate CG is positively biased with respect to the substrate 10 of the pixel region A1 to form a depletion region in the substrate 10. When light is incident from the back surface 10b of the substrate 10 and collides with the substrate lattice to generate photoelectrons, under the action of the electric field in the depletion region, the photoelectrons gather on the surface of the photosensitive region 11 or cross the potential barrier and enter the floating gate FG. Since the floating gate FG of the photosensitive region 11 is connected to the floating gate FG of the charge read region 12, the aggregation of photoelectrons will change the state of the floating gate FG of the charge read region 12, and further change the drain current and / or threshold voltage of the read transistor. The vertical charge transfer imaging sensor realizes photoelectric sensing and imaging by detecting this change. In this embodiment, the read transistor in the pixel of the vertical charge transfer imaging sensor is, for example, an n-type device, wherein the source region S and the drain region D have n-type doping. It can be understood that in the case where the read transistor is a p-type device, the source region S and the drain region D have p-type doping.

[0086] The polysilicon layer 114a covers the substrate 10 and the deep trench isolation dielectric 121 from one side of the back surface 10b of the substrate 10. The polysilicon layer 114a has conductivity, for example, has the same p-type doping as the substrate 10. In this embodiment, the polysilicon layer 114a contacts the substrate 10 of each pixel region A1 and the common substrate region A2, so as to be electrically connected to the substrate 10 of each pixel region A1 and the common substrate region A2.

[0087] In this embodiment, the substrate terminal voltage of the MOS capacitor is applied to the common substrate region A2 from one side of the front surface 10a of the substrate 10. This substrate terminal voltage is transmitted along the thickness direction of the substrate 10 to the polysilicon layer 114a. Since the polysilicon layer 114a is electrically connected to the substrate 10 of each pixel region A1, the purpose of applying a voltage to the substrate 10 of multiple pixel regions A1 is achieved, and the voltage transmission path is as Figure 5 indicated by the dotted arrow in the figure.

[0088] The common substrate region A2 may have a substrate contact region (pick up, not shown in the figure) formed near the front surface 10a of the substrate 10. The substrate contact region has a doping concentration of a first doping type greater than that of the surrounding substrate region. The substrate terminal voltage of the MOS capacitor can be applied to the common substrate region A2 through the substrate contact region. The relatively high doping concentration of the substrate contact region helps to reduce the contact resistance.

[0089] To avoid a large difference in the voltage applied to the substrate 10 of each pixel region A1 due to the different distances between the application positions of the substrate terminal voltage and the pixel region A1, which may affect the photosensitive performance, according to the number of pixel regions A1, a plurality of common substrate regions A2 can be dispersedly arranged in the substrate 10. Thus, when applying a voltage to the substrate 10 of each pixel region A1 by using the common substrate region A2 and the polysilicon layer 114a, applying the voltage from a plurality of common substrate regions A2 helps to equalize the voltages at different positions of the polysilicon layer 114a, that is, to equalize the voltages applied to the substrate 10 of each pixel region A1. The second quantity is greater than or equal to 1. The first quantity is, for example, greater than or equal to the second quantity. Each common substrate region A2 is, for example, adjacent to at least two pixel regions A1 and is shared by at least two pixel regions A1. As an example, the ratio of the first quantity to the second quantity is about 100:1 to 200:1. The substrate 10 may further include a peripheral region located outside the first quantity of pixel regions A1 and the second quantity of common substrate regions A2. The peripheral region can be used to form part of the circuits of the vertical charge transfer imaging sensor device.

[0090] The thickness of the polysilicon layer 114a can be set according to the need for isolating the pixel regions A1 and the need for conductivity. Specifically, if the thickness of the polysilicon layer 114a is too large, the polysilicon layer 114a connecting adjacent pixel regions A1 is relatively thick, which easily increases the risk of crosstalk. If the thickness of the polysilicon layer 114a is too small, the resistance of the polysilicon layer 114a will increase, resulting in an increase in voltage loss. As an example, the thickness of the polysilicon layer 114a is in the range of 0.1 μm to 0.5 μm, and more specifically, for example, in the range of 0.2 μm to 0.3 μm. On the back surface 10b of the substrate 10, the vertical charge transfer imaging sensor device may further include a high-k dielectric layer 115 covering the polysilicon layer 114a.

[0091] In this embodiment, the top surface of the third isolation dielectric layer 113 at the end of the deep trench isolation dielectric 121 facing the back surface 10b of the substrate 10 is flush with the back surface 10b of the substrate 10, so that the surface of the polysilicon layer 114 is flat, which helps to reduce the difficulty of further forming other structures (such as a grid) on the polysilicon layer 114a and improves the quality and reliability of the vertical charge transfer imaging sensor device.

[0092] As Figure 5As shown, the vertical charge transfer imaging sensor device may further include an interlayer dielectric layer 111 formed on one side of the front surface 10a of the substrate 10, a substrate contact plug CT1, a control gate contact plug CT2, and a metal wiring layer 112; wherein, the interlayer dielectric layer 111 covers the substrate 10 and the gate structure, the substrate contact plug CT1 penetrates through the interlayer dielectric layer 111 and is electrically connected to the common substrate region A2 (i.e., electrically connected to the substrate 10 of the common substrate region A2), the control gate contact plug CT2 penetrates through the interlayer dielectric layer 111 and is electrically connected to the control gate CG, and the metal wiring layer 112 is formed on the surface of the interlayer dielectric layer 111 and is electrically connected to the substrate contact plug CT1 and the control gate contact plug CT2 respectively. In addition, contact plugs electrically connected to the source region (S) and the drain region (D) of the above-mentioned read transistor may be formed in the interlayer dielectric layer 111, and the metal wiring layer 112 may be electrically connected to each of the contact plugs respectively.

[0093] In one embodiment, the input port of the substrate terminal voltage of the MOS capacitor is located on one side of the front surface 10a of the substrate 10. Such an input port may be realized by a front metal pad formed on the side of the metal wiring layer 112 away from the substrate 10. The front metal pad is electrically connected to the substrate contact plug CT1 through the metal wiring layer 112, for example. Thus, when the substrate terminal voltage is applied through this input port, the substrate terminal voltage is applied to the common substrate region A2 from the front surface 10a side, and is further applied to each pixel region A1 through the polysilicon layer 114a. In another embodiment, the input port of the substrate terminal voltage of the MOS capacitor is located on one side of the back surface 10b of the substrate 10. Such an input port may be realized by a back metal pad formed in the peripheral region of the back surface 10b of the substrate 10. The vertical charge transfer imaging sensor device may further include a via hole formed in the peripheral region and electrically connected to the metal wiring layer 112. The back metal pad is electrically connected to the corresponding via hole. Thus, when the substrate terminal voltage is applied through this input port, the substrate terminal voltage is applied to the back metal pad from the back surface 10b side, and is further applied to the common substrate region A2 from the front surface 10a side through the corresponding via hole, the metal wiring layer 112, and the substrate contact plug CT1, and is further applied to the substrate 10 of each pixel region A1 through the polysilicon layer 114a. It should be noted that the input port for applying the substrate terminal voltage may be set on the front surface 10a side or the back surface 10b side of the substrate 10 according to needs. However, according to the embodiments of the present invention, the transmission path of the substrate terminal voltage applied through the input port is first applied to the common substrate region A2 from the front surface 10a side of the substrate 10, then transmitted to the polysilicon layer 114a, and applied to the substrate 10 of each pixel region A1 through the polysilicon layer 114a.

[0094] In the vertical charge transfer imaging sensor device described in the embodiments of the present invention, the deep trench isolation medium 121 formed in the deep trench DT isolates the pixel region A1 and the common substrate region A2 in the substrate 10, which helps to avoid the crosstalk of photoelectrons between different pixel regions A1; moreover, the gate structure and the pixel region A1 thereunder form a MOS capacitor, and the substrate terminal voltage of the MOS capacitor is applied to the common substrate region A2 from one side of the front surface 10a of the substrate 10. This substrate terminal voltage is transmitted to each pixel region A1 through the common substrate region A2 and the polysilicon layer 114a, so that it is not necessary to form a metal electrode on the back surface 10b of the substrate 10, and problems such as difficult control of interface defects and large contact resistance when forming a metal electrode on the back surface 10b of the substrate 10 can be avoided; in addition, in the deep trench isolation medium 121, the third isolation medium layer 113 covers the deep trench electrode 106 from one side of the back surface 10b of the substrate 10, and the top surface of the third isolation medium layer 113 is flush with the back surface 10b of the substrate 10. On the one hand, this can avoid the short circuit caused by the contact between the deep trench electrode 106 and the polysilicon layer 114a, and on the other hand, it makes the surface of the polysilicon layer 114a flat, which helps to reduce the manufacturing difficulty of other structures formed on the polysilicon layer 114a and improve the quality and reliability of the vertical charge transfer imaging sensor device.

[0095] It should be noted that the embodiments in this specification are described in a progressive manner. Each part focuses on the differences from the previous part. For the same and similar parts among each part, reference can be made to each other.

[0096] The above description is only a description of the preferred embodiments of the present invention and does not define any scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention all belong to the protection scope of the technical solution of the present invention.

Claims

1. A manufacturing method of a vertical charge transfer imaging sensor device, characterized in that, comprising: providing a substrate, the substrate having a first doping type and including opposite front and back surfaces; forming a deep trench, a shallow trench, a deep trench isolation medium filling the deep trench, and a shallow trench isolation medium filling the shallow trench on one side of the front surface, the deep trench isolation medium isolating a first number of pixel regions and a second number of common substrate regions located between the pixel regions in the substrate, the shallow trench isolation medium isolating a photosensitive region and a charge reading region within the pixel region, wherein the deep trench isolation medium includes a first isolation medium layer covering the sidewalls and bottom wall of the deep trench, a deep trench electrode filled in the deep trench, and a second isolation medium layer covering the deep trench electrode from one side of the front surface; forming a gate structure on the surface of the pixel region; thinning the substrate from one side of the back surface to expose the deep trench isolation medium from one side of the back surface, and removing a part of the deep trench isolation medium from the exposed area, and forming a groove at one end of the deep trench facing the back surface; filling a third isolation medium layer in the groove and making the top surface of the third isolation medium layer flush with the back surface of the substrate; and forming a polysilicon layer on one side of the back surface, the polysilicon layer covering the substrate and the third isolation medium layer, the polysilicon layer being electrically connected to the substrates of each of the pixel regions and the common substrate regions, wherein the gate structure and the pixel region thereunder form a MOS capacitor, and the substrate end voltage of the MOS capacitor is applied to the common substrate region from one side of the front surface of the substrate.

2. The manufacturing method according to claim 1, characterized in that, the cross-section of the deep trench is in a grid structure, and after thinning the substrate from one side of the back surface, the deep trench portions in each region of the grid structure penetrate through the substrate.

3. The manufacturing method according to claim 1, characterized in that, when thinning the substrate from one side of the back surface, a CMP process is performed to make the top surface of the exposed deep trench isolation medium flush with the back surface of the substrate.

4. The manufacturing method according to claim 1, characterized in that, before removing a part of the deep trench isolation medium from the exposed area after thinning the substrate from one side of the back surface, at least a part of the first isolation medium layer covering the bottom wall of the deep trench is exposed, or at least a part of the deep trench electrode is exposed.

5. The manufacturing method according to claim 1, characterized in that, removing a part of the deep trench isolation medium from the exposed area is performed by self-aligned wet etching.

6. The manufacturing method according to claim 1, characterized in that, the bottom surface of the groove exposes the deep trench electrode.

7. The manufacturing method according to claim 1, characterized in that, filling a third isolation medium layer in the groove and making the top surface of the third isolation medium layer flush with the back surface of the substrate includes: depositing a medium material in the groove and on the back surface of the substrate; and Perform CMP processing to expose the back surface of the substrate. The remaining dielectric material fills the grooves to form a third isolation dielectric layer, and the top surface of the third isolation dielectric layer is flush with the back surface of the substrate.

8. The manufacturing method according to claim 7, characterized in that, before depositing the dielectric material, it further includes: forming a linear oxide layer along the back surface of the substrate and the inner surface of the grooves.

9. The manufacturing method according to claim 1, characterized in that, forming the polysilicon layer includes: depositing an amorphous silicon layer on one side of the back surface of the substrate; and performing a laser crystallization process to convert the amorphous silicon layer into the polysilicon layer.

10. A vertical charge transfer imaging sensor device, characterized in that, comprising: a substrate having a first doping type and including opposite front and back surfaces. Deep trenches, shallow trenches, deep trench isolation dielectrics filling the deep trenches, and shallow trench isolation dielectrics filling the shallow trenches are formed in the substrate. Among them, the deep trenches penetrate the substrate. The deep trench isolation dielectrics isolate a first number of pixel regions and a second number of common substrate regions located between the pixel regions in the substrate. The shallow trench isolation dielectrics isolate a photosensitive region and a charge reading region within the pixel regions. The deep trench isolation dielectrics include a first isolation dielectric layer covering the sidewalls of the deep trenches, a deep trench electrode filled in the deep trenches, a second isolation dielectric layer covering the deep trench electrode from the front side, and a third isolation dielectric layer covering the deep trench electrode from the back side. The top surface of the third isolation dielectric layer is flush with the back surface of the substrate; a polysilicon layer covering the substrate and the deep trench isolation dielectrics from one side of the back surface of the substrate. The polysilicon layer is electrically connected to the substrates of each of the pixel regions and the common substrate regions; and a gate structure formed on the surface of the pixel regions. The gate structure and the pixel regions below it form a MOS capacitor. Among them, the substrate end voltage of the MOS capacitor is applied to the common substrate region from the front side of the substrate.

11. The vertical charge transfer imaging sensor device according to claim 10, characterized in that, the gate structure includes a gate dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate stacked on the surfaces of the photosensitive region and the charge reading region. Among them, the floating gate, the inter-gate dielectric layer, and the control gate extend from the photosensitive region to the charge reading region. The vertical charge transfer imaging sensor device further includes a source region and a drain region formed in the charge reading region and located on both sides of the gate structure respectively. The gate structure, the source region, and the drain region form a reading transistor.

12. The vertical charge transfer imaging sensor device according to claim 10, characterized in that, it further includes: an interlayer dielectric layer covering the substrate and the gate structure from the front side of the substrate; a substrate contact plug penetrating the interlayer dielectric layer and electrically connected to the common substrate region; and a metal wiring layer formed on the surface of the interlayer dielectric layer. The metal wiring layer is electrically connected to the substrate contact plug.

13. The vertical charge transfer imaging sensor device according to claim 12, characterized in that, the substrate further includes a peripheral region formed around the first number of pixel regions and the second number of common substrate regions, and the metal wiring layer extends to the peripheral region; the vertical charge transfer imaging sensor device further includes: a via hole, located in the peripheral region and penetrating the substrate, and the via hole is electrically connected to the metal wiring layer; and a back metal pad, formed in the peripheral region and located on the back side of the substrate, and the back metal pad is electrically connected to the corresponding via hole, wherein the back metal pad is electrically connected to the common substrate region through the via hole, the metal wiring layer, and the substrate contact plug, and the back metal pad is an input port of the substrate terminal voltage of the MOS capacitor.

14. The vertical charge transfer imaging sensor device according to claim 10, characterized in that, it further includes a high-k dielectric layer covering the polysilicon layer from the back side.

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