High-resolution programmable PT100 platinum resistor analog circuit

Abstract

The invention relates to the technical field of electrical measurement, in particular to a high-resolution programmable PT100 platinum resistor analog circuit which comprises a processor U1, a digital-to-analog converter U2, a first-stage buffer operation network, a precise voltage division network, a reference precise resistor and a second-stage buffer operation network. The processor U1 is connected with the input end of the digital-to-analog converter U2, the digital-to-analog converter U2 is connected with the first input end of the first-stage buffer operation network, the first output end of the first-stage buffer operation network is connected with the input end of the precise voltage-dividing network, and the output end of the precise voltage-dividing network is connected with the second input end of the first-stage buffer operation network. The second output end of the first-stage buffer operation network is connected with one end of a reference precision resistor, the other end of the reference precision resistor is the output end of the circuit and is connected with the input end of a second-stage buffer operation network, and the output end of the second-stage buffer operation network is connected with the reference voltage input end of the digital-to-analog converter U2; any resistance value can be automatically output, and the resolution ratio is high.

Description

Technical Field

[0001] The invention relates to the technical field of electrical measurement, and in particular to a high-resolution programmable PT100 platinum resistance simulation circuit. Background Art

[0002] Temperature is an indispensable parameter for electronic and mechanical products. Temperature measurement is an important technical means of scientific research, especially for products such as engines that require real-time temperature monitoring.

[0003] In the related technology, the PT100 platinum resistance temperature sensor is often used to monitor the product temperature. The measurement principle is to measure the temperature by using the property that the resistance value of the metal platinum material changes with the temperature. In order to obtain the intuitive product temperature value, it is only necessary to collect the resistance value output by the PT100 platinum resistance temperature sensor at this moment and convert it into a voltage value, and then input it into the ADC (Analog-to-Digital Converter) to convert it to the processor for calculation and display.

[0004] Since the resistance value of the PT100 platinum resistor will only change when the temperature changes, when measuring the product temperature, the temperature of high-risk products with enclosed spaces such as engines will be relatively high, and this temperature is difficult to simulate. Therefore, a product that can change the resistance value at any time is needed to simulate the performance of the PT100 platinum resistor that the resistance value can change, thereby replacing the PT100 platinum resistor.

[0005] At present, there are very few products on the market that can output any resistance value. The traditional method is still to obtain a resistance value that can be changed at any time by toggling the sliding rheostat, and to refer to the PT100 platinum resistor temperature resistance corresponding table. The corresponding resistance value for each degree is about 0.4 ohms. According to industry experience and standards, higher-precision products need to be able to output resistance values ​​with a resolution twice or more less than 0.4 ohms to ensure that the output accuracy of the PT100 platinum resistor is less than 1°C. Therefore, it is necessary to design a circuit that can output any resistance value, which can not only save manual operation during debugging, but also control the resolution of the output resistance value to be less than twice or more than 0.4 ohms, so as to simulate the material properties of the PT100 platinum resistor. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a high-resolution programmable PT100 platinum resistor simulation circuit, which can automatically output any resistance value, and the resolution of the output resistance value is less than twice or more than 0.4 ohms.

[0007] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0008] The invention provides a high-resolution programmable PT100 platinum resistor simulation circuit, comprising: a processor U1, a digital-to-analog converter U2, a first-stage buffer operation network, a precision voltage divider network, a reference precision resistor and a second-stage buffer operation network; the output end of the processor U1 is connected to the input end of the digital-to-analog converter U2, the output end of the digital-to-analog converter U2 is connected to the first input end of the first-stage buffer operation network, the first output end of the first-stage buffer operation network is connected to the input end of the precision voltage divider network, the output end of the precision voltage divider network is connected to the second input end of the first-stage buffer operation network, the second output end of the first-stage buffer operation network is connected to one end of the reference precision resistor, the other end of the reference precision resistor serves as the output end of the circuit and is connected to the input end of the second-stage buffer operation network, and the output end of the second-stage buffer operation network is connected to the reference voltage input end of the digital-to-analog converter U2.

[0009] By adopting the above technical solution, when the circuit simulates the PT100 platinum resistor, the processor U1 sends the programmable digital quantity to the digital-to-analog converter U2, and the digital-to-analog converter U2 converts the digital quantity into the corresponding analog voltage and sends the analog voltage to the first-level buffer operation network. The voltage value of the analog voltage after passing through the first-level buffer operation network remains unchanged, and then the analog voltage is divided by the precision voltage divider network of the latter stage, and the voltage value of the analog voltage after the voltage division becomes smaller, and the voltage value of the analog voltage after the voltage division remains unchanged after passing through the first-level buffer operation network. At this time, the voltage value of the analog voltage after the voltage division is the input voltage value of the reference precision resistor, and the output voltage value after the input voltage value passes through the reference precision resistor is output as the positive output terminal of the three-wire system, and the output voltage value is sent to the second-level buffer operation network. The output voltage value after passing through the second-level buffer operation network remains unchanged, and the output voltage value is the reference voltage of the digital-to-analog converter U2 at this moment.

[0010] In the above process, the entire circuit is regarded as a variable unknown resistor RX, and the output current of the entire circuit is I. According to the node current method, the output current I is equal to the sum of the currents of each branch, that is, the output current I is equal to the current I1 flowing through the reference precision resistor plus the current I2 flowing through the second-level buffer operation network.

[0011] The current I1 flowing through the precision resistor R1 is the voltage across the reference precision resistor divided by the resistance value of the reference precision resistor itself. The second-stage buffer operation network works in a negative feedback state, and the input impedance is approximately infinite. This circuit shunt can be ignored, that is, I2 = 0, and I = I1.

[0012] So we have:

[0013] I=output voltage value of reference precision resistor / RX;

[0014] I1 = (output voltage value of reference precision resistor - analog voltage value after voltage division) / resistance value of reference precision resistor;

[0015] I = I1;

[0016] The output voltage value of the reference precision resistor = reference voltage value;

[0017] Analog voltage value = dat*reference voltage value / digital range;

[0018] Wherein, dat is the programmable digital value range.

[0019] Combining the above formulas, we can obtain:

[0020] RX = resistance value of reference precision resistor / (2*dat) / (3*digital range).

[0021] Thus, the RX resistance value range and the corresponding resolution are obtained, and then the temperature range and resolution can be obtained synchronously by corresponding to the PT100 platinum resistance temperature resistance table, so as to obtain the minimum adjustment amount of the resistance value of this circuit and the corresponding minimum temperature adjustment amount. In specific implementation, it can automatically output any resistance value, and the resolution of the output resistance value is less than twice or more than 0.4 ohms.

[0022] Optionally, the first-level buffer operation network includes: a buffer amplifier U3, a capacitor C2, and a capacitor C3; pin 1 of the buffer amplifier U3 is respectively connected to pin 2 and the input end of the precision voltage divider network, pin 3 is connected to the OUTA pin of the digital-to-analog converter U2, pin 4 is connected to a -5V voltage and is grounded through the capacitor C3, pin 5 is connected to the output end of the precision voltage divider network, pin 6 and pin 7 are grounded and pin 7 is connected to a reference precision resistor, and pin 8 is connected to a +5V voltage and is grounded through the capacitor C2.

[0023] By adopting the above technical solution, the first-level buffer operation network can reduce other interference signals to the analog voltage sent by the DAC, making the signal more stable.

[0024] Optionally, the precision voltage divider network includes: a precision resistor R1, a precision resistor R2, and a capacitor C4; one end of the precision resistor R1 is connected to pin 1 of the buffer amplifier U3, and the other end is connected to pin 5 of the buffer amplifier U3; the precision resistor R2 and the capacitor C4 are connected in parallel, one end of the precision resistor R2 and the capacitor C4 are connected to pin 5 of the buffer amplifier U3, and the other end of the precision resistor R2 and the capacitor C4 are grounded.

[0025] By adopting the above technical solution, the precision voltage divider network can divide the analog voltage signal passing through the first buffer operation network by two-thirds, and then send the divided analog voltage signal to the first-level buffer operation network through the first-level buffer operation network channel 2, that is, the divided analog voltage signal is sent to the buffer channel 2 of the buffer amplifier U3, thereby reducing the influence of other interference signals.

[0026] Optionally, the reference precision resistor includes a reference precision resistor R3, one end of which is connected to pin 7 of the buffer amplifier U3, and the other end serves as a positive electrode for outputting the resistance value and is connected to the input end of the second-stage buffer operation network.

[0027] By adopting the above technical solution, the reference precision resistor can output a simulated resistance value, and the output resistance value determines the lower limit threshold of the output resistance value of the circuit.

[0028] Optionally, the second-stage buffer operation network includes: resistor R4, capacitor C5, capacitor C6, capacitor C7, and operational amplifier U4; one end of the resistor R4 is connected to the reference precision resistor R3, and the other end is connected to pin 3 of the operational amplifier U4; one end of the capacitor C7 is connected to pin 3 of the operational amplifier U4, and the other end is grounded; pin 4 of the operational amplifier U4 is connected to a -5V voltage and grounded through capacitor C6, pin 8 is connected to a +5V voltage and grounded through capacitor C5, and pin 1 is connected to the REF pin of the digital-to-analog converter U2.

[0029] By adopting the above technical solution, the second-stage buffer operation network can provide a reference voltage for the input of the digital-to-analog converter U2.

[0030] Optionally, SPI communication is adopted between the processor U1 and the digital-to-analog converter U2.

[0031] Optionally, the SPI_NSS pin of the processor U1 is connected to the CS pin of the digital-to-analog converter U2, the SPI_SCK pin is connected to the SCLK pin of the digital-to-analog converter U2, the SPI_MOSI pin is connected to the DIN pin of the digital-to-analog converter U2, the VDD pin is connected to the +3.3V voltage and to the ground through the capacitor C1, and the GND pin is grounded.

[0032] Optionally, the high-resolution programmable PT100 platinum resistance analog circuit uses a three-wire interface output.

[0033] By adopting the above technical solution, when the circuit is used externally, a three-wire temperature measurement method can be adopted, or the three-wire system can be converted into a two-wire temperature measurement method.

[0034] In summary, the present invention at least includes the following beneficial technical effects:

[0035] 1. The resistance value of the equivalent resistor RX of this high-resolution programmable PT100 platinum resistor simulation circuit can be controlled by changing the programmable digital quantity dat by the processor U1, realizing the circuit function of controlling the output of a high-resolution PT100 platinum resistance value through software programming.

[0036] 2. The resolution of this high-resolution programmable PT100 platinum resistor analog circuit is the resolution of the selected digital-to-analog converter DAC, which can achieve high-precision control and easily achieve a minimum resolution of two times or more than 0.4 ohms. At the same time, this circuit is no longer the traditional manual change of the sliding rheostat to change the resistance value, and the operation is simple and flexible. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A circuit schematic diagram of a high-resolution programmable PT100 platinum resistor simulation circuit in an embodiment of the present invention;

[0038] Figure 2 The figure is a circuit principle block diagram of a high-resolution programmable PT100 platinum resistance simulation circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0040] The terms used in the following embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to be used as limitations of the present invention. As used in the specification of the present invention and the appended claims, the singular expressions "one", "a kind of", "said", "above", "the" and "this" are intended to also include plural expressions, unless there is a clear contrary indication in its context. It should also be understood that the term "and / or" used in the present invention refers to and includes any or all possible combinations of one or more listed items. The term "exemplary" means "used as an example, embodiment or illustrative", and any embodiment described as "exemplary" here does not have to be interpreted as being superior to or better than other embodiments. The terms "first" and "second" are only used for descriptive purposes, and cannot be understood as implying or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" can expressly or implicitly include one or more of these features, and in the description of the embodiments of the present invention, unless otherwise specified, the meaning of "multiple" is two or more.

[0041] An embodiment of the present invention provides a high-resolution programmable PT100 platinum resistor simulation circuit.

[0042] refer to Figure 1 and Figure 2 A high-resolution programmable PT100 platinum resistor analog circuit includes: a processor U1 (MCU, Microcontroller Unit), a digital-to-analog converter U2 (DAC, Digital-to-Analog Converter), a first-level buffer operation network, a precision voltage divider network, a reference precision resistor and a second-level buffer operation network.

[0043] The output end of the processor U1 is connected to the input end of the digital-to-analog converter U2, the output end of the digital-to-analog converter U2 is connected to the first input end of the first-stage buffer operation network, the first output end of the first-stage buffer operation network is connected to the input end of the precision voltage divider network, the output end of the precision voltage divider network is connected to the second input end of the first-stage buffer operation network, the second output end of the first-stage buffer operation network is connected to one end of a reference precision resistor, one end of the reference precision resistor away from the first-stage buffer operation network serves as the output end of the circuit and is connected to the input end of the second-stage buffer operation network, and the output end of the second-stage buffer operation network is connected to the reference voltage input end of the digital-to-analog converter U2.

[0044] The high-resolution programmable PT100 platinum resistance analog circuit adopts the internal three-wire output mode, and the external three-wire interface is adopted. The printed circuit board is arranged in the three-wire interface mode. When the circuit is used externally, the three-wire temperature measurement mode can be adopted, and the three-wire system can be converted into a two-wire temperature measurement mode.

[0045] refer to Figure 1 and Figure 2 , the processor U1 and the digital-to-analog converter U2 use SPI (Serial Peripheral Interface) to communicate. The SPI_NSS pin of the processor U1 is connected to the CS pin of the digital-to-analog converter U2, and the SPI_SCK pin of the processor U1 is connected to the SCLK pin of the digital-to-analog converter U2. The SPI_MOSI pin of the processor U1 is connected to the DIN pin of the digital-to-analog converter U2. The VDD pin of the digital-to-analog converter U2 is connected to the +3.3V voltage, and is connected to the ground through the capacitor C1. The GND pin of the digital-to-analog converter U2 is connected to the ground. The digital-to-analog converter U2 has four-channel output. In the embodiment of the present application, only one of the channels is used, that is, the OUTA pin of the digital-to-analog converter U2 is connected to the first-level buffer operation network. The processor U1 sends the programmable digital quantity to the digital-to-analog converter U2 through the SPI communication protocol. The digital-to-analog converter U2 converts the digital quantity into a corresponding analog voltage, and sends the analog voltage to the first-level buffer operation network through the first-level buffer operation network channel 1, that is, the analog voltage is sent to the buffer channel 1 of the buffer amplifier U3 described below.

[0046] refer to Figure 1 and Figure 2 , the first-stage buffer operation network includes a buffer amplifier U3, a capacitor C2, and a capacitor C3. Since the buffer amplifier U3 has many pins, the buffer amplifier U3 is divided into U3A and U3B in the figure for representation. Among them, the buffer amplifier U3 has two channels, the pin 1 of the buffer amplifier U3 is connected to the pin 2 of the buffer amplifier U3, and the pin 1 of the buffer amplifier U3 is connected to the input end of the precision voltage divider network as the first output end of the first-stage buffer operation network, the pin 3 of the buffer amplifier U3 is connected to the OUTA pin of the digital-to-analog converter U2 as the first input end of the first-stage buffer operation network, the pin 4 of the buffer amplifier U3 is connected to the -5V voltage and is connected to the ground through the capacitor C3, the pin 5 of the buffer amplifier U3 is connected to the output end of the precision voltage divider network as the second input end of the first-stage buffer operation network, the pin 6 of the buffer amplifier U3 is grounded to the pin 7, the pin 7 of the buffer amplifier U3 is connected to one end of the reference precision resistor as the second output end of the first-stage buffer operation network, and the pin 8 of the buffer amplifier U3 is connected to the +5V voltage and is connected to the ground through the capacitor C2. The first-level buffer operation network can reduce other interference signals to the analog voltage sent by the DAC, making the signal more stable.

[0047] refer to Figure 1 and Figure 2 , the precision voltage divider network includes a precision resistor R1 with a precision of one ten-thousandth, a precision resistor R2 with a precision of one ten-thousandth, and a capacitor C4. One end of the precision resistor R1 is connected to pin 1 of the buffer amplifier U3, and the other end of the precision resistor R1 is connected to pin 5 of the buffer amplifier U3. The precision resistor R2 is connected in parallel with the capacitor C4, one end of the precision resistor R2 and the capacitor C4 is connected to pin 5 of the buffer amplifier U3, and the other end of the precision resistor R2 and the capacitor C4 is connected to the ground. The precision voltage divider network can divide the analog voltage signal passing through the first buffer operation network by two-thirds, and then send the divided analog voltage signal to the first-level buffer operation network through the first-level buffer operation network channel 2, that is, send the divided analog voltage signal to the buffer channel 2 of the buffer amplifier U3, thereby reducing the influence of other interference signals.

[0048] refer to Figure 1 and Figure 2 The reference precision resistor includes a reference precision resistor R3 with a precision of 0.5%, one end of which is connected to pin 7 of the buffer amplifier U3, and the other end of which is used as the positive electrode of the output resistance value of the high-resolution programmable PT100 platinum resistor analog circuit of this design. The output resistance value determines the lower limit threshold of the output resistance value of this circuit. Among them, the resistance value of the reference precision resistor R3 is 68 ohms.

[0049] refer to Figure 1 and Figure 2 , the second-stage buffer operation network includes resistor R4, capacitor C5, capacitor C6, capacitor C7 and operational amplifier U4. One end of resistor R4 is connected to the reference precision resistor R3, and the other end of resistor R4 is connected to pin 3 of operational amplifier U4. One end of capacitor C7 is connected to pin 3 of operational amplifier U4, and the other end of capacitor C7 is connected to ground. Pin 4 of operational amplifier U4 is connected to -5V voltage and connected to ground through capacitor C6. Pin 8 of operational amplifier U4 is connected to +5V voltage and connected to ground through capacitor C5, and pin 1 of operational amplifier U4 is connected to REF pin of digital-to-analog converter U2.

[0050] In order to ensure the clarity and completeness of the specific implementation methods of this application, the implementation principle of the high-resolution programmable PT100 platinum resistor simulation circuit is now further explained.

[0051] refer to Figure 1 and Figure 2 , the processor U1 sends the programmable digital quantity to the digital-to-analog converter U2 through the SPI communication protocol. The digital-to-analog converter U2 converts the digital quantity into the corresponding analog voltage, the voltage value of the analog voltage is Ui, and sends the analog voltage to the buffer channel 1 of the buffer amplifier U3 in the first-level buffer operation network. The voltage value of the analog voltage after passing through the first-level buffer operation network channel 1 remains unchanged, and then the analog voltage is divided by 2 / 3 through the precision voltage divider network of the subsequent stage, and the voltage value of the analog voltage after the voltage division is Ui*2 / 3. After the analog voltage after the voltage division passes through the first-level buffer operation network channel 2, the voltage value remains unchanged and is still Ui*2 / 3. At this time, the voltage value Ui*2 / 3 is the input voltage value of the reference precision resistor R3, and the output voltage value after the input voltage value passes through the reference precision resistor R3 is Uo. On the one hand, the output voltage value Uo is output to the outside as the positive output terminal of the three-wire system, and on the other hand, the output voltage value Uo will be sent to the buffer amplifier U4 in the second-level buffer operation network. The output voltage value Uo after passing through the second-stage buffer operation network remains unchanged, and the output voltage value Uo is the reference voltage UREF input to the 6-pin of the digital-to-analog converter U2 at this moment, that is, Uo=UREF.

[0052] The entire circuit is regarded as a variable unknown resistor RX, and the output current of the entire circuit is I. According to the node current method, the output current I is equal to the sum of the currents of each branch, that is, the output current I is equal to the current I1 flowing through the reference precision resistor R3 plus the current I2 flowing through the second-level buffer operation network.

[0053] The current I1 flowing through the precision resistor R1 is the voltage UR3 across the reference precision resistor R3 divided by the resistance value of the reference precision resistor R3 itself. The second-stage buffer operation network works in a negative feedback state, and the input impedance is approximately infinite. This circuit shunt can be ignored, that is, I2 = 0, and I = I1.

[0054] So we have:

[0055] I=Uo / RX(1)

[0056] I1=(Uo-Ui*2 / 3) / 68(2)

[0057] I=I1(3)

[0058] Uo=UREF(4)

[0059] Ui=dat*UREF / 4095(5)

[0060] Among them, dat is a programmable digital value ranging from 0 to 4095, and UREF is the reference voltage input to pin 6 of the digital-to-analog converter U2.

[0061] Combining the above equations (1) to (5), we can obtain:

[0062] RX=68 / (1-(2*dat) / (3*4095))(6)

[0063] It can be obtained that the RX resistance value range of the present invention is 68 ohms to 204 ohms, and the resolution can be about 0.011 ohms. The corresponding PT100 platinum resistance temperature resistance table has a temperature range of -81°C to 278°C, and the resolution can be about 0.028°C, that is, the minimum adjustment amount of the resistance value of this circuit is 0.011 ohms, which is converted into a minimum adjustment amount of 0.028°C corresponding to the temperature, which is suitable for debugging the engine temperature measurement circuit. Specifically, the output resistance value is converted into a corresponding temperature through a platinum resistance temperature sensor, which can be displayed, facilitating the debugging of the generator. The staff does not need to provide a real ambient temperature (such as a dangerous temperature of more than 100 or 200 degrees), but only needs to replicate the ambient temperature through this simulation circuit.

[0064] This specific embodiment uses a 12-bit digital-to-analog converter U2, a 2 / 3 precision voltage divider network, and a reference precision resistor R3 with a resistance value of 68 ohms. The resolution of the circuit can reach 1 / 4096, which is converted into a corresponding resistance value resolution of approximately 0.011 ohms, which is much smaller than the 0.4 ohms per degree corresponding to the PT100 platinum resistor.

[0065] It should be understood that in specific implementation, the resistance value range of the analog circuit RX can be further changed by changing the range of the programmable digital quantity dat, the resistance value of the reference precision resistor R3 and the voltage divider ratio of the precision voltage divider network, and corresponding changes can be made according to the actual needs of the user.

[0066] For example, the resistance value of the reference precision resistor R3 is 50 ohms, the range of the programmable digital quantity dat is 0 to 65535, and the voltage division ratio of the precision voltage division network is 3 / 4. Then:

[0067] RX=50 / (1-(3*dat) / (4*65535)), RX resistance value range is 50 ohms to 200 ohms, and the resolution can be 0.00057 ohms. Corresponding to the PT100 platinum resistor temperature resistance table, the temperature range is -125℃~267℃.

[0068] Therefore, the resistance value of the equivalent resistor RX of the high-resolution programmable PT100 platinum resistor analog circuit can be controlled by changing the programmable digital quantity dat by the processor U1, realizing the circuit function of controlling the output of a high-resolution PT100 platinum resistor value by software programming. The resolution of the circuit is the resolution of the selected digital-to-analog converter DAC, realizing high-precision control, and easily achieving a minimum resolution twice or more smaller than 0.4 ohms. At the same time, the circuit is no longer the traditional manual change of the sliding rheostat to change the resistance value, and the operation is simple and flexible.

[0069] As described above, the above embodiments are only used to introduce the technical solution of the present invention in detail, but the description of the above embodiments is only used to help understand the method and core idea of ​​the present invention and should not be understood as limiting the present invention. Changes or substitutions that can be easily thought of by technicians in this technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A high-resolution programmable PT100 platinum resistor simulation circuit, characterized in that: include: Processor U1, digital-to-analog converter U2, first-stage buffer operation network, precision voltage divider network, reference precision resistor and second-stage buffer operation network; the output end of the processor U1 is connected to the input end of the digital-to-analog converter U2, the output end of the digital-to-analog converter U2 is connected to the first input end of the first-stage buffer operation network, the first output end of the first-stage buffer operation network is connected to the input end of the precision voltage divider network, the output end of the precision voltage divider network is connected to the second input end of the first-stage buffer operation network, the second output end of the first-stage buffer operation network is connected to one end of the reference precision resistor, the other end of the reference precision resistor serves as the output end of the circuit and is connected to the input end of the second-stage buffer operation network, and the output end of the second-stage buffer operation network is connected to the reference voltage input end of the digital-to-analog converter U2.

2. The high-resolution programmable PT100 platinum resistance simulation circuit as described in claim 1, characterized in that: The first-level buffer operation network includes: a buffer amplifier U3, a capacitor C2, and a capacitor C3; pin 1 of the buffer amplifier U3 is respectively connected to pin 2 and the input end of the precision voltage divider network, pin 3 is connected to the OUTA pin of the digital-to-analog converter U2, pin 4 is connected to a -5V voltage and is grounded through the capacitor C3, pin 5 is connected to the output end of the precision voltage divider network, pin 6 and pin 7 are grounded and pin 7 is connected to a reference precision resistor, and pin 8 is connected to a +5V voltage and is grounded through the capacitor C2.

3. The high-resolution programmable PT100 platinum resistance simulation circuit as described in claim 2, characterized in that: The precision voltage divider network includes: a precision resistor R1, a precision resistor R2, and a capacitor C4; one end of the precision resistor R1 is connected to pin 1 of the buffer amplifier U3, and the other end is connected to pin 5 of the buffer amplifier U3; the precision resistor R2 and the capacitor C4 are connected in parallel, one end of the precision resistor R2 and the capacitor C4 are connected to pin 5 of the buffer amplifier U3, and the other end of the precision resistor R2 and the capacitor C4 are grounded.

4. The high-resolution programmable PT100 platinum resistance simulation circuit as described in claim 3 is characterized in that: The reference precision resistor includes a reference precision resistor R3, one end of which is connected to pin 7 of the buffer amplifier U3, and the other end serves as a positive electrode for outputting the resistance value and is connected to the input end of the second-stage buffer operation network.

5. The high-resolution programmable PT100 platinum resistance simulation circuit as claimed in claim 4, characterized in that: The second-stage buffer operation network includes: resistor R4, capacitor C5, capacitor C6, capacitor C7, and operational amplifier U4; one end of the resistor R4 is connected to the reference precision resistor R3, and the other end is connected to pin 3 of the operational amplifier U4; one end of the capacitor C7 is connected to pin 3 of the operational amplifier U4, and the other end is grounded; pin 4 of the operational amplifier U4 is connected to a -5V voltage and is grounded through capacitor C6, pin 8 is connected to a +5V voltage and is grounded through capacitor C5, and pin 1 is connected to the REF pin of the digital-to-analog converter U2.

6. The high-resolution programmable PT100 platinum resistance simulation circuit according to any one of claims 1 to 5, characterized in that: The processor U1 and the digital-to-analog converter U2 communicate with each other using SPI.

7. The high-resolution programmable PT100 platinum resistance simulation circuit as claimed in claim 6, characterized in that: The SPI_NSS pin of the processor U1 is connected to the CS pin of the digital-to-analog converter U2, the SPI_SCK pin is connected to the SCLK pin of the digital-to-analog converter U2, the SPI_MOSI pin is connected to the DIN pin of the digital-to-analog converter U2, the VDD pin is connected to the +3.3V voltage and to the ground through the capacitor C1, and the GND pin is grounded.

8. The high-resolution programmable PT100 platinum resistance simulation circuit according to claim 1, characterized in that: The high-resolution programmable PT100 platinum resistance simulation circuit adopts a three-wire interface output.

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