Bias voltage generation circuit and method and constant current source
By using the bias voltage generation circuit of the voltage source VDD and the transistor group in a high-speed circuit, the single bias of the transistor group is used to generate two bias voltages, and by compensating the base current design, the problems of unstable bias voltage generation and high power consumption in the prior art are solved, and a circuit design with high stability and low power consumption is realized.
Patent Information
- Application Number
- CN202510262979.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-06
- Publication Date
- 2025-06-06
AI Technical Summary
In high-speed circuit design, it is difficult for the prior art to effectively generate two stable bias voltages through a single path, and the stability and reliability of the design are insufficient under the changes in process, voltage and temperature.
A bias voltage generation circuit including voltage source VDD and a transistor group is adopted. Through the combination of transistors Q1, Q2, Q3 and Q4, a single bias from transistor Q1, transistor Q3 to transistor Q4 is formed to generate two bias voltages, and the base current is compensated by an additional transistor to improve stability.
It realizes the generation of two bias voltages through one branch, saves the power consumption of the circuit, maintains good consistency under PVT changes, has high robustness, and significantly reduces the impact of base current on the bias current magnitude.
Smart Images
Figure CN120103916A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of power supplies, and in particular to a bias voltage generating circuit, a generating method and a constant current source having the bias voltage generating circuit. Background Art
[0002] In the process of analog circuit design, the generation of bias voltage for constant current source is a crucial step. To achieve this goal, designers usually use specially designed bias circuits to complete this task. For example, in the circuit design of common source common gate or common emitter common base configuration, two different sets of bias voltages are required to ensure the normal operation of the circuit. The generation of these bias voltages often relies on the diode connection method of the transistor, which can effectively generate the required voltage. However, this design method also brings an additional requirement, that is, an additional current supply is required to support the generation of bias voltage. Therefore, in the circuit design, each set of bias voltage actually corresponds to an independent current path. In the application scenario of high-speed circuits, the power consumption of bias current may become quite significant, and even become an important component of the total power consumption of the entire circuit.
[0003] For the design of MOS (metal oxide semiconductor field effect transistor) circuits, there is a simpler method, which is to directly generate the required two sets of bias voltages through resistors on a single path. This method seems to simplify the circuit design, but in fact there is a problem that cannot be ignored. Since the characteristics of resistors cannot be consistent with transistors under different process, voltage and temperature (PVT) changes, the resistor-based bias circuit performs poorly in terms of stability. Therefore, although this method can reduce the complexity of the design in some cases, in the pursuit of circuit stability and reliability, designers often need to find other more reliable solutions.
[0004] Therefore, a design is needed that can generate two bias voltages through only one branch. Summary of the invention
[0005] In order to overcome the above technical defects, the purpose of the present invention is to provide a bias voltage generating circuit, a generating method and a constant current source having the bias voltage generating circuit, wherein the bias voltage generating circuit still maintains stable performance under the fluctuation of manufacturing PVT (process, temperature, power supply voltage).
[0006] The present invention discloses a bias voltage generating circuit, comprising a voltage source VDD and a triode group, wherein the triode group comprises:
[0007] Transistor Q1 and transistor Q2, transistor Q1 is connected between voltage source VDD and ground terminal, transistor Q2 is connected with transistor Q1 to compensate base current of transistor Q1;
[0008] The triode group also includes:
[0009] Transistor Q3 and transistor Q4, wherein the transistor Q2 and the transistor Q4 have the same size, so that VBE2 of transistor Q2 is equal to VBE4 of transistor Q4; transistor Q3 is connected between transistor Q1 and the ground terminal, and transistor Q4 is connected between transistor Q3 and the ground terminal, forming a single-path bias from transistor Q1, transistor Q3 to transistor Q4, and transistor Q1 generates a first bias voltage VB1, and transistor Q4 generates a second bias voltage VB2.
[0010] Preferably, the transistor Q1 , the transistor Q2 , the transistor Q3 , and the transistor Q4 are PNP transistors.
[0011] Preferably, the emitter of transistor Q1 is connected to the voltage source VDD, and the collector is connected to transistor Q3;
[0012] The emitter of transistor Q2 is connected to the base of transistor Q1, the collector is grounded, and the base is connected to the collector of transistor Q1 to be connected to transistor Q3;
[0013] The base of the transistor Q1 is externally connected to a bias circuit to provide a first bias voltage VB1 to the bias circuit.
[0014] Preferably, the emitter of the transistor Q3 is connected to the collector of the transistor Q1 and the base of the transistor Q2, the base is connected to the collector of the transistor Q3, and the collector is grounded;
[0015] The base and collector of the transistor Q4 are grounded, and the emitter is externally connected to a bias circuit to provide a second bias voltage VB2 to the bias circuit.
[0016] The invention also discloses a constant current source, comprising a bias circuit and the bias voltage generating circuit as described above.
[0017] Preferably, the bias circuit comprises a first transistor group and a second transistor group;
[0018] The first transistor group is connected to the triode Q1;
[0019] The second transistor group is connected to the fourth triode Q4.
[0020] Preferably, the first transistor group includes a first transistor and a second transistor;
[0021] The emitter of the first transistor is connected to the voltage source VDD, and the base is connected to the transistor Q1;
[0022] The emitter of the second transistor is connected to the voltage source VDD, and the base is connected to the transistor Q1;
[0023] The second transistor group includes a third transistor and a fourth transistor;
[0024] The emitter of the third transistor is connected to the collector of the first transistor, and the base is connected to the transistor Q4;
[0025] The emitter of the fourth transistor is connected to the collector of the second transistor, and the base is connected to the transistor Q4.
[0026] The present invention further discloses a bias voltage generating method, comprising the following steps:
[0027] A bias voltage generating circuit including a voltage source VDD and a triode group is configured;
[0028] The transistor group includes a transistor Q1 connected between a voltage source VDD and a ground terminal, and the transistor group includes a transistor Q2 connected to the transistor Q1 to compensate for a base current of the transistor Q1;
[0029] The transistor Q2 and the transistor Q4 included in the transistor group have the same size, so that VBE2 of the transistor Q2 is equal to VBE4 of the transistor Q4; the transistor Q3 included in the transistor group is connected between the transistor Q1 and the ground terminal, and the transistor Q4 is connected between the transistor Q3 and the ground terminal, forming a single-path bias from the transistor Q1, the transistor Q3 to the transistor Q4, and the transistor Q1 generates a first bias voltage VB1, and the transistor Q4 generates a second bias voltage VB2.
[0030] Compared with the prior art, the above technical solution has the following beneficial effects:
[0031] 1. Two bias voltages can be generated through one branch, thus saving the power consumption of one branch;
[0032] 2. No resistor is required to achieve this, and good consistency can be guaranteed under PVT changes, with high robustness;
[0033] 3. The additional transistor is used to compensate the base current of the original transistor, which can significantly reduce the influence of the base current on the bias current. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] The drawings constituting a part of this application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:
[0035] Figure 1A schematic diagram of a circuit design of a bias voltage generating circuit in accordance with a preferred embodiment of the present invention;
[0036] Figure 2 A schematic diagram of a circuit design of a constant current source in accordance with a preferred embodiment of the present invention;
[0037] Figure 3 The schematic diagram of the circuit design of the bias voltage generating circuit in the prior art is shown. DETAILED DESCRIPTION
[0038] The advantages of the present invention are further described below in conjunction with the accompanying drawings and specific embodiments.
[0039] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.
[0040] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. The singular forms of "a", "said" and "the" used in this disclosure and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.
[0041] It should be understood that although the terms first, second, third, etc. may be used in the present disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present disclosure, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining"
[0042] In the description of the present invention, it is necessary to understand that the terms "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.
[0043] In the description of the present invention, unless otherwise specified and limited, it should be noted that the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection, or it can be the internal connection between two components. It can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to the specific circumstances.
[0044] In the following description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present invention, and have no specific meanings. Therefore, "module" and "component" can be used interchangeably.
[0045] See also Figure 1 , shows a circuit design schematic diagram of a bias voltage generating circuit in accordance with a preferred embodiment of the present invention. In this embodiment, a bias voltage generating circuit is shown, including a voltage source VDD and a transistor group. There is only one current IB1 between the transistor group and the ground terminal. Therefore, the transistor group includes a transistor Q1 and a transistor Q2. The transistor Q1 is connected between the voltage source VDD and the ground terminal, and the transistor Q2 is connected to the transistor Q1 to compensate for the base current of the transistor Q1. The transistor group also includes: a transistor Q3 and a transistor Q4. The transistor Q2 and the transistor Q4 have the same size, so that the VBE2 of the transistor Q2 is equal to the VBE4 of the transistor Q4. The transistor Q3 is connected between the transistor Q1 and the ground terminal, and the transistor Q4 is connected between the transistor Q3 and the ground terminal, forming a single bias from the transistor Q1, the transistor Q3 to the transistor Q4, and the transistor Q1 generates a first bias voltage VB1, and the transistor Q4 generates a second bias voltage VB2.
[0046] Through the above configuration, the single bias of transistors Q1, Q3 and Q4 can successfully generate two bias voltages by designing a low-power circuit structure. These voltages can provide the necessary bias for various circuits, especially those that require high matching accuracy or require common emitter and common base current sources. In the traditional common emitter current mirror design, due to the fluctuation of VCE (collector-emitter voltage), its matching effect is often unsatisfactory. However, by introducing a common base, not only can the fluctuation of VCE be significantly reduced, but also the VCE voltage of the two common emitters can be ensured to remain basically consistent, thereby achieving a better matching effect.
[0047] In addition, since no resistors are used in the entire circuit design, but it is composed entirely of the same type of transistors, the circuit can still maintain excellent matching characteristics under different process, voltage and temperature (PVT) conditions. In high-speed applications, a larger current is usually required. At this time, the current contribution provided by the bias generation circuit is particularly important.
[0048] In order to ensure that the system can maintain a good matching effect, the current ratio between the bias generation circuit and the bias circuit should be controlled within a reasonable range and should not be too high. In this way, the bias generation circuit itself will also occupy a considerable portion of the current resources. To address this problem, the above configuration outputs two different bias voltages at the same time through a single bias generation circuit. This design not only simplifies the circuit structure, but also directly halves the current consumption, thereby effectively reducing power consumption without sacrificing performance.
[0049] By carefully configuring transistor Q2, we can effectively compensate for the base current of transistor Q1, reducing its base current by β times, so that the current flowing through Q1 is more accurately close to the current source IB1 we set. In other words, the role of transistor Q2 is to absorb the base current generated by Q1 and its bias circuit, and at the same time adjust the collector-emitter voltage VCE of Q1 to make it equal to VBE1 (the base-emitter voltage of Q1) plus VBE2 (the base-emitter voltage of Q2), ensuring that VCE is greater than VBE1. This design allows transistor Q1 to always remain in an amplified state under different process, voltage and temperature conditions. The same principle applies to transistor Q4, which can absorb the base current of the bias circuit related to the second bias voltage VB2.
[0050] Since the collector of Q4 is directly grounded, it can obtain a very large VCE value, which not only ensures the performance of the high-β transistor Q4, but also ensures that under PVT conditions, the transistor Q4 can be stably maintained in the amplification region, thereby ensuring the stability and reliability of the circuit.
[0051] When all transistors are in the amplification region, under PVT, the bias circuit and the generating circuit can maintain the same current density to achieve precise current matching.
[0052] In other implementations, the transistors Q1 , Q2 , Q3 , and Q4 are PNP transistors, and NPN transistors may be used instead.
[0053] Further, the emitter of transistor Q1 is connected to the voltage source VDD, and the collector is connected to transistor Q3; the emitter of transistor Q2 is connected to the base of transistor Q1, the collector is grounded, and the base is connected to the collector of transistor Q1 to be connected to transistor Q3; the base of transistor Q1 is externally connected to a bias circuit to provide a first bias voltage VB1 to the bias circuit. The emitter of transistor Q3 is connected to the collector of transistor Q1 and the base of transistor Q2, the base is connected to the collector of transistor Q3, and the collector is grounded; the base and collector of transistor Q4 are grounded, and the emitter is externally connected to a bias circuit to provide a second bias voltage VB2 to the bias circuit.
[0054] When deeply studying the second bias voltage VB2 generated by the emitter of transistor Q4, the inventor found that it is obtained by subtracting VBE1, VBE2, VBE3 from VDD and adding VBE4 (VB2=VDD-VBE1-VBE2-VBE3+VBE4). This discovery is based on the key configuration that the emitter of transistor Q2 is connected to the bias circuit that provides current to the base of transistor Q1 and the emitter of transistor Q4.
[0055] When the bias circuit provides equal current to the emitter of transistor Q2 and the emitter of transistor Q4, for example, by configuring transistors with the same current density, and the size configuration of transistor Q2 and transistor Q4 is the same, VBE2=VBE4 can be achieved. This allows us to approximately consider VB2=VDD-VBE1-VBE3 when calculating VB2.
[0056] Further, see Figure 3 It can be observed that compared with the voltage generated by the conventional bias voltage generating circuit (VB2=VDD-VBE3-VBE4 in the conventional circuit), if the current density of all transistors of the external bias circuit is also set to be equal (i.e., the same bias circuit is used), then VBE3 in the present invention will be equal to VBE1 in the conventional method, and VBE4 in the present invention will be equal to VBE3 in the conventional method.
[0057] This not only proves that the second bias voltage VB2 is equal to the voltage VB2 generated in the conventional bias voltage generating circuit, but also demonstrates a significant advantage of the present invention: through a clever design, a single bias is used to replace the original dual bias voltage generation. This innovation not only simplifies the circuit design and reduces the cost, but also improves the stability and reliability of the circuit. In the field of modern electronic engineering, this optimization is of great significance for improving the performance and efficiency of integrated circuits.
[0058] On the other hand, corresponding to the above circuit example, the present invention further discloses a constant current source, which includes a bias circuit and a bias voltage generating circuit as described in the above example.
[0059] Preferably, the bias circuit includes a first transistor group and a second transistor group; the first transistor group is connected to the transistor Q1; the second transistor group is connected to the fourth transistor Q4. Preferably, the first transistor group includes a first transistor and a second transistor; the emitter of the first transistor is connected to the voltage source VDD, and the base is connected to the transistor Q1; the emitter of the second transistor is connected to the voltage source VDD, and the base is connected to the transistor Q1; the second transistor group includes a third transistor and a fourth transistor; the emitter of the third transistor is connected to the collector of the first transistor, and the base is connected to the transistor Q4; the emitter of the fourth transistor is connected to the collector of the second transistor, and the base is connected to the transistor Q4.
[0060] On the other hand, the present invention also discloses a bias voltage generating method, which includes the following steps: configuring a bias voltage generating circuit including a voltage source VDD and a transistor group; the transistor Q1 included in the transistor group is connected between the voltage source VDD and the ground terminal, and the transistor Q2 included in the transistor group is connected to the transistor Q1 to compensate for the base current of the transistor Q1; the transistor Q2 and the transistor Q4 included in the transistor group have the same size, so that the VBE2 of the transistor Q2 is equal to the VBE4 of the transistor Q4; the transistor Q3 included in the transistor group is connected between the transistor Q1 and the ground terminal, and the transistor Q4 is connected between the transistor Q3 and the ground terminal, forming a single-path bias from the transistor Q1, the transistor Q3 to the transistor Q4, and the transistor Q1 generates a first bias voltage VB1, and the transistor Q4 generates a second bias voltage VB2.
[0061] In summary, through the bias voltage generating circuit and method and constant current source provided by the present invention, two bias voltages can be generated through one branch, thereby saving the power consumption of one branch; at the same time, no resistor is required to achieve it, and good consistency can be guaranteed under changes in PVT, with high robustness; in addition, the solution of the present invention utilizes an additional transistor to compensate for the base current of the original transistor, thereby significantly reducing the influence of the base current on the bias current.
[0062] The preferred embodiments of the present invention disclosed above are only used to help explain the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is only limited by the claims and their full scope and equivalents. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
[0063] Those skilled in the art can understand that, in addition to implementing the system, device, unit and its various modules provided by the present invention in a purely computer-readable program code, it is entirely possible to implement the same program in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers and embedded microcontrollers by logically programming the method steps. Therefore, the system, device and its various modules provided by the present invention can be considered as a hardware component, and the modules included therein for implementing various programs can also be regarded as structures within the hardware component; the modules for implementing various functions can also be regarded as both software programs for implementing the method and structures within the hardware component.
[0064] In addition, all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program is stored in a storage medium, including a number of instructions to enable a single-chip microcomputer, a chip or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), disk or optical disk and other media that can store program codes.
[0065] In addition, various implementation modes of the embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the embodiments of the present invention, they should also be regarded as the contents disclosed by the embodiments of the present invention.
Claims
1. A bias voltage generating circuit, comprising a voltage source VDD and a transistor group, characterized in that: The transistor group includes: a transistor Q1 and a transistor Q2, wherein the transistor Q1 is connected between the voltage source VDD and the ground terminal, and the transistor Q2 is connected to the transistor Q1 to compensate for the base current of the transistor Q1; The transistor group also includes: a transistor Q3 and a transistor Q4, wherein the transistor Q2 and the transistor Q4 have the same size, so that the VBE2 of the transistor Q2 is equal to the VBE4 of the transistor Q4; the transistor Q3 is connected between the transistor Q1 and the ground terminal, and the transistor Q4 is connected between the transistor Q3 and the ground terminal, forming a single-path bias from the transistor Q1, the transistor Q3 to the transistor Q4, and the transistor Q1 generates a first bias voltage VB1, and the transistor Q4 generates a second bias voltage VB2.
2. The bias voltage generating circuit according to claim 1, wherein: The transistors Q1 , Q2 , Q3 and Q4 are PNP transistors.
3. The bias voltage generating circuit according to claim 2, wherein: The emitter of the transistor Q1 is connected to the voltage source VDD, and the collector is connected to the transistor Q3; The emitter of the transistor Q2 is connected to the base of the transistor Q1, the collector is grounded, and the base is connected to the collector of the transistor Q1 to be connected to the transistor Q3; The base of the transistor Q1 is externally connected to a bias circuit to provide the first bias voltage VB1 to the bias circuit.
4. The bias voltage generating circuit according to claim 3, wherein: The emitter of the transistor Q3 is connected to the collector of the transistor Q1 and the base of the transistor Q2, the base is connected to the collector of the transistor Q3, and the collector is grounded; The base and collector of the transistor Q4 are grounded, and the emitter is externally connected to the bias circuit to provide the second bias voltage VB2 to the bias circuit.
5. A constant current source, comprising a bias circuit, characterized in that: It also includes the bias voltage generating circuit as described in any one of claims 1-4.
6. The constant current source according to claim 5, characterized in that: The bias circuit includes a first transistor group and a second transistor group; the first transistor group is connected to the transistor Q1; and the second transistor group is connected to the fourth transistor Q4.
7. The constant current source according to claim 6, characterized in that: The first transistor group includes a first transistor and a second transistor; the emitter of the first transistor is connected to the voltage source VDD, and the base is connected to the transistor Q1; the emitter of the second transistor is connected to the voltage source VDD, and the base is connected to the transistor Q1; the second transistor group includes a third transistor and a fourth transistor; the emitter of the third transistor is connected to the collector of the first transistor, and the base is connected to the transistor Q4; the emitter of the fourth transistor is connected to the collector of the second transistor, and the base is connected to the transistor Q4.
8. A method for generating a bias voltage, characterized in that: The steps include: A bias voltage generating circuit including a voltage source VDD and a triode group is configured; The transistor Q1 included in the transistor group is connected between the voltage source VDD and the ground terminal, and the transistor Q2 included in the transistor group is connected to the transistor Q1 to compensate for the base current of the transistor Q1; The transistor Q2 and the transistor Q4 included in the transistor group have the same size, so that the VBE2 of the transistor Q2 is equal to the VBE4 of the transistor Q4; the transistor Q3 included in the transistor group is connected between the transistor Q1 and the ground terminal, and the transistor Q4 is connected between the transistor Q3 and the ground terminal, forming a single-path bias from the transistor Q1, the transistor Q3 to the transistor Q4, and the transistor Q1 generates a first bias voltage VB1, and the transistor Q4 generates a second bias voltage VB2.