CNFET-based High-Speed Digital Low Dropout Linear Regulator Power Chip

Abstract

The present invention discloses a high-speed digital low-dropout linear regulator power supply chip based on CNFET, which includes a silicon-based SOC and a CNFET power management chip layer grown above the silicon-based SOC. A plurality of digital LDOs are provided on the CNFET power management chip layer, the input ends of which are connected to an external power supply end, and the output ends are connected to the silicon-based SOC to supply power to the silicon-based SOC. The digital LDO includes: a comparator, a coarse adjustment unit, a fine adjustment unit, and a voltage output unit connected in sequence; the input ends of the comparator are respectively connected to a reference voltage end and the voltage output unit, and the output ends are respectively connected to the coarse adjustment unit and the fine adjustment unit; the coarse adjustment unit includes an adjustment controller and a coarse adjustment power transistor array connected to each other; the fine adjustment unit includes a shift register and a fine adjustment power transistor array connected to each other. The present invention can achieve efficient and stable voltage regulation while taking into account the response speed and adjustment accuracy.

Description

Technical Field

[0001] The present invention relates to the technical field of chip research and development, and particularly relates to a high-speed digital low-dropout linear regulator power supply chip based on CNFET. Background Art

[0002] A carbon nanotube field-effect transistor (CNFET) is a transistor using carbon nanotubes as the channel material, which has high electron mobility, low power consumption, and excellent electrical properties. Due to the characteristic of a large working current of a large-scale system-on-chip (SOC), it has high requirements for the output current magnitude of the power management module. Compared with silicon-based MOSFETs, CNFETs have a higher current density, so a low-dropout linear regulator (LDO) with a larger output current can be designed using the CNFET process, improving the output current of the LDO. Currently, LDOs can be mainly divided into analog LDOs and digital LDOs. Among them, the core functional unit of an analog LDO is an error amplifier, and this structure is relatively sensitive to process variations and is difficult to implement under the current immature CNFET process. Digital LDO technology benefits from a digital control method, has a larger output current, more stable performance, and stronger robustness in the face of process variations. These characteristics make digital LDOs more suitable for implementation using CNFET technology and effectively utilize the advantage of the high current density of CNFETs.

[0003] However, currently, most CNFETs and SOC chips are interconnected and co-packaged in the form of wirebond (wire bonding), resulting in an increase in signal delay and power consumption between the two. The reliability of the packaging also leads to a low overall chip yield, further increasing the production cost. In addition, there is currently no analog LDO or digital LDO based on CNFET, and the current digital LDO has a low response speed and regulation accuracy, making it difficult to respond and regulate quickly and accurately under large changes in load current and unable to effectively maintain the stability of the output voltage. There is an urgent need to develop a high-speed digital LDO structure based on CNFET. Summary of the Invention

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is as follows:

[0005] A high-speed digital low-dropout linear regulator power chip based on CNFET, including a CNFET power management chip layer and a silicon-based SOC. The CNFET power management chip layer is grown above the silicon-based SOC. One or more digital LDOs are provided on the CNFET power management chip layer. The input ends of the digital LDOs are connected to an external power supply terminal, and the output ends of the digital LDOs are connected to the silicon-based SOC to supply power to the silicon-based SOC. The digital LDO includes: a comparator, a coarse adjustment unit, a fine adjustment unit, and a voltage output unit connected in sequence;

[0006] The input ends of the comparator are respectively connected to a reference voltage terminal and the voltage output unit, and the output end of the comparator is respectively connected to the coarse adjustment unit and the fine adjustment unit; the comparator is used to compare the magnitude of the reference voltage and the output voltage fed back by the voltage output unit and output a comparison signal;

[0007] The coarse adjustment unit includes an adjustment controller and a coarse adjustment power transistor array connected to each other. The adjustment controller controls the on-off states of the transistors in the coarse adjustment power transistor array according to the comparison signal output by the comparator so as to match the magnitude of the current load current;

[0008] The fine adjustment unit includes a shift register and a fine adjustment power transistor array connected to each other. The shift register performs a shift operation after the coarse adjustment unit finishes adjustment to control the on-off states of the transistors in the fine adjustment power transistor array until the output voltage is adjusted to the reference voltage.

[0009] Further, the input end of the coarse adjustment unit further includes a multi-phase comparator array for further comparing the magnitude of the reference voltage and the output voltage fed back by the voltage output unit and outputting a corresponding comparison signal. The input ends of the multi-phase comparator array are respectively connected to the reference voltage terminal and the voltage output unit, and the output ends are respectively connected to the coarse adjustment unit and the fine adjustment unit; the multi-phase comparator array is further provided with a trigger end for controlling its own operation, and the trigger end is connected to the output end of the comparator.

[0010] Further, the adjustment controller includes a first-stage adjustment controller, a second-stage adjustment controller, a stage conversion judgment module, and a coarse adjustment control register;

[0011] The first-stage adjustment controller is used to perform preliminary adjustment on the coarse adjustment control register according to the comparison signal. The input end of the first-stage adjustment controller is connected to the output end of the comparator, and the output end of the first-stage adjustment controller is respectively connected to the stage conversion judgment module and the coarse adjustment control register;

[0012] The second-stage regulation controller is used to perform secondary regulation on the coarse-tuning control register according to the comparison signal between the reference voltage and the output voltage fed back by the voltage output unit. The input end of the second-stage regulation controller is respectively connected to the output ends of the stage conversion judgment module and the multi-phase comparator array, and the output end of the second-stage regulation controller is respectively connected to the coarse-tuning control register and the shift register of the fine-tuning unit;

[0013] The coarse-tuning control register is connected to the coarse-tuning power transistor array and is used to control the switching states of the corresponding transistors in the coarse-tuning power transistor array;

[0014] The stage conversion judgment module is used to control whether the second-stage regulation controller is started according to the output signal of the first-stage regulation controller.

[0015] Further, the first-stage regulation controller includes:

[0016] The first judgment module is used to judge the value of the received comparison signal and output a judgment result;

[0017] The first regulation module is used to set the value of the coarse-tuning control register according to the judgment result of the judgment unit. If the judgment result is that the output voltage is higher than the reference voltage and the difference between the two is greater than the preset threshold, all the values of the coarse-tuning control register are set to the first value so that all the transistors in the coarse-tuning power transistor array are turned on; if the judgment result is that the output voltage is lower than the reference voltage and the difference between the two is greater than the preset threshold, all are set to the second value so that all the transistors in the coarse-tuning power transistor array are turned off.

[0018] Further, the second-stage regulation controller includes:

[0019] The second judgment module is used to judge the value of the coarse-tuning control register;

[0020] The second regulation module is used to adjust the value of the coarse-tuning control register according to the judgment result of the second judgment module. If the judgment result is that all the values of the coarse-tuning control register have been set to the first value, adjust the values in the coarse-tuning control register to adjust so that some transistors in the coarse-tuning power transistor array are turned off, and the number of currently turned-on transistors matches the magnitude of the current load; if the judgment result is that all the values of the coarse-tuning control register have been set to the second value, adjust the values in the coarse-tuning control register to adjust so that the coarse-tuning power transistor array is adjusted to have some transistors turned on, and the number of currently turned-on transistors matches the magnitude of the current load.

[0021] Further, the first-stage adjustment controller further includes a fine-tuning locking module and a fine-tuning unlocking module. The fine-tuning locking module is configured to output a fine-tuning locking signal to lock the shift register of the fine-tuning unit when the first-stage adjustment controller preliminarily adjusts the coarse-tuning control register according to the comparison signal. The fine-tuning unlocking module is configured to output a fine-tuning unlocking signal to unlock the shift register of the fine-tuning unit after the second-stage adjustment controller adjusts the value of the coarse-tuning control register according to the received comparison signal and completes the adjustment.

[0022] Further, the coarse-tuning unit further includes a coarse-tuning code storage unit and a coarse-tuning pulse generator. The input end of the coarse-tuning code storage unit is connected to the coarse-tuning control register. The output end of the coarse-tuning code storage unit is respectively connected to the second-stage adjustment controller and the fine-tuning unit. The coarse-tuning code storage unit is configured to store the value in the coarse-tuning control register. The input end of the coarse-tuning pulse generator is respectively connected to the output ends of the first-stage adjustment controller and the second-stage adjustment controller. The output end of the coarse-tuning pulse generator is connected to the input end of the coarse-tuning control register. The coarse-tuning pulse generator is configured to perform pulse conversion on the signals output by the first-stage adjustment controller and the second-stage adjustment controller.

[0023] Further, the fine-tuning unit further includes a clock frequency adjustment module and an adjustment end judgment module. The clock frequency adjustment module is connected to the output end of the comparator, the output end of the multi-phase comparator array of the coarse-tuning unit, the shift register, the adjustment end judgment module, and the coarse-tuning code storage unit of the coarse-tuning unit. The clock frequency adjustment module is configured to divide the clock signal with different frequency division ratios according to the output signals of the coarse-tuning code storage unit and the comparator. The adjustment end judgment module is configured to judge whether the output signal of the shift register changes. If it no longer changes, an adjustment end signal is output.

[0024] Further, the digital LDO further includes a reset terminal, which is respectively connected to the input ends of the first-stage adjustment controller of the coarse-tuning unit, the second-stage adjustment controller of the coarse-tuning unit, the multi-phase comparator array of the coarse-tuning unit, and the coarse-tuning code storage unit of the coarse-tuning unit. The reset terminal signal is generated by the adjustment end judgment module of the fine-tuning unit and is used to reset the output signals of the corresponding modules receiving the reset terminal signal.

[0025] Furthermore, the high-speed digital low-dropout linear regulator power supply chip further includes an upper oxide layer and a lower oxide layer respectively disposed on the upper and lower sides of the CNFET power management chip layer. The silicon-based SOC and the CNFET power management chip layer are isolated by the lower oxide layer. The lower oxide layer is provided with a conductive member passing through the lower oxide layer at the position corresponding to the power terminal of the silicon-based SOC, so that the power terminal is electrically connected to the LDO power supply chip. The upper oxide layer is provided with a plurality of metal regions distributed in a circumferential manner along the edge. The signal terminal of the silicon-based SOC is electrically connected to the metal region through a conductive member passing through the upper oxide layer, the CNFET power management chip layer, and the lower oxide layer.

[0026] Compared with the prior art, the advantages of the present invention are as follows:

[0027] By growing the CNFET power management chip layer above the silicon-based SOC, the present invention can effectively utilize the vertical space, reduce the total physical path for connection between the two, reduce the overall area of the chip, and achieve higher integration. At the same time, by adopting the combination of the coarse adjustment unit and the fine adjustment unit to realize the output voltage control and adjustment, first, the coarse adjustment unit controls the coarse adjustment power transistor array, which can achieve a fast response to load mutations, significantly improve the transient response speed, and avoid large voltage fluctuations. Then, the fine adjustment unit controls the fine adjustment power transistor array to finely adjust the output voltage, which can reduce the output voltage ripple and achieve higher output voltage accuracy. It can quickly and accurately respond to the adjustment under the condition of large load current changes while taking into account the response speed and adjustment accuracy, effectively maintaining the stability of the output voltage, so as to achieve efficient and stable voltage regulation in a wide load range and better meet the application scenarios with higher requirements for voltage stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 FIG. is a three-dimensional integration schematic diagram of the high-speed digital low-dropout linear regulator power supply chip based on CNFET and the silicon-based SOC chip in this embodiment.

[0029] Figure 2 FIG. is a three-dimensional integration cross-sectional view of the high-speed digital low-dropout linear regulator power supply chip based on CNFET and the silicon-based SOC chip in this embodiment.

[0030] Figure 3 FIG. is a structural schematic diagram of a single digital LDO in the high-speed digital low-dropout linear regulator power supply chip based on CNFET in this embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] In order to better understand the above technical solutions, the above technical solutions will be described in detail below in conjunction with the accompanying drawings of the specification and specific embodiments.

[0032] As shown Figures 1 to 3 In the high-speed digital low-dropout linear regulator power supply chip based on CNFET of this embodiment, it includes a CNFET power management chip layer and a silicon-based SOC. The CNFET power management chip layer is grown above the silicon-based SOC. One or more digital LDOs are provided on the CNFET power management chip layer. The input ends of the respective digital LDOs are connected to an external power supply terminal, and the output ends of the respective digital LDOs are connected to the silicon-based SOC to supply power to the silicon-based SOC. Among them, the digital LDO includes: a comparator, a coarse adjustment unit, a fine adjustment unit, and a voltage output unit connected in sequence;

[0033] The input ends of the comparator are respectively connected to a reference voltage terminal and the voltage output unit, and the output end of the comparator is respectively connected to the coarse adjustment unit and the fine adjustment unit; the comparator is used to compare the magnitude of the reference voltage and the output voltage fed back by the voltage output unit and output a comparison signal;

[0034] The coarse adjustment unit includes an adjustment controller and a coarse adjustment power transistor array connected to each other. The adjustment controller controls the on / off states of the respective transistors in the coarse adjustment power transistor array according to the comparison signal output by the comparator so as to match the current load current magnitude;

[0035] The fine adjustment unit includes a shift register and a fine adjustment power transistor array connected to each other. The shift register performs a shift operation after the coarse adjustment unit finishes adjustment to control the on / off states of the respective transistors in the fine adjustment power transistor array until the output voltage is adjusted to the reference voltage.

[0036] In this embodiment, by growing the CNFET power management chip layer above the silicon-based SOC, the vertical space can be effectively utilized, the total physical path for connection between the two can be reduced, the overall area of the chip can be decreased, and higher integration can be achieved; at the same time, by adopting the combination of the coarse adjustment unit and the fine adjustment unit to achieve output voltage control and adjustment, first, the coarse adjustment unit controls the coarse adjustment power transistor array, which can achieve a fast response to load mutations, significantly improve the transient response speed, and avoid large voltage fluctuations. Then, the fine adjustment unit controls the fine adjustment power transistor array to finely adjust the output voltage, which can reduce the output voltage ripple and achieve higher output voltage accuracy. It can make a fast and accurate response and adjustment under the condition of large load current changes while taking into account the response speed and adjustment accuracy, and effectively maintain the stability of the output voltage, so as to achieve efficient and stable voltage regulation in a wide load range.

[0037] In this embodiment, the input end of the coarse adjustment unit further includes a multi-phase comparator array, which is used to further compare the magnitudes of the reference voltage and the output voltage fed back by the voltage output unit and output corresponding comparison signals. The input ends of the multi-phase comparator array are respectively connected to the reference voltage terminal and the voltage output unit, and the output ends are respectively connected to the coarse adjustment unit and the fine adjustment unit. The multi-phase comparator array is also provided with a trigger terminal for controlling its own operation, and the trigger terminal is connected to the output terminal of the comparator.

[0038] It can be understood that all digital LDOs in the power supply chip based on CNFET in this embodiment can preferably adopt the high-speed digital LDO structure based on the multi-phase comparator array. Since the high-speed digital LDO structure based on the multi-phase comparator array mainly adopts an asynchronous and synchronous hybrid control method, all digital LDOs will carry out adjustment work simultaneously, avoiding the situation where a single digital LDO works while other digital LDOs are idle, giving full play to the advantage of simultaneous adjustment of multiple digital LDOs, being able to solve the problem of local overheating when the current of a single digital LDO is too large, and improving the output current and adjustment speed of the digital LDO power supply chip. In addition, the multi-phase comparator array compares the input voltage successively according to the delay sequence by multiple comparators, and its output can more accurately reflect the change of the output voltage relative to the reference voltage. And the multi-phase comparator array is controlled by a trigger signal, without the dynamic power consumption brought by the clock signal, and its working frequency is not limited by the working frequency of the comparator itself, having a higher working speed and lower power consumption compared with the comparator controlled by the clock signal.

[0039] In this embodiment, the adjustment controller includes a first-stage adjustment controller, a second-stage adjustment controller, a stage conversion judgment module, and a coarse adjustment control register, where:

[0040] The first-stage adjustment controller is used to preliminarily adjust the coarse adjustment control register according to the comparison signal. The input end of the first-stage adjustment controller is connected to the output end of the comparator, and the output end of the first-stage adjustment controller is respectively connected to the stage conversion judgment module and the coarse adjustment control register;

[0041] The second-stage adjustment controller is used to perform secondary adjustment on the coarse adjustment control register according to the comparison signal between the reference voltage and the output voltage fed back by the voltage output unit. The input ends of the second-stage adjustment controller are respectively connected to the stage conversion judgment module and the output end of the multi-phase comparator array, and the output ends of the second-stage adjustment controller are respectively connected to the coarse adjustment control register and the shift register of the fine adjustment unit;

[0042] The coarse adjustment control register is connected to the coarse adjustment power transistor array and is used to control the on-off states of the corresponding transistors in the coarse adjustment power transistor array;

[0043] The phase transition judgment module is used to control whether the second-stage adjustment controller is started according to the output signal of the first-stage adjustment controller.

[0044] In this embodiment, the first-stage adjustment controller includes:

[0045] The first judgment module is used to judge the value of the received comparison signal and output a judgment result;

[0046] The first adjustment module is used to set the value of the coarse adjustment control register according to the judgment result of the judgment unit. If the judgment result is that the output voltage is higher than the reference voltage and the difference between the two is greater than the preset threshold, the value of the coarse adjustment control register is all set to the first value (for example, specifically set to 0) so that all transistors in the coarse adjustment power transistor array are turned on; if the judgment result is that the output voltage is lower than the reference voltage and the difference between the two is greater than the preset threshold, then all are set to the second value (for example, specifically set to 1) so that all transistors in the coarse adjustment power transistor array are turned off.

[0047] In this embodiment, the second-stage adjustment controller includes:

[0048] The second judgment module is used to judge the value of the coarse adjustment control register;

[0049] The second adjustment module is used to adjust the value of the coarse adjustment control register according to the judgment result of the second judgment module. If the judgment result is that the value of the coarse adjustment control register has been all set to the first value, adjust the value in the coarse adjustment control register to adjust so that some transistors in the coarse adjustment power transistor array are turned off, and the number of currently turned-on transistors matches the magnitude of the current load current; if the judgment result is that the value of the coarse adjustment control register has been all set to the second value, adjust the value in the coarse adjustment control register to adjust so that the coarse adjustment power transistor array is adjusted to have some transistors turned on, and the number of currently turned-on transistors matches the magnitude of the current load current.

[0050] It can be understood that the first-stage adjustment controller sets the value of the coarse adjustment control register through the comparison signal, so that the coarse adjustment power transistor array is in a state of all-on or all-off, and can quickly adjust the output current to reduce the voltage deviation when there is an obvious overshoot or undershoot in the output voltage; the second-stage adjustment controller can correct the value of the coarse adjustment control register according to the upper and lower deviation conditions of the adjusted voltage and the reference voltage determined by the multi-phase comparator array, so that the number of turned-on transistors controlled by the coarse adjustment control register matches the magnitude of the current load current, reducing circuit oscillation or instability phenomena caused by voltage fluctuations.

[0051] In this embodiment, the first-stage adjustment controller further includes a fine-tuning locking module and a fine-tuning unlocking module. The fine-tuning locking module is configured to output a fine-tuning locking signal to lock the shift register of the fine-tuning unit when the first-stage adjustment controller preliminarily adjusts the coarse-tuning control register according to the comparison signal; the fine-tuning unlocking module is configured to output a fine-tuning unlocking signal to unlock the shift register of the fine-tuning unit after the second-stage adjustment controller adjusts the value of the coarse-tuning control register according to the received comparison signal and completes the adjustment.

[0052] It can be understood that locking the shift register of the fine-tuning unit at the beginning of the coarse-tuning stage of the coarse-tuning unit can avoid control logic competition (such as overshoot oscillation) caused by the simultaneous operation of the coarse-tuning unit and the fine-tuning unit, and prevent additional losses caused by redundant adjustment when the coarse-tuning is not completed; the fine-tuning unit only starts to adjust after the coarse-tuning unit is completed, ensuring strict timing of the two-stage adjustment, reducing multi-loop coupling interference, and improving the adjustment efficiency.

[0053] In this embodiment, the coarse-tuning unit further includes a coarse-tuning code storage unit and a coarse-tuning pulse generator. The input end of the coarse-tuning code storage unit is connected to the coarse-tuning control register, and the output end of the coarse-tuning code storage unit is respectively connected to the second-stage adjustment controller and the fine-tuning unit. The coarse-tuning code storage unit is used to store the value in the coarse-tuning control register; the input end of the coarse-tuning pulse generator is respectively connected to the output ends of the first-stage adjustment controller and the second-stage adjustment controller, and the output end of the coarse-tuning pulse generator is connected to the input end of the coarse-tuning control register. The coarse-tuning pulse generator is used to perform pulse conversion on the signals output by the first-stage adjustment controller and the second-stage adjustment controller. Specifically, as Figure 3 shown, the st1 and st2 signals received at the input end of the coarse-tuning pulse generator are in the form of a rising edge, specifically, the signal changes from 0 to 1, and the function of the coarse-tuning pulse generator is to convert the rising edge into a short pulse, specifically, the signal changes from 0 to 1, and after a short period of time, it changes from 1 to 0, and then corresponding output is performed.

[0054] In this embodiment, the fine-tuning unit further includes a clock frequency adjustment module and an adjustment end judgment module. The clock frequency adjustment module is connected to the output end of the comparator, the output end of the multi-phase comparator array of the coarse-tuning unit, the shift register, the adjustment end judgment module, and the coarse-tuning code storage unit of the coarse-tuning unit. The clock frequency adjustment module is used to divide the clock signal with different frequency division ratios according to the output signals of the coarse-tuning code storage unit and the comparator. The adjustment end judgment module is used to judge whether the output signal of the shift register changes. If it no longer changes, an adjustment end signal is output.

[0055] Specifically, the function of the clock frequency adjustment module is to ensure that the system is in a stable state under different load conditions. To ensure system stability, the digital LDO needs to operate at different working frequencies under different load conditions. The clock frequency adjustment module will divide the clock signal with different frequency division ratios according to the output of the coarse adjustment code temporary storage unit and the comparator, so that the digital LDO operates at a clock frequency that can ensure system stability. The function of the adjustment end judgment module is to output the tune_end signal according to the output of the shift register. The specific working principle is that when the output of the shift register no longer changes, the tune_end signal is set to high level.

[0056] In this embodiment, the digital LDO further includes a reset terminal, and the reset terminal is respectively connected to the input terminals of the first-stage adjustment controller of the coarse adjustment unit, the second-stage adjustment controller of the coarse adjustment unit, the multi-phase comparator array of the coarse adjustment unit, and the coarse adjustment code temporary storage unit of the coarse adjustment unit. The reset terminal signal is generated by the adjustment end judgment module of the fine adjustment unit and is used to reset the output signals of the corresponding modules that receive the reset terminal signal.

[0057] Specifically, as Figure 3 shown, the output signal of the reset terminal is the tune_end signal, indicating that a round of adjustment of the entire system is completed. The tune_end signal is used to reset the controllers and memories in the system. For example, the first-stage adjustment controller and the second-stage adjustment controller complete the reset of the output signals under the control of the tune_end signal; the coarse adjustment code temporary storage unit completes the reset of the output signals under the control of the tune_end signal; the multi-phase comparator array completes the reset of the output signals under the control of the tune_end signal.

[0058] In this embodiment, as Figure 1 and Figure 2 shown, the high-speed digital low-dropout linear regulator power chip further includes an upper oxide layer and a lower oxide layer respectively disposed on the upper and lower sides of the CNFET power management chip layer. The silicon-based SOC is isolated from the CNFET power management chip layer through the lower oxide layer. A conductive member passing through the lower oxide layer is provided at the position corresponding to the power supply terminal of the silicon-based SOC so that the power supply terminal is electrically connected to the LDO power chip. A plurality of metal regions are arranged in a circumferential distribution along the edge on the upper oxide layer. The signal terminal of the silicon-based SOC is electrically connected to the metal region through a conductive member passing through the upper oxide layer, the CNFET power management chip layer, and the lower oxide layer.

[0059] In a specific application embodiment, the CNFET power management chip can be grown above the silicon-based SOC, and the two are isolated through the SiO2 oxide layer and connected through vias. The power input of the CNFET power management chip is at the top of the entire three-dimensional integrated circuit structure, specifically by the oxide layer (Figure 2 Input is performed on the PAD on the silicon-based SOC (silicon oxide). The power supply of the silicon-based SOC (Power) is provided by a CNFET power management chip. Specifically, M1 represents the first layer of metal in the CNFET process, CNT represents CNFET, M2 represents the second layer of metal in the CNFET process, and M3 represents the third layer of metal in the CNFET process. The power supply of the silicon-based SOC is electrically connected to the PAD on the oxide layer through the above-mentioned form of multi-layer metal connection. Each digital LDO input terminal in the CNFET grown above the silicon-based SOC is connected to an external power supply PAD (i.e., the metal area), and the output terminal can be directly connected to the power supply pin of the silicon-based SOC through a metal via to supply power to the SOC. The signal line (Signal) in the SOC directly passes through the CNFET layer through a via and is directly connected to the PAD. This avoids the problem of separate packaging of the power management chip and the silicon-based SOC, reduces the IR drop (voltage drop) between the two chips, is beneficial to improving the efficiency of the power management chip, and integrates the CNFET power management chip and the large-scale SOC through three-dimensional integration technology, which can reduce the area of the SOC and improve the yield of the SOC. The high-speed adjustment ability and high current density of the CNFET power management chip are used to provide an efficient power management function for the SOC, improving the power-on speed and power stability of the SOC. Figure 2 In a specific application embodiment, taking... as an example to illustrate the working process of the CNFET-based high-speed digital low-dropout linear regulator power chip in this embodiment (the "\" on the arrow line in the following indicates that the bit width of the signal line is greater than 1, that is, multiple signals are transmitted on this line at the same time): Figure 2 When the circuit is working normally, the output voltage V

[0060] is equal to the reference voltage V Figure 3 . When the load changes, the voltage at V Figure 3 will also change accordingly, deviating from the reference voltage value. At this time, the comparator compares the reference voltage V

[0061] at its input terminal with the V out fed back by the voltage output unit, and outputs an os or us signal when the difference between the two exceeds a preset threshold. These two signals represent that the output voltage has an upward fluctuation (os) or a downward fluctuation (us). ref When the load changes, the voltage at V out will also change accordingly, deviating from the reference voltage value. At this time, the comparator compares the reference voltage V ref at its input terminal with the V fb fed back by the voltage output unit, and outputs an os or us signal when the difference between the two exceeds a preset threshold. These two signals represent that the output voltage has an upward fluctuation (os) or a downward fluctuation (us).

[0062] When the coarse adjustment unit detects that the comparator generates an os or us signal, the first-stage adjustment controller will set the value of the coarse adjustment control register to all 0s or all 1s, so that all the transistors in the coarse adjustment power transistor array are turned off or all turned on (for example, when the coarse adjustment unit receives the os signal, the coarse adjustment power transistor array will be all turned off, and when it receives the us signal, the coarse adjustment power transistor array will be all turned on).

[0063] While controlling the change of the coarse adjustment control register, the first-stage adjustment controller will generate a fine adjustment lock signal to lock the shift register (specifically a 64-bit shift register) in the fine adjustment unit, making it unable to perform shift operations. In addition, after the coarse adjustment unit detects that the comparator generates an os or us signal, the multi-phase comparator array will also start working simultaneously, comparing the reference voltage with the output voltage, and outputting a series of comparison results to the second-stage adjustment controller. When all the comparators in the comparator array have completed the comparison, it will output a comparison end signal AE. When both the st1 and AE signals are valid, the second-stage adjustment controller will start working. Among them, the st1 signal indicates that the first-stage adjustment controller has completed the output of the control signal, and the second-stage adjustment controller can start working.

[0064] The second-stage adjustment controller corrects the value of the coarse adjustment control register again according to the comparison results of the multi-phase comparator array to ensure that the number of turned-on coarse adjustment power transistors controlled by the coarse adjustment control register matches the magnitude of the current load. The specific process of the second-stage adjustment controller working is as follows: The first step is to first receive the output results of the multi-phase comparator array, and the output results of the multi-phase comparator array will increase or decrease correspondingly with the change in the magnitude of the load current; the second step is to perform a corresponding callback on the value of the coarse adjustment control register according to the content stored in the coarse adjustment code temporary storage unit (that is, the value in the coarse adjustment control register) and the output results of the multi-phase comparator array. For example, if the first-stage adjustment controller previously set the value of the coarse adjustment control register to all 0s, the second-stage adjustment controller will increase the value of the coarse adjustment control register from 0 by a certain amount. If the first-stage adjustment controller previously set the value of the coarse adjustment control register to all 1s, the second-stage adjustment controller will decrease the value of the coarse adjustment control register from all 1s by a certain amount, so that the number of turned-on coarse adjustment power transistors is roughly matched with the magnitude of the current load.

[0065] After the second-stage regulation controller finishes its operation, the st2 signal will become high level, indicating the completion of the second-stage regulation controller's operation. At this time, the second-stage regulation controller outputs a fine-tuning unlock signal, enabling the shift register in the fine-tuning unit to start working. The shift register will perform shift operations based on the output of the comparator. When the comparator detects that the output voltage of the digital LDO is lower than the reference voltage, the value of the shift register will increase by 1 at the rising edge of each clock signal; when the comparator detects that the output voltage of the digital LDO is higher than the reference voltage, the value of the shift register will decrease by 1 at the rising edge of each clock signal. Through the above adjustment method, the output voltage can be accurately and quickly restored to the value before the load current changes, thereby improving the power supply stability of the SOC.

[0066] The above are only the preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the idea of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A high-speed digital low-dropout linear regulator power supply chip based on CNFET, characterized in that It includes a CNFET power management chip layer and a silicon-based SOC. The CNFET power management chip layer is grown above the silicon-based SOC. One or more digital LDOs are provided on the CNFET power management chip layer. The input ends of each of the digital LDOs are connected to an external power supply terminal, and the output ends of each of the digital LDOs are connected to the silicon-based SOC to supply power to the silicon-based SOC. The digital LDO includes: a comparator, a coarse adjustment unit, a fine adjustment unit, and a voltage output unit connected in sequence; The input ends of the comparator are respectively connected to a reference voltage terminal and the voltage output unit, and the output end of the comparator is respectively connected to the coarse adjustment unit and the fine adjustment unit; the comparator is used to compare the magnitude of the reference voltage and the output voltage fed back by the voltage output unit and output a comparison signal; The coarse adjustment unit includes an adjustment controller and a coarse adjustment power transistor array connected to each other. The adjustment controller controls the on / off states of the transistors in the coarse adjustment power transistor array according to the comparison signal output by the comparator so as to match the current load current magnitude; The fine adjustment unit includes a shift register and a fine adjustment power transistor array connected to each other. The shift register performs a shift operation after the coarse adjustment unit finishes adjustment to control the on / off states of the transistors in the fine adjustment power transistor array until the output voltage is adjusted to the reference voltage.

2. The high-speed digital low-dropout linear regulator power supply chip based on CNFET according to claim 1, characterized in that The input end of the coarse adjustment unit further includes a multi-phase comparator array for further comparing the magnitude of the reference voltage and the output voltage fed back by the voltage output unit and outputting a corresponding comparison signal. The input ends of the multi-phase comparator array are respectively connected to the reference voltage terminal and the voltage output unit, and the output ends are respectively connected to the coarse adjustment unit and the fine adjustment unit; the multi-phase comparator array is also provided with a trigger end for controlling its own operation or not, and the trigger end is connected to the output end of the comparator.

3. The high-speed digital low-dropout linear regulator power supply chip based on CNFET according to claim 2, characterized in that, The adjustment controller includes a first-stage adjustment controller, a second-stage adjustment controller, a stage conversion judgment module, and a coarse adjustment control register; The first-stage adjustment controller is used to preliminarily adjust the coarse adjustment control register according to the comparison signal. The input end of the first-stage adjustment controller is connected to the output end of the comparator, and the output end of the first-stage adjustment controller is respectively connected to the stage conversion judgment module and the coarse adjustment control register; The second-stage adjustment controller is used to perform secondary adjustment on the coarse adjustment control register according to the comparison signal between the reference voltage and the output voltage fed back by the voltage output unit. The input ends of the second-stage adjustment controller are respectively connected to the stage conversion judgment module and the output end of the multi-phase comparator array, and the output ends of the second-stage adjustment controller are respectively connected to the coarse adjustment control register and the shift register of the fine adjustment unit; The coarse adjustment control register is connected to the coarse adjustment power transistor array and is used to control the on / off states of the corresponding transistors in the coarse adjustment power transistor array; The stage conversion judgment module is used to control whether the second-stage adjustment controller is started according to the output signal of the first-stage adjustment controller.

4. The high-speed digital low-dropout linear regulator power supply chip based on CNFET according to claim 3, characterized in that, The first-stage adjustment controller includes: The first judgment module is used to judge the value of the received comparison signal and output a judgment result; The first adjustment module is used to set the value of the coarse adjustment control register according to the judgment result of the judgment unit. If the judgment result is that the output voltage is higher than the reference voltage and the difference between the two is greater than a preset threshold, all values of the coarse adjustment control register are set to a first value to turn on all transistors in the coarse adjustment power transistor array; if the judgment result is that the output voltage is lower than the reference voltage and the difference between the two is greater than a preset threshold, all are set to a second value to turn off all transistors in the coarse adjustment power transistor array.

5. The high-speed digital low-dropout linear regulator power supply chip based on CNFET according to claim 3, wherein The second-stage adjustment controller includes: The second judgment module is used to judge the value of the coarse adjustment control register; The second adjustment module is used to adjust the value of the coarse adjustment control register according to the judgment result of the second judgment module. If the judgment result is that all values of the coarse adjustment control register have been set to the first value, adjust the values in the coarse adjustment control register to turn off some transistors in the coarse adjustment power transistor array, and the number of currently turned-on transistors matches the magnitude of the current load current; if the judgment result is that all values of the coarse adjustment control register have been set to the second value, adjust the values in the coarse adjustment control register to adjust the coarse adjustment power transistor array to turn on some transistors, and the number of currently turned-on transistors matches the magnitude of the current load current.

6. The high-speed digital low-dropout linear regulator power supply chip based on CNFET according to claim 3, characterized in that, The first-stage adjustment controller further includes a fine adjustment locking module and a fine adjustment unlocking module. The fine adjustment locking module is used to output a fine adjustment locking signal to lock the shift register of the fine adjustment unit when the first-stage adjustment controller preliminarily adjusts the coarse adjustment control register according to the comparison signal; the fine adjustment unlocking module is used to output a fine adjustment unlocking signal to unlock the shift register of the fine adjustment unit after the second-stage adjustment controller finishes adjusting the value of the coarse adjustment control register according to the received comparison signal.

7. The high-speed digital low-dropout linear regulator power supply chip based on CNFET according to claim 3, wherein The coarse adjustment unit further includes a coarse adjustment code temporary storage unit and a coarse adjustment pulse generator. The input end of the coarse adjustment code temporary storage unit is connected to the coarse adjustment control register, the output end of the coarse adjustment code temporary storage unit is respectively connected to the second-stage adjustment controller and the fine adjustment unit, and the coarse adjustment code temporary storage unit is used to store the value in the coarse adjustment control register; the input end of the coarse adjustment pulse generator is respectively connected to the output ends of the first-stage adjustment controller and the second-stage adjustment controller, the output end of the coarse adjustment pulse generator is connected to the input end of the coarse adjustment control register, and the coarse adjustment pulse generator is used to perform pulse conversion on the signals output by the first-stage adjustment controller and the second-stage adjustment controller.

8. The CNFET-based high-speed digital low-dropout linear regulator power supply chip according to any one of claims 1 to 7, characterized in that, The fine-tuning unit further includes a clock frequency adjustment module and an adjustment end judgment module. The clock frequency adjustment module is respectively connected to the output end of the comparator, the output end of the multi-phase comparator array of the coarse-tuning unit, the shift register, the adjustment end judgment module, and the coarse-tuning code temporary storage unit of the coarse-tuning unit. The clock frequency adjustment module is used to divide the clock signal with different frequency division ratios according to the output signals of the coarse-tuning code temporary storage unit and the comparator. The adjustment end judgment module is used to judge whether the output signal of the shift register changes. If it no longer changes, an adjustment end signal is output.

9. The high-speed digital low-dropout linear regulator power supply chip based on CNFET according to any one of claims 1 to 7, characterized in that, The digital LDO further includes a reset terminal, and the reset terminal is respectively connected to the first-stage adjustment controller of the coarse-tuning unit, the second-stage adjustment controller of the coarse-tuning unit, the multi-phase comparator array of the coarse-tuning unit, and the input end of the coarse-tuning code temporary storage unit of the coarse-tuning unit. The reset terminal signal is generated by the adjustment end judgment module of the fine-tuning unit and is used to reset the output signals of the corresponding modules that receive the reset terminal signal.

10. The high-speed digital low-dropout linear regulator power supply chip based on CNFET according to claim 1, wherein, The high-speed digital low-dropout linear regulator power chip further includes an upper-side oxide layer and a lower-side oxide layer respectively disposed on the upper and lower sides of the CNFET power management chip layer; the silicon-based SOC is isolated from the CNFET power management chip layer through the lower-side oxide layer. A conductive member passing through the lower-side oxide layer is provided at the position corresponding to the power supply terminal of the silicon-based SOC so that the power supply terminal is electrically connected to the LDO power chip. A plurality of metal regions are arranged in a circumferential distribution along the edge on the upper-side oxide layer. The signal terminal of the silicon-based SOC is connected to the metal region through a conductive member passing through the upper-side oxide layer, the CNFET power management chip layer, and the lower-side oxide layer.

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