Instruction generation method, electronic equipment and storage medium

Abstract

The invention relates to the field of chip design, in particular to an instruction generation method, electronic equipment and a storage medium. The instruction generator generates a plurality of instructions com according to the instruction description file ISA; acquiring an instruction data conflict scene list, searching for the instruction data conflict scene list when instruction data conflict exists between the current instruction and the previous instruction, and when the current instruction meets constraint conditions of the current instruction in the kth conflict processing entry hazk in the instruction data conflict scene list, performing instruction data conflict processing on the kth conflict processing entry hazk in the instruction data conflict scene list; and when the current instruction meets the constraint condition prk of the previous instruction of the hazk and the previous instruction meets the constraint condition prk of the previous instruction of the hazk, adding the current instruction into the instruction stream after the clock cycle number specified by the previous instruction is later than the clock cycle number specified by the previous instruction according to the hazk. The method does not depend on the completeness degree of a compiler, the problem of instruction data conflict is not needed to be solved through the compiler in the middle and later periods of a project, and the verification time duration is shortened.

Description

Technical Field

[0001] The present invention relates to the field of chip design, and in particular to an instruction generation method, electronic equipment and storage medium. Background Art

[0002] The development process of the processor includes software design and hardware design. The compiler is used to compile the software design code into an executable file that can be recognized by the hardware. In the development process, software design, compiler and hardware design are developed in parallel. Instructions need to be generated during the hardware design process, and then it is verified whether the processor can execute the instructions normally and whether there are instruction data conflicts during the execution process. Instruction data conflict means that when an instruction depends on the result of the previous instruction in the form of pipeline overlapping execution, there is an instruction data conflict. Generally, there is a certain time interval between adjacent instructions or non-adjacent instructions, or special instructions are required to interrupt, so as to solve the instruction data conflict. In the traditional method, due to the incomplete hardware, the instruction data conflict in the instruction stream is not considered in the early stage of hardware design. Instead, the compiler is used to verify the instruction data conflict in the instruction stream after the compiler function is complete. The compiler function is generally complete in the middle and late stages of the project. At this time, there is a large time delay in verifying the instruction data conflict, and the instruction data conflict slows down the length of chip verification. Therefore, there is an urgent need for a method for resolving instruction data conflicts that can shorten the verification time. Summary of the invention

[0003] In view of the above technical problems, the technical solution adopted by the present invention is: a method for generating instructions, the method comprising the following steps:

[0004] S100, obtaining an instruction description file ISA, where the ISA includes a plurality of instruction codes.

[0005] S200, the instruction generator generates a plurality of instructions com according to the instruction description file ISA.

[0006] S300, obtaining an instruction data conflict scenario list, wherein the instruction data conflict scenario list includes multiple register types, each register type includes N conflict processing entries, wherein the i-th conflict processing entry haz i = {pr i ,cr i ,dt i}, pr i is the constraint condition of the previous instruction of the current instruction, cr i is the constraint condition of the current instruction, dt i is the number of clock cycles that the current instruction is later than the previous instruction when there is an instruction-data conflict. The value range of i is 1 to N.

[0007] S400, the instruction generator generates an instruction stream that does not include instruction data conflicts according to com and the instruction data conflict scenario list; wherein the jth instruction com in com j When adding to the instruction stream, include:

[0008] S410, get com j The previous instruction com j-1 .

[0009] S420, when com j and com j-1 When there is a conflict in command data, according to com j and com j-1 Find the list of instruction data conflict scenarios at com j The kth conflict handling entry haz in the list of instruction data conflict scenarios is satisfied k The constraints of the current instruction in cr k , and com j-1 Satisfy the command data conflict scenario list haz k The constraint pr of the previous instruction k When, according to haz k com j Later than the previous instruction com j-1 Number of clock cycles dt k Then add the instruction stream, where the value of k ranges from 1 to N.

[0010] In addition, the present invention also provides a non-transitory computer-readable storage medium, in which at least one instruction or at least one program is stored, and the at least one instruction or the at least one program is loaded and executed by a processor to implement the above method.

[0011] In addition, the present invention also provides an electronic device, including a processor and the above-mentioned non-transitory computer-readable storage medium.

[0012] The present invention has at least the following beneficial effects:

[0013] The present invention provides an instruction generation method, an electronic device and a storage medium, which generate multiple instructions com according to an instruction description file ISA; for the generated multiple instructions com, a list of instruction data conflict scenarios is searched according to a current instruction and a previous instruction having an instruction data conflict in com, a conflict processing entry satisfying a constraint condition is obtained, and then the time for the current instruction to be added to the instruction stream is delayed according to the number of clock cycles in the conflict processing entry, an instruction stream not including instruction data conflicts is generated, and the problem of instruction data conflicts in the instruction stream is solved. The present invention does not rely on the completeness of the compiler, and does not need to wait until the middle and later stages of the project to solve the problem of instruction data conflicts through the compiler, so that the solution of the instruction data conflict problem can be advanced to the instruction generation stage, shortening the length of verification time. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 A flow chart of an instruction generation method provided by an embodiment of the present invention;

[0016] Figure 2 A flow chart of a data conflict diagnosis method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0018] Embodiment 1

[0019] See also Figure 1 , which shows a method for generating instructions, the method comprising the following steps:

[0020] S100, obtaining an instruction description file ISA, where the ISA includes a plurality of instruction codes.

[0021] The ISA includes instruction codes of different instruction types, and the instruction codes of different instruction types have different formats. The instruction code of each instruction type includes an instruction type, an operator, and an operand.

[0022] Among them, the instruction types include arithmetic operation instructions, logical operation instructions, shift operation instructions, etc.

[0023] The operator is the operation to be performed by the computer, such as calculation, shift, jump or transfer, etc. The types of operators include arithmetic operators, logical operators, shift operators, etc.

[0024] The operand is the source of data required for the operation performed by the instruction. The operand is the operand itself, the address of the operation, or the calculation method of the address of the operation.

[0025] S200, the instruction generator generates a plurality of instructions com according to the instruction description file ISA. It should be noted that the instruction generator is used for hardware verification of the bottom-layer processor.

[0026] S300, obtaining an instruction data conflict scenario list, wherein the instruction data conflict scenario list includes multiple register types, each register type includes N conflict processing entries, wherein the i-th conflict processing entry haz i = {pr i ,cr i ,dt i}, pr i is the constraint condition of the previous instruction of the current instruction, cr i is the constraint condition of the current instruction, dt i is the number of clock cycles that the current instruction is later than the previous instruction when there is an instruction-data conflict. The value range of i is 1 to N.

[0027] Among them, the constraint condition cr of the current instruction i Also included are the current instruction type, current operator, and current operand.

[0028] Among them, the constraint condition pr of the previous instruction of the current instruction i Includes the previous instruction type, the previous instruction operator, and the previous instruction operand.

[0029] Optionally, the operand is the operand itself, the register address storing the operand, or the calculation method of the register address storing the operand. Other operand expression types in the prior art also fall within the protection scope of the present invention.

[0030] As an example, for the current instruction and the previous instruction in each conflict processing entry, when the register addresses read by the operands in the two instructions are the same, that is, when the operands with the same register addresses exist in the two instructions, then there is an instruction data conflict between the two instructions. For example, the current instruction is to calculate a=b+c, ​​and the previous instruction is f=d+h. At this time, if the register address pointed to by c in the current instruction is the same as the register address pointed to by d in the previous instruction, then there is an instruction data conflict between the current instruction and the previous instruction.

[0031] The number of clock cycles in the instruction data conflict scenario list is used to solve the instruction data conflict problem. When the current instruction and its previous instruction read the same register, the execution time of the current instruction relative to the previous instruction is suspended for one to several clock cycles until the instruction data conflict problem disappears and then continues to be executed.

[0032] It should be noted that the command data conflict scenario list is a pre-configured list.

[0033] S400, the instruction generator generates an instruction stream that does not include instruction data conflicts according to com and the instruction data conflict scenario list; wherein the jth instruction com in com j When adding to the instruction stream, include:

[0034] S410, get com j The previous instruction com j-1 .

[0035] S420, when com j and com j-1 When there is a conflict in command data, according to com j and com j-1 Find the list of instruction data conflict scenarios at com j The kth conflict handling entry haz in the list of instruction data conflict scenarios is satisfied k The constraints of the current instruction in cr k , and com j-1 Satisfy the command data conflict scenario list haz k The constraint pr of the previous instruction k When, according to haz k com j Later than the previous instruction com j-1 Number of clock cycles dt k Then add the instruction stream, where the value of k ranges from 1 to N.

[0036] The clock cycle is the minimum time unit for a processor to process an operation.

[0037] Through S420, before generating the instruction stream, the problem of instruction data conflict can be solved by delaying the adjacent instructions with instruction data conflict for a specified number of clock cycles, thereby generating an instruction stream that does not include instruction data conflict.

[0038] Among them, S420 also includes judging com j Satisfy the constraints of the current instruction cr k The steps include: j The instruction type is the same as cr k Are the instruction types in the same? j The operator and cr k Are the operators the same? j Whether the value of the operand falls into cr k Within the range of operand values, when com j The instruction type is the same as cr k The same instruction type as in com j The operator and cr k The operators are the same, and com j The value of the operand falls into cr k When the operand value is within the range, com j Satisfy the constraints of the current instruction cr k Similarly, com j-1 Satisfy the constraint pr of the previous instruction k The judgment steps and judgment com j Satisfy the constraints of the current instruction cr k The steps are the same and will not be repeated here.

[0039] Optionally, the operand value is the address of a register, and the operand value range is the address range of the register.

[0040] As a preferred embodiment, the constraint condition cr of the current instruction in the instruction data conflict scenario list i It also includes other user-defined constraints, such as other constraints on the register addresses where operands are stored.

[0041] As a preferred embodiment, S420 will com j Later than the previous instruction com j-1 Number of clock cycles dt k The steps include: in the previous instruction com j-1 After that, insert dt k After the empty instruction of clock cycles, at dt k +1 clock cycle will com j Add to the command stream.

[0042] As a preferred embodiment, S420 will com j Later than the previous instruction com j-1 Number of clock cycles dt k The steps include: in the previous instruction com j-1 Afterwards, in dt k After inserting other instructions in the clock cycle, k +1 clock cycle will com j Adding other instructions to the instruction stream. Inserting other instructions can enable each clock cycle to process the corresponding instructions and maximize the use of processor resources.

[0043] As a preferred embodiment, S420 further includes determining com j and com j-1 Steps to check if there is a conflict in command data: Get com j The register address and com j-1 The register address of each operand in the j The register address and com j-1 Does the register address of each operand in the intersection exist? If so, determine the com j and com j-1 There is an instruction data conflict; otherwise, there is no instruction data conflict. It should be noted that the register address of the operand is obtained by decoding.

[0044] As a preferred embodiment, in S300, the instruction data conflict scenario list is a spreadsheet file, in which all conflict processing entries constitute a table, and the field names in the table include but are not limited to the constraint condition pr of the previous instruction of the current instruction. i , the constraints of the current instruction cr i , when a conflict occurs, constrain the number of clock cycles dt issued by the current instruction relative to the previous instruction i Furthermore, the constraint pr of the previous instruction of the current instruction i The subfield name also includes the previous instruction type, the previous instruction operator and the previous instruction operand, the current instruction constraint cr i The subfield names of also include the current instruction type, the current operator and the current operand. Constructing the instruction data conflict scenario list in the format of a spreadsheet file can reduce the difficulty of configuring the instruction data conflict scenario list.

[0045] Embodiment 1 of the present invention provides an instruction generation method, which generates multiple instructions com according to an instruction description file ISA; for the generated multiple instructions com, a list of instruction data conflict scenarios is searched according to a current instruction and a previous instruction having an instruction data conflict in com, and a conflict processing entry that satisfies a constraint condition is obtained, and then the time for the current instruction to be added to the instruction stream is delayed according to the number of clock cycles in the conflict processing entry, so as to generate an instruction stream that does not include instruction data conflicts, thereby solving the problem of instruction data conflicts in the instruction stream.

[0046] Embodiment 1 of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0047] Embodiment 1 of the present invention further provides an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0048] Embodiment 1 of the present invention further provides a computer program product, which includes program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0049] Embodiment 1 can realize direct correction of instructions in an existing instruction stream that have instruction data conflicts into instruction streams that do not include instruction data conflicts. In the prior art, instructions that have instruction data conflicts are diagnosed by writing lines of code, implanting logic for determining instruction data conflicts into the code, and determining whether an instruction data conflict has occurred through the code. This method not only has a high cost for determination, but is also prone to omissions. In order to further diagnose which instructions in the instruction stream have instruction data conflicts, the present invention also provides embodiment 2.

[0050] Embodiment 2

[0051] See also Figure 2 , which shows a method for diagnosing instruction data conflicts, the method comprising the following steps:

[0052] P100, obtain the executable file including instructions.

[0053] Among them, the executable file of the instruction is also called a bin file, which is a binary code file, including machine code that can be directly executed by the processor. The machine code is an instruction directly executed by computer hardware.

[0054] P200, reversely parse the executable file according to the instruction description file ISA to obtain a template file.

[0055] Among them, the instruction description file ISA is configured with multiple mapping relationships, each mapping relationship is a mapping relationship between an instruction and its binary code. It should be noted that the instruction description file ISA is the same as that in the first embodiment, and will not be described in detail.

[0056] The template file is an input file of the instruction generator, which is used to configure the generation rules of the instructions, or the random generation rules of the instructions. In the prior art, the template files used to generate instructions all fall within the protection scope of the present invention.

[0057] The reverse parsing step includes: finding instructions that have a mapping relationship with the binary code according to the binary code in the executable file, parsing to obtain multiple instructions, and generating a template file. The template file includes multiple lines of instructions generated by translating the binary code. The reverse parsing process converts the executable file back into the corresponding instructions to prepare for subsequent instruction diagnosis. It should be noted that the template file is a script file that can be processed by the instruction generator.

[0058] P300, inputs the template file into the instruction generator, and the instruction generator performs instruction data conflict diagnosis on the instruction stream in the template file. The instruction generator is used for hardware verification of the underlying processor.

[0059] Furthermore, the pth instruction in the instruction stream is p The diagnostic steps include:

[0060] P310, get com p The associated constraints include com p Constraints, com p The previous instruction in the instruction stream is p-1 The constraints and com p and com p-1 The number of clock cycles between p .

[0061] Among them, com p The constraints of the current instruction in the first embodiment are the same as the constraints of the current instruction in the first embodiment. i Same,com p The previous instruction in the instruction stream is p-1 The constraint condition of the previous instruction of the current instruction in the first embodiment is the same as the constraint condition pr i For the same, please refer to the description in Embodiment 1 and will not go into details here.

[0062] The clock cycle is the minimum time unit for a processor to process an operation.

[0063] P320, according to com p The associated constraint condition of the instruction data conflict scenario list is searched, wherein the instruction data conflict scenario list includes multiple register types, each register type includes N conflict processing entries, wherein the i-th conflict processing entry haz i = {pr i ,cr i ,dt i}, pr i is the constraint condition of the previous instruction of the current instruction, cr i is the constraint condition of the current instruction, dt i To constrain the number of clock cycles issued by the current instruction relative to the previous instruction when a conflict occurs, the value of i ranges from 1 to N.

[0064] Among them, the content in the instruction data conflict scenario list is the same as that in the first embodiment and will not be repeated here.

[0065] Further, when com p The constraints and com p The previous instruction com p-1 The constraints of the qth conflict handling entry haz are satisfied at the same time q , where q ranges from 1 to N and does not satisfy haz q The interval duration dt q When the conflict instruction com is output p .

[0066] As a preferred embodiment, in P320, the instruction data conflict scenario list is a spreadsheet file, in which all conflict processing entries constitute a table, and the field names in the table include but are not limited to the constraint condition pr of the previous instruction of the current instruction i , the constraints of the current instruction cr i , when a conflict occurs, constrain the number of clock cycles dt issued by the current instruction relative to the previous instruction i Furthermore, the constraint pr of the previous instruction of the current instruction i The subfield name also includes the previous instruction type, the previous instruction operator and the previous instruction operand, the current instruction constraint cr i The subfield names of also include the current instruction type, the current operator and the current operand. Constructing the instruction data conflict scenario list in the format of a spreadsheet file can reduce the difficulty of configuring the instruction data conflict scenario list.

[0067] Optionally, the value of the current operand or the operand of the previous instruction in the corresponding cell in the table is the address of a register or the address range of a register.

[0068] P400 outputs the command line where the command data conflict exists and the conflict scenario to achieve rapid positioning.

[0069] The conflict scenario may be an instruction data conflict, an instruction data conflict of different types of registers, or an instruction data conflict of different scenarios. The instruction data conflict of different types of registers is classified according to the register type in the instruction data conflict scenario list. The instruction data conflict of different scenarios is classified according to the conflict handling items.

[0070] Embodiment 2 of the present invention provides an instruction data conflict diagnosis method, which can reversely parse an executable file into a template file that can be recognized by an instruction generator, and obtain the constraints of the current instruction and its previous instruction based on the current instruction in the instruction stream in the template file. When the constraints of a conflict processing entry in the conflict list are met at the same time, when the number of clock cycles between the current instruction and its previous instruction in the instruction stream does not meet the constraint of the number of clock cycles in the conflict processing entry, it is considered that there is an instruction data conflict between the current instruction and the previous instruction, and the current instruction with the instruction data conflict is output, thereby diagnosing the conflicting instructions in the executable file.

[0071] Embodiment 2 of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0072] Embodiment 2 of the present invention further provides an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0073] Embodiment 2 of the present invention further provides a computer program product, which includes program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0074] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A method for generating instructions, It is characterized in that The method comprises the following steps: S100, obtaining an instruction description file ISA, where the ISA includes a plurality of instruction codes; S200, the instruction generator generates a plurality of instructions com according to the instruction description file ISA; S300, obtaining an instruction data conflict scenario list, wherein the instruction data conflict scenario list includes multiple register types, each register type includes N conflict processing entries, wherein the i-th conflict processing entry haz i = {pr i ,cr i ,dt i }, pr i is the constraint condition of the previous instruction of the current instruction, cr i is the constraint condition of the current instruction, dt i is the number of clock cycles that the current instruction is later than the previous instruction when there is an instruction-data conflict, and the value range of i is 1 to N; S400, the instruction generator generates an instruction stream that does not include instruction data conflicts according to com and the instruction data conflict scenario list; wherein the jth instruction com in com j When adding to the instruction stream, include: S410, get com j The previous instruction com j-1 ; S420, when com j and com j-1 When there is a conflict in command data, according to com j and com j-1 Find the list of instruction data conflict scenarios in com j The kth conflict handling entry haz in the list of instruction data conflict scenarios is satisfied k The constraints of the current instruction in cr k , and com j-1 Satisfy the command data conflict scenario list haz k The constraint pr of the previous instruction k When, according to haz k com j Later than the previous instruction com j-1 Number of clock cycles dt k Then add the instruction stream, where the value of k ranges from 1 to N.

2. The method according to claim 1, It is characterized in that S420 also includes judging com j and com j-1 Steps to check if there is a conflict in command data: Get com j The register address and com j-1 The register address of each operand in the j The register address and com j-1 Does the register address of each operand in the intersection exist? If so, determine the com j and com j-1 There is a command-data conflict; otherwise, there is not.

3. The method according to claim 1, It is characterized in that S420 Lieutenant General com j Later than the previous instruction com j-1 Number of clock cycles dt k The steps include: in the previous instruction com j-1 After that, insert dt k After the empty instruction of clock cycles, at dt k +1 clock cycle will com j Add to the command stream.

4. The method according to claim 1, It is characterized in that S420 Lieutenant General com j Later than the previous instruction com j-1 Number of clock cycles dt k The steps include: in the previous instruction com j-1 Afterwards, in dt k After inserting other instructions in the clock cycle, k +1 clock cycle will com j Add to the command stream.

5. The method according to claim 1, It is characterized in that The constraint condition cr of the current instruction in the instruction data conflict scenario list i Other user-defined constraints are also included.

6. The method according to claim 1, It is characterized in that The instruction data conflict scenario list is a spreadsheet file, in which all conflict processing entries form a table, and the field names in the table include the constraint conditions pr of the previous instruction of the current instruction i , the constraints of the current instruction cr i , when a conflict occurs, constrain the number of clock cycles dt issued by the current instruction relative to the previous instruction i .

7. The method according to claim 6, It is characterized in that The constraint condition pr of the previous instruction of the current instruction i Also included are subfield names: previous instruction type, previous instruction operator, and previous instruction operand.

8. The method according to claim 6, It is characterized in that The constraint condition cr of the current instruction i Also included are subfield names: Current Instruction Type, Current Operator, and Current Operand.

9. A non-transitory computer-readable storage medium, wherein at least one instruction or at least one program is stored in the storage medium. It is characterized in that The at least one instruction or the at least one program is loaded and executed by the processor to implement the method according to any one of claims 1 to 8.

10. An electronic device, It is characterized in that The invention comprises a processor and the non-transitory computer-readable storage medium as claimed in claim 9.

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