Master-slave communication method, device, equipment and medium

Abstract

The invention discloses a master-slave communication method, device, equipment and medium, relates to the technical field of communication, is applied to a host, and comprises the following steps: writing communication data into a plurality of registers in the host; based on a preset valid data cut-off signal, screening out a plurality of registers from the plurality of registers as valid registers; the preset valid data cut-off signal is used for indicating whether the communication data fragments stored in the register are valid data needing to be sent to the slave, and the host and the slave are devices based on an enhanced serial peripheral interface protocol; and sending the communication data fragments stored in the effective registers to the slave, then waiting for the slave to return response data, and adjusting the level of a preset data receiving mark signal when the response data returned by the slave meets a preset condition, and determining whether the communication of the master and slave machines is ended or not based on the level change of the preset data receiving mark signal. According to the method, errors in the simulation process can be reduced, and the simulation verification efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a master-slave communication method, device, equipment and medium. Background Art

[0002] The existing espi_master host model has two shortcomings in actual use. 1) espi_master writes commands, addresses, data and crc (Cyclic Redundancy Check) check codes into the internal registers of the model through the IO (Input / Output) interface. The data written here changes according to the different write commands. This method cannot intuitively and clearly display the data written to espi_slave, which is not conducive to checking the correctness of the espi (Enhanced Serial Peripheral Interface) protocol during the simulation verification process. 2) After espi_master receives data from espi_slave, there is no flag signal at the interface to indicate that the data has been received, which is not conducive to the simulation verification personnel to check the correctness of the received data, reducing the efficiency of simulation verification.

[0003] It can be seen that how to intuitively and clearly display the data written into the slave machine during the communication process between the master and the slave machine and improve the efficiency of simulation verification is a problem that needs to be solved by those skilled in the art. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a master-slave communication method, device, equipment and medium, which can intuitively and clearly display the data written to the slave during the master-slave communication process, reduce errors in the simulation process, and improve the efficiency of simulation verification.

[0005] In a first aspect, the present invention discloses a master-slave communication method, which is applied to a host and includes:

[0006] Write communication data to multiple registers in the host;

[0007] Based on a preset valid data cutoff signal, a number of registers are selected from a plurality of registers as valid registers; the preset valid data cutoff signal is used to indicate whether the communication data fragment stored in the register is valid data that needs to be sent to the slave, and both the host and the slave are devices based on the enhanced serial peripheral interface protocol;

[0008] The communication data fragments stored in each valid register are sent to the slave, and then the slave is waited for to return the response data, and the level of the preset data reception flag signal is adjusted when the response data returned by the slave meets the preset conditions, so as to determine whether the current communication between the master and the slave is ended based on the level change of the preset data reception flag signal.

[0009] Optionally, write the communication data to multiple registers in the host, including:

[0010] The communication data is written into a plurality of registers in the host through the input / output interface based on the enhanced serial peripheral interface protocol; the communication data includes a target command sent by the host to the slave, relevant address information, data to be sent, and a cyclic redundancy check code; the target command is a command supported by the enhanced serial peripheral interface protocol.

[0011] Optionally, the communication data fragments stored in each valid register are sent to the slave, and then the slave is waited for to return response data, including:

[0012] The enhanced serial peripheral interface is driven to write the communication data fragments stored in each valid register into the slave, so that after receiving the communication data fragments, the slave calculates the target check code corresponding to the received communication data fragments, and determines whether to wait for the slave to return response data based on the target check code and the cyclic redundancy check code; wherein the communication data fragments stored in the valid registers include the cyclic redundancy check code;

[0013] If the target check code is the same as the cyclic redundancy check code, wait for the slave to return the response data;

[0014] If the target check code is different from the cyclic redundancy check code, it is determined that there is an error in the received communication data segment, and an error signal is returned by the receiving slave;

[0015] The communication data fragments stored in each valid register are resent to the slave based on the error signal.

[0016] Optionally, before adjusting the level of the preset data reception flag signal when the response data returned by the slave device meets the preset condition, the method further includes:

[0017] Configure a preset data reception flag signal at the enhanced serial peripheral interface.

[0018] Optionally, before adjusting the level of the preset data reception flag signal when the response data returned by the slave device meets the preset condition, the method further includes:

[0019] Determine the number of bytes corresponding to the response data returned by the slave;

[0020] Whether the response data returned by the slave meets the preset condition is determined based on the size relationship between the byte quantity and the preset byte threshold.

[0021] Optionally, when the response data returned by the slave device meets a preset condition, adjusting the level of the preset data reception flag signal includes:

[0022] If the number of bytes is equal to the preset byte threshold, it is determined that the response data returned by the slave meets the preset condition, and the level of the preset data reception flag signal is adjusted.

[0023] Optionally, the master-slave communication method further includes:

[0024] If the number of bytes is less than the preset byte threshold, it is determined that the response data returned by the slave does not meet the preset conditions, and the slave is waited for to return the remaining response data;

[0025] If the response data returned by the slave still does not meet the preset conditions after waiting for the target time, the communication is terminated and the corresponding error message is sent to the preset display terminal so that the corresponding communication detection can be performed based on the error message.

[0026] In a second aspect, the present invention discloses a master-slave communication device, which is applied to a host, comprising:

[0027] A first data writing module, used for writing communication data into a plurality of registers in the host;

[0028] A register screening module, used for screening a number of registers from a plurality of registers as valid registers based on a preset valid data cutoff signal; the preset valid data cutoff signal is used for indicating whether a communication data fragment stored in the register is valid data to be sent to a slave, and both the host and the slave are devices based on an enhanced serial peripheral interface protocol;

[0029] The level adjustment module is used to send the communication data fragments stored in each valid register to the slave, then wait for the slave to return response data, and adjust the level of the preset data reception flag signal when the response data returned by the slave meets the preset conditions, so as to determine whether the current communication between the master and the slave is completed based on the level change of the preset data reception flag signal.

[0030] In a third aspect, the present invention provides an electronic device, comprising:

[0031] Memory for storing computer programs;

[0032] The processor is used to execute the computer program to implement the above-mentioned master-slave communication method.

[0033] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, and the computer program implements the aforementioned master-slave communication method when executed by a processor.

[0034] In the present invention, a host writes communication data into a plurality of registers in the host; based on a preset valid data cutoff signal, a plurality of registers are screened out from the plurality of registers as valid registers; the preset valid data cutoff signal is used to indicate whether the communication data fragments stored in the registers are valid data that need to be sent to the slave, and both the host and the slave are devices based on an enhanced serial peripheral interface protocol; the communication data fragments stored in each valid register are sent to the slave, and then the slave is waited for to return response data, and when the response data returned by the slave meets a preset condition, the level of a preset data reception flag signal is adjusted, so as to determine whether the current communication between the master and the slave is ended based on the level change of the preset data reception flag signal.

[0035] Beneficial effect: The present invention intercepts the valid data to be sent to the slave machine by presetting the valid data cutoff signal, thereby accelerating the simulation process and effectively reducing errors in the simulation process. A preset data reception flag signal is configured at the interface, and the level of the preset data reception flag signal is adjusted when the response data meets the preset conditions, and then the communication between the master and slave machines is determined to be over according to the level change of the preset data reception flag signal. In this way, the simulation personnel can quickly capture the data return moment and accelerate the efficiency of simulation verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1 A flow chart of a master-slave communication method provided by an embodiment of the present invention;

[0038] Figure 2 A schematic diagram of a data packet provided by an embodiment of the present invention;

[0039] Figure 3 A schematic diagram of an improved master-slave communication provided by an embodiment of the present invention;

[0040] Figure 4 A waveform diagram of complete communication between a master and a slave provided by an embodiment of the present invention;

[0041] Figure 5 A schematic diagram of the structure of a master-slave communication device provided by an embodiment of the present invention;

[0042] Figure 6 A structural diagram of an electronic device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] The terms "including" and "having" in the specification of the present invention and the above-mentioned drawings, as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0045] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0046] The existing espi_master host model has two shortcomings in actual use. 1) espi_master writes commands, addresses, data and CRC (Cyclic Redundancy Check) check codes into the internal registers of the model through the IO (Input / Output) interface. The data written here changes according to different write commands. This method cannot intuitively and clearly display the data written to espi_slave, which is not conducive to checking the correctness of the espi (Enhanced Serial Peripheral Interface) protocol during the simulation verification process. 2) After espi_master receives data from espi_slave, there is no flag signal at the interface to show that the data has been received, which is not conducive to the simulation verification personnel to check the correctness of the received data, reducing the efficiency of simulation verification. In order to solve the above technical problems, the present invention discloses a master-slave communication method, device, equipment and medium, which can intuitively and clearly display the data written to the slave during the master-slave communication process, reduce errors in the simulation process, and improve the efficiency of simulation verification.

[0047] See also Figure 1 As shown, an embodiment of the present invention provides a master-slave communication method, which is applied to a host, including:

[0048] Step S11, writing the communication data into a plurality of registers in the host.

[0049] In the embodiment of the present invention, the host first writes the communication data into multiple registers in the host through the input / output interface based on the enhanced serial peripheral interface protocol; the communication data includes the target command sent by the host to the slave, the relevant address information, the data to be sent, and the cyclic redundancy check code; the target command is a command supported by the enhanced serial peripheral interface protocol. Specifically, Figure 2 As shown, the command, address, data and crc check bit to be sent are encapsulated into a data packet, which receives relevant data through temp_command (command frame) and 16 8-bit wide registers from temp_data1 (1st byte data frame) to temp_data16 (nth byte data frame). Among them, temp_command represents the command sent from espi_master (espi host) to espi_slave (espi slave), which can be commands supported by espi protocol such as PUT_IOWR_SHORT, PUT_IORD_SHORT, PUT_NP / GET_PC. Temp_data1 to temp_data16 represent the address, data, crc check code, etc. sent from the master side to the slave side.

[0050] Step S12: Based on a preset valid data cutoff signal, select several registers from multiple registers as valid registers; the preset valid data cutoff signal is used to indicate whether the communication data fragment stored in the register is valid data that needs to be sent to the slave, and both the host and the slave are devices based on the enhanced serial peripheral interface protocol.

[0051] In an embodiment of the present invention, the host configures a preset valid data cutoff signal, and then based on the preset valid data cutoff signal, selects several registers from multiple registers as valid registers. Among them, the preset valid data cutoff signal is used to indicate whether the communication data fragment stored in the register is valid data that needs to be sent to the slave, and both the host and the slave are devices based on the enhanced serial peripheral interface protocol. Specifically, tx_end_bytes is a preset valid data cutoff signal, which serves as an end mark signal, indicating that the data at this position and before are valid. In addition, the next 8-bit wide data at the interception position of the tx_end_bytes signal is a crc check code. In a specific embodiment, tx_end_bytes is 11, indicating that temp_data1 to temp_data11 are valid fields of address and data; Temp_data12 is a crc check bit, and the data fields after temp_data12 are invalid and will not be sent to the espi_slave side. Thus, tx_end_bytes indicates whether the communication data fragment stored in the register is valid data that needs to be sent to the slave, and then selects several registers from multiple registers as valid registers.

[0052] Step S13, sending the communication data fragments stored in each valid register to the slave, then waiting for the slave to return response data, and adjusting the level of the preset data reception flag signal when the response data returned by the slave meets the preset conditions, so as to determine whether the current communication between the master and the slave is completed based on the level change of the preset data reception flag signal.

[0053] In an embodiment of the present invention, after selecting several registers from multiple registers as valid registers according to a preset valid data cutoff signal, the communication data fragments stored in each valid register can be sent to the slave, and then the slave is waited for to return response data. Specifically, the enhanced serial peripheral interface is driven to write the communication data fragments stored in each valid register into the slave, so that after receiving the communication data fragments, the slave calculates the target check code corresponding to the received communication data fragments, and determines whether to wait for the slave to return response data based on the target check code and the cyclic redundancy check code; wherein, the communication data fragments stored in the valid register include a cyclic redundancy check code; if the target check code is the same as the cyclic redundancy check code, wait for the slave to return response data; if the target check code is different from the cyclic redundancy check code, it is determined that there is an error in the received communication data fragment, and an error signal returned by the slave is received; based on the error signal, the communication data fragments stored in each valid register are resent to the slave. That is to say, after writing the communication data fragments stored in each valid register into the slave, the slave will verify whether there is a difference between the received data and the data sent by the host according to the target check code corresponding to the received communication data fragment and the cyclic redundancy check code sent by the host, and then verify the integrity of the data received by the slave, and then ensure the accuracy of the communication. If the target check code is the same as the cyclic redundancy check code, it proves that the data is complete, then the slave can perform corresponding response operations according to the received communication data fragment to generate response data, and return the response data to the host, and the host can also wait for the slave to return the response data. If the target check code is not the same as the cyclic redundancy check code, it proves that the data is incomplete, then the slave will return an error signal to the host to remind the host that the communication data fragments it has received are wrong, so that the host will resend the communication data fragments stored in each valid register to the slave when receiving the error signal sent by the slave. By sending the communication data fragments again, the accuracy and integrity of the communication data between the master and the slave are guaranteed. In a specific embodiment, Espi_slave side receives relevant commands, addresses, data and CRC check bits, and returns data after a response cycle of 2 cycles.

[0054] In an embodiment of the present invention, the host waits for the slave to return response data, and then adjusts the level of the preset data reception flag signal when the response data returned by the slave meets the preset condition, so as to determine whether the current communication between the master and the slave is ended based on the level change of the preset data reception flag signal. Therefore, before adjusting the level of the preset data reception flag signal when the response data returned by the slave meets the preset condition, the present invention first configures the preset data reception flag signal at the enhanced serial peripheral interface. Then, the level of the preset data reception flag signal can be adjusted when the response data returned by the slave meets the preset condition.

[0055] Then determine the number of bytes corresponding to the response data returned by the slave; and judge whether the response data returned by the slave meets the preset conditions according to the size relationship between the number of bytes and the preset byte threshold. It is necessary to first determine the number of bytes of the response data returned by the slave, and then judge the size relationship between the number of bytes of the response data and the preset byte threshold, and then judge whether the response data returned by the slave meets the preset conditions according to the judgment result.

[0056] Specifically, if the number of bytes of the response data is equal to the preset byte threshold, it is determined that the response data returned by the slave meets the preset conditions, and the level of the preset data receiving flag signal is adjusted. If the number of bytes is less than the preset byte threshold, it is determined that the response data returned by the slave does not meet the preset conditions, and the slave is waiting to return the remaining response data; if the response data returned by the slave still does not meet the preset conditions after waiting for the target time, the communication is terminated, and the corresponding error message is sent to the preset display terminal, so as to perform corresponding communication detection based on the error message. In a specific embodiment, espi_master waits until the number of bytes received is 17 bytes, and then pulls up the receive_data_success signal, that is, adjusts the level of the preset data receiving flag signal to a high level. In this way, when the level of the preset data receiving flag signal is monitored to become a high level, it is determined that the communication between the master and the slave is over. If espi_master waits until the number of bytes received is less than 17 bytes, it is determined that the response data returned by the slave does not meet the preset conditions, and the host needs to continue to wait for the slave to return the remaining response data. However, if the number of bytes received by the slave espi_master is still less than 17 bytes after the host waits for the target time, it means that there may be a problem with this communication, and the communication can be terminated directly without further waiting. Then the corresponding error message is sent to the preset display terminal, so that the corresponding communication detection can be performed based on the error message, and the communication problem between the master and the slave can be solved in time, and then the subsequent communication process can be guaranteed to be smooth.

[0057] In an embodiment of the present invention, the host can write communication data into multiple registers in the host; based on a preset valid data cutoff signal, select several registers from the multiple registers as valid registers; the preset valid data cutoff signal is used to indicate whether the communication data fragments stored in the register are valid data that need to be sent to the slave, and the host and the slave are both devices based on the enhanced serial peripheral interface protocol; the communication data fragments stored in each valid register are sent to the slave, and then the slave is waited for to return response data, and the level of the preset data receiving flag signal is adjusted when the response data returned by the slave meets the preset conditions, so as to determine whether the current communication between the master and the slave is ended based on the level change of the preset data receiving flag signal. In this way, the present invention intercepts the valid data that needs to be sent to the slave by the preset valid data cutoff signal, thereby accelerating the simulation process and effectively reducing errors in the simulation process. And the preset data receiving flag signal is configured at the interface, and the level of the preset data receiving flag signal is adjusted when the response data meets the preset conditions, and then the current communication between the master and the slave is determined according to the level change of the preset data receiving flag signal. In this way, the simulation personnel can quickly capture the data return moment and accelerate the efficiency of simulation verification.

[0058] Based on the above embodiment, the present invention discloses a master-slave communication method, which can intuitively and clearly display the data written by the master to the slave, and display the exact time when the data reception is completed according to the flag signal. Next, the improvement points of the espi_master host will be described in detail.

[0059] like Figure 3 As shown, the present invention encapsulates the command, address, data and crc check bit to be sent into a data packet, and the packet receives relevant data through 16 8-bit wide registers, namely temp_command (command frame), temp_data1 (1st byte data frame to be sent) to temp_data16 (16th byte data frame to be sent). Then, a preset valid data cutoff signal is configured, and the valid data to be sent to the slave is intercepted through the preset valid data cutoff signal, and it is used as an interception signal of valid data and invalid data.

[0060] In addition, the preset data receiving flag signal is configured. After the communication data fragments stored in each valid register are sent to the slave, the host waits for the slave to return the response data, and adjusts the level of the preset data receiving flag signal when the response data returned by the slave meets the preset conditions. The end of communication is determined according to the level change of the preset data receiving flag signal. When the amount of received data reaches 17 bytes, the preset data receiving flag signal is pulled high, indicating that the data received from the espi_slave side is completed.

[0061] In this way, the simulation process can be accelerated, errors in the simulation process can be effectively reduced, and the simulation personnel can quickly capture the data return moment through the signal level change, thereby accelerating the efficiency of simulation verification.

[0062] Next, the specific master-slave communication process will be described in detail.

[0063] The host side of the present invention writes data into registers in espi_master through the I / O interface, including registers such as temp_command, temp_data1, temp_data2 ... Temp_data16, and simultaneously controls the range of the address and data valid fields through the tx_end_bytes preset valid data cutoff signal.

[0064] The waveform of a complete communication between espi_master and espi_slave is as follows: Figure 4 As shown in the figure, the preset valid data cutoff signal of tx_end_bytes is 11, indicating that temp_data1 to temp_data11 are valid fields for address and data. Among them, temp_command represents the command sent by espi_master to espi_slave, which can be commands supported by espi protocol such as PUT_IOWR_SHORT, PUT_IORD_SHORT, PUT_NP / GET_PC; Temp_data1 to temp_data16 represent the address, data, crc check code, etc. sent by the master side to the slave side; tx_end_bytes is an end mark signal, indicating that the data at this position and before are valid. The next 8-bit wide data at the interception position of the tx_end_bytes signal is the crc check code.

[0065] Then, Temp_data12 is the crc check bit, and the data fields after temp_data12 are invalid and will not be sent to the espi_slave side. In this way, tx_end_bytes is used to indicate whether the communication data fragment stored in the register is valid data that needs to be sent to the slave, and then several registers are selected from multiple registers as valid registers. After selecting several registers as valid registers from multiple registers according to the preset valid data cutoff signal, the communication data fragments stored in each valid register can be sent to the slave, and then the slave is waited for to return the response data. Specifically, the enhanced serial peripheral interface is driven to write the communication data fragments stored in each valid register into the slave, so that after receiving the communication data fragments, the slave calculates the target check code corresponding to the received communication data fragments, and judges whether to wait for the slave to return the response data based on the target check code and the cyclic redundancy check code; wherein, the communication data fragments stored in the valid registers include the cyclic redundancy check code; if the target check code is the same as the cyclic redundancy check code, wait for the slave to return the response data; if the target check code is different from the cyclic redundancy check code, it is determined that there is an error in the received communication data fragment, and the error signal returned by the slave is received; based on the error signal, the communication data fragments stored in each valid register are resent to the slave. That is to say, after writing the communication data fragments stored in each valid register into the slave, the slave will verify whether there is a difference between the received data and the data sent by the host according to the target check code corresponding to the received communication data fragment and the cyclic redundancy check code sent by the host, and then verify the integrity of the data received by the slave, thereby ensuring the accuracy of the communication. If the target check code is the same as the cyclic redundancy check code, it proves that the data is complete, and the slave can perform corresponding response operations based on the received communication data fragments to generate response data and return the response data to the host, and the host can wait for the slave to return the response data. If the target check code is the same as the cyclic redundancy check code, it proves that the data is incomplete, and the slave will return an error signal to the host to remind the host that the communication data fragments it received are wrong, so that the host will resend the communication data fragments saved in each valid register to the slave when receiving the error signal sent by the slave.

[0066] The Espi_slave side receives the relevant commands, addresses, data and CRC check bits, and returns the data after a response cycle of 2 cycles; the host will wait for the slave to return the response data, and then adjust the level of the preset data reception flag signal when the response data returned by the slave meets the preset conditions, so as to determine whether the current communication between the master and slave is over based on the level change of the preset data reception flag signal. Specifically, espi_master waits until the number of bytes received is 17, and the relevant signal is pulled high. As shown in simulation waveform 2.5, when in_has_receive_byte is 17, the signal receive_data_success jumps to a high level, and reg_receive registers 0 to 15 return data. In this way, when the level of the preset data reception flag signal is detected to be a high level, it is determined that a complete communication process between Espi_master and espi_slave is over.

[0067] Beneficial effect: The present invention intercepts the valid data to be sent to the slave machine by presetting the valid data cutoff signal, thereby accelerating the simulation process and effectively reducing errors in the simulation process. A preset data reception flag signal is configured at the interface, and the level of the preset data reception flag signal is adjusted when the response data meets the preset conditions, and then the communication between the master and slave machines is determined to be over according to the level change of the preset data reception flag signal. In this way, the simulation personnel can quickly capture the data return moment and accelerate the efficiency of simulation verification.

[0068] See also Figure 5 As shown, an embodiment of the present invention provides a master-slave communication device, which is applied to a host, including:

[0069] A first data writing module 11, used to write communication data into a plurality of registers in the host;

[0070] A register screening module 12, used for screening a number of registers from a plurality of registers as valid registers based on a preset valid data cutoff signal; the preset valid data cutoff signal is used to indicate whether the communication data fragment stored in the register is valid data to be sent to the slave, and both the host and the slave are devices based on the enhanced serial peripheral interface protocol;

[0071] The level adjustment module 13 is used to send the communication data fragments stored in each valid register to the slave, then wait for the slave to return response data, and adjust the level of the preset data reception flag signal when the response data returned by the slave meets the preset conditions, so as to determine whether the current communication between the master and the slave is completed based on the level change of the preset data reception flag signal.

[0072] Since the embodiments of the device part correspond to the above embodiments, please refer to the description of the embodiments of the method part for the embodiments of the device part, and will not be repeated here.

[0073] In an embodiment of the present invention, the host can write communication data into multiple registers in the host; based on a preset valid data cutoff signal, select several registers from the multiple registers as valid registers; the preset valid data cutoff signal is used to indicate whether the communication data fragments stored in the register are valid data that need to be sent to the slave, and the host and the slave are both devices based on the enhanced serial peripheral interface protocol; the communication data fragments stored in each valid register are sent to the slave, and then the slave is waited for to return response data, and the level of the preset data receiving flag signal is adjusted when the response data returned by the slave meets the preset conditions, so as to determine whether the current communication between the master and the slave is ended based on the level change of the preset data receiving flag signal. In this way, the present invention intercepts the valid data that needs to be sent to the slave by the preset valid data cutoff signal, thereby accelerating the simulation process and effectively reducing errors in the simulation process. And the preset data receiving flag signal is configured at the interface, and the level of the preset data receiving flag signal is adjusted when the response data meets the preset conditions, and then the current communication between the master and the slave is determined according to the level change of the preset data receiving flag signal. In this way, the simulation personnel can quickly capture the data return moment and accelerate the efficiency of simulation verification.

[0074] Furthermore, the present application also discloses an electronic device. Figure 6 It is a structural diagram of an electronic device according to an exemplary embodiment, and the content in the figure cannot be regarded as any limitation on the scope of use of this application. The electronic device may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the master-slave communication method disclosed in any of the aforementioned embodiments. In addition, the electronic device in this embodiment may specifically be an electronic computer.

[0075] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0076] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0077] The operating system 221 is used to manage and control the hardware devices on the electronic device and the computer program 222, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the master-slave communication method performed by the electronic device disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

[0078] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the master-slave communication method disclosed above. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the above embodiments, and no further description will be given here.

[0079] Furthermore, the present application also discloses a computer program product, including a computer program / instruction; wherein the computer program / instruction, when executed by a processor, implements the aforementioned disclosed response transmission method. The specific steps of the method can refer to the corresponding contents disclosed in the aforementioned embodiment, and will not be repeated here.

[0080] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0081] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0082] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0083] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0084] The technical solution provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technicians in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A master-slave communication method, characterized in that: Applied to the host, including: Writing communication data into a plurality of registers in the host; Based on a preset valid data cutoff signal, a plurality of registers are selected from the plurality of registers as valid registers; the preset valid data cutoff signal is used to indicate whether the communication data fragment stored in the register is valid data that needs to be sent to the slave, and both the host and the slave are devices based on an enhanced serial peripheral interface protocol; The communication data fragments stored in each of the valid registers are sent to the slave, and then the slave is waited for to return response data, and the level of the preset data reception flag signal is adjusted when the response data returned by the slave meets the preset conditions, so as to determine whether the current communication between the master and the slave is ended based on the level change of the preset data reception flag signal.

2. The master-slave communication method according to claim 1, characterized in that: The step of writing the communication data into a plurality of registers in the host comprises: The communication data is written into a plurality of registers in the host through an input / output interface based on an enhanced serial peripheral interface protocol; the communication data includes a target command sent by the host to the slave, relevant address information, data to be sent, and a cyclic redundancy check code; the target command is a command supported by the enhanced serial peripheral interface protocol.

3. The master-slave communication method according to claim 2, characterized in that: The sending of the communication data fragments stored in each of the valid registers to the slave machine, and then waiting for the slave machine to return response data, comprises: driving the enhanced serial peripheral interface to write the communication data fragments stored in each of the valid registers into the slave machine, so that after receiving the communication data fragments, the slave machine calculates the target check code corresponding to the received communication data fragments, and determines whether to wait for the slave machine to return response data based on the target check code and the cyclic redundancy check code; wherein the communication data fragments stored in the valid registers include the cyclic redundancy check code; If the target check code is the same as the cyclic redundancy check code, waiting for the slave to return response data; If the target check code is different from the cyclic redundancy check code, it is determined that there is an error in the received communication data segment, and an error signal returned by the slave is received; The communication data fragments stored in each of the valid registers are resent to the slave based on the error signal.

4. The master-slave communication method according to claim 1, characterized in that: Before adjusting the level of the preset data reception flag signal when the response data returned by the slave meets the preset condition, the method further includes: The preset data receiving flag signal is configured at the enhanced serial peripheral interface.

5. The master-slave communication method according to any one of claims 1 to 4, characterized in that: Before adjusting the level of the preset data reception flag signal when the response data returned by the slave meets the preset condition, the method further includes: Determine the number of bytes corresponding to the response data returned by the slave; Whether the response data returned by the slave meets a preset condition is determined according to the size relationship between the byte quantity and a preset byte threshold.

6. The master-slave communication method according to claim 5, characterized in that: The step of adjusting the level of the preset data reception flag signal when the response data returned by the slave device meets the preset condition comprises: If the number of bytes is equal to the preset byte threshold, it is determined that the response data returned by the slave meets the preset condition, and the level of the preset data reception flag signal is adjusted.

7. The master-slave communication method according to claim 5, characterized in that: Also includes: If the number of bytes is less than the preset byte threshold, determining that the response data returned by the slave does not meet the preset condition, and waiting for the slave to return the remaining response data; If the response data returned by the slave still does not meet the preset conditions after waiting for the target time, the communication is terminated and corresponding error information is sent to the preset display terminal so as to perform corresponding communication detection based on the error information.

8. A master-slave communication method, characterized in that: Applied to the host, including: A first data writing module, used for writing communication data into a plurality of registers in the host; A register screening module, used for screening a number of registers from the plurality of registers as valid registers based on a preset valid data cutoff signal; the preset valid data cutoff signal is used to indicate whether the communication data fragment stored in the register is valid data that needs to be sent to the slave, and both the host and the slave are devices based on the enhanced serial peripheral interface protocol; A level adjustment module is used to send the communication data fragments stored in each of the valid registers to the slave, then wait for the slave to return response data, and adjust the level of the preset data reception flag signal when the response data returned by the slave meets the preset conditions, so as to determine whether the current communication between the master and slave is completed based on the level change of the preset data reception flag signal.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the master-slave communication method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the master-slave communication method according to any one of claims 1 to 7 are implemented.

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