TLC flash memory read redundancy size calculation method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a TLC flash memory read redundancy calculation method and device, electronic equipment and a storage medium, and relates to the technical field of TLC flash memories. Known randomly-generated binary data are written into a TLC flash memory, an expected data mask is calculated, each reading level is subjected to multiple times of offset, the binary data are read, an actual data mask is obtained, the actual data mask is compared with the expected data mask, and the offset step length of each reading level is calculated through statistics. And adding the offset step lengths to obtain the reading redundancy size of the TLC flash memory. Therefore, the reading redundancy of the TLC flash memories of different manufacturers can be calculated, and the reliability of the TLC flash memories of different manufacturers can be compared.

Description

Technical Field

[0001] The present invention relates to the technical field of TLC flash memory, and in particular to a method, device, electronic device and storage medium for calculating the read redundancy size of a TLC flash memory. Background Art

[0002] NAND flash memory is a non-volatile storage technology that stores data by controlling the amount of charge in a storage cell. Each storage cell can represent one or more bits of information, which are distinguished by different states of voltage threshold (Vt). In NAND flash memory, data reading, programming (writing), and erasing operations are achieved by changing the Vt of the storage cell.

[0003] With the evolution of NAND flash memory, different manufacturers have launched their own products, but each manufacturer has different focuses on its own products, so the programming of particles from different manufacturers is different. Different programmed Vt distributions lead to different read redundancies between NAND flash memories. It is difficult to determine the accuracy of data reading and the reliability of storage units of products from different manufacturers without knowing the read redundancy size of products from different manufacturers. Summary of the invention

[0004] In view of this, an object of an embodiment of the present invention is to provide a method, device, electronic device and storage medium for calculating the read redundancy size of a TLC flash memory to at least partially improve the above-mentioned problem.

[0005] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows: In a first aspect, an embodiment of the present invention provides a method for calculating a TLC flash memory read redundancy size, the method comprising: Randomly generate binary data, and write the binary data into a TLC flash memory; the TLC flash memory includes a plurality of word lines, the word lines include three pages, the pages include a plurality of storage cells, the storage cells include eight states, and the eight states are isolated by seven read levels; Calculating an expected data mask for each of the pages based on the binary data; For each of the read levels of each of the pages of each of the word lines, the read level is shifted in a first direction and data is read to obtain a first actual data mask, and a first shift step length of the read level is calculated according to the first actual data mask and the expected data mask; Repeating the first direction shifting of the reading level until a first preset condition is reached, and calculating a final first shifting step length of the reading level; Performing a second direction shift on the read level and performing data reading to obtain a second actual data mask, and calculating a second shift step length of the read level according to the second actual data mask and the expected data mask; Repeating the second direction shifting of the reading level until a preset condition is met, and calculating a final second shifting step length of the reading level; Circularly calculating a first direction offset step length and a second direction offset step length of each read level of each page of each word line; The read redundancy size of the TLC flash memory is calculated by adding the offset step lengths of each first direction and the offset step lengths of each second direction.

[0006] Optionally, performing a first direction shift on the read level and performing data reading to obtain a first actual data mask, and calculating a first shift step length of the read level according to the first actual data mask and the expected data mask, includes: Finding a corresponding first state value according to the read level and the first direction offset; Determine whether the data reading is the first data reading; If the data reading is the first data reading, the offset is taken as 0, and a default reading is performed to obtain a first actual data mask; According to the first actual data mask and the expected data mask, a fault bit count of the current data read is calculated, and according to the fault bit count, a first offset step length of the read level and a pass flag are set; the pass flag includes a pass and a fail, the pass flag is a pass that indicates that the fault bit count obtained by the current read meets the judgment standard of the TLC flash memory, and the pass flag is a fail that indicates that the fault bit count obtained by the current read does not meet the judgment standard of the TLC flash memory; If the data reading is not the first data reading, taking the offset as the offset of the preset rule, performing offset reading to obtain a first actual data mask; The fault bit count of the current data read is calculated according to the first actual data mask and the expected data mask, and the first offset step length of the read level is calculated according to the fault bit count, the pass flag and the number of data reads.

[0007] Optionally, the calculating, according to the first actual data mask and the expected data mask, a fault bit count of the current data read, and setting, according to the fault bit count, a first offset step size of the read level and a pass flag, comprises: Comparing the first actual data mask with the expected data mask to obtain error data; For any of the erroneous data, according to the position of the erroneous data on the page, find the expected value of the position corresponding to the first actual data mask; If the expected value matches the first state value, increasing the fault bit count of the first state value by one; Traversing each of the erroneous data to obtain a fault bit count of the first state value; Determining whether the fault bit count is less than a preset fault number; If yes, setting the first offset step of the read level to a first preset offset, and recording the passing mark as passed; If not, the first offset step of the read level is set to a second preset offset, and the pass flag is recorded as a failure.

[0008] Optionally, the calculating, according to the first actual data mask and the expected data mask, a fault bit count of the current data read, and the calculating, according to the fault bit count, the pass flag and the number of data reads, a first offset step of the read level, comprises: Comparing the first actual data mask with the expected data mask to obtain error data; For any of the erroneous data, according to the position of the erroneous data on the page, find the expected value of the position corresponding to the first actual data mask; If the expected value matches the first state value, increasing the fault bit count of the first state value by one; Traversing each of the erroneous data to obtain a fault bit count of the first state value; Determining whether the fault bit count is less than a preset fault number; If yes, determine whether it is the second offset and the pass mark is passed; If it is the second shift and the pass mark is passed, the first shift step length of the read level is set to the first preset shift step length, and the first direction shift is ended; If it is not the second offset or the pass flag is failure, subtract the first offset step length of the read level by a value of a preset rule; If not, determine whether it is the second offset and the pass flag is failure; If it is the second shift and the pass mark is failure, the first shift step length of the read level is set to the second preset shift step length, and the first direction shift is ended; If it is not the second offset or the pass mark is passed, the first offset step length of the read level is added with the value of the preset rule.

[0009] Optionally, performing a second direction shift on the read level and performing data reading to obtain a second actual data mask, and calculating a second shift step length of the read level according to the second actual data mask and the expected data mask, includes: Finding a corresponding second state value according to the read level and the second direction offset; Determine whether the data reading is the first data reading; If the data reading is the first data reading, the offset is taken as 0, and a default reading is performed to obtain a second actual data mask; According to the second actual data mask and the expected data mask, a fault bit count of the current data read is calculated, and according to the fault bit count, a second offset step size of the read level and a pass flag are set; the pass flag includes a pass and a fail, the pass flag is a pass that indicates that the fault bit count obtained by the current read meets the judgment standard of the TLC flash memory, and the pass flag is a fail that indicates that the fault bit count obtained by the current read does not meet the judgment standard of the TLC flash memory; If the data reading is not the first data reading, taking the offset as the offset of the preset rule, performing offset reading to obtain a second actual data mask; The fault bit count of the current data read is calculated according to the second actual data mask and the expected data mask, and the second offset step of the read level is calculated according to the fault bit count, the pass flag and the number of data reads.

[0010] Optionally, the calculating, according to the second actual data mask and the expected data mask, a fault bit count of the current data read, and setting, according to the fault bit count, a second offset step size of the read level and a pass flag, comprises: comparing the second actual data mask and the expected data mask to obtain error data; For any of the erroneous data, according to the position of the erroneous data on the page, find the expected value of the position corresponding to the second actual data mask; If the expected value matches the second state value, increasing the fault bit count of the second state value by one; Traversing each of the erroneous data to obtain a fault bit count of the second state value; Determining whether the fault bit count is less than a preset fault number; If yes, setting the second offset step of the read level to a second preset offset, and recording the passing mark as passed; If not, the second offset step length of the read level is set to the first preset offset, and the pass mark is recorded as failure.

[0011] Optionally, the calculating, according to the second actual data mask and the expected data mask, a fault bit count of the current data read, and the calculating, according to the fault bit count, the pass flag and the number of data reads, a second offset step of the read level comprises: comparing the second actual data mask and the expected data mask to obtain error data; For any of the erroneous data, according to the position of the erroneous data on the page, find the expected value of the position corresponding to the second actual data mask; If the expected value matches the second state value, increasing the fault bit count of the second state value by one; Traversing each of the erroneous data to obtain a fault bit count of the second state value; Determining whether the fault bit count is less than a preset fault number; If yes, determine whether it is the second offset and the pass mark is passed; If it is the second shift and the pass mark is passed, the second shift step length of the read level is set to the first preset shift step length, and the second direction shift is ended; If it is not the second offset or the pass flag is failure, the second offset step length of the read level is added with the value of the preset rule; If not, determine whether it is the second offset and the pass flag is failure; If it is the second shift and the pass mark is failure, the second shift step length of the read level is set to the second preset shift step length, and the second direction shift is ended; If it is not the second offset or the pass flag is passed, the second offset step length of the read level is subtracted from the value of the preset rule.

[0012] In a second aspect, an embodiment of the present invention provides a TLC flash memory read redundancy size calculation device, the device comprising: A data writing unit, configured to randomly generate binary data and write the binary data into a TLC flash memory; the TLC flash memory comprises a plurality of word lines, the word lines comprise three pages, the pages comprise a plurality of storage cells, the storage cells comprise eight states, and the eight states are isolated by seven read levels; An expected data calculation unit, used for calculating an expected data mask of each of the pages according to the binary data; a first offset step length calculation unit, configured to perform a first direction offset on each of the read levels of each of the pages of each of the word lines and perform data reading to obtain a first actual data mask, and calculate a first offset step length of the read level according to the first actual data mask and the expected data mask; A final first offset step length calculation unit, used for repeatedly performing a first direction offset on the reading level until a first preset condition is reached, and calculating a final first offset step length of the reading level; A second offset step length calculation unit, configured to perform a second direction offset on the read level and perform data reading to obtain a second actual data mask, and calculate a second offset step length of the read level according to the second actual data mask and the expected data mask; A final second offset step length calculation unit, used for repeatedly performing a second direction offset on the reading level until a preset condition is met, and calculating a final second offset step length of the reading level; A cyclic calculation unit, used for cyclically calculating a first direction offset step length and a second direction offset step length of each read level of each page of each word line; The read redundancy size calculation unit is used to add each first direction offset step length and each second direction offset step length to calculate the read redundancy size of the TLC flash memory.

[0013] In a third aspect, an embodiment of the present invention provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the above-described methods when executing the program.

[0014] In a fourth aspect, an embodiment of the present invention provides a storage medium having a computer program stored thereon, wherein the computer program implements any of the above-described methods when executed by a processor.

[0015] The embodiments of the present invention provide a method, device, electronic device and storage medium for calculating the read redundancy size of a TLC flash memory. The method performs multiple offsets on the read level, and finally calculates the first direction offset step length and the second direction offset step length of the read level. All the first direction offset step lengths and the second direction offset step lengths are added together to obtain the read redundancy size of the TLC flash memory, so that the read redundancy size of the TLC flash memory of different manufacturers can be calculated, and then the reliability of the TLC flash memory of different manufacturers can be compared.

[0016] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A schematic structural block diagram of an electronic device provided by an embodiment of the present invention; Figure 2 A schematic diagram of a flow chart of a method for calculating a TLC flash memory read redundancy size provided by an embodiment of the present invention; Figure 3 A Vt distribution diagram of a TLC flash memory provided by an embodiment of the present invention; Figure 4 A schematic diagram of a flow chart of step S230 provided in an embodiment of the present invention; Figure 5 A schematic structural block diagram of a TLC flash memory read redundancy size calculation device provided in an embodiment of the present invention.

[0019] Icon: 100-electronic device; 101-memory; 102-communication interface; 103-processor; 104-bus; 300-TLC flash memory read redundant size calculation device; 310-data writing unit; 320-expected data calculation unit; 330-first offset step calculation unit; 340-final first offset step calculation unit; 350-second offset step calculation unit; 360-final second offset step calculation unit; 370-loop calculation unit; 380-read redundant size calculation unit. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0023] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0024] With the evolution of NAND flash memory, different manufacturers have launched their own products, but each manufacturer has different focuses on its own products, so the programming of particles from different manufacturers is different. Different programmed Vt distributions lead to different read redundancies between NAND flash memories. It is difficult to determine the accuracy of data reading and the reliability of storage units of products from different manufacturers without knowing the read redundancy size of products from different manufacturers.

[0025] Based on the above situation, the embodiment of the present invention provides a method, device, electronic device and storage medium for calculating the read redundancy size of a TLC flash memory, which relates to the technical field of TLC flash memory. By writing known randomly generated binary data into the TLC flash memory and calculating the expected data mask, multiple offsets are performed on each read level, and the binary data is read to obtain the actual data mask. After comparing the actual data mask with the expected data mask, the offset step length of each read level is statistically calculated, and then the offset step lengths are added together to obtain the read redundancy size of the TLC flash memory. In this way, the read redundancy size of TLC flash memories of different manufacturers can be calculated, and then the reliability of TLC flash memories of different manufacturers can be compared.

[0026] To implement the process steps and functions of each example of the present invention, please refer to Figure 1 , Figure 1A schematic structural block diagram of an electronic device provided by an embodiment of the present invention. The electronic device 100 includes a memory 101 and a processor 103, and the memory 101 and the processor 103 are electrically connected to each other directly or indirectly to realize data transmission or interaction. For example, these elements can be electrically connected to each other through one or more communication buses 104 or signal lines. The memory 101 can be used to store software programs and modules, and the processor 103 executes the software programs and modules stored in the memory 101 to perform various functional applications and data processing.

[0027] The electronic device 100 may be, but is not limited to, a personal computer (PC), a server, a distributed computer, etc. It is understandable that the electronic device 100 is not limited to a physical server, but may also be a virtual machine on a physical server, a virtual machine built on a cloud platform, etc., which can provide the same functions as the server or virtual machine. The operating system of the electronic device 100 may be, but is not limited to, a Windows system, a Linux system, etc.

[0028] Among them, the memory 101 can be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable read-only memory (EEPROM), etc.

[0029] The communication connection between the electronic device 100 and an external device is achieved through at least one communication interface 102 (which can be wired or wireless).

[0030] The processor 103 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the embodiment of the present invention can be completed by the hardware integrated logic circuit in the processor 103 or the instructions in the form of software. The processor 103 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.

[0031] Understandably, Figure 1 The structure shown is for illustration only. The electronic device 100 may also include Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown. Figure 1 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0032] The following is an exemplary description of the TLC flash memory read redundancy size calculation method provided by the present invention. Specifically, Figure 2 A flow chart of a method for calculating the read redundancy size of a TLC flash memory provided by an embodiment of the present invention, see Figure 2 , the execution subject of this method can be the above Figure 1 The electronic device 100 shown in FIG. 1 includes: Figure 2 The following steps are shown: S210: Randomly generate binary data, and write the binary data into the TLC flash memory.

[0033] Among them, the TLC flash memory includes multiple word lines, the word line (Word-Line, WL) includes three pages (page), the page includes multiple storage cells, the storage cell includes eight states, and the eight states are isolated by seven read levels.

[0034] A WL of TLC flash memory can store 3 bits of data, corresponding to 3 pages, namely low position (LP), middle position (MP), and upper position (UP).

[0035] S220: Calculate the expected data mask of each page according to the binary data.

[0036] See also Figure 3 , Figure 3 A Vt distribution diagram of a TLC flash memory provided by an embodiment of the present invention, one WL corresponds to 3 pages, and page number is a number corresponding to all WLs, for example, WL1 corresponds to page number 0; 1; 2, and WL2 corresponds to page number: 3; 4; 5. The data mask is a combination of the data of the 3 page numbers corresponding to the WL, for example, WL1 corresponds to page0, page1, page2, the data of page0 is 0110110, the data of page1 is 1001101, and the data of page2 is 1101100, and the data mask obtained by page2<<2|page1<<1|page0 is 6516712.

[0037] S230: for each read level of each page of each word line, shift the read level in a first direction and read data to obtain a first actual data mask, and calculate a first shift step of the read level according to the first actual data mask and the expected data mask.

[0038] See also Figure 3 , perform a first direction offset on the read level, which may be a left offset, and calculate the first offset step of the even edge (EvenEdge), where Even Edge corresponds to E0, E2, E4…E12.

[0039] The first offset step length indicates that the read level is offset by the first offset step length, and the data read from the TLC flash memory is still accurate.

[0040] S240: Repeat step S230 until the first preset condition is met, and calculate the final first offset step length of the reading level.

[0041] Through multiple offsets, the final first offset step of the reading level is calculated.

[0042] S250: Shifting the read level in a second direction and reading data to obtain a second actual data mask, and calculating a second shift step length of the read level according to the second actual data mask and the expected data mask.

[0043] See also Figure 3 , perform a second direction offset on the read level, which may be to the right, and calculate the second offset step of the odd edge (OddEdge), where Odd Edge corresponds to E1, E3, E5…E13.

[0044] S260: Repeat step S250 until a preset condition is met, and calculate the final second offset step length of the reading level.

[0045] S270 : cyclically calculating the first direction offset step length and the second direction offset step length of each read level of each page of each word line.

[0046] The above steps S230 to S260 are looped to calculate the first direction offset step length and the second direction offset step length of each read level of each page of the TLC flash memory.

[0047] The specific looping steps may be to first loop all WLs, start from the first WL, loop each page of the WL, and then loop each read level.

[0048] Optionally, refer to Figure 3 , including 7 read levels, namely 1, 2, 3, 4, 5, 6, and 7. The read levels can be divided into LP[1, 5], MP[2, 4, 6], and UP[3, 7] according to the data characteristics. LP[1, 5] means that the low-order data is different, MP[2, 4, 6] means that the middle-order data is different, and UP[3, 7] means that the high-order data is different. Therefore, LP[1, 5] or MP[2, 4, 6] or LP[1, 5] can be offset at the same time to reduce the number of cycles.

[0049] S280: Add each first direction offset step length and each second direction offset step length to calculate the read redundancy size of the TLC flash memory.

[0050] The calculated first direction offset step length or the second direction offset step length may be a negative number, for example, if the offset is to the left, the offset amount is a negative number. Therefore, each first direction offset step length and each second direction offset step length are added together.

[0051] The method performs multiple offsets on the read level, and finally calculates the first direction offset step and the second direction offset step of the read level. All the first direction offset step and the second direction offset step are added together to obtain the read redundancy size of the TLC flash memory, so that the read redundancy size of the TLC flash memory of different manufacturers can be calculated, and then the reliability of the TLC flash memories of different manufacturers can be compared.

[0052] For ease of understanding, the first direction offset is set to a left offset, and the second direction offset is set to a right offset. There is no limitation in actual use.

[0053] There are many ways to calculate the first offset step length. In one possible implementation, see Figure 4 , Figure 4 A schematic flow chart of step S230 provided in an embodiment of the present invention, the above step S230 may include the following: Figure 4 The following steps are shown: S231: Find the corresponding first state value according to the read level and the first direction offset.

[0054] See also Figure 3 If the read level is numbered 1 and the first direction offset is to the left, the first state value is 7.

[0055] S232: Determine whether the data reading is the first data reading; if so, execute step S233, if not, execute step S235.

[0056] S233: Taking the offset as 0, performing default reading, and obtaining the first actual data mask.

[0057] That is, the first data reading part performs an offset and directly reads the data to obtain a first actual data mask.

[0058] S234: Calculate the fault bit count of the current data read according to the first actual data mask and the expected data mask, and set the first offset step length and the pass flag of the read level according to the fault bit count.

[0059] Among them, the pass flag includes pass and fail. The pass flag is pass, which indicates that the fault bit count currently read meets the judgment standard of the TLC flash memory, and the pass flag is fail, which indicates that the fault bit count currently read does not meet the judgment standard of the TLC flash memory.

[0060] See also Figure 3 Taking read level 1 as an example, the expected data is 76402315. If the actual read data is 76402315, it indicates that the read is correct. If the actual read data is 66402315, it indicates that the read is wrong. By comparing the data of the current page in this way, the fault bit count can be obtained.

[0061] Specifically, step S234 may include: S2341: Compare the first actual data mask and the expected data mask to obtain error data.

[0062] As above, the expected data is 76402315. If the actual read data is 66402315, it indicates that the read is wrong. However, the actual read data is 66412320, which means there are more position errors. By comparing the first actual data mask and the expected data mask, all the error data are obtained.

[0063] S2342: For any erroneous data, find the expected value of the position corresponding to the first actual data mask according to the position of the erroneous data in the page.

[0064] As shown above, the first bit was mistakenly read as 6, and the expected value of its corresponding position was found, and the expected value of the first bit was 7; the eighth bit was mistakenly read as 0, and its expected value was 5.

[0065] S2343: If the expected value matches the first state value, the fault bit count of the first state value is increased by one.

[0066] As in the above example, if the first state value is 7 and the first bit expected value is 7, the position where the error is read will be recorded as a faulty bit count.

[0067] S2344: traverse each erroneous data to obtain a fault bit count of the first state value.

[0068] All erroneous data are processed in step S2343, and the fault bit count of the first state value is performed.

[0069] S2345: Determine whether the fault bit count is less than a preset fault number. If so, execute step S2346; if not, execute step S2347.

[0070] S2346: setting the first offset step of the read level to a first preset offset, and recording the pass mark as passed; Whether the fault bit count is less than the preset fault number indicates that the current read voltage meets the judgment standard of the TLC flash memory, that is, without offset, the judgment standard of the TLC flash memory meets the requirements, and the current first offset step is set to the first preset offset, the first preset offset is -128, and a record pass flag is stored as pass.

[0071] S2347: Set the first offset step of the read level to the second preset offset, and record the pass flag as failure.

[0072] In contrast to step S2346, the current first offset step is set to the second preset offset, the second preset offset is 127, and a record passing flag is stored as failure.

[0073] S235: Taking the offset as the offset of the preset rule, performing offset reading, and obtaining a first actual data mask.

[0074] The second reading and subsequent readings require an offset to the reading level. The offset can be set according to certain rules. For example, since the offset range provided by various manufacturers is -128~127, with a unit of 10mv, the offset can be performed using the binary rule. The second reading is the first offset, and the offset is the largest. If it is offset to the left, the offset is -128, and if it is offset to the right, the offset is 127. Subsequent offsets are performed by halving or increasing by half.

[0075] S236: Calculate the fault bit count of the current data read according to the first actual data mask and the expected data mask, and calculate the first offset step of the read level according to the fault bit count, the pass flag and the number of data reads.

[0076] Specifically, step S236 may include: S23601: Compare the first actual data mask and the expected data mask to obtain error data.

[0077] S23602: For any erroneous data, find the expected value of the position corresponding to the first actual data mask according to the position of the erroneous data in the page.

[0078] S23603: If the expected value matches the first state value, the fault bit count of the first state value is increased by one.

[0079] S23604: traverse each erroneous data to obtain a fault bit count of the first state value.

[0080] Steps S23601-S23604 are the same as the above steps S2341-S2344, and finally the fault bit count of the first state value is calculated.

[0081] S23605: Determine whether the fault bit count is less than the preset fault number; if so, execute step S23606, if not, execute step S23609.

[0082] S23606: Determine whether it is the second offset and the pass flag is passed. If yes, execute step S23607; if not, execute step S23608.

[0083] S23607: If it is the second shift and the pass flag is passed, the first shift step of the read level is set to the first preset shift step, and the first direction shift is ended.

[0084] The pass mark indicates the default read, which meets the TLC flash memory criteria. The second offset is -128, which still meets the TLC flash memory criteria, indicating that the maximum left offset value still meets the criteria and cannot be offset to the left any further. The first offset step is directly set to the first preset offset step. The first preset offset step is smaller than -128, which means that the first offset step of the read level is wide enough. For example, it can be set to 200, ending the offset calculation.

[0085] S23608: If it is not the second offset or the pass flag is a failure, the first offset step of the read level is subtracted from the value of the preset rule.

[0086] The default rules are , where time is the number of reads.

[0087] S23609: If not, determine whether it is the second offset and the pass mark is failure; if so, execute step S23610; if not, execute step S23611.

[0088] S23610: If it is the second shift and the pass flag is failure, the first shift step of the read level is set to the second preset shift step, and the first direction shift is ended.

[0089] The pass mark of failure indicates the default read, which does not meet the judgment criteria of TLC flash memory. The second offset is +127, which still does not meet the judgment criteria of TLC flash memory. The performance of this read level is very poor. The first offset step is directly set to the second preset offset step, for example, it can be set to -200, to end this offset calculation.

[0090] S23611: If it is not the second offset or the pass flag is passed, the first offset step length of the read level is added to the value of the preset rule.

[0091] The following is an example of a common situation. In the left offset calculation, the first default reading meets the standard and the first offset step is set to -128. The second reading at the position of -128 does not meet the standard, so the value of the preset rule needs to be added. , the first offset step is -128+64=-64, and the third reading is performed at the position of -64. If it meets the standard, the value of the preset rule needs to be subtracted, which is , the first offset step is -64-32=-96, the fourth reading is at position -96, which does not meet the standard, so the value of the preset rule needs to be added, which is , the first offset step is -96+16=-80, and the fifth reading is performed at the position of -80, which meets the standard. Then the value of the preset rule needs to be subtracted, which is , the first offset step is -80-8=-88, the sixth reading is at position -88, which does not meet the standard, so the value of the preset rule needs to be added, which is , the first offset step is -88+4=-84, and the seventh reading is performed at the position of -84, which meets the standard. Then the value of the preset rule needs to be subtracted, which is , the first offset step is -80-2=-82. The eighth reading is at position -82, which does not meet the standard. The value of the preset rule needs to be added. , the first offset step is -82+1=-81. The calculation can be ended after the eighth calculation. That is, the preset condition in step S240 can be that the calculation is ended after 8 times. Figure 3 , it can be considered that the read level 1 is offset to the left by 81, which still meets the judgment criteria of TLC flash memory, and the size of E0 can be considered to be 81.

[0092] There may be multiple ways to calculate the second offset step length. In one possible implementation, the above step S250 may include the following steps: S251: Find the corresponding second state value according to the read level and the second direction offset.

[0093] See also Figure 3 If the read level is numbered 1 and the first direction offset is to the right, the first state value is 6.

[0094] S252: Determine whether the data reading is the first data reading; if so, execute step S253, if not, execute step S255.

[0095] S253: Taking the offset as 0, performing default reading, and obtaining a second actual data mask.

[0096] S254: Calculate the fault bit count of the current data read according to the second actual data mask and the expected data mask, and set the second offset step length and the pass flag of the read level according to the fault bit count.

[0097] Among them, the pass flag includes pass and fail. The pass flag is pass, which indicates that the fault bit count currently read meets the judgment standard of the TLC flash memory, and the pass flag is fail, which indicates that the fault bit count currently read does not meet the judgment standard of the TLC flash memory.

[0098] Specifically, step S254 may include: S2541: Compare the second actual data mask and the expected data mask to obtain error data.

[0099] S2542: For any erroneous data, find the expected value of the position corresponding to the second actual data mask according to the position of the erroneous data in the page.

[0100] S2543: If the expected value matches the second state value, the fault bit count of the second state value is increased by one.

[0101] S2544: traverse each erroneous data to obtain a fault bit count of the second state value.

[0102] S2545: Determine whether the fault bit count is less than a preset fault number. If so, execute step S2546; if not, execute step S2547.

[0103] S2546: Set the second offset step of the read level to a second preset offset, and record the pass flag as passed.

[0104] S2547: Set the second offset step of the read level to the first preset offset, and record the pass flag as failure.

[0105] S255: If the data read is not the first data read, take the offset as the offset of the preset rule, perform offset reading, and obtain a second actual data mask; S256: Calculate the fault bit count of the current data read according to the second actual data mask and the expected data mask, and calculate the second offset step of the read level according to the fault bit count, the pass flag and the number of data reads.

[0106] Specifically, step S256 may include: S25601: Compare the second actual data mask and the expected data mask to obtain erroneous data.

[0107] S25602: For any erroneous data, find the expected value of the position corresponding to the second actual data mask according to the position of the erroneous data in the page.

[0108] S25603: If the expected value matches the second state value, the fault bit count of the second state value is increased by one.

[0109] S25604: traverse each error data to obtain a fault bit count of a second state value; S25605: Determine whether the fault bit count is less than the preset fault number; if so, execute step S25606, if not, execute step S25609.

[0110] S25606: If yes, determine whether it is the second offset and the pass mark is passed; if yes, execute step S25607; if no, execute step S25608.

[0111] S25607: If it is the second shift and the pass flag is passed, the second shift step length of the read level is set to the first preset shift step length, and the second direction shift is ended.

[0112] S25608: If it is not the second offset or the pass mark is a failure, the second offset step length of the read level is added to the value of the preset rule.

[0113] S25609: If not, determine whether it is the second offset and the pass mark is failure; if so, execute step S25610; if not, execute step S25611.

[0114] S25610: If it is the second shift and the pass flag is failure, the second shift step of the read level is set to the second preset shift step, and the second direction shift is ended.

[0115] S25611: If it is not the second offset or the pass flag is passed, the second offset step of the read level is subtracted from the value of the preset rule.

[0116] The logic of steps S251-S256 is similar to that of steps S231-S236, but the specific operations are opposite. The logic principle of steps S251-S256 will not be described in detail. The following is an example of a common situation. In the rightward offset calculation, the first default reading meets the standard, and the second offset step is set to 127. The second reading at the position of 127 does not meet the standard, so the value of the preset rule needs to be subtracted, which is , the second offset step is 127-64=63, and the third reading is performed at position 63. If it meets the standard, the value of the preset rule needs to be added, which is , the second offset step is 63+32=95, and the fourth reading is performed at position 95. If it does not meet the standard, the value of the preset rule needs to be subtracted, which is , the second offset step is -95-16=79, and the fifth reading is performed at position 79. If it meets the standard, the value of the preset rule needs to be added, which is , the second offset step is 79+8=87. The sixth reading is performed at position 87, which does not meet the standard. The value of the preset rule needs to be subtracted, which is , the second offset step is 87-4=83, the seventh reading is performed at position 83, which meets the standard, and the value of the preset rule needs to be added, which is , the second offset step is 83+2=85, the eighth reading is at the position of -85, which does not meet the standard, so the value of the preset rule needs to be subtracted, which is , the second offset step is 85-1=84. The calculation can be ended after the eighth calculation. Figure 3 , it can be considered that the read level 1 is offset to the right by 84, which still meets the judgment criteria of TLC flash memory, and the size of E1 can be considered to be 84.

[0117] Furthermore, an embodiment of the present invention also provides a TLC flash memory read redundancy size calculation device, referring to Figure 5 , the TLC flash memory read redundancy size calculation device 300 includes: The data writing unit 310 is used to randomly generate binary data and write the binary data into the TLC flash memory; the TLC flash memory includes multiple word lines, the word line includes three pages, the page includes multiple storage cells, the storage cell includes eight states, and the eight states are isolated by seven read levels.

[0118] The expected data calculation unit 320 is used to calculate the expected data mask of each page according to the binary data.

[0119] The first offset step calculation unit 330 is used to perform a first direction offset on each read level of each page of each word line and read data to obtain a first actual data mask, and calculate a first offset step of the read level according to the first actual data mask and the expected data mask.

[0120] The final first offset step length calculation unit 340 is used to repeatedly perform a first direction offset on the reading level until a first preset condition is reached, and calculate a final first offset step length of the reading level.

[0121] The second offset step length calculation unit 350 is used to perform a second direction offset on the read level and read data to obtain a second actual data mask, and calculate a second offset step length of the read level according to the second actual data mask and the expected data mask.

[0122] The final second offset step length calculation unit 360 is used to repeatedly perform the second direction offset on the reading level until a preset condition is met, and calculate the final second offset step length of the reading level.

[0123] The loop calculation unit 370 is used to loop calculate the first direction offset step length and the second direction offset step length of each read level of each page of each word line.

[0124] The read redundancy size calculation unit 380 is used to add each first direction offset step length and each second direction offset step length to calculate the read redundancy size of the TLC flash memory.

[0125] In summary, the embodiments of the present invention provide a method, device, electronic device and storage medium for calculating the read redundancy size of a TLC flash memory, which writes known randomly generated binary data to the TLC flash memory, calculates the expected data mask, performs multiple offsets on each read level, reads the binary data, obtains the actual data mask, compares the actual data mask with the expected data mask, statistically calculates the offset step length of each read level, and then adds the offset step lengths to obtain the read redundancy size of the TLC flash memory. In this way, the read redundancy size of TLC flash memories from different manufacturers can be calculated, and the reliability of TLC flash memories from different manufacturers can be compared.

[0126] In the embodiments provided by the present invention, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and a module, a program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0127] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0128] If the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a computer-readable storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0129] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0130] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A method for calculating the read redundancy size of a TLC flash memory, characterized in that: The method comprises: Randomly generate binary data, and write the binary data into a TLC flash memory; the TLC flash memory includes a plurality of word lines, the word lines include three pages, the pages include a plurality of storage cells, the storage cells include eight states, and the eight states are isolated by seven read levels; Calculating an expected data mask for each of the pages based on the binary data; For each of the read levels of each of the pages of each of the word lines, the read level is shifted in a first direction and data is read to obtain a first actual data mask, and a first shift step length of the read level is calculated according to the first actual data mask and the expected data mask; Repeating the first direction shifting of the reading level until a first preset condition is reached, and calculating a final first shifting step length of the reading level; Performing a second direction shift on the read level and performing data reading to obtain a second actual data mask, and calculating a second shift step length of the read level according to the second actual data mask and the expected data mask; Repeating the second direction shifting of the reading level until a preset condition is met, and calculating a final second shifting step length of the reading level; Circularly calculating a first direction offset step length and a second direction offset step length of each read level of each page of each word line; The read redundancy size of the TLC flash memory is calculated by adding the offset step lengths of each first direction and the offset step lengths of each second direction.

2. The method according to claim 1, characterized in that The step of performing a first direction shift on the read level and performing data reading to obtain a first actual data mask, and calculating a first shift step length of the read level according to the first actual data mask and the expected data mask, comprises: Finding a corresponding first state value according to the read level and the first direction offset; Determine whether the data reading is the first data reading; If the data reading is the first data reading, the offset is taken as 0, and a default reading is performed to obtain a first actual data mask; According to the first actual data mask and the expected data mask, a fault bit count of the current data read is calculated, and according to the fault bit count, a first offset step length of the read level and a pass flag are set; the pass flag includes a pass and a fail, the pass flag is a pass that indicates that the fault bit count obtained by the current read meets the judgment standard of the TLC flash memory, and the pass flag is a fail that indicates that the fault bit count obtained by the current read does not meet the judgment standard of the TLC flash memory; If the data reading is not the first data reading, taking the offset as the offset of the preset rule, performing offset reading to obtain a first actual data mask; The fault bit count of the current data read is calculated according to the first actual data mask and the expected data mask, and the first offset step length of the read level is calculated according to the fault bit count, the pass flag and the number of data reads.

3. The method according to claim 2, characterized in that The step of calculating the fault bit count of the current data read according to the first actual data mask and the expected data mask, and setting the first offset step length and the pass flag of the read level according to the fault bit count, comprises: Comparing the first actual data mask with the expected data mask to obtain error data; For any of the erroneous data, according to the position of the erroneous data on the page, find the expected value of the position corresponding to the first actual data mask; If the expected value matches the first state value, increasing the fault bit count of the first state value by one; Traversing each of the erroneous data to obtain a fault bit count of the first state value; Determining whether the fault bit count is less than a preset fault number; If yes, setting the first offset step of the read level to a first preset offset, and recording the passing mark as passed; If not, the first offset step of the read level is set to a second preset offset, and the pass mark is recorded as a failure.

4. The method according to claim 2, characterized in that: The step of calculating the fault bit count of the current data read according to the first actual data mask and the expected data mask, and calculating the first offset step of the read level according to the fault bit count, the pass flag and the number of data reads, comprises: Comparing the first actual data mask with the expected data mask to obtain error data; For any of the erroneous data, according to the position of the erroneous data on the page, find the expected value of the position corresponding to the first actual data mask; If the expected value matches the first state value, increasing the fault bit count of the first state value by one; Traversing each of the erroneous data to obtain a fault bit count of the first state value; Determining whether the fault bit count is less than a preset fault number; If yes, determine whether it is the second offset and the pass mark is passed; If it is the second shift and the pass mark is passed, the first shift step length of the read level is set to the first preset shift step length, and the first direction shift is ended; If it is not the second offset or the pass flag is failure, the first offset step length of the read level is added with the value of the preset rule; If not, determine whether it is the second offset and the pass flag is failure; If it is the second shift and the pass mark is failure, the first shift step length of the read level is set to the second preset shift step length, and the first direction shift is ended; If it is not the second offset or the pass flag is passed, the first offset step length of the read level is subtracted from the value of the preset rule.

5. The method according to claim 1, characterized in that The step of performing a second direction shift on the read level and performing data reading to obtain a second actual data mask, and calculating a second shift step length of the read level according to the second actual data mask and the expected data mask, comprises: Finding a corresponding second state value according to the read level and the second direction offset; Determine whether the data reading is the first data reading; If the data reading is the first data reading, the offset is taken as 0, and a default reading is performed to obtain a second actual data mask; According to the second actual data mask and the expected data mask, a fault bit count of the current data read is calculated, and according to the fault bit count, a second offset step size of the read level and a pass flag are set; the pass flag includes a pass and a fail, the pass flag is a pass that indicates that the fault bit count obtained by the current read meets the judgment standard of the TLC flash memory, and the pass flag is a fail that indicates that the fault bit count obtained by the current read does not meet the judgment standard of the TLC flash memory; If the data reading is not the first data reading, taking the offset as the offset of the preset rule, performing offset reading to obtain a second actual data mask; The fault bit count of the current data read is calculated according to the second actual data mask and the expected data mask, and the second offset step length of the read level is calculated according to the fault bit count, the pass flag and the number of data reads.

6. The method according to claim 5, characterized in that The step of calculating the fault bit count of the current data read according to the second actual data mask and the expected data mask, and setting the second offset step length and the pass flag of the read level according to the fault bit count, comprises: Comparing the second actual data mask with the expected data mask to obtain error data; For any of the erroneous data, according to the position of the erroneous data on the page, find the expected value of the position corresponding to the second actual data mask; If the expected value matches the second state value, increasing the fault bit count of the second state value by one; Traversing each of the erroneous data to obtain a fault bit count of the second state value; Determining whether the fault bit count is less than a preset fault number; If yes, setting the second offset step of the read level to a second preset offset, and recording the passing mark as passed; If not, the second offset step length of the read level is set to the first preset offset, and the pass mark is recorded as failure.

7. The method according to claim 5, characterized in that The step of calculating the fault bit count of the current data read according to the second actual data mask and the expected data mask, and calculating the second offset step of the read level according to the fault bit count, the pass flag and the number of data reads, comprises: Comparing the second actual data mask with the expected data mask to obtain error data; For any of the erroneous data, according to the position of the erroneous data on the page, find the expected value of the position corresponding to the second actual data mask; If the expected value matches the second state value, increasing the fault bit count of the second state value by one; Traversing each of the erroneous data to obtain a fault bit count of the second state value; Determining whether the fault bit count is less than a preset fault number; If yes, determine whether it is the second offset and the pass mark is passed; If it is the second shift and the pass mark is passed, the second shift step length of the read level is set to the first preset shift step length, and the second direction shift is ended; If it is not the second offset or the pass flag is failure, the second offset step length of the read level is added with the value of the preset rule; If not, determine whether it is the second offset and the pass flag is failure; If it is the second shift and the pass mark is failure, the second shift step length of the read level is set to the second preset shift step length, and the second direction shift is ended; If it is not the second offset or the pass flag is passed, the second offset step length of the read level is subtracted from the value of the preset rule.

8. A TLC flash memory read redundancy size calculation device, characterized in that: The device comprises: A data writing unit, configured to randomly generate binary data and write the binary data into a TLC flash memory; the TLC flash memory comprises a plurality of word lines, the word lines comprise three pages, the pages comprise a plurality of storage cells, the storage cells comprise eight states, and the eight states are isolated by seven read levels; An expected data calculation unit, used for calculating an expected data mask of each of the pages according to the binary data; a first offset step length calculation unit, configured to perform a first direction offset on each of the read levels of each of the pages of each of the word lines and perform data reading to obtain a first actual data mask, and calculate a first offset step length of the read level according to the first actual data mask and the expected data mask; A final first offset step length calculation unit, used for repeatedly performing a first direction offset on the reading level until a first preset condition is reached, and calculating a final first offset step length of the reading level; A second offset step length calculation unit, configured to perform a second direction offset on the read level and perform data reading to obtain a second actual data mask, and calculate a second offset step length of the read level according to the second actual data mask and the expected data mask; A final second offset step length calculation unit, used for repeatedly performing a second direction offset on the reading level until a preset condition is met, and calculating a final second offset step length of the reading level; A cyclic calculation unit, used for cyclically calculating a first direction offset step length and a second direction offset step length of each read level of each page of each word line; The read redundancy size calculation unit is used to add each first direction offset step length and each second direction offset step length to calculate the read redundancy size of the TLC flash memory.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the method according to any one of claims 1 to 7 is implemented.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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