Method for realizing memory cache consistency, CXL equipment, host and storage medium

Abstract

A method for realizing memory cache consistency, a CXL device, a host and a storage medium, a cache proxy of the CXL device interacts with a host proxy of the host based on a CXL protocol, obtains an address translation entry of the device stored in a host memory, and caches the address translation entry in an ATC; and maintaining the consistency of the ATC and the address translation entries stored in the memory of the host, including: sending an invalidation instruction to the host to invalidate part or all of the address translation entries of the device stored in the memory of the host; according to the embodiment of the invention, resources occupied by the address translation entry can be released in time.

Description

Technical Field

[0001] The present disclosure relates to data storage technology, and more specifically, to a method for implementing memory cache consistency, a CXL device, a host, and a storage medium. Background Art

[0002] CXL (Compute Express Link) technology is a new type of high-speed interconnection technology that supports high-bandwidth, low-latency data transmission, has better flexibility and scalability, and can achieve mixed use of different types of hardware devices. The application scenarios of CXL technology are very broad, including data centers, artificial intelligence, and processor interconnection. In the data center field, CXL technology can interconnect different computing and storage resources to improve system performance and efficiency; in the field of artificial intelligence, CXL technology can enable accelerators such as GPUs and FPGAs to better collaborate with the main processor and increase the speed of AI model training and reasoning; in terms of processor interconnection, CXL technology can achieve interconnection between processors from different manufacturers, improving the overall performance and flexibility of the system.

[0003] With the promotion of CXL technology applications, how to enable CXL devices to quickly access host memory and effectively maintain the consistency of memory cache has become an urgent problem to be solved. Summary of the invention

[0004] The embodiment of the present disclosure provides a CXL device, including an address translation cache ATC and a cache agent, wherein the cache agent is configured to:

[0005] Interacting with the host based on the CXL protocol, obtaining the address translation entry of the device stored in the host memory, and caching the address translation entry in the ATC; and

[0006] Interacting with the host based on the CXL protocol to maintain consistency between the address translation entries stored in the ATC and the host memory, including: sending an invalidation instruction to the host to invalidate part or all of the address translation entries of the device stored in the host memory.

[0007] The embodiment of the present disclosure further provides a host, including a host agent and a host memory, wherein the host agent is configured as follows:

[0008] Interacting with the CXL device based on the CXL protocol, sending the address translation entry of the CXL device stored in the host memory to the CXL device to be stored in the address translation cache ATC of the CXL device; and

[0009] Interacting with the CXL device based on the CXL protocol to maintain consistency between the address translation entries stored in the host memory and the ATC includes: receiving an invalidation instruction sent by the CXL device to invalidate part or all of the address translation entries of the CXL device.

[0010] The embodiment of the present disclosure also provides a method for implementing memory cache consistency, which is applied to a CXL device, including:

[0011] Interacting with the host based on the CXL protocol, obtaining the address translation entry of the device stored in the host memory, and caching the address translation entry in the ATC; and

[0012] The CXL protocol is used to interact with the host to maintain the consistency of the address translation entries stored in the ATC and the host memory, including: sending an invalidation instruction to the host to request invalidation of part or all of the address translation entries of the device stored in the host memory.

[0013] The embodiment of the present disclosure also provides a method for implementing memory cache consistency, which is applied to a host and includes:

[0014] Interacting with the CXL device based on the CXL protocol, sending the address translation entry of the CXL device stored in the host memory to the CXL device to be stored in the address translation cache ATC of the CXL device; and

[0015] Interacting with the CXL device based on the CXL protocol to maintain consistency between the address translation entries stored in the host memory and the ATC includes: receiving an invalidation instruction sent by the CXL device to invalidate part or all of the address translation entries of the CXL device.

[0016] The embodiments of the present disclosure also provide a non-transitory computer storage medium storing a computer program, which can implement the method of the embodiments of the present disclosure when executed by a processor.

[0017] In the above embodiment of the present disclosure, the cache agent of the CXL device and the host agent of the host interact based on the CXL protocol, obtain the address translation entries of the device stored in the host memory and cache them in the ATC; and maintain the consistency of the address translation entries stored in the ATC and the host memory. The cache agent of the CXL device can actively send an invalidation instruction to the host to invalidate some or all of the address translation entries of the device stored in the host memory. As the initiator of DMA and address translation services, the CXL device can determine the host physical address that needs to be accessed more timely and accurately than the host. By invalidating the address translation entries related to the host physical address that does not need to be accessed, the storage space of the host memory and the device cache can be released in time, thereby improving the utilization of resources.

[0018] Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or be understood by implementing the present disclosure. Other advantages of the present disclosure can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0020] Figure 1A is a schematic diagram of a system consisting of a CXL device and a host according to an embodiment of the present disclosure;

[0021] Figure 1B is a schematic diagram of a system composed of a CXL device and a host according to another embodiment of the present disclosure;

[0022] Figure 2A is a schematic diagram of a data structure of a cache line according to an embodiment of the present disclosure;

[0023] Figure 2B is a schematic diagram of a data structure of a cache line according to another embodiment of the present disclosure;

[0024] Figure 3 is a flow chart of a method for implementing memory cache consistency in a CXL device according to an embodiment of the present disclosure;

[0025] Figure 4 is a flow chart of a method for implementing memory cache consistency in a host according to an embodiment of the present disclosure;

[0026] Figure 5 is a schematic diagram of a system composed of a CXL device and a host according to another embodiment of the present disclosure;

[0027] Figure 6 is a flow chart of a CXL device initiating an invalidation operation according to another embodiment of the present disclosure;

[0028] Figure 7 is a flowchart of another embodiment of the present disclosure in which a CXL device and a host interact to obtain an address translation entry;

[0029] Figure 8 This is a flowchart of a host initiating an invalidation operation according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] The present disclosure describes multiple embodiments, but the description is exemplary rather than restrictive, and it is apparent to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present disclosure. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0031] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed in the present disclosure may also be combined with any conventional features or elements to form a unique invention scheme defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present disclosure may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other limitations. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0032] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be appreciated by those of ordinary skill in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art can easily understand that these orders can be changed and still remain within the spirit and scope of the disclosed embodiments.

[0033] When a PCIe device accesses the host physical memory (for example, performing a DMA operation), it needs to convert the bus domain address (referred to as the bus domain address) used by the device side into the host physical address. The translation agent (TA) on the host side can provide an address translation service (ATS) and store address translation entries including the bus domain address and the host physical address in the address translation and protection table (ATPT) of the host memory. The address translation can be completed by the TA based on the ATPT. When there are many PCIe devices and the host memory resources are accessed frequently, the address translation will become a system bottleneck. In order to improve efficiency, an address translation cache (ATC) can be added on the device side to cache the address translation entries used by the device. The PCIE protocol allows the host to invalidate the address translation entries stored in the ATPT and ATC to maintain the consistency of the address translation entries stored in the ATPT and ATC.

[0034] CXL (Compute Express Link) runs on top of the PCIE physical layer, supporting high-bandwidth, low-latency data transmission, with better flexibility and scalability. Based on the characteristics of memory access, the CXL standard supports various use cases through the following three protocols: CXL.io protocol (i.e. CXL input and output protocol): This protocol leverages the broad industry adoption and familiarity of PCIe. As the basic communication protocol; CXL.cache protocol (i.e. CXL cache protocol): This protocol is designed for more specific applications and supports CXL devices to read and write data in cachelines to the host memory, usually each cacheline consists of 64Bytes. CXL.memory protocol (i.e. CXL storage protocol): This protocol enables the host to access the memory connected to the device. Accordingly, the CXL Alliance has identified three types of CXL devices: Type 1 CXL devices (CXL Type1 Device), which support CXL.io and CXL.cache, such as accelerators such as smart NICs, which usually lack local memory. Communicate with the host processor's memory through the CXL protocol; Type 2 CXL devices (CXL Type2 Device), support CXL.io, CXL.cache and CXL.memory, such as GPU, ASIC and FPGA equipped with DDR or HBM memory (also known as accelerators), through the CXL protocol, the host's memory can be used by the accelerator, and the accelerator's memory can also be used by the host CPU. Co-located in the same cache coherent domain, Type 2 devices can complete a large amount of calculations inside the device and exchange a large amount of data with the host; and, Type 3 CXL devices (CXL Type3Device), support CXL.io and CXL.memory protocols, such as memory devices connected to the host through CXL, can provide additional bandwidth and capacity for the host processor.

[0035] In the CXL architecture, in order to maintain the consistency of the address translation entries stored in ATPT and ATC, the method specified by the PCIE protocol can be continued, that is, when the host determines that the address translation entry is invalid, it sends an instruction to notify the CLX device to invalidate the corresponding address translation entry in the ATC. However, this method has some shortcomings. For example, the host cannot timely know the changes in the CXL device's access requirements for data in the host memory, and it is difficult to determine which address translation entries can be invalidated based on the host physical address of these data, resulting in the storage resources occupied by the address translation entries not being released in time for other services to use, that is, the efficiency of the invalidation operation is not high. In addition, in the CXL architecture, if the CXL device implements the address translation service based on the CXL.io protocol, the host CPU needs to decode the corresponding instructions of the CXL.io protocol and then convert them into read and write operations on the host memory or ATC, which is inefficient.

[0036] An embodiment of the present disclosure provides a CXL device, such as Figure 1A As shown, the CXL device 1 includes a cache agent 11 and an ATC 12. The cache agent 11 is configured as follows:

[0037] Interacting with the host based on the CXL protocol, obtaining the address translation entry of the device stored in the host memory, and caching the address translation entry in the ATC; and

[0038] The CXL protocol is used to interact with the host to maintain the consistency of the address translation entries stored in the ATC and the host memory, including: sending an invalidation instruction to the host to request invalidation of part or all of the address translation entries of the device stored in the host memory.

[0039] Figure 1A The host 2 includes a host agent 21 and a host memory 22. The processing performed by the host agent 21 is described in the following embodiments. The host 2 can be connected to multiple CXL devices 1 at the same time. Figure 1B As shown, when multiple CXL devices 1 can access the host memory, the host allocates accessible host memory space to each CXL device and provides address translation services. Each CXL device in the multiple CXL devices 1 can interact with the host, obtain the address translation entries of the device stored in the host memory and store them in the ATC, and maintain the consistency of the address translation entries shared by the ATC of the device and the host memory.

[0040] In addition to the ATC, the cache of the CXL device may also have other cache areas (not shown in the figure), and the other cache areas and the ATC may be located in the same cache or in different caches. The cache agent may be implemented by a processor in the CXL device in hardware, but is not limited thereto. In the illustrated example, the cache agent 11 in the CXL device 1 may interact with the host agent 21 via the CXL.io protocol and the CXL.cache protocol, and the CXL device 1 may be a type 1 CXL device or a type 2 CXL device that supports the CXL.io protocol and the CXL.cache protocol.

[0041] Figure 1A In the system shown, after the host detects that a CXL device is connected, it can determine the host memory space to be accessed by the CXL device according to the task to be performed by the CXL device, thereby generating an address translation entry for the CXL device, wherein the host physical address in the address translation entry is determined according to the host memory space to be accessed, and the bus domain address in the address translation entry can be an input / output virtual address (IOVA: IO Virtual Address) assigned by an input / output memory management unit (IOMMU: input / output memory management unit). In the disclosed embodiment, the host can generate a corresponding address translation entry when the CXL device sends an ATS request, store the generated address translation entry in the host memory and return it to the CXL device; or, the host can also generate an address translation entry in advance and store it in the host memory such as ATPT, and find the corresponding address translation entry from ATPT and return it to the CXL device when the CXL device requests it.

[0042] Taking the execution of DMA operation as an example, when the CXL device accesses the data in the host memory, it can search for the corresponding address conversion entry in ATC according to the bus domain address to be accessed (i.e., DMA address). If it is found, the bus domain address is converted into the host physical address before accessing the host memory; if it is not found, the cache agent interacts with the host based on the CXL protocol, such as sending an ATS request, obtaining the address conversion entry corresponding to the bus domain address and storing it in ATC, and accessing the host memory after converting the bus domain address into the host physical address. As the initiator of ATS and DMA, the CXL device has a better understanding of the host physical address range that needs to be accessed in some scenarios than the host. It can determine whether the address conversion entry stored in ATC can be invalidated in a more timely manner. When maintaining the consistency of the address conversion entries stored in ATC and the host memory, the embodiment of the present disclosure allows the CXL device to actively send an invalidation instruction to the host, requesting to invalidate some or all of the address conversion entries of the device stored in the host memory. Thus, through the invalidation operation, the cache space and memory space occupied by the address conversion entries that do not need to be accessed and are invalidated are released in time, thereby improving the utilization rate of the cache and memory.

[0043] There may be many CXL devices connected to the host. For a certain CXL device, the address translation entries stored in the ATC of the CXL device are also stored in the host memory, and the address translation entries stored in the host memory may also store the address translation entries of other CXL devices. For each CXL device, it is necessary to maintain the consistency of the address translation entries stored in the ATC of the CXL device and in the host memory. In the above definition of the CXL device cache agent, the ATC of the CXL device is abbreviated as ATC to simplify the description.

[0044] In an exemplary embodiment of the present disclosure, the cache agent sends an invalidation instruction to the host to invalidate some or all of the address translation entries of the device stored in the host memory, including: when it is determined that some or all of the address translation entries in the ATC are invalid, the some or all of the address translation entries in the ATC are set to invalid, and based on the CXL protocol, the invalidation instruction is sent to the host to invalidate some or all of the address translation entries stored in the host memory. In one example, the cache agent determines that one or more of the address translation entries in the ATC are invalid, including: when it is determined based on business characteristics that the host physical address in some or all of the address translation entries in the ATC will not be accessed within a predetermined time, the some or all of the address translation entries are determined to be invalid.

[0045] In one example, the predetermined time may be a fixed time length such as 1 hour. In another example, the predetermined time may also be a subsequent execution time of the task, that is, the address translation entry corresponding to the host physical address that is no longer needed to be accessed for executing the current task may be judged as invalid. The present disclosure is not limited to this.

[0046] The computing function of the CXL device (such as Type2 device) has a certain prediction function for the data to be accessed, so the content of the host-side ATPT cache is reduced based on this. Taking the accelerator used to perform image processing as an example, it is assumed that the accelerator needs to access the host memory to obtain the image data to be processed when performing the image processing task. Before accessing the host memory (such as performing a DMA operation), the accelerator needs to perform address conversion based on the address conversion entries in the ATC or host memory to obtain the host physical address of the image data. According to the task, the accelerator can know the host memory address range (for example, 0 to 1000) that the DMA operation is about to access. After the access starts, the corresponding address conversion entries can be obtained through the ATS and stored in the ATC. As the image processing proceeds, the accelerator can determine whether some of the host physical addresses that have been accessed need to be accessed during the execution of this task according to the task characteristics and business completion status. For some host physical addresses that no longer need to be accessed (for example, 0 to 500), it can be determined that the corresponding part or all of the address conversion entries in the ATC are invalid. At this time, the cache agent in the accelerator can set some or all of the address translation entries in the ATC to invalidate, and send an invalidation instruction to the host based on the CXL protocol to invalidate some or all of the address translation entries stored in the host memory, thereby releasing the storage resources of the ATC and the host memory in time.

[0047] In an exemplary embodiment of the present disclosure, the address translation entry is stored in a cache line of the ATC and a memory block of the host memory, each cache line in the ATC is mapped to a memory block in the host memory, and the cache line and the memory block having a mapping relationship share data; wherein the data stored in a cache line in the ATC includes:

[0048] An operation code, used to indicate an operation to be performed, wherein the operation includes an invalidation operation on an address translation entry;

[0049] A status code, used to indicate the status of each address translation entry stored in the cache line;

[0050] A plurality of address translation entries, wherein each address translation entry includes a host physical address and a bus domain address.

[0051] In this embodiment, the cache lines and memory blocks with a mapping relationship share data, that is, the data structure of a memory block is the same as the data structure of a cache line, and also includes the above-mentioned operation code, status code and multiple address translation entries. In this embodiment, the address translation entries are stored in the memory blocks mapped to the cache lines in the ATC, so the ATPT function can be realized. Therefore, the address translation entries stored in these memory blocks can be regarded as ATPT. Different from the conventional ATPT, the data stored in these memory blocks also include operation codes and status codes in addition to the address translation entries.

[0052] In an example of this embodiment, Figure 2A As shown, the data structure of a cache line in ATC includes an opcode, a status code, and multiple address translation entries. Each address translation entry includes a bus domain address and a host physical address. In this example, the size of a cacheline is 64 bytes, and the size of the memory block mapped to the cacheline needs to be the same as the cacheline, that is, also 64 bytes. Assuming that the size of the bus domain address and the host physical address are both 32 bits, the size of an address translation entry is 8 bytes, and 7 address translation entries (Address translation entry) can be stored in a cacheline, that is, N=7. The remaining 8 bytes can be allocated to the opcode and status code, or some bytes can be reserved.

[0053] The possible values ​​of the operation code (OpCode) in this example include: 000, indicating that the operation is a request for an address translation entry (TransRequest); 001, indicating that the operation is a return of an address translation entry (TransComplete); 010, indicating that the operation is an invalidation operation initiated by the host (HostAddrInvReq); 011, indicating that the operation is an invalidation operation initiated by the device (DevAddrInvReq), and other values ​​are reserved (Reserved). The status code can use 6 bits to indicate whether the status (Status) of the 6 address translation entries is valid or invalid. For example, when the value is 0, it means that the corresponding address translation entry is invalid, and when the value is 1, it means that the corresponding address translation entry is valid.

[0054] In different computer systems, the size of the cacheline can vary, such as 128 bytes, 256 bytes or even more, and the size of the bus domain address and the host physical address can also vary, such as 64 bits, 128 bits, etc. For this purpose, the size and position of the above-mentioned status code and operation code (such as the position of the interactive status code and operation code), and the number and position of the address translation entries can be adjusted. In another example, Figure 2BAs shown, the data structure of a cache line in ATC includes M groups of data, and the data structure of each group of data includes an operation code, a status code and multiple address translation entries, and each address translation entry includes a bus domain address and a host physical address.

[0055] In an exemplary embodiment of the present disclosure, the cache agent sends an invalidation instruction to the host based on the CXL protocol, including: when it is determined that all address translation entries stored in one or more cache lines are invalid, sending an invalidation instruction to the host based on the CXL.io protocol or the CXL.cache protocol, carrying an operation field and a memory block address; wherein the operation indicated by the operation field is an invalidation operation initiated by the device side, and the memory block address is the address of the memory block to which the cache line is mapped. Neither the CXL.cache protocol nor the CXL.io protocol defines an invalidation instruction for an address translation entry initiated by the device side. The invalidation instruction sent by the CXL device to the host in this embodiment is an extension of the CXL.io protocol or the CXL.cache protocol. The operation field used in the invalidation instruction may be different from the operation code in the cache line.

[0056] In another exemplary embodiment of the present disclosure, as described above, the data stored in the cacheline includes an operation code, a status code, and a plurality of address translation entries, and the cache agent sends an invalidation instruction to the host based on the CXL protocol, including:

[0057] When it is determined that some or all of the address translation entries stored in the cache line of the ATC are invalid, a write request of the CXL.cache protocol is sent to the host, carrying the address of the memory block to which the cache line is mapped (the memory block to which the cache line is mapped is also the memory block used to store the some or all of the address translation entries);

[0058] After receiving a write-permitted response returned by the host, sending the invalidation instruction to the host to write into the memory block to which the cache line is mapped;

[0059] Among them, the invalidation instruction includes an operation code, a status code and multiple address translation entries stored in the cache line, the operation indicated by the operation code is an invalidation operation initiated by the device side, and the status code includes multiple status bits to indicate whether the status of each address translation entry in the multiple address translation entries is valid or invalid.

[0060] In the first example, the cache agent initiates the above invalidation operation when it determines that some address translation entries in a cache line are invalid; in the second example, the cache agent initiates the invalidation operation when it determines that all address translation entries in a cache line are invalid; in the third example, the cache agent initiates the invalidation operation when it determines that all address translation entries in N cache lines are invalid, where N is a positive integer greater than or equal to 2. In terms of the communication resources consumed by signaling interaction, the first example consumes more than the second example, and the second example consumes more than the third example, but the first example can initiate the invalidation operation more timely.

[0061] The invalidation instruction of this embodiment is different from the previous embodiment. The device-to-host request (D2H Request) defined by the CXL.cache protocol includes the read and write operations of the CXL device to the host memory. The cache agent of this embodiment completes the invalidation operation on the address translation entry through the write data process initiated by the write request of the CXL.cache protocol, and sends the invalidation instruction as the data requested to be written to the host. This implementation method is to use CXL.cache as the underlying basic protocol, and use the invalidation instruction as the load of the CXL.cache protocol. The content of the invalidation instruction is transparent to the CXL.cache protocol. In this embodiment, the invalidation instruction is directly written as data into the memory block of the host memory for storing the address translation entry, and its data structure is the same as the data structure of the memory block and cache line storing the address translation entry. When generating the invalidation instruction, the cache line where the said part or all of the address translation entries that need to be invalidated are located can be found, the data of the cache line can be read out, the value of the operation code can be updated to the value representing the invalidation operation, and the status code can be updated to indicate that the status of the said part or all of the address translation entries is invalid, thereby obtaining the invalidation instruction. In another example, if the cache agent has set the status bits corresponding to the part or all of the address translation entries that need to be invalidated to a value indicating invalidity, the status code in the read data may not be updated when the invalidation instruction is generated. The host can determine that the invalidation operation is being performed this time by parsing the operation code in the written data. For the address translation entries whose status is invalid, the storage space occupied by them can be released.

[0062] In an exemplary embodiment of the present disclosure, the cache agent interacts with the host based on the CXL.cache protocol to maintain consistency between the ATC and the address translation entries stored in the host memory, including:

[0063] receiving and parsing an invalidation request sent by the host, the invalidation request carrying an operation field, a status field and an address of the first memory block, the operation indicated by the operation field being an invalidation operation initiated by the host, and the status field being used to indicate an address translation entry that needs to be invalidated;

[0064] When determining that the first memory block is mapped to a first cache line in the ATC, updating a status code in the first cache line according to the status field to change the status of the address translation entry to be invalidated in the first cache line to invalid;

[0065] A response is sent to the host, indicating completion of invalidation of the address translation entry.

[0066] In this embodiment, the host actively initiates the invalidation process to maintain the consistency between the address conversion entries stored in the ATC and the host memory. The host-to-device request (H2D Request) defined in the CXL.cache protocol includes a variety of snoop requests (listening requests), but does not support invalidation operations for address conversion entries in cache lines. In this embodiment, the H2D Request defined in the CXL.cache protocol is extended to support the host to initiate an invalidation operation for address conversion entries. The operation field in the above invalidation request does not need to be the same as the value of the operation code in the cache line. The status field in the above invalidation request can include multiple status bits like the status code in the cache line, indicating that the status of multiple address conversion entries in the first cache line is valid or invalid, or a status bit can be used to indicate that the status of all address conversion entries in the first cache line is invalid. After receiving the invalidation request, the cache agent in this embodiment identifies that the host has initiated an invalidation request for the address conversion entry according to the operation field, and then updates the status code in the first cache line according to the status field to complete the invalidation operation and return a response.

[0067] In another exemplary embodiment of the present disclosure, the cache agent interacts with the host based on the CXL.cache protocol to maintain consistency between the ATC and the address translation entries stored in the host memory, including:

[0068] Receiving and parsing a snoop request sent by the host, the snoop request carrying an address of a first memory block, the first memory block storing an address translation entry that needs to be invalidated;

[0069] When determining that the first memory block is mapped to the first cache line in the ATC, sending a read request of the CXL.cache protocol to the host, carrying the address of the first memory block;

[0070] Receive data stored in the first memory block returned by the host, and write the received data into the first cache line, wherein the data includes an operation code, a status code and multiple address translation entries, wherein the operation indicated by the operation code is an invalidation operation initiated by the host, and the status code includes multiple status bits to indicate whether the status of each of the multiple address translation entries is valid or invalid.

[0071] As mentioned above, the first cache line and the first memory block with a mapping relationship share data and have the same data structure. The data read from the first memory block has updated the state of the address translation entry (e.g., the state position corresponding to the address translation entry to be invalidated has been set to 0). After the cache agent writes the read data into the first cache line, the invalidation operation of the address translation entry is completed.

[0072] This embodiment adopts a different method from the previous embodiment to implement the invalidation operation initiated by the host for the address translation entry. The previous embodiment is to extend the CXL.cache protocol to support the invalidation request initiated by the host. This embodiment can trigger the CXL device to read out the data containing the invalidation information from the first memory block based on the existing snoop request (listening request) of the CXL.cache protocol, and then write it into the first cache line to complete the invalidation operation initiated by the host for the address translation entry. In order to distinguish it from the processing of other snoop requests, the cache agent in the CXL device can determine whether the memory block with the memory block address is mapped to the cache line in the ATC according to the memory block address carried by the snoop request. If it is mapped, the operation of reading the memory block data is triggered to complete the invalidation operation for the address translation entry. If it is not mapped to the cache line in the ATC, it is processed according to other situations specified in the protocol.

[0073] In an exemplary embodiment of the present disclosure, the cache agent interacts with the host based on the CXL protocol, obtains the address translation entry of the device stored in the host memory, and caches the address translation entry in the ATC, including:

[0074] Sending an address translation request to the host based on the CXL.cache protocol, carrying the bus domain address in the requested address translation entry;

[0075] After receiving the notification of reading the address translation entry sent by the host based on the CXL.cache protocol, the address translation entry of the request completed by the host is read from the host memory and written into the ATC.

[0076] In an example of this embodiment, when the CXL device initiates DMA and fails to find a corresponding address translation entry in the local ATC, it may send an address translation request to the host based on the CXL.cache protocol.

[0077] In other embodiments of the present disclosure, the cache agent can interact with the host based on the CXL.io protocol to obtain the address translation entries of the device stored in the host memory. This embodiment provides a method for interacting with the host based on the CXL.cache protocol to obtain the address translation entries of the device stored in the host memory, and provides a new ATS implementation process. The cache agent of the CXL device in this embodiment directly accesses the host memory based on the device-to-host request (D2H Request) of the CXL.cache protocol, obtains the required address translation entries from the host memory and writes them into the ATC. The CXL device and the host do not need to decode the instructions sent by the other end before executing data reading and writing, which is more efficient.

[0078] In an exemplary embodiment of the present disclosure, the cache agent sends an address translation request to the host based on the CXL.cache protocol, including:

[0079] Sending a write request of the CXL.cache protocol to the host, carrying an address of a second memory block in the host memory, where the second memory block is a memory block for storing the requested address translation entry;

[0080] After receiving a write-permitted response from the host, sending the address conversion request as write-requested data to the host, so as to be written into the second memory block;

[0081] Among them, the address translation request includes an operation code, a status code and multiple address translation entries; the operation indicated by the operation code is to request an address translation entry, the status code is used to indicate the position of the requested address translation entry in the multiple address translation entries or to indicate the status of each address translation entry in the multiple address translation entries, the multiple address translation entries include the requested address translation entry, and the requested address translation entry only contains the bus domain address to be converted, that is, the host physical address in the requested address translation entry is invalid data, such as 0x FF FF FF FF.

[0082] The write request (Write) from the device to the host in the CXL.cache protocol includes multiple types, such as WOWrInv, WrInv, CleanEvict, etc. After these write requests carrying the host physical address are sent, the host will reply with a response indicating whether it can be written. If it can, the CXL device sends data to the host to the host physical address. Taking WOWrInv as an example, the WOWrInv request adopts weak memory order, and usually writes data to the host memory when the cache line data of the CXL device is invalid. This request supports the CXL device to write 0-63Bytes of data to the host. After the CXL device sends the WOWrInv request, if the feedback received is Fast_GO_WritePull, the CXL device can write data to the host memory. The write request used in the embodiment of the present disclosure is not limited to the existing ones in the CXL.cache protocol, but can also be a newly defined write request, and the response (Response) returned by the host to allow writing can also be newly defined, and it is not necessary to use the original response type. This embodiment applies the write process to ATC to obtain address translation entries.

[0083] In an example of this embodiment, the data structure of the address translation request generated by the cache agent is the same as the data structure of the cache line, wherein the value of the opcode is the value of the opcode indicating that the operation is to request an address translation entry, and the value of the status code can be determined according to the position of the requested address translation entry in the cache line. For example, a cache line includes 7 address translation entries, and 7 bits are used to represent the status of the 7 address translation entries respectively. If the bus domain address to be converted corresponds to the third and fourth address translation entries, the status code can be set to 0011000 to indicate that the request is for the third and fourth address translation entries. The status code in the write request of this example is different from the status code in the cache line in terms of meaning and value. The multiple address translation entries in the address translation request can be directly read from the cache line where the requested address translation entry is located, and the bus domain address in the requested address translation entry is added to generate an address translation request (). The host physical address in the requested address translation entry needs to be filled in by the host.

[0084] In another example of this embodiment, the address translation request also includes an operation code, a status code, and multiple address translation entries, but the status code is the same as the status code in the cache line, which is used to indicate the state of each address translation entry in the multiple address translation entries (i.e., valid or invalid), rather than being used to indicate the position of the requested address translation entry in the multiple address translation entries. The host can find the address translation entry in the second memory line where the host physical address is missing, and determine it as the requested address translation entry. The status bit corresponding to the requested address translation entry in the status code can be set to a value indicating invalidity.

[0085] In an exemplary embodiment of the present disclosure, after receiving the notification of reading the address translation entry sent by the host, the cache agent reads the requested address translation entry supplemented by the host from the host memory and writes it into the ATC, including:

[0086] receiving a snoop request of the CXL.cache protocol sent by the host, wherein the snoop request carries the address of the second memory block;

[0087] Determine that the second memory block is mapped to a cache line in the ATC, and send a read request of the CXL.cache protocol to the host, carrying the address of the second memory block;

[0088] Receiving updated data in the second memory block returned by the host, and writing the received data into a cache line in the ATC to which the second memory block is mapped;

[0089] The data of the second memory block returned by the host includes an operation code, a status code and multiple address translation entries, the operation code indicates the operation of completing the address translation, the status code includes multiple status bits to indicate the status of each address translation entry in the multiple address translation entries, the multiple address translation entries include the requested address translation entry and the requested address translation entry includes the host physical address and the bus domain address.

[0090] After the CXL device writes the address translation request into the memory block of the host memory, the host completes the host physical address in the requested address translation entry, and then can notify the CXL device to read the requested address translation entry. In this embodiment, this notification is implemented based on the snoop request of the CXL.cache protocol, and the snoop request carries the address of the second memory block. In one example, the snoop request can use the snoop request with the operation code SnpInv. SnpInv is used to notify the CXL device that the address translation entry in the Cacheline has expired, triggering the CXL device to initiate a cacheline re-read operation; when the cache agent of the CXL device determines that the second memory block is mapped to the cache line of the ATC, it identifies it as a notification of reading data, and thus sends a read request of the CXL.cache protocol to the host to read the data in the second memory block. There are also multiple types of read requests of the CXL.cache protocol, such as RdCurr, RdOWn, RdShared and RdAny. Taking RdOwn as an example, the cache agent sends an RdOwn request carrying the address of the second memory block; the host can return GO-E and the data in the second memory block. The embodiment of the present disclosure uses the read request defined in the CXL.cache protocol, but the present disclosure is not limited thereto, and a newly defined read request from the CXL device to the host may also be used.

[0091] In an exemplary embodiment of the present disclosure, the cache agent is further configured to: interact with the host based on the CXL.io protocol, obtain address information of a memory block allocated by the host to the device for storing address translation entries, and establish a mapping relationship between the address of the cache line in the ATC and the address of the memory block in the host memory for storing address translation entries of the device.

[0092] The establishment of the mapping relationship in this embodiment can be started after accessing the host and completed before requesting the address translation entry. The address information of the memory block used to store the address translation entry can be the first address and quantity information of multiple consecutive memory blocks. The CXL device allocates the same number of consecutive cache lines in the cache as ATC. The mapping relationship established in this embodiment can be the mapping relationship between the first address of the cache line in the ATC and the first address of the memory block used to store the address translation entry. After the mapping relationship is established, the mapping relationship between the cache line in the ATC and the memory block storing the address translation entry of the device in the host memory can be determined.

[0093] In an exemplary embodiment of the present disclosure, the cache proxy is further configured to: interact with the host based on the CXL.io protocol to determine at least one of the following parameters:

[0094] The granularity of address translation, that is, the size of the continuous host physical address space corresponding to an address translation entry;

[0095] The format of the address, such as a 32-bit address or a 64-bit address;

[0096] The data structure information of the cache line in the ATC includes at least one of the number of bits of the operation code, the number of bits of the status code, and the number of address translation entries.

[0097] The cache agent of the CXL device interacts with the host based on the CXL.io protocol to determine the above parameters, and can also be started after accessing the host and completed before requesting the address translation entry. Not every bus domain address and host physical address must use an address translation entry, and multiple consecutive bus domain addresses and multiple consecutive host physical addresses can use one address translation entry. For example, for a 32-bit bus domain address and a 32-bit host physical address, only the upper 30 bits of the bus domain address and the upper 30 bits of the host physical address can be retained in the address translation entry. At this time, when converting a 32-bit bus domain address to a 32-bit host physical address, the first 30 bits of the 32-bit host physical address can be obtained by searching the address translation entry, and the last 2 bits of the 32-bit host physical address can copy the last 2 bits of the 32-bit bus domain address.

[0098] In the above embodiments of the present disclosure, ATS is implemented by using the CXL protocol in the CXL architecture, and the consistency of the address translation entries in the cache memory can be maintained, and the device can actively initiate the invalidation operation of the cached address translation entries. In actual application scenarios, the CXL device is more aware of which address translation entries should be cached. The CXL device can actively initiate the invalidation of the address translation entries stored in the ATC and the host memory based on the access requirements for the host physical address, thereby releasing the corresponding resources more timely and effectively.

[0099] An embodiment of the present disclosure further provides a host. As shown in FIG1 , the host 2 includes a host agent 21 and a host memory 22. The host agent 21 is configured as follows:

[0100] Interacting with the CXL device based on the CXL protocol, sending the address translation entry of the CXL device stored in the host memory to the CXL device to be stored in the address translation cache ATC of the CXL device; and

[0101] Interacting with the CXL device based on the CXL protocol to maintain consistency between the address translation entries stored in the host memory and the ATC includes: receiving an invalidation instruction sent by the CXL device to invalidate part or all of the address translation entries of the CXL device.

[0102] In an exemplary embodiment of the present disclosure, the address translation entry is stored in a memory block of the host memory and a cache line of the ATC, each memory block in the host memory is mapped to each cache line in the ATC, and the cache lines and memory blocks having a mapping relationship share data;

[0103] The data stored in the memory block mapped to the cache line in the ATC includes:

[0104] An operation code, used to indicate an operation to be performed, wherein the operation includes an invalidation operation on an address translation entry;

[0105] A status code, used to indicate the status of each address translation entry stored in the memory block;

[0106] A plurality of address translation entries, wherein each address translation entry includes a host physical address and a bus domain address.

[0107] In this embodiment, cache lines and memory blocks with a mapping relationship share data, and it is necessary to maintain the consistency of the data in the cache lines and memory blocks with a mapping relationship. For example, when an address translation entry in a cache line is invalid, the address translation entry in the memory block to which the cache line is mapped also needs to be invalidated.

[0108] In an exemplary embodiment of the present disclosure, the host agent receives an invalidation instruction sent by the CXL device to invalidate part or all of the address translation entries of the CXL device, including:

[0109] receiving an invalidation instruction of the CXL.io protocol or the CXL.cache protocol sent by the CXL device, wherein the invalidation instruction carries an operation field and an address of a memory block, wherein the operation indicated by the operation field is an invalidation operation initiated by the device end, and the memory block is used to store the part or all of the address translation entries;

[0110] The invalidation instruction is parsed to set the address translation entry stored in the memory block to be invalid.

[0111] This embodiment corresponds to an invalidation instruction sent by the CXL device to the host when all address translation entries stored in the cache line are invalid, and the invalidation instruction is an embodiment of an extension of the CXL.io protocol or the CXL.cache protocol. In this embodiment, the host agent needs to decode the invalidation instruction to perform an invalidation operation to set the address translation entry stored in the memory block address to invalid. The invalidation operation can be to update the status code in the memory block, or to set the memory block to invalid through other marks.

[0112] In an exemplary embodiment of the present disclosure, the host agent receives an invalidation instruction sent by the CXL device to invalidate part or all of the address translation entries of the CXL device, including:

[0113] receiving a write request of the CXL.cache protocol sent by the CXL device, wherein the write request carries an address of a memory block;

[0114] When determining that the memory block is used to store the address translation entry of the CXL device, returning a write permission response to the CXL device;

[0115] An invalidation instruction sent by the CXL device as data to be written is received, and the invalidation instruction is written into the memory block for storing the part or all of the address translation entries.

[0116] Among them, the invalidation instruction includes an operation code, a status code and multiple address conversion entries, the operation indicated by the operation code is an invalidation operation initiated by the device side, and the status code includes multiple status bits to indicate whether the status of each address conversion entry in the multiple address conversion entries is valid or invalid.

[0117] In this embodiment, the CXL device writes the invalidation instruction as data directly into the memory block for storing address conversion entries in the host memory by sending a write data process. After receiving the write request, the host agent searches for the memory block address range allocated to the CXL device for storing address conversion entries according to the memory block address carried by the write request, and can determine that the memory block is used to store the address conversion entries of the CXL device, and then returns a response allowing writing to the CXL device. After the data is written to the memory block, the host parses the written data and determines that the invalidation operation of the address conversion entry initiated by the device is executed this time. For the address conversion entry with an invalid status, the host can release the storage space occupied by it as needed (such as when the memory occupancy reaches a threshold). In this process, the host does not need to decode the write request to execute the operation of updating the status code in the memory block, and the instruction processing is simpler.

[0118] In an exemplary embodiment of the present disclosure, the host agent interacts with the CXL device based on the CXL protocol to maintain consistency between the address translation entries stored in the host memory and the ATC, including:

[0119] Sending an invalidation request to the CXL device, the invalidation request carrying an operation field, a status field, and an address of a first memory block, wherein the operation indicated by the operation field is an invalidation operation initiated by the host, and the status field is used to indicate to the CXL device an address translation entry that needs to be invalidated, wherein the address translation entry that needs to be invalidated is stored in the first memory block;

[0120] A response returned by the CXL device is received.

[0121] This embodiment is a host-initiated invalidation process, and this embodiment extends the H2D Request defined in the CXL.cache protocol to support the host-initiated invalidation of address translation entries. Before initiating the invalidation process, or after receiving a response from the CXL device indicating that the invalidation is completed, the host updates the status code in the first memory block to set the address translation entry to be invalidated to be invalid.

[0122] In an exemplary embodiment of the present disclosure, the host agent interacts with the CXL device based on the CXL protocol to maintain consistency between the address translation entries stored in the host memory and the ATC, including:

[0123] Sending a snoop request to the CXL device, the snoop request carrying an address of a first memory block, the first memory block storing an address translation entry to be invalidated and mapped to a first cache line in an ATC of the CXL device;

[0124] receiving a read request of the CXL.cache protocol sent by the CXL device, wherein the read request carries the address of the first memory block;

[0125] The data stored in the first memory block is sent to the CXL device; the data includes an operation code, a status code and a plurality of address translation entries, the operation code indicates an invalidation operation initiated by the host, and the status code includes a plurality of status bits to indicate whether the status of each of the plurality of address translation entries is valid or invalid.

[0126] This embodiment is also an invalidation process initiated by the host. The host first updates the status code in the memory block where the address translation entry to be invalidated is located to indicate that the status of the address translation entry to be invalidated is invalid, and then triggers the CXL device based on the snoop request to read the data containing the invalidation information from the first memory block and write it into the first cache line.

[0127] In an exemplary embodiment of the present disclosure, the host agent interacts with the CXL device based on the CXL protocol, and sends the address translation entry of the CXL device stored in the host memory to the CXL device, including:

[0128] receiving an address translation request sent by the CXL device based on a CXL.cache protocol, wherein the address translation request carries a bus domain address in a requested address translation entry;

[0129] Complete the requested address translation entry, and notify the CXL device to read the address translation entry based on the CXL.cache protocol;

[0130] A read request sent by the CXL device based on the CXL.cache protocol is received, and the supplemented address translation entry is sent to the CXL device for storage.

[0131] In an embodiment with a CXL device cache agent as the execution subject, the cache agent sends an address translation request to the host based on the CXL.cache protocol, carrying the bus domain address in the requested address translation entry, and after receiving the notification of reading the address translation entry sent by the host, reads the address translation entry supplemented by the host from the host memory and writes it into the ATC. This embodiment is the processing flow of the host in the address translation request process.

[0132] In an example of this embodiment, the host agent receives the address translation request sent by the CXL device based on the CXL.cache protocol, including:

[0133] receiving a write request of the CXL.cache protocol sent by the CXL device, wherein the write request carries an address of a second memory block in the host memory;

[0134] When determining that the second memory block is used to store the address translation entry of the CXL device, returning a write permission response to the CXL device;

[0135] receiving an address translation request sent by the CXL device as data requested to be written, and writing the address translation request into the second memory block;

[0136] The address translation request includes an operation code, a status code and multiple address translation entries; the operation indicated by the operation code is to request an address translation entry, the status code is used to indicate the position of the requested address translation entry in the multiple address translation entries or to indicate the status of each address translation entry in the multiple address translation entries, the multiple address translation entries include the requested address translation entry, and the requested address translation entry only includes the bus domain address to be converted.

[0137] In this example, when the CXL device is connected, the host agent can allocate an address range for storing address translation entries to the CXL device. After receiving the write request sent by the CXL device, it can be determined whether the second memory block is used to store the address translation entries of the CXL device according to the address of the second memory block carried by the write request. If so, a response allowing writing is fed back. In one example, the status code is used to indicate the position of the requested address translation entry in the multiple address translation entries. After the host agent needs to write the address translation request to the second memory block, it needs to update the status code in the second memory block according to whether the address translation entry in the second memory block includes a valid host physical address and a bus domain address. In another example, the status code is used to indicate the status of each address translation entry in the multiple address translation entries. The host agent can find the address translation entry whose host physical address is missing in the second memory row and determine it as the requested address translation entry.

[0138] In an example of this embodiment, the host agent completes the requested address translation entry, and notifies the CXL device to read the address translation entry based on the CXL.cache protocol, including:

[0139] Perform the following operations on the data in the second memory block: add the host physical address to the address translation entry of the request, update the status code to indicate whether the status of each of the multiple address translation entries is valid or invalid, and change the operation indicated by the operation code to return the address translation entry;

[0140] Sending a snoop request to the CXL device, wherein the snoop request carries the address of the second memory block;

[0141] In this example, when the host agent updates the status code, the address translation entry of the request has been completed, its status can be set to valid, and the status of other address translation entries in the second memory block can remain unchanged.

[0142] In an example of this embodiment, the host agent receives a read request sent by the CXL device based on the CXL.cache protocol, and sends the supplemented address translation entry to the CXL device for storage, including:

[0143] receiving a read request of the CXL.cache protocol sent by the CXL device, wherein the read request carries the address of the second memory block;

[0144] The updated data in the second memory block is sent to the CXL device, and stored in a second cache line of the ATC by the CXL device.

[0145] In an example of this embodiment, after the host agent detects that a CXL device is connected, the address translation entry of the CXL device may not be generated, nor stored in the ATPT. After receiving the address translation request of the CXL device, the host agent generates the address translation entry requested by the CXL device according to a predetermined rule. This processing method can reduce the host memory occupied by the address translation entry. The memory block mapped to the cache line in the ATC in the embodiment of the present disclosure stores the address translation entry of the CXL device, which can be used to implement the function of ATPT without the need to establish ATPT separately.

[0146] In an exemplary embodiment of the present disclosure, the host agent is further configured to:

[0147] Interacting with the CXL device host based on the CXL.io protocol, obtaining address information of the cache line in the ATC, establishing a mapping relationship between the cache line in the ATC and the memory block in the host memory; and determining at least one of the following parameters:

[0148] The granularity of address translation, that is, the size of the continuous host physical address space corresponding to an address translation entry;

[0149] The format of the address, such as 32-bit address or 64-bit address;

[0150] The data structure information of the cache line in the ATC includes at least one of the number of bits of the operation code, the number of bits of the status code, and the number of address translation entries.

[0151] An embodiment of the present disclosure also provides a method for achieving memory cache consistency, which is applied to a CXL device, such as Figure 3 As shown, including:

[0152] Step 110, interacting with the host based on the CXL protocol, obtaining the address translation entry of the device stored in the host memory, and caching the address translation entry in the ATC; and

[0153] Step 120, interacting with the host based on the CXL protocol to maintain consistency between the ATC and the address translation entries stored in the host memory, including: sending an invalidation instruction to the host to invalidate some or all of the address translation entries of the device stored in the host memory.

[0154] In an exemplary embodiment of the present disclosure, the address translation entry is stored in a cache line of the ATC and a memory block of the host memory, each cache line in the ATC is mapped to a memory block in the host memory, and the cache line and the memory block having a mapping relationship share data; wherein the data stored in a cache line in the ATC includes:

[0155] An operation code, used to indicate an operation to be performed, wherein the operation includes an invalidation operation on an address translation entry;

[0156] A status code, used to indicate the status of each address translation entry stored in the cache line;

[0157] A plurality of address translation entries, wherein each address translation entry includes a host physical address and a bus domain address;

[0158] The cache agent sends an invalidation instruction to the host to invalidate some or all of the address translation entries of the device stored in the host memory, including: when determining that some or all of the address translation entries in the ATC are invalid, setting the some or all of the address translation entries in the ATC to invalid, and sending an invalidation instruction to the host based on the CXL protocol to invalidate some or all of the address translation entries stored in the host memory.

[0159] In an exemplary embodiment of the present disclosure, sending an invalidation instruction to the host based on the CXL.cache protocol includes:

[0160] When it is determined that all address translation entries stored in one or more cache lines are invalid, an invalidation instruction is sent to the host based on the CXL.io protocol or the CXL.cache protocol, carrying an operation field and a memory block address; wherein the operation indicated by the operation field is an invalidation operation initiated by the device end, and the memory block address is the address of the memory block to which the cache line is mapped; or

[0161] When it is determined that some or all of the address translation entries stored in the cache line of the ATC are invalid, a write request of the CXL.cache protocol is sent to the host, carrying the address of the memory block to which the cache line is mapped; and, after receiving a response allowing write returned by the host, the invalidation instruction is sent to the host to write to the memory block to which the cache line is mapped; wherein the invalidation instruction includes an operation code, a status code and multiple address translation entries stored in the cache line, the operation indicated by the operation code is an invalidation operation initiated by the device end, and the status code includes multiple status bits to indicate whether the status of each address translation entry in the multiple address translation entries is valid or invalid.

[0162] An embodiment of the present disclosure also provides a method for achieving memory cache consistency, which is applied to a host, such as Figure 4 As shown, including:

[0163] Step 210, interacting with the CXL device based on the CXL protocol, sending the address translation entry of the CXL device stored in the host memory to the CXL device, so as to be stored in the address translation cache ATC of the CXL device; and

[0164] Step 220 , interacting with the CXL device based on the CXL protocol to maintain consistency between the address translation entries stored in the host memory and the ATC, including: receiving an invalidation instruction sent by the CXL device to invalidate some or all of the address translation entries of the CXL device.

[0165] In an exemplary embodiment of the present disclosure, the address translation entry is stored in a memory block of a host memory and a cache line of an ATC, each memory block in the host memory is mapped to each cache line in the ATC, and the cache line and memory block having a mapping relationship share data; wherein the data stored in the memory block mapped to the cache line in the ATC includes:

[0166] An operation code, used to indicate an operation to be performed, wherein the operation includes an invalidation operation on an address translation entry;

[0167] A status code, used to indicate the status of each address translation entry stored in the memory block;

[0168] A plurality of address translation entries, wherein each address translation entry includes a host physical address and a bus domain address.

[0169] In an exemplary embodiment of the present disclosure, the receiving an invalidation instruction sent by the CXL device to invalidate some or all address translation entries of the CXL device includes:

[0170] receiving an invalidation instruction of the CXL.io protocol or the CXL.cache protocol sent by the CXL device, the invalidation instruction carrying an operation field and an address of a memory block, wherein the operation indicated by the operation field is an invalidation operation initiated by the device end, and the memory block is used to store some or all of the address translation entries; and parsing the invalidation instruction to set the address translation entries stored in the memory block to be invalid; or

[0171] receiving a write request of the CXL.cache protocol sent by the CXL device, the write request carrying the address of a memory block for storing the part or all of the address translation entries; returning a response allowing the write to the CXL device when determining that the memory block is mapped to a cache line in the ATC of the CXL device; and receiving an invalidation instruction sent by the CXL device as data to be written, and writing the invalidation instruction into the memory block for storing the part or all of the address translation entries; wherein the invalidation instruction includes an operation code, a status code and a plurality of address translation entries, the operation indicated by the operation code is an invalidation operation initiated by the device end, and the status code includes a plurality of status bits to indicate whether the status of each of the plurality of address translation entries is valid or invalid.

[0172] The present disclosure also provides a non-transitory computer storage medium storing a computer program. When the computer program is executed by a processor, the method for achieving memory cache consistency described in any embodiment of the present disclosure can be implemented.

[0173] The system composed of a host and a CXL device according to an embodiment of the present disclosure is as follows: Figure 5 As shown, the host 100 includes a host CPU 101, a host memory 102, and a coherent and memory logic 103. The host memory 102 may be a local DDR, and a portion of the host memory 102 is used to store address translation entries of the CXL device. This portion of the region includes multiple memory blocks, which may be referred to as ATPT. The home agent may be implemented by the coherent and memory logic 103. The CXL device of this embodiment takes an accelerator 200 as an example. The accelerator 200 is a second type (Type 2) CXL device, including a device cache 201 and a processor 202. A portion of the region in the device cache 201 is used as an address translation cache (ATC), and the cache agent may be implemented by the processor 202. Although only one CXL device is shown in the figure, the host may allow multiple CXL devices to access, and the address translation entries stored in the ATCs of the multiple CXL devices may be mapped to different regions of the ATPT in the host memory.

[0174] Although Figure 5 The example is to implement the host agent based on consistency and storage logic, but in other examples, the host agent of the embodiment of the present disclosure can also be implemented based on the host CPU or other hardware. Similarly, the cache agent of the embodiment of the present disclosure can be implemented based on the processor of the CXL device or based on other hardware.

[0175] Host Agent and Cache Agent are concepts introduced in the CXL architecture. In this application, Host Agent and Cache Agent are not limited to sending and receiving CXL.cache related protocol commands. The host-side functional module used to maintain the consistency of address translation entries stored in the host memory and the device cache can be called a host agent, and the device-side functional module used to maintain the consistency of address translation entries stored in the host memory and the device cache can be called a cache agent. In some embodiments of the present disclosure, Host Agent and Cache Agent can also send and receive CXL.io related protocol commands to maintain consistency.

[0176] In the PCIe architecture, the TA function can implement the mapping of bus addresses to CPU physical memory addresses and the physical address isolation protection between multiple devices. In the scenario of large-block data transmission between the host and the CXL device, for example, data is transmitted between the CXL device and the host through DMA, and multiple memory accesses of DMA require frequent access to the host memory to complete address conversion, which is inefficient. The Host Agent and Cache Agent of this embodiment can be compatible with the TA function in the PCIe architecture based on the CXL protocol, provide address conversion services, and improve the efficiency of Device access to the system main memory.

[0177] In the CXL architecture, there is no specific provision on how to maintain the memory cache consistency between the CXL device and the host. In one example of this embodiment, the Host Agent and the Cache Agent can maintain the memory cache consistency between the CXL device and the host based on the CXL.io protocol, forming a mapping from the host-side ATPT to the device-side ATC, i.e., a shared address translation entry. In another example of this embodiment, the Host Agent and the Cache Agent can maintain the consistency of the address translation entries shared by the ATC of the CXL device and the host memory based on the CXL.cache protocol.

[0178] The address translation entries of CXL devices can be changed dynamically; for example, the host physical address used to store the address translation entry may be invalidated because the physical page is swapped out (swapped to disk space). When the new physical page is mapped again, a new address translation entry needs to be established. In the case where the host or other system software modifies the address translation entry of the CXL device, the modified address translation result is directly written to the ATPT, and the host agent can reflect the modification to the ATC of the device through the consistency protocol of CXL, that is, the corresponding address translation entry in the ATC is invalidated. In other scenarios, as the initiator of ATS and DMA, the CXL device knows the host physical address range that needs to be accessed better than the host. Therefore, compared with the PCIe architecture, this embodiment adds an invalidation operation initiated by the CXL device. When the cache agent of the CXL device determines that the address translation entry is invalid, the address translation entry in the ATC can be set to invalid, and the process of invalidating the address translation entry is initiated to the host, and the corresponding address translation entry of the host memory is invalidated, thereby improving the utilization of the host memory and the device cache.

[0179] In this embodiment, in order to implement ATS and maintain consistency, before address translation occurs, the host may predefine or interact with the CXL device to determine the following:

[0180] Address information of a memory block in the host memory used to store address translation entries, such as a range of host physical addresses that can be used to store address translation entries, which address range can be regarded as an address range of ATPT;

[0181] How to dynamically divide the storage area of ​​address translation entries for connected CXL devices, that is, split ATPT into a corresponding number of independent memory areas according to the number of CXL devices, and notify the corresponding CXL devices of the address information of these memory areas (such as the first address) to establish a mapping between ATC and the corresponding memory areas of ATPT;

[0182] The size and data structure of the memory block. The size of the memory block is the same as the size of the cacheline, such as 64 bytes. ATPT stores address translation entries in units of physical pages (pages), and the page size is 8 bytes. Each memory block includes 8 physical pages and can store 7 address translation entries. The remaining bytes can be used as operation codes and status codes, or reserved.

[0183] In CXL.cache, D2H Request includes a write operation request from the device to the host in units of cacheline (such as WOWrInv: partial cacheline can be written). This embodiment can use the write operation from the device to the host to complete the invalidation of the address translation entry initiated by the device.

[0184] Before performing address conversion, the CXL device can allocate ATC and notify the host of the ATC address information. The size and data structure of the cache line: predefine or interact with the CXL device to determine the address format, the granularity of address conversion, and the data structure of the cache line. The interaction of these configuration information can be completed based on the CXL.io protocol.

[0185] In an example of the disclosed embodiment, the CXL device and the host implement the device-initiated invalidation process through the following steps: Figure 6 As shown, including:

[0186] Step 310, the cache agent determines that some or all of the address translation entries in the ATC are invalid if it determines that the host physical addresses in some or all of the address translation entries will not be accessed within a predetermined time based on the service characteristics;

[0187] Step 320: the cache agent sends a write request of the CXL.cache protocol to the host agent, carrying the address of the memory block for storing the part or all of the address translation entries;

[0188] Step 330, the host agent receives the CXL.cache protocol write request sent by the cache agent, and when determining that the memory block is mapped to a cache line in the ATC of the CXL device, returns a write-permitted response to the cache agent;

[0189] Step 340, after receiving the write-permitted response returned by the host agent, the cache agent sends the invalidation instruction as the data requested to be written to the host agent;

[0190] The above-mentioned invalidation instruction includes an operation code, a status code and multiple address translation entries stored in the cache line, the operation indicated by the operation code is an invalidation operation initiated by the device side, and the status code includes multiple status bits to indicate whether the status of each address translation entry in the multiple address translation entries is valid or invalid.

[0191] Step 350 : The host agent receives the invalidation instruction sent by the CXL device as data to be written, and writes the invalidation instruction into the memory block for storing the part or all of the address translation entries.

[0192] In an example of the embodiment of the present disclosure, when the CXL device needs to obtain an address translation entry through the ATS, it can interact with the host and implement it through the following steps: Figure 6 As shown, including:

[0193] Step 410: The cache agent sends a write request of the CXL.cache protocol to the host agent, carrying the address of a second memory block in the host memory, where the second memory block is a memory block for storing the requested address translation entry;

[0194] In this step, the cache agent can trigger the CXL.cache Write transaction through the Cache protocol layer.

[0195] Step 420: the host agent receives the CXL.cache protocol write request sent by the cache agent, and returns a write permission response to the cache agent when determining that the second memory block is used to store the address translation entry of the CXL device;

[0196] Step 430, after receiving the write-permitted response returned by the host agent, the cache agent sends the address translation request as data requested to be written to the host agent;

[0197] The address translation request of this example includes an operation code, a status code and multiple address translation entries; the operation indicated by the operation code is to request an address translation entry, the status code is used to indicate the position of the requested address translation entry in the multiple address translation entries or to indicate the status of each address translation entry in the multiple address translation entries, the multiple address translation entries include the requested address translation entry, and the requested address translation entry only includes the bus domain address to be converted.

[0198] Step 440, the host agent receives the address translation request sent by the cache agent as data requested to be written, and writes the address translation request into the second memory block;

[0199] Step 450, the host agent performs the following operations on the data in the second memory block to complete the requested address translation entry: adding the host physical address to the requested address translation entry, updating the status code to indicate whether the status of each of the multiple address translation entries is valid or invalid, and changing the operation indicated by the operation code to return the address translation entry;

[0200] Step 460: the host agent sends a snoop request of the CXL.cache protocol to the cache agent, wherein the snoop request carries the address of the second memory block;

[0201] In this step, a Host to Device Request is triggered from the CXL.cache layer, and the operation code may be SnpInv to notify the Device that the Cacheline has been invalidated, triggering the device to initiate a Cacheline re-read operation.

[0202] Step 470, the cache agent receives the snoop request sent by the host agent, determines that the second memory block is mapped to the cache line in the ATC, and sends a read request of the CXL.cache protocol to the host agent, carrying the address of the second memory block;

[0203] Before sending a read request, the cache proxy can return a response RspSHitSE or RspIHitSe to the Host, indicating that the current cacheline is in the Invalid state or the shared state.

[0204] Step 480 , the host agent receives the CXL.cache protocol read request sent by the cache agent, and sends the updated data in the second memory block to the cache agent;

[0205] The updated data in the second memory block includes an operation code, a status code and multiple address translation entries, wherein the operation indicated by the operation code is to complete the address translation, the status code includes multiple status bits to indicate the status of each address translation entry in the multiple address translation entries, the multiple address translation entries include the requested address translation entry and the requested address translation entry includes a host physical address and a bus domain address.

[0206] Step 490: The cache agent receives the updated data in the second memory block returned by the host agent, and writes the data into the cache line in the ATC to which the second memory block is mapped, thereby completing the ATS.

[0207] In an example of the disclosed embodiment, the CXL device and the host implement the host-initiated invalidation process through the following steps: Figure 8 As shown, including:

[0208] Step 510: The host agent sends a snoop request to the cache agent, carrying the address of a first memory block, where the first memory block stores an address translation entry that needs to be invalidated and is mapped to a first cache line in the ATC of the CXL device;

[0209] In one example, the snoop request sent by the host agent to the cache agent is a Host to Device Request sent by the host, and the operation code is SnpInv. In this embodiment, it is used to indicate that the host is about to set the corresponding address translation entry to be invalid.

[0210] Step 520, the cache agent receives and parses the snoop request sent by the host agent, and when determining that the first memory block is mapped to the first cache line in the ATC, sends a read request of the CXL.cache protocol to the host agent, carrying the address of the first memory block;

[0211] When the cache agent receives a Host to Device Request with an opcode of SnpInv, it can send a RspIHitSe response to the host agent, and then the host agent sends a read request of the CXL.cache protocol.

[0212] Step 530 , the host agent receives the CXL.cache protocol read request sent by the cache agent, and sends the data stored in the first memory block to the cache agent to be written into the first cache line in the ATC of the CXL device;

[0213] The data stored in the first memory block includes an operation code, a status code and multiple address translation entries, the operation code indicates an invalidation operation initiated by the host, and the status code includes multiple status bits to indicate whether the status of each address translation entry in the multiple address translation entries is valid or invalid.

[0214] Step 540: The cache agent receives the data stored in the first memory block returned by the host agent, and writes the received data into the first cache line.

[0215] The CXL device and the host interact to implement the TA function, and the specific implementation of maintaining the consistency of ATC and APTP by invalidation can also use the methods in the aforementioned CXL device embodiment and the host embodiment, which will not be repeated here.

[0216] Those skilled in the art will appreciate that the functional modules / units in all or some steps, systems, and devices disclosed in the above method can be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. A CXL device, comprising an address translation cache ATC and a cache agent, It is characterized in that The caching proxy is configured to: Interacting with the host based on the CXL protocol, obtaining the address translation entry of the device stored in the host memory, and caching the address translation entry in the ATC; and Interacting with the host based on the CXL protocol to maintain consistency between the address translation entries stored in the ATC and the host memory, including: sending an invalidation instruction to the host to invalidate part or all of the address translation entries of the device stored in the host memory.

2. The CXL device according to claim 1, Features: The cache agent sends an invalidation instruction to the host to invalidate some or all of the address translation entries of the device stored in the host memory, including: when determining that some or all of the address translation entries in the ATC are invalid, setting the some or all of the address translation entries in the ATC to invalid, and sending an invalidation instruction to the host based on the CXL protocol to invalidate some or all of the address translation entries stored in the host memory.

3. The CXL device according to claim 2, Features: The address translation entries are stored in the cache lines of the ATC and the memory blocks of the host memory. Each cache line in the ATC is mapped to a memory block in the host memory. The cache lines and memory blocks having a mapping relationship share data. The data stored in a cache line in the ATC includes: An operation code, used to indicate an operation to be performed, wherein the operation includes an invalidation operation on an address translation entry; A status code, used to indicate the status of each address translation entry stored in the cache line; A plurality of address translation entries, wherein each address translation entry includes a host physical address and a bus domain address.

4. The CXL device according to claim 2, Features: The cache agent sends an invalidation instruction to the host based on the CXL protocol, including: when it is determined that all address translation entries stored in one or more cache lines are invalid, sending an invalidation instruction to the host based on the CXL.io protocol or the CXL.cache protocol, carrying an operation field and a memory block address; wherein the operation indicated by the operation field is an invalidation operation initiated by the device side, and the memory block address is the address of the memory block to which the cache line is mapped.

5. The CXL device according to claim 3, Features: The cache agent sends an invalidation instruction to the host based on the CXL protocol, including: When determining that some or all of the address translation entries stored in the cache line of the ATC are invalid, sending a write request of the CXL.cache protocol to the host, carrying the address of the memory block to which the cache line is mapped; After receiving a write-permitted response returned by the host, sending the invalidation instruction to the host to write into the memory block to which the cache line is mapped; Among them, the invalidation instruction includes an operation code, a status code and multiple address translation entries stored in the cache line, the operation indicated by the operation code is an invalidation operation initiated by the device side, and the status code includes multiple status bits to indicate whether the status of each address translation entry in the multiple address translation entries is valid or invalid.

6. The CXL device according to claim 2, Features: The cache agent determines that one or more address translation entries in the ATC are invalid, including: based on business characteristics, determining that the host physical addresses in some or all of the address translation entries in the ATC will not be accessed within a predetermined time, and determining that the some or all of the address translation entries are invalid.

7. The CXL device according to claim 3, Features: The cache agent interacts with the host based on the CXL.cache protocol to maintain consistency between the address translation entries stored in the ATC and the host memory, including: receiving and parsing an invalidation request sent by the host, the invalidation request carrying an operation field, a status field and an address of the first memory block, the operation indicated by the operation field being an invalidation operation initiated by the host, and the status field being used to indicate an address translation entry that needs to be invalidated; When determining that the first memory block is mapped to a first cache line in the ATC, updating a status code in the first cache line according to the status field to change the status of the address translation entry to be invalidated in the first cache line to invalid; A response is sent to the host, indicating completion of invalidation of the address translation entry.

8. The CXL device according to claim 3, Features: The cache agent interacts with the host based on the CXL.cache protocol to maintain consistency between the address translation entries stored in the ATC and the host memory, including: Receiving and parsing a snoop request sent by the host, the snoop request carrying an address of a first memory block, the first memory block storing an address translation entry that needs to be invalidated; When determining that the first memory block is mapped to the first cache line in the ATC, sending a read request of the CXL.cache protocol to the host, carrying the address of the first memory block; Receive data stored in the first memory block returned by the host, and write the received data into the first cache line, wherein the data includes an operation code, a status code and multiple address translation entries, wherein the operation indicated by the operation code is an invalidation operation initiated by the host, and the status code includes multiple status bits to indicate whether the status of each of the multiple address translation entries is valid or invalid.

9. The CXL device according to claim 3, Features: The cache agent interacts with the host based on the CXL protocol, obtains the address translation entry of the device stored in the host memory, and caches the address translation entry in the ATC, including: Sending an address translation request to the host based on the CXL.cache protocol, carrying the bus domain address in the requested address translation entry; After receiving the notification of reading the address translation entry sent by the host based on the CXL.cache protocol, the address translation entry of the request completed by the host is read from the host memory and written into the ATC.

10. The CXL device according to claim 9, Features: The cache agent sends an address translation request to the host based on the CXL.cache protocol, including: Sending a write request of the CXL.cache protocol to the host, carrying an address of a second memory block in the host memory, where the second memory block is a memory block for storing the requested address translation entry; After receiving a write-permitted response from the host, sending the address conversion request as write-requested data to the host, so as to be written into the second memory block; The address translation request includes an operation code, a status code and multiple address translation entries; the operation indicated by the operation code is to request an address translation entry, the status code is used to indicate the position of the requested address translation entry in the multiple address translation entries or to indicate the status of each address translation entry in the multiple address translation entries, the multiple address translation entries include the requested address translation entry, and the requested address translation entry only includes the bus domain address to be converted.

11. The CXL device according to claim 10, Features: After receiving the notification of reading the address translation entry sent by the host, the cache agent reads the requested address translation entry supplemented by the host from the host memory and writes it into the ATC, including: receiving a snoop request of the CXL.cache protocol sent by the host, wherein the snoop request carries the address of the second memory block; Determine that the second memory block is mapped to a cache line in the ATC, and send a read request of the CXL.cache protocol to the host, carrying the address of the second memory block; Receiving updated data in the second memory block returned by the host, and writing the received data into a cache line in the ATC to which the second memory block is mapped; Among them, the data of the second memory block returned by the host includes an operation code, a status code and multiple address translation entries, the operation code indicates the operation of completing the address translation, the status code includes multiple status bits to indicate the status of each address translation entry in the multiple address translation entries, the multiple address translation entries include the requested address translation entry and the requested address translation entry includes the host physical address and the bus domain address.

12. The CXL device of claim 3, Features: The cache agent is also configured to: interact with the host based on the CXL.io protocol, obtain address information of the memory block allocated by the host to the device for storing address translation entries, and establish a mapping relationship between the address of the cache line in the ATC and the address of the memory block in the host memory for storing the address translation entries of the device.

13. The CXL device of claim 12, Features: The cache proxy is further configured to interact with the host based on the CXL.io protocol to determine at least one of the following parameters: The granularity of address translation, that is, the size of the continuous host physical address space corresponding to an address translation entry; The format of the address; The data structure information of the cache line in the ATC includes at least one of the number of bits of the operation code, the number of bits of the status code, and the number of address translation entries.

14. A host, comprising a host agent and a host memory, It is characterized in that The host agent is configured as: interacting with the CXL device based on the CXL protocol, and sending the address translation entry of the CXL device stored in the host memory to the CXL device to be stored in the address translation cache ATC of the CXL device; and Interacting with the CXL device based on the CXL protocol to maintain consistency between the address translation entries stored in the host memory and the ATC includes: receiving an invalidation instruction sent by the CXL device to invalidate part or all of the address translation entries of the CXL device.

15. The host according to claim 14, Features: The address translation entries are stored in the memory blocks of the host memory and the cache lines of the ATC, each memory block in the host memory is mapped to each cache line in the ATC, and the cache lines and memory blocks having a mapping relationship share data; The data stored in the memory block mapped to the cache line in the ATC includes: An operation code, used to indicate an operation to be performed, wherein the operation includes an invalidation operation on an address translation entry; A status code, used to indicate the status of each address translation entry stored in the memory block; A plurality of address translation entries, wherein each address translation entry includes a host physical address and a bus domain address.

16. The host according to claim 15, Features: The host agent receives the invalidation instruction sent by the CXL device to invalidate part or all of the address translation entries of the CXL device, including: receiving an invalidation instruction of the CXL.io protocol or the CXL.cache protocol sent by the CXL device, wherein the invalidation instruction carries an operation field and an address of a memory block, wherein the operation indicated by the operation field is an invalidation operation initiated by the device end, and the memory block is used to store the part or all of the address translation entries; The invalidation instruction is parsed to set the address translation entry stored in the memory block to be invalid.

17. The host according to claim 15, Features: The host agent receives the invalidation instruction sent by the CXL device to invalidate part or all of the address translation entries of the CXL device, including: receiving a write request of the CXL.cache protocol sent by the CXL device, wherein the write request carries an address of a memory block for storing the part or all of the address translation entries; If it is determined that the memory block is mapped to a cache line in the ATC of the CXL device, returning a write permission response to the CXL device; receiving an invalidation instruction sent by the CXL device as data to be written, and writing the invalidation instruction into the memory block for storing the part or all of the address translation entries; Among them, the invalidation instruction includes an operation code, a status code and multiple address conversion entries, the operation indicated by the operation code is an invalidation operation initiated by the device side, and the status code includes multiple status bits to indicate whether the status of each address conversion entry in the multiple address conversion entries is valid or invalid.

18. The host according to claim 15, Features: The host agent interacts with the CXL device based on the CXL protocol to maintain consistency of the address translation entries stored in the host memory and the ATC, including: Sending a snoop request to the CXL device, the snoop request carrying an address of a first memory block, the first memory block storing an address translation entry to be invalidated and mapped to a first cache line in an ATC of the CXL device; receiving a read request of the CXL.cache protocol sent by the CXL device, wherein the read request carries the address of the first memory block; Writing the data stored in the first memory block into a first cache line in the ATC of the CXL device; wherein the data includes an operation code, a status code, and a plurality of address translation entries, the operation indicated by the operation code is an invalidation operation initiated by a host, and the status code includes a plurality of status bits to indicate whether the status of each of the plurality of address translation entries is valid or invalid.

19. The host according to claim 15, Features: The host agent interacts with the CXL device based on the CXL protocol, and sends the address translation entry of the CXL device stored in the host memory to the CXL device, including: receiving an address translation request sent by the CXL device based on a CXL.cache protocol, wherein the address translation request carries a bus domain address in a requested address translation entry; Complete the requested address translation entry, and notify the CXL device to read the address translation entry based on the CXL.cache protocol; A read request sent by the CXL device based on the CXL.cache protocol is received, and the supplemented address translation entry is sent to the CXL device for storage.

20. The host according to claim 19, Features: The host agent receives the address translation request sent by the CXL device based on the CXL.cache protocol, including: receiving a write request of the CXL.cache protocol sent by the CXL device, wherein the write request carries an address of a second memory block in the host memory; When determining that the second memory block is used to store the address translation entry of the CXL device, returning a write permission response to the CXL device; receiving an address translation request sent by the CXL device as data requested to be written, and writing the address translation request into the second memory block; The address translation request includes an operation code, a status code and multiple address translation entries; the operation indicated by the operation code is to request an address translation entry, the status code is used to indicate the position of the requested address translation entry in the multiple address translation entries or to indicate the status of each address translation entry in the multiple address translation entries, the multiple address translation entries include the requested address translation entry, and the requested address translation entry only includes the bus domain address to be converted.

21. The host according to claim 20, Features: The host agent completes the requested address translation entry and notifies the CXL device to read the address translation entry based on the CXL.cache protocol, including: Perform the following operations on the data in the second memory block: add the host physical address to the address translation entry of the request, update the status code to indicate whether the status of each of the multiple address translation entries is valid or invalid, and change the operation indicated by the operation code to return the address translation entry; Sending a snoop request to the CXL device, wherein the snoop request carries the address of the second memory block; The host agent receives the read request sent by the CXL device based on the CXL.cache protocol, and sends the supplemented address translation entry to the CXL device for storage, including: receiving a read request of the CXL.cache protocol sent by the CXL device, wherein the read request carries the address of the second memory block; The updated data in the second memory block is sent to the CXL device, and stored in a second cache line of the ATC by the CXL device.

22. The host according to claim 14, Features: The host agent is also configured to: Interacting with the CXL device host based on the CXL.io protocol, obtaining address information of the cache line in the ATC, and establishing a mapping relationship between the cache line in the ATC and the memory block in the host memory; And, determine at least one of the following parameters: The granularity of address translation, that is, the size of the continuous host physical address space corresponding to an address translation entry; The format of the address; The data structure information of the cache line in the ATC includes at least one of the number of bits of the operation code, the number of bits of the status code, and the number of address translation entries.

23. A method for achieving memory cache consistency, applied to CXL devices, include: Interacting with the host based on the CXL protocol, obtaining the address translation entry of the device stored in the host memory, and caching the address translation entry in the ATC; and The CXL protocol is used to interact with the host to maintain the consistency of the address translation entries stored in the ATC and the host memory, including: sending an invalidation instruction to the host to request invalidation of part or all of the address translation entries of the device stored in the host memory.

24. The method of claim 23, Features: The address translation entries are stored in the cache lines of the ATC and the memory blocks of the host memory. Each cache line in the ATC is mapped to a memory block in the host memory. The cache lines and memory blocks having a mapping relationship share data. The data stored in a cache line in the ATC includes: An operation code, used to indicate an operation to be performed, wherein the operation includes an invalidation operation on an address translation entry; A status code, used to indicate the status of each address translation entry stored in the cache line; A plurality of address translation entries, wherein each address translation entry includes a host physical address and a bus domain address; The cache agent sends an invalidation instruction to the host, requesting to invalidate some or all address translation entries of the device stored in the host memory, including: when determining that some or all address translation entries in the ATC are invalid, sending an invalidation instruction to the host based on the CXL.cache protocol to invalidate some or all address translation entries stored in the host memory.

25. The method of claim 24, Features: The sending of an invalidation instruction to the host based on the CXL.cache protocol to request invalidation of some or all of the address translation entries stored in the host memory includes: Sending a write request of the CXL.cache protocol to the host, carrying the address of the memory block storing the part or all of the address translation entries; After receiving the write-permitted response returned by the host, the invalidation instruction is written as the data requested to be written into the memory block storing the part or all of the address translation entries; wherein the invalidation instruction includes information of invalidating the address translation entry; The invalidation instruction includes an operation code and a status code, the operation indicated by the operation code is an invalidation operation initiated by the device side, and the status code indicates that all address translation entries are invalid; or, the invalidation instruction includes an operation code, a status code and multiple address translation entries, the operation indicated by the operation code is an invalidation operation initiated by the device side, and the status code includes multiple status bits to indicate whether the status of each address translation entry in the multiple address translation entries is valid or invalid.

26. A method for achieving memory cache consistency, applied to a host, include: interacting with the CXL device based on the CXL protocol, and sending the address translation entry of the CXL device stored in the host memory to the CXL device to be stored in the address translation cache ATC of the CXL device; and Interacting with the CXL device based on the CXL protocol to maintain consistency between the address translation entries stored in the host memory and the ATC includes: receiving an invalidation instruction sent by the CXL device to invalidate part or all of the address translation entries of the CXL device.

27. The method of claim 26, Features: The address translation entries are stored in the memory blocks of the host memory and the cache lines of the ATC, each memory block in the host memory is mapped to each cache line in the ATC, and the cache lines and memory blocks having a mapping relationship share data; The data stored in the memory block mapped to the cache line in the ATC includes: An operation code, used to indicate an operation to be performed, wherein the operation includes an invalidation operation on an address translation entry; A status code, used to indicate the status of each address translation entry stored in the memory block; A plurality of address translation entries, wherein each address translation entry includes a host physical address and a bus domain address.

28. The method of claim 27, Features: The receiving the invalidation instruction sent by the CXL device to invalidate some or all of the address translation entries of the CXL device includes: receiving a write request of the CXL.cache protocol sent by the CXL device, wherein the write request carries an address of a memory block for storing the part or all of the address translation entries; Returning a write permission response to the CXL device; An invalidation instruction sent by the CXL device as data to be written is received, and the invalidation instruction is written into a memory block for storing the part or all of the address translation entries; wherein the invalidation instruction includes information of invalidating the address translation entry.

29. A non-transitory computer storage medium storing a computer program, It is characterized in that When the computer program is executed by a processor, the method according to any one of claims 23 to 28 can be implemented.

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