A Machine Learning-Based Method and System for Predicting Delays in the Logic Synthesis Stage

Abstract

This invention relates to a machine learning-based method and system for delay prediction in the logic synthesis stage, belonging to the field of digital integrated circuit design automation technology. Drawing inspiration from natural language processing, this invention analogizes a timing path to a sentence in a natural language processing task, with the basic elements constituting a sentence called a token. A timing path consists of multiple standard cells and nets connected together, and each token in a timing path contains information about both the standard cells and the nets. This invention first uses a graph attention network to predict the physical dimensions of the nets in the timing path, and then uses an LSTM-Attention network to capture the timing and physical dependencies of each part of the entire timing path. This invention accurately and efficiently feeds forward the timing performance after routing to the logic synthesis process to guide timing optimization and convergence in the logic synthesis stage, significantly reducing the number of iterations in chip design.

Description

Technical Field

[0001] This invention relates to a machine learning-based method and system for predicting delays in the logic synthesis stage, which is applied in the digital chip design process and belongs to the field of digital integrated circuit design automation technology. Background Technology

[0002] As chips become larger and more complex, chip design cycles lengthen. Utilizing machine learning techniques to achieve "unmanned" agile chip design flows is a key direction in chip design methodology. A primary challenge in achieving agile chip design is reducing the runtime of Electronic Design Automation (EDA) tools. Timing is a critical performance indicator for chips, and static timing analysis (STA) tools are called at each stage of the digital chip design flow to ensure that the current stage's design meets timing constraints. If a timing violation occurs in the current stage and cannot be corrected at that stage, it is necessary to backtrack to a previous stage and redesign. In traditional digital chip design flows, to achieve timing convergence, designers often need to perform repeated static timing analysis (STA) and multiple iterations between logic synthesis and place-and-route. Traditional logic synthesis tools use "lookup tables" to estimate latency, assuming that most latency in the timing path is related to logic gates and ignoring interconnect latency. However, in advanced processes, wire latency dominates the total path latency, making traditional design flows more expensive and unacceptable.

[0003] Accurate and efficient timing prediction can feed forward the timing performance of later design stages to earlier design stages, guiding timing convergence and optimization in early design, thereby significantly reducing chip design iterations. Existing machine learning-based timing prediction methods are mostly applied to the post-placement stage. For example, random forests or graph neural networks are used to predict net delays in the post-placement stage, and transformers are used to predict post-routing path delays. These methods are all done under the premise that the location coordinates of circuit cells or modules are known. In the logic synthesis stage before placement, designers cannot obtain the actual cell location information and the interconnection information between cells, which makes timing prediction in the logic synthesis stage more difficult. Existing machine learning-based timing prediction methods for the logic synthesis stage have the following drawbacks. First, methods used to predict whether a timing path is a critical path and methods used to predict the net length of the entire path or the total net length cannot provide the necessary timing information (timing length, slack) to guide circuit optimization in subsequent design stages. Secondly, timing predictions made at the level of a single net or cell instead of the path level can lead to error accumulation because they ignore the timing and physical dependencies along the path. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a machine learning-based path delay prediction method for the logic synthesis stage, used to predict the timing path delay after routing during the logic synthesis stage. This invention draws on concepts from Natural Language Processing (NLP), analogizing a timing path to a sentence in an NLP task, with the basic elements constituting a sentence called tokens. A timing path is composed of multiple standard units and wires connected together, and each "token" of a timing path contains information about both the standard units and the wires. This invention first uses a graph attention network to predict the physical dimensions of individual wires in the timing path, and then uses an LSTM-Attention network to capture the temporal and physical dependencies of each part of the entire timing path.

[0005] Terminology Explanation:

[0006] 1. Logic Synthesis: Logic synthesis is the process of transforming a higher level of abstraction in a circuit design into an optimized gate-level netlist.

[0007] 2. Static Timing Analysis (STA): STA is essentially a timing check, its purpose being to check whether all flip-flops in the design are functioning correctly. Static timing analysis includes setup time checks and hold time checks. Setup time checks ensure that the data signal arrives at the register a certain time before the register starts sampling; hold time checks ensure that the data signal remains valid for a certain period of time after the register starts sampling, preventing the register from missing signals.

[0008] 3. Natural Language Processing: Natural Language Processing (NLP) studies the theories and methods of computer text processing to achieve representational reasoning.

[0009] 4. Layout planning: Layout planning determines the overall structure of the chip, including the chip size, the location of input / output modules, and the location of hard macros (modules with fixed area and shape).

[0010] 5. Layout: The layout determines the position of all modules (mainly the position of standard units).

[0011] 6. CTS: CTS (Clock Tree Synthesis) is a technique where a clock tree is the physical implementation of a clock signal. Clock tree synthesis aims to generate a clock distribution network to ensure that all components on the chip receive clock signals at the same frequency.

[0012] 7. Routing: The purpose of routing is to find appropriate paths according to logical relationships to interconnect macro modules, standard cells and input / output interface units (I / O Pads) within the chip core.

[0013] 8. HPWL: HPWL stands for Half-perimeter Wirelength. This model first determines the maximum and minimum coordinates of all pins within a wirenet, thus obtaining a minimum rectangle containing all pins of the wirenet. Half the perimeter of this rectangle is the estimated wire length of the wirenet.

[0014] The technical solution of the present invention is as follows:

[0015] A machine learning-based method for predicting latency in the logic synthesis stage includes the following steps:

[0016] Step 1: For multiple chip designs, use electronic design automation (EDA) tools to perform logic synthesis, placement and routing, and timing analysis to obtain the corresponding netlists and timing reports;

[0017] Step 2: Use a C++ program to parse the netlists and timing reports before and after layout to obtain the net features and labels required for training the line length prediction model;

[0018] Step 3: Input the samples from Step 2, i.e., the line network features and corresponding labels, into the Graph Attention Network (GAT) for training to obtain the line length prediction model and prediction results;

[0019] Step 4: Use a C++ program to parse the timing report and netlist from the logic synthesis stage, obtain the features of each cell in each timing path, and combine the net-related features used to predict the line length in Step 2 with the predicted line length in Step 3 (i.e., the output of the prediction model in Step 3) to obtain the features of the entire timing path; that is, the features of the entire timing path include the cell-related information obtained from the timing report and netlist, as well as the net features used by the line length prediction model in Step 2 and the line length output by the prediction model in Step 3; parse the timing report after routing to obtain the corresponding timing path delay label;

[0020] Step 5: Analogize the temporal path to a sentence in a natural language processing task. The basic elements that make up a sentence are called tokens. A temporal path consists of multiple standard units and wires connected together. Each "token" that makes up a temporal path contains information about both the standard units and the wires. Each "token" is a vector with several features. Embed the entire temporal path into a low-dimensional vector.

[0021] Step 6: Input the features of the entire temporal path (processed in Steps 4 and 5) and the corresponding post-wiring temporal path delay labels into the LSTM-Attention network for training to obtain the path delay model. The model output is the prediction result.

[0022] Furthermore, in step 1, the commercial logic synthesis tool Cadence Genus and the commercial place-and-route tool Cadence Innovus are used to perform logic synthesis and place-and-route on the chip design, respectively; static timing analysis (STA) is performed on the netlists at each stage to obtain the corresponding timing reports; the timing reports mainly include the timing path and the timing and physical characteristics of each unit constituting the timing path.

[0023] Further, in step 2, the entire netlist is represented as a directed graph, where each net is a node and each cell is an edge. The selected net features include: the total area of ​​cells in the entire netlist, the area of ​​the cells connected to the net's input, the area of ​​all cells connected to the net, the fan-in size, the fan-out size, the sum and standard deviation of the fan-in and fan-out values ​​of 2-hop neighbors, and the sum of the cell type encoding values ​​connected to the net. All selected net features of each node constitute the feature vector of that node. The label is the HPWL value of the net after layout.

[0024] Furthermore, in step 3, the graph attention network is used to automatically learn the importance of each neighbor node. To better reflect the structural information of the graph, this invention only focuses on the attention coefficients of each node and its 1-hop neighbor nodes. The initial input of the graph attention network is a combination of feature vectors of each node, and the number of attention heads is set to 2. The graph attention network includes three graph attention layers and two fully connected layers. After the initial input passes through the three graph attention layers h1, h2, and h3, the outputs of the first three layers are concatenated, instead of using only the output of the last layer as in most GNN-related works.

[0025] Furthermore, in step 4, the characteristics of the units on the selected timing path are: unit type, number of fan-out units, unit output load, and unit input transmission delay; these unit characteristics are also closely related to the timing path latency. The number of units constituting different timing path sequences in a circuit design is not unique. This invention selects the number of units in the timing path with the maximum number of units as the length of all timing path sequences; timing path sequences with fewer units than the maximum number of units are padded with zeros to reach the maximum number of units; the corresponding timing path latency labels can be extracted from the post-routing timing report. Based on the "start_point" and "end_point" of the timing path in the timing report, the timing path characteristics during the logic synthesis stage (i.e., the model input characteristics in step 6) and the post-routing timing path latency labels can be matched.

[0026] Further, in step 6, the sequence data representing the temporal path is input into the LSTM-Attention network. The circuit delay propagates step by step along the temporal path. The LSTM can calculate the dependencies of elements in the sequence step by step. Each level considers information such as the current input and the hidden state of the previous level. The output of the hidden state of the LSTM layer is the input of the attention layer. The role of the attention layer is to highlight key information. The LSTM-Attention network includes an input layer (X1, X2, X3, X4), LSTM layers (LSTM1, LSTM2, LSTM3, LSTM4), hidden states (h1, h2, h3, h4), attention layer, two fully connected layers, and output. The LSTM layer is used to process the sequence data and generate hidden states. Each hidden state corresponds to the output of a time step.

[0027] A terminal device includes a memory and a processor, the memory storing a computer program that, when executed by the processor, implements the steps in a machine learning-based logic synthesis stage delay prediction method as described above.

[0028] The beneficial effects of this invention are as follows:

[0029] This invention proposes a machine learning-based path delay prediction method for the logic synthesis stage. By feeding forward the timing performance after routing into the logic synthesis process, it guides timing optimization and convergence during the logic synthesis stage, significantly reducing the number of iterations in chip design. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the path embedding method used in this study.

[0031] Figure 2 This is a schematic diagram of the overall process of this method;

[0032] Figure 3 This is a schematic diagram of the graph attention network structure;

[0033] Figure 4 This is a schematic diagram of the LSTM-Attention network structure. Detailed Implementation

[0034] The present invention will be further described below with reference to the embodiments and accompanying drawings, but is not limited thereto.

[0035] Example 1:

[0036] Embodiments of the present invention provide a machine learning-based path delay prediction method for the logic synthesis stage, such as... Figure 2 As shown, this is used to predict timing path delays during the routing stage of chip design, specifically during the logic synthesis stage. The specific implementation steps are as follows:

[0037] Step 1: Detailed information on the circuit design used in the embodiments of the present invention is shown in Table 1.

[0038] Table 1 Circuit Design Details

[0039]

[0040] For multiple chip designs, call electronic design automation (EDA) tools to perform logic synthesis, placement and routing, and timing analysis processes to obtain the corresponding netlists and timing reports.

[0041] The RTL circuit design was synthesized and placed and routed using the commercial logic synthesis tool Cadence Genus and the commercial place-and-route tool Cadence Innovus, respectively. Static timing analysis (STA) was performed on the netlists at each stage to obtain the corresponding timing reports. The timing reports mainly include the timing path and the timing and physical characteristics of each unit that constitutes the timing path.

[0042] Step 2: Use a C++ program to parse the netlists and timing reports before and after layout to obtain the net features and labels required for training the line length prediction model.

[0043] The entire netlist is represented as a directed graph, where each net is a node and each cell is an edge. The selected net features include: the total area of ​​all cells in the netlist, the area of ​​the cells connected to the net's input, the area of ​​all cells connected to the net, the fan-in size, the fan-out size, the sum and standard deviation of the fan-in and fan-out values ​​of the 2-hop neighbors, and the sum of the cell type codes connected to the net. All the selected net features of each node constitute the feature vector of that node. The label is the HPWL value of the net after placement.

[0044] Step 3: Input the samples from Step 2, i.e., the line network features and corresponding labels, into the Graph Attention Network (GAT) for training to obtain the line length prediction model and prediction results.

[0045] Graph attention networks are used to automatically learn the importance of each neighbor node. To better reflect the structural information of the graph, this invention only focuses on the attention coefficients of each node and its 1-hop neighbors. The initial input of the graph attention network is a combination of feature vectors of each node, and the number of attention heads is set to 2. The graph attention network includes three graph attention layers and two fully connected layers, as shown in the schematic diagram below. Figure 3 As shown, after the initial input passes through three graph attention layers h1, h2, and h3, the outputs of the first three layers are concatenated, instead of using only the output of the last layer as is done in most GNN-related works.

[0046] Step 4: Use a C++ program to parse the timing report and netlist from the logic synthesis stage, obtain the features of each cell in each timing path, and combine the net-related features used to predict the line length in Step 2 with the line length predicted in Step 3 (i.e., the output of the prediction model in Step 3) to obtain the features of the entire timing path; that is, the features of the entire timing path include the cell-related information obtained from the timing report and netlist, as well as the net features used by the line length prediction model in Step 2 and the line length output by the prediction model in Step 3; parse the timing report after routing to obtain the corresponding timing path delay label.

[0047] The characteristics of the units on the selected timing path are: unit type, number of fan-out units, unit output load, and unit input transmission delay; these unit characteristics are also closely related to the timing path latency. The number of units constituting different timing path sequences in a circuit design is not unique. This invention selects the number of units in the timing path with the maximum number of units as the length of all timing path sequences; timing path sequences with fewer units than the maximum number of units are padded with zeros to reach the maximum number of units; the corresponding timing path latency labels can be extracted from the post-routing timing report. Based on the "start_point" and "end_point" of the timing path in the timing report, the timing path characteristics in the logic synthesis stage (i.e., the model input characteristics in step 6) and the post-routing timing path latency labels can be matched.

[0048] Step 5: Analogize a temporal path to a sentence in a natural language processing task. The basic elements that make up a sentence are called tokens. A temporal path consists of multiple standard units and interconnected networks. Each token in a temporal path contains information from both the standard units and the networks. Each token is a vector with several features. Embed the entire temporal path into a low-dimensional vector. A schematic diagram of the path embedding is shown below. Figure 1 As shown. In Figure 1 In this context, dff, and2, not, or2, xor2, nand2, and nor2 represent standard units.

[0049] Step 6: Input the features of the entire temporal path (processed in Steps 4 and 5) and the corresponding post-wiring temporal path delay labels into the LSTM-Attention network for training to obtain the path delay model. The model output is the prediction result.

[0050] Sequence data representing a temporal path is input into the LSTM-Attention network. The circuit delay propagates step-by-step along the temporal path. The LSTM can calculate the dependencies between elements in the sequence step by step, considering information such as the current input and the hidden state of the previous level at each level. The output of the hidden state of the LSTM layer is the input of the attention layer, which highlights key information. The LSTM-Attention network consists of an input layer (X1, X2, X3, X4), LSTM layers (LSTM1, LSTM2, LSTM3, LSTM4), hidden states (h1, h2, h3, h4), an attention layer, two fully connected layers, and an output. The LSTM layers process the sequence data and generate hidden states, with each hidden state corresponding to the output at a time step. The structure is as follows: Figure 4 As shown.

[0051] Example 2

[0052] A terminal device includes a memory and a processor. The memory stores a computer program that, when executed by the processor, implements the steps in a machine learning-based logic synthesis stage delay prediction method as described in Embodiment 1.

[0053] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0054] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. A machine learning-based method for predicting delays in the logic synthesis stage, characterized in that, The steps include the following: Step 1: For multiple chip designs, use electronic design automation tools to perform logic synthesis, placement and routing, and timing analysis to obtain the corresponding netlists and timing reports; Step 2: Use a C++ program to parse the netlists and timing reports before and after layout to obtain the net features and labels required for training the line length prediction model; Step 3: Input the samples from Step 2, i.e., the line network features and corresponding labels, into the graph attention network for training to obtain the line length prediction model and prediction results; Step 4: Use a C++ program to parse the timing report and netlist from the logic synthesis stage, obtain the characteristics of each cell in each timing path, and combine them with the net features used to predict the line length in Step 2 and the predicted line length in Step 3 to obtain the characteristics of the entire timing path; that is, the characteristics of the entire timing path include the cell-related information obtained from the timing report and netlist, as well as the net features used by the line length prediction model in Step 2 and the line length output by the prediction model in Step 3; parse the timing report after routing to obtain the corresponding timing path delay label; Step 5: Analogize the temporal path to a sentence in a natural language processing task. The basic elements that make up a sentence are called tokens. A temporal path consists of multiple standard units and wires connected together. Each token that makes up a temporal path contains information about both the standard units and the wires. Each token is a vector with several features. Embed the entire temporal path into a low-dimensional vector. Step 6: Input the features of the entire temporal path (processed in Steps 4 and 5) and the corresponding post-wiring temporal path delay labels into the LSTM-Attention network for training to obtain the path delay model. The model output is the prediction result.

2. The machine learning-based delay prediction method for logic synthesis stage according to claim 1, characterized in that, In step 1, the logic synthesis tool Cadence Genus and the place-and-route tool Cadence Innovus are used to perform logic synthesis and place-and-route on the chip design, respectively. Static timing analysis is performed on the netlists at each stage to obtain corresponding timing reports. The timing reports include the timing path and the timing and physical characteristics of each unit that constitutes the timing path.

3. The machine learning-based delay prediction method for logic synthesis stage according to claim 1, characterized in that, In step 2, the entire netlist is represented as a directed graph, where each net is a node and each cell is an edge. The selected net features include: the total area of ​​cells in the entire netlist, the area of ​​cells connected to the net's input, the area of ​​all cells connected to the net, the fan-in size, the fan-out size, the sum and standard deviation of the fan-in and fan-out values ​​of 2-hop neighbors, and the sum of the cell type encoding values ​​connected to the net. All selected net features of each node constitute the feature vector of that node. The label is the HPWL value of the net after layout.

4. The machine learning-based delay prediction method for logic synthesis stage according to claim 1, characterized in that, In step 3, the graph attention network is used to automatically learn the importance of each neighbor node; it only focuses on the attention coefficients of each node and its 1-hop neighbor nodes; the initial input of the graph attention network is the combination of feature vectors of each node, and the number of attention heads is set to 2; the graph attention network includes three graph attention layers and two fully connected layers.

5. The machine learning-based delay prediction method for logic synthesis stage according to claim 1, characterized in that, In step 4, the characteristics of the cells on the selected timing path are: cell type, number of cell fan-outs, cell output load, and cell input transmission delay. The number of cells in the timing path with the maximum number of cells is selected as the sequence length of all timing paths. Timing path sequences with fewer cells than the maximum number of cells are padded with zeros to make the sequence length reach the maximum number of cells. The corresponding timing path delay label is extracted from the timing report after routing. The timing path characteristics in the logic synthesis stage and the timing path delay label after routing are matched according to the "start_point" and "end_point" of the timing path in the timing report.

6. The machine learning-based delay prediction method for logic synthesis stage according to claim 1, characterized in that, In step 6, the sequence data representing the temporal path is input into the LSTM-Attention network. The circuit delay propagates step by step along the temporal path. The LSTM calculates the dependencies of elements in the sequence step by step, and each level considers the current input and the hidden state information of the previous level. The output of the hidden state of the LSTM layer is the input of the attention layer, and the role of the attention layer is to highlight key information. The LSTM-Attention network includes an input layer (X1,X2,X3,X4), LSTM layers (LSTM1,LSTM2,LSTM3,LSTM4), hidden states (h1,h2,h3,h4), attention layer, two fully connected layers, and output. The LSTM layer is used to process the sequence data and generate hidden states, and each hidden state corresponds to the output of a time step.

7. A terminal device, comprising a memory and a processor, wherein the memory stores a computer program that, when executed by the processor, implements the steps of a machine learning-based logic synthesis stage delay prediction method as described in any one of claims 1-6.

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