A method for repairing and improving power electromigration introduced by a power switching unit

Abstract

This invention belongs to the field of integrated circuit design, and specifically relates to a method for repairing and improving power electromigration (EM) introduced by power switching units in integrated circuits. The power layout above the power switching unit is arranged as follows: one or more VDD power lines are arranged on layers M3 and M5; on the vertical metal layers of M3 and M5, one or more gated power vertical VDD_gated nets are distributed on both sides of the normally open power supply VDD as the center; VSS wirings are arranged near each VDD_gated net; a horizontal VDD_gated net is arranged on layer M2, and the horizontal VDD_gated net of layer M2 and the vertical VDD_gated net of layer M3 are connected through via V23. This invention directly improves the EM phenomenon above the power switching unit, prevents this type of EM violation from the power layout perspective, and also improves the robustness of the power supply, making the overall power network more robust.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, and specifically relates to a method for repairing and improving power electromigration introduced by power switching units in integrated circuits. Background Technology

[0002] When electrons move within a metallic conductor, they collide with metal atoms, causing these collisions to move—a phenomenon known as atom displacement. Over time, a significant amount of metal atoms move along the interconnect, leading to localized accumulation or loss of metal atoms. Macroscopically, this manifests as deformation and breakage of the interconnect. The loss of a large number of metal atoms creates an open circuit at the point of loss; conversely, the lost atoms accumulate at other locations on the interconnect, widening or deforming it. If these accumulations come into contact with other interconnects, a short circuit will form. This phenomenon, caused by electron migration leading to atomic displacement and the resulting series of phenomena, is called electromigration.

[0003] Electromigration, or EM phenomenon, occurs as long as a chip is in use. Clearly, the deformation of the metal interconnects caused by EM is irreversible. Therefore, the longer a chip is used, the more EM accumulates, the more severe the metal deformation becomes, and the greater the likelihood of open circuits or short circuits in the metal interconnects. When the accumulated EM effect is sufficient to eventually lead to open circuits and short circuits in the metal interconnects, the chip fails. Therefore, the EM phenomenon is deeply related to the chip's lifespan and stability; this is why, theoretically, the lifespan of a chip is finite.

[0004] Based on the different carriers in which electromigration occurs, it is divided into two types: PEM and SEM. Electromigration occurring on PG (Power & Ground) interconnects is called PEM, while electromigration occurring on signal lines is called SEM.

[0005] Low power consumption is a crucial performance objective for digital chips, and the pursuit of low power consumption is endless. Power Shut-Off (PSO) technology is one such low-power technology. This technology reduces power consumption by shutting off the power supply voltage to a region or submodule within the chip that is not currently needed. One of the special standard units required for PSO technology is the power switch cell. The power switch cell receives a normally open voltage as input and outputs a shutdown control voltage. Due to the large current output of the power switch cell, the resulting power electromigration (PEM) phenomenon is exceptionally pronounced, easily leading to EM violations. Therefore, the power supply structure or strategy above the power switch cell is extremely important. An inadequate power supply structure easily results in a large number of PEM violations, making subsequent repairs difficult and inefficient.

[0006] Existing solutions for EM violations mainly involve widening the violation net to increase the maximum current density carrying capacity and inserting buffer units to reduce the actual current density on the violation net. Then, the repair is automated by using a program to improve repair efficiency and reduce the workload of manual repair. These solutions primarily focus on addressing SEM problems on the signal net.

[0007] While these common industry-standard methods for improving and repairing EM violations can theoretically improve and repair them, the EM violations on the lower-level metal M2 layer caused by the high current characteristics of power switching units are numerous and difficult to repair. In the later stages of physical implementation, script-based repair is not feasible, and manual repair is extremely difficult. Even if forced repair is attempted, the efficiency is extremely low, severely impacting project progress. Secondly, manual repair cannot quickly reproduce the violations. If, due to unforeseen circumstances, the physical implementation is redone, all EM repair actions must be repeated, which is undoubtedly tedious and inefficient. Ultimately, individual repair is necessary, typically requiring several iterations to completely resolve the issues, further extending the design cycle. Summary of the Invention

[0008] To address the problems existing in the prior art, this invention proposes a method for repairing and improving power electromigration introduced by power switching units. It primarily solves the power electromigration violation problem caused by the introduction of power switching units in low-power physical implementations, and improves the power electromigration phenomenon on the lower metal layer above the power switching unit. This invention is applicable to repairing PEM problems above the power switching unit.

[0009] Technical solution

[0010] A method for repairing and improving power electromigration introduced by a power switching unit employs the following arrangement of the power supply layout above the power switching unit:

[0011] The power supply VDD wiring consists of one or more wires, arranged on layers M3 and M5;

[0012] VSS wiring is arranged near each VDD_gated wiring to form a VDD_gated and VSS power supply pair, so that the voltage network is evenly distributed.

[0013] On the vertical metal layers of M3 and M5, one or more gated power vertical VDD_gated nets are distributed on the left and right sides with the normally open power supply VDD as the center.

[0014] The horizontal VDD_gated net is arranged in layer M2, and the horizontal VDD_gated net of layer M2 and the vertical VDD_gated net of layer M3 are connected through via V23;

[0015] The output current is output from the horizontal M2 above the center of the power switch unit to the left and right sides respectively;

[0016] For the power network layout, where power switching units are present, follow the above scheme. Where power switching units are absent, follow the conventional layout.

[0017] Furthermore, the power supply layout implementation process described above is as follows:

[0018] Step 1: First, locate all power switch units by unit type;

[0019] Step 2: Then, based on the physical location of the switching unit, the power supply layout is carried out according to the power supply structure of the power switching unit proposed in this invention.

[0020] Step 3: After completing the layout of all power switch units, based on the physical location of the switch units, install route blockages above all switch units to prevent subsequent tools from laying cables in these areas.

[0021] Step 4: Then, for the remaining area, perform power layout at the same intervals for the regular power pairs (VDD_gated, VSS).

[0022] Step 5: After powering on all areas, remove all wiring obstacles to avoid affecting subsequent signal layout and wiring.

[0023] Beneficial effects

[0024] The proposed solution for repairing and improving EM violations also targets current density. Its advantage lies in changing the power supply structure above the power switching unit. This structural change achieves current shunting, rapidly reducing current density and significantly improving the EM phenomenon on the voltage net. By altering the power supply structure, the EM phenomenon on the lower metal layer M2 above all power switching units is directly improved. This prevents such EM violations from the power supply layout perspective. After layout and routing are completed, no corresponding EM violations exist, greatly reducing the ECO burden in the later stages of design and accelerating the design cycle. Furthermore, this power supply structure also improves the robustness of the power supply, making the overall power network more robust. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of a conventional PG layout for a power switch unit;

[0026] Figure 2 This is a schematic diagram illustrating the overall principle of the repair method according to an embodiment of the present invention;

[0027] Figure 3 This is a schematic diagram of the power input / output pin layout of the M1 layer power switch cell in an embodiment of the present invention;

[0028] Figure 4 This is a schematic diagram of the power supply layout M1, VIA12, and M2 above the power switch unit in an embodiment of the present invention;

[0029] Figure 5 This is a schematic diagram of the power supply layout M2, VIA23, and M3 above the power switch unit in an embodiment of the present invention;

[0030] Figure 6 This is a schematic diagram of the power supply layout M3 above the power switch unit in an embodiment of the present invention;

[0031] Figure 7 This is a schematic diagram of the power supply layout M3, VIA34, and M4 above the power switch unit in an embodiment of the present invention;

[0032] Figure 8 This is a schematic diagram of the power supply layout M4, VIA45, and M5 above the power switch unit in an embodiment of the present invention;

[0033] Figure 9 This is a schematic diagram of the power supply layout M5 above the power switch unit in an embodiment of the present invention;

[0034] Figure 10 This is a schematic diagram of the power supply layout process of the present invention. Detailed Implementation

[0035] The technical solutions provided in this application will be further described below with reference to specific embodiments and accompanying drawings. The advantages and features of this application will become clearer from the following description.

[0036] In the physical implementation of ICs, multiple metal layers are often required. To distinguish between different metal layers, M is used. n VIA represents the nth layer of the metal. n,n+1 This represents a via connecting the nth and n+1th metal layers. For example, M1 represents the first metal layer, M2 represents the second metal layer, VIA23 represents the via connecting metal M2 and metal M3, and so on. A conventional power supply structure works by connecting the PG pins of the top and bottom units layer by layer through vias. Starting from the third layer, the winding directions of adjacent metal layers are crisscrossed, meaning the winding direction of odd-numbered layers is primarily vertical, and the winding direction of even-numbered layers is primarily horizontal. The layout of the power supply structure generally involves evenly distributing each of the upper and middle metal layers across the entire design area, with adjacent layers forming a crisscrossing power network. The lower and middle layers are connected via short power lines or direct vias to the power tracks or pins of layers M2 and M1 (both M2 and M1 are horizontal). Therefore, the power supply structure is actually a network shape in three-dimensional space, hence it is also called a power network layout.

[0037] like Figure 1 The diagram shows a typical power network layout for a power switch cell. In low-power designs, the power switch cell controls the switching between the VDD power supply and the output power supply VDD_gated. The power network layout near the power switch cell has a significant impact on IREM (voltage drop, electromigration).

[0038] Considering the existing input power supply VDD pin location based on the power switch unit and the IREM of the normally open power supply VDD, the VDD power supply is positioned as high as possible above the VDD pin location. And next to it ( Figure 1 The output power supply VDD_gated is arranged in the middle (left side).

[0039] The input terminal of the power switch unit is connected to VDD. The connection between VDD_gated and the power switch unit is VDD_gatednet, which includes horizontal VDD_gatednet and vertical VDD_gatednet.

[0040] Specifically, the VDD is one or more wires arranged in layers M3 and M5;

[0041] The horizontal VDD_gated net is arranged in layer M2;

[0042] The vertical VDD_gated net consists of one or more vertically arranged in layers M3 and M5.

[0043] When the power switch unit is turned on, the output current flows to the output power supply VDD_gated via the VDD_gated net of layer M2. Because the output current of the power switch unit is large and originates from the narrow lower metal layer M2, a significant amount of output current flows along the VDD_gated net of layer M2 towards the higher VDD_gated power supply on the left. Therefore, this small segment of the VDD_gated net is prone to PEM violations, and even with a wide vertical VDD_gated net arrangement in M3 and M5, it is still difficult to mitigate these PEM violations.

[0044] For the above design scenario, this embodiment adopts the following processing method: (e.g.) Figure 2 )

[0045] The power supply layout above the power switch unit is arranged symmetrically, specifically:

[0046] The power supply VDD wiring consists of one or more wires, arranged on layers M3 and M5.

[0047] On the vertical metal layers of M3 and M5, one or more gated power vertical VDD_gated nets are distributed on the left and right sides with the normally open power supply VDD as the center.

[0048] VSS wiring is arranged near each VDD_gated wiring to form a VDD_gated and VSS power supply pair, so that the voltage network is evenly distributed.

[0049] The horizontal VDD_gated net is arranged in layer M2, and the horizontal VDD_gated net of layer M2 and the vertical VDD_gated net of layer M3 are connected through via V23.

[0050] The output current is output from the horizontal M2 above the center of the power switch unit to the left and right sides respectively.

[0051] For the power network layout, where power switching units are present, follow the above scheme. Where power switching units are absent, follow the conventional layout.

[0052] Furthermore, the VDD / vertical VDD_gated nets of the M3 and M5 layers are parallel and aligned; in the routing direction, vias V34 and V45 are added at intervals, and vias V34 and V45 are connected by a short horizontal M4 line.

[0053] Furthermore, the horizontal power lines above the power switch unit are widened: M2 uses twice the wire width, and M4 uses a shorter, wider wire. This widening is only done locally above the power switch unit to reduce the use of winding resources and decrease the probability of DRC violations.

[0054] In the non-power switch unit area, the low-level power interconnect M2 to the middle-level power M5 are directly connected through vias to reduce the use of wiring resources.

[0055] Furthermore, the wiring on layer M3 (including VSS, VDD, and VDD gated) uses a combination of wider power lines, with the combined width consistent with the width and coordinate position of layer M5 above.

[0056] The M3 layer is the main routing layer for signal cabling, and also a lower-level routing layer (with a smaller minimum line width allowed by the manufacturing process). Using multiple power lines in combination facilitates power supply disassembly. When signal cabling resources are scarce here, a few thin M3 lines (PG nets) can be appropriately cut. This solves the cabling resource shortage without significantly impacting IR and EM. This arrangement can reserve cabling resources for later ECO or for resolving DRC violations.

[0057] In summary, the power network layout near the chip's power switching unit is as follows: (e.g.) Figures 3-9 )

[0058] like Figure 3 The layout of the metal M1 layer is shown, including all pins of the power switch unit: the layout of the input power supply VDD pin, the output power supply VDD_gated pin, and the ground power supply VSS pin of the power switch unit. All output pins of the unit are located on the metal M1 layer.

[0059] like Figure 4 For M2 layout: M2 is the same as M1, with the main routing layer direction being horizontal. M1 and M2 are parallel to each other on the upper and lower layers, and are connected in the middle by numerous through-holes VIA12.

[0060] Starting from layer M3, the main routing directions of adjacent layers are alternating between vertical and horizontal.

[0061] The M2 and M3 layers of the power network above the power switch unit are as follows: Figure 5 As shown, the VDD_gated in the M2 layer uses a local width doubling (which does not introduce additional DRC violations) to increase the maximum current density carrying capacity; the current output by the power switch cell flows along the VDD_gated net of the M2 layer and simultaneously flows to the higher VDD_gated power supplies on the left and right sides, splitting the current in two to reduce the current density.

[0062] like Figure 6 As shown, the M3 layer features a wide array of multiple power supply lines, with the width and coordinates of the array consistent with the M5 layer above. The M3 layer is a primary routing layer for signal cabling and also a lower-level routing layer (with a smaller minimum line width allowed by the manufacturing process). Using multiple power supply lines facilitates power supply disassembly. When signal cabling resources are scarce here, a few thinner PG net lines in the M3 layer can be reduced. This resolves the cabling resource shortage without significantly impacting IR and EM, essentially reserving some cabling resources for later ECO operations or for resolving DRC violations.

[0063] like Figure 7 As shown, M4 uses a short horizontal line layout, and its width is increased to two or three times the line width. This reduces the use of M4 wiring resources while ensuring the robustness of the power supply structure above the power switch unit. M3 and M4 are connected as many times as possible via numerous VIA34 connectors.

[0064] like Figure 8 , Figure 9 As shown, a wider vertical PG power supply is arranged on the M5 layer to further enhance power supply interconnection. The width and coordinate position are consistent with the combined width of the PG net in the M3 layer below. The M5 layer is a middle routing layer. Compared with M3, the cost of signal lines is relatively reduced, and a single wider power PG can be used.

[0065] Since the reinforcement of the M3 and M5 power supplies (a wider power net combination or a wider power net) is only done above the power switch cell, and the total area of ​​the power switch cell only accounts for a small part of the total design area, the winding resources consumed by this PG reinforcement will not be too much.

[0066] By modifying the power supply PG structure to reduce current density, and strengthening the PGs of M2, M3, and M5 to increase the upper limit of allowable current density, Figure 1 The PEM improvements mentioned can produce immediate results.

[0067] The power supply layout implementation process is as follows:

[0068] Step 1: First, locate all power switch units by unit type;

[0069] Step 2: Then, based on the physical location of the switching unit, the power supply layout is carried out according to the power supply structure of the power switching unit proposed in this invention.

[0070] Step 3: After completing the layout of all power switch units, based on the physical location of the switch units, install route blockages above all switch units to prevent subsequent tools from laying cables in these areas.

[0071] Step 4: Then, for the remaining area, perform power layout at the same intervals for the regular power pairs (VDD_gated, VSS).

[0072] Step 5: After powering on all areas, remove all wiring obstacles to avoid affecting subsequent signal layout and wiring.

[0073] When implementing a physical version of a memory subsystem, using Figure 1 An IREM inspection and analysis of the power supply layout structure shown revealed a large number of power EM violations related to the gated power supply VDD_gated on the lower metal M2 above the power switch unit, with the worst violation reaching 200% (EM is measured as the percentage of actual current to maximum carrying current; less than or equal to 100% is considered satisfactory; greater than 100% is considered an over-limit violation, and the higher the percentage, the more serious the violation).

[0074] After adopting the solution described in this invention, the relevant power supply EM was reduced to less than 80%, which not only fixed all PEM violations, but also significantly improved the overall PEM of the PG network and enhanced the robustness of the power supply network.

[0075] The above description is merely a description of preferred embodiments of this application and is not intended to limit the scope of this application in any way. Any changes or modifications made by those skilled in the art based on the above-disclosed technical content should be considered as equivalent and valid embodiments and fall within the scope of protection of the technical solution of this application.

[0076] Appendix: Glossary of Terms

[0077]

Claims

1. A method for repairing and improving power electromigration introduced by a power switching unit, characterized in that, The power supply layout above the power switch unit is arranged as follows: The power supply VDD wiring consists of one or more wires, arranged on layers M3 and M5. On the vertical metal layers of M3 and M5, one or more gated power vertical VDD_gated nets are distributed on the left and right sides with the normally open power supply VDD as the center. VSS wiring is arranged near each VDD_gated wiring to form a VDD_gated and VSS power supply pair, so that the voltage network is evenly distributed. The horizontal VDD_gated net is arranged in layer M2, and the horizontal VDD_gated net of layer M2 and the vertical VDD_gated net of layer M3 are connected through via V23; The output current is output from the horizontal M2 above the center of the power switch unit to the left and right sides respectively; For the layout of the power network, where there are power switch units, the power layout shall be carried out according to the above scheme; where there are no power switch units, the conventional layout shall be followed.

2. The method for repairing and improving power electromigration introduced by a power switching unit as described in claim 1, characterized in that, The horizontal power lines above the power switch unit are widened: M2 uses double the line width, and M4 uses a short-width line; the widening is only done locally above the power switch unit.

3. The method for repairing and improving power electromigration introduced by a power switching unit as described in claim 2, characterized in that, In the non-power switch unit area, the low-level power interconnect M2 to the middle-level power M5 are directly connected through vias to reduce the use of wiring resources.

4. The method for repairing and improving power electromigration introduced by a power switching unit as described in claim 1, characterized in that, The wiring on layer M3 uses a combination of wide power lines, with the combined width and coordinate position consistent with the width of layer M5 above.

5. The method for repairing and improving power electromigration introduced by a power switching unit as described in claim 1, characterized in that, The VDD / vertical VDD_gated nets of the M3 and M5 layers are parallel and aligned; in the routing direction, vias V34 and V45 are added at intervals, and vias V34 and V45 are connected by a short horizontal M4 line.

6. A method for repairing and improving power electromigration introduced by a power switching unit as described in any one of claims 1-5, characterized in that, The power supply layout implementation process is as follows: Step 1: First, locate all power switch units by unit type; Step 2, then based on the physical location of the switching unit, according to any of claims 1-5 A power layout scheme is provided above the power switch unit as described above; Step 3: After completing the layout of all power switch units, based on the physical location of the switch units, install wiring obstacles above all switch units to prevent subsequent tools from wiring in these areas. Step 4: Then, for the remaining area, perform the power supply layout at the same intervals as usual. Step 5: After powering on all areas, remove all wiring obstacles to avoid affecting subsequent signal layout and wiring.

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