Single time programmable memory circuit based on magnetic tunnel junction

Abstract

The invention discloses a one-time programmable memory circuit based on a magnetic tunnel junction, which belongs to the field of integrated circuits and has two working modes: a normal read-write mode and a one-time programmable (OTP) mode. The memory unit is composed of a magnetic tunnel junction and three memory access transistors, and in a normal read-write mode, only one memory access transistor is opened; in a one-time programmable mode, the other two memory access transistors are opened to reduce partial voltage and increase programming current, and meanwhile, multi-bit parallel programming is realized and the write success rate is ensured through a peripheral self-termination write circuit. The circuit provided by the invention can reduce the programming voltage to 2.5 V in a single programmable mode, the self-termination writing circuit can save 5% of energy consumption in each bit writing, and 32-bit parallel programming can save 98% of programming time.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a single-time programmable memory circuit based on a magnetic tunnel junction. Background Art

[0002] With the vigorous development of computer and artificial intelligence fields, embedded applications are becoming more and more extensive, and product security is receiving more and more attention. On the one hand, it is necessary to store trimming information to ensure that the normal function of the product will not be affected by process fluctuations and errors. On the other hand, some product information needs to be highly confidential to ensure that the product will not be analyzed, simulated and copied. In order to achieve highly reliable storage to retain security information for a long time, manufacturers use technologies such as laser trimming, but some of these technologies are time-consuming and expensive, and some require data to be loaded from the outside each time. Many FLASH manufacturers provide a special register inside FLASH: a one-time programmable (OTP) register, which provides a new idea. OTP memory is a digital, non-volatile memory that only allows data to be written once in the memory structure. Before the OTP operation starts, all storage cells will be written to the same state. After the OTP operation starts, the state of the selected storage cell will be modified and this process is irreversible. Common OTP storage cells can be divided into three categories: fuse-type storage cells, anti-fuse-type storage cells, and non-volatile storage cells based on charge capture.

[0003] The main working unit of STT-MRAM is the magnetic tunnel junction (MTJ), which consists of a fixed layer and a free layer with magnetic properties, and a non-magnetic oxide isolation layer. The single-time programmable memory based on the magnetic tunnel junction is a short-circuit type storage unit similar to an anti-fuse, which utilizes the breakdown of the MTJ, also known as the electrical breakdown of the non-magnetic oxide isolation layer. To achieve this process, it is necessary to apply a high-intensity electric field to the insulating layer and pass a high-density current through the MTJ to achieve a microscopic short circuit and a sudden drop in resistance. Specifically, the breakdown first occurs at the defects on the interface between the fixed layer and the free layer. These defects will continuously capture charges. As these charges accumulate at the defects, the activation energy of the bonds inside the oxide isolation layer decreases, eventually leading to the breakdown of the oxide isolation layer and the MTJ short circuit. Summary of the invention

[0004] The present invention provides a single-time programmable memory circuit based on a magnetic tunnel junction, which can achieve highly reliable storage and retain security information for a long time, solving the technical problems of traditional solutions such as being time-consuming and expensive.

[0005] The embodiment of the present invention provides a single-time programmable memory circuit based on a magnetic tunnel junction, comprising: a read amplifier circuit, a write self-termination circuit, a dual-operation mode write circuit and a latch circuit;

[0006] The read amplifier circuit is used to amplify the voltage signal and read the storage data of the storage unit. The read amplifier circuit includes a read reference resistor and multiple storage units. The read reference resistor is used to output a reference signal during the read operation. The magnetic state in the storage unit is obtained by comparing the reference signal size with the signal size output by the memory in the same path. Each storage unit is composed of a magnetic tunnel junction and three NMOS tubes as memory access transistors. In the normal read-write mode, only one NMOS tube is turned on, and in the single-time programmable mode, three memory access transistors are turned on at the same time. The read amplifier circuit reads the storage information according to the resistance characteristics of the magnetic tunnel junction under different magnetization states;

[0007] The latch circuit and the read amplifier circuit are connected by leads and are used to detect the voltage difference change and save data after it stabilizes;

[0008] The dual working mode write circuit is used for performing normal writing and single programming OTP operation;

[0009] The write self-termination circuit is used to detect the voltage change on the bit line of the storage unit when the dual working mode write circuit completes writing or programming, and sends a write termination signal to the dual working mode write circuit after detecting the voltage change.

[0010] Optionally, in one embodiment of the present invention, the magnetic tunnel junction of the storage unit is composed of a fixed layer, a free layer and an oxide isolation layer composed of magnetic media; the magnetic moment direction of the fixed reference layer does not change; the magnetic moment direction of the free layer is the same as or opposite to that of the fixed layer, and the relative magnetization direction of the fixed layer and the free layer of the magnetic tunnel junction and whether the oxide isolation layer is broken down determine the state of the magnetic tunnel junction;

[0011] When the memory cell is used as a normal memory cell, the state of the magnetic tunnel junction is antiparallel AP or parallel P, and it can be written or read through the normal read-write mode; after the memory cell is programmed in the single-time programmable OTP mode, the state of the magnetic tunnel junction is antiparallel AP or breakdown state, and it can no longer be written subsequently, and can only be read through the normal read mode; when the direction of the free layer of the magnetic tunnel junction is parallel to the fixed layer, the magnetic resistance of the magnetic tunnel junction is low to R P ; When the magnetization direction of the free layer is antiparallel to the fixed layer, the magnetic resistance is high R AP ;When the oxide isolation layer of the magnetic tunnel junction is electrically broken down, the magnetic resistance can be ignored;

[0012] The memory cell access operation is controlled by the bit lines BL and BLB, the source lines SL and SLB, and the word lines WL and OTPWL.

[0013] Optionally, in one embodiment of the present invention, the read amplifier circuit includes two parts: a current-type sensitive amplifier CSA and a latch circuit. The current-type sensitive amplifier is composed of 4 PMOS tubes, 8 NMOS tubes and 2 capacitors; the gates of the 2 PMOS tubes are connected to the clamping voltage LOW to ensure that the data in the storage cell is not rewritten, and the gates of the 2 NMOS tubes are connected to the read enable signal READEN to control the operation of the read amplifier circuit. The 2 capacitors record the offset voltage in the pre-charging stage and eliminate the offset voltage in the amplification stage. In the amplification stage, the 2 NMOS tubes and the 2 PMOS tubes form a positive feedback circuit to amplify the voltage difference between the storage cell resistance and the read reference resistance, and output the data in the storage cell in the form of high and low levels at the leads SA1 and SA2 of the latch circuit and the read amplifier circuit. According to whether the storage cell has been programmed in the one-time programmable OTP mode, the reference resistance of the read amplifier circuit is selected through the OTPEN signal to achieve the maximum read margin.

[0014] Optionally, in one embodiment of the present invention, the latch circuit is composed of 5 PMOS tubes, 5 NMOS tubes and 1 inverter. The specific connection method is that the two input data of the read amplifier circuit pass through two transmission gates composed of 1 PMOS and 1 NMOS respectively, and the obtained results are connected to the two ends of a cross-coupled inverter composed of 3 PMOS tubes and 3 NMOS tubes, so that the voltages of the left and right nodes of the cross-coupled inverter remain stable.

[0015] Optionally, in one embodiment of the present invention, the dual working mode write circuit is composed of 2 voltage converters, 2 transmission gates and 1 logic circuit. The specific connection method is that the output of the logic circuit is input into the voltage converter, and the obtained result is connected to the bit line BL and the source line SL of the storage cell through two transmission gates respectively to complete the writing or single programming of the storage cell.

[0016] Optionally, in one embodiment of the present invention, in the readout amplifier mode, when the memory cell is read out, the read amplifier circuit starts to work, only one group of memory cells is activated by one word line WL, only data under one address is read out and at this time only one of the three memory access transistors of the memory cell is turned on; the operation of the read amplifier circuit is as follows:

[0017] In the pre-charge stage, since the word line WL is not activated, there is no closed loop in the read amplifier circuit, and there is no current flowing from the power supply through the storage cell to the ground. The capacitor in the read amplifier circuit will record the offset voltage and the threshold voltage of the PMOS tube M1 and the PMOS tube M2;

[0018] When the word line WL and the amplification stage enable signal AMP become high, the amplification stage begins. At this time, the precharge stage enable signal PRE becomes low. Both sides of the read amplifier circuit are turned on at the same time, and the voltage V at the lead node SA1 SA1 and the voltage V at the lead node SA2 SA2 It will rise rapidly first and then discharge. Due to the resistance difference between the storage unit at both ends of the read amplifier circuit and the read reference resistor, the discharge speed is different and the voltage V SA1 and voltage V SA2 A voltage difference will be generated that is related to the difference in resistance between the two ends;

[0019] A positive feedback circuit composed of two NMOS tubes and two PMOS tubes further amplifies the voltage difference and obtains a stable voltage difference at the end of the amplification stage;

[0020] At the end of the amplification phase, the voltage V SA1 and voltage V SA2 They are stored on both sides of the two transmission gates of the latch;

[0021] In the second stage of amplification, the latching phase begins when the LAT signal voltage in the latch is pulled high;

[0022] The voltages of the lead nodes SA1 and SA2 are sent to the latch for amplification, and the output of the latch circuit is the reading result.

[0023] Optionally, in one embodiment of the present invention, in normal write mode, the dual working mode write circuit is in normal write mode, only one group of storage cells is activated by a WL, only one of the three memory access transistors of the storage cell is turned on and multiple storage cells are written at one time; in normal write mode, the OTP mode enable signal of the dual working mode write circuit is high, the PMOS tube M3 is turned off, the two voltage converters are regarded as symmetrical and apply a voltage difference to the bit line BL and the source line SL of the storage cell according to the input Din0 and Din1 signals and generate a write current, completing the state conversion of the magnetic tunnel junction from antiparallel AP to parallel P or parallel P to antiparallel AP.

[0024] Optionally, in one embodiment of the present invention, in the one-time programmable OTP mode, the dual working mode write circuit corresponding to the selected storage cell is in the one-time programming OTP mode, only one group of storage cells is activated by a WL, the three memory access transistors of the storage cell are all turned on and multiple storage cells are written at one time; the dual working mode write circuit corresponding to the unselected storage cell is in the normal write mode, and the magnetic tunnel junction is written to the anti-parallel AP state; in the one-time programmable OTP mode, the OTPEN of the dual working mode write circuit is low, the PMOS tube M3 is turned on, and the output high level of the level converter on the left will be higher than the output high level in the normal write mode; in the one-time programmable OTP mode, the programming current direction of the storage cell is fixed, the level converter on the left applies a high level, and the level converter on the right applies a low level, and the magnetic tunnel junction MTJ is ensured to be broken down by reducing the voltage division of the memory access transistor and increasing the write voltage.

[0025] Optionally, in one embodiment of the present invention, the write self-termination circuit is composed of a capacitor C, a comparator COMP, an inverter, and a switch S1 between two input terminals of the comparator, and the N port of the comparator is connected to VDD. The write self-termination circuit is used to detect whether the magnetic tunnel junction is broken down in the single-time programmable OTP mode and close the write path of the storage unit that has completed the breakdown. The working principle of the write self-termination circuit is as follows:

[0026] Before starting single-shot programming, switch S1 is closed and the voltage across the comparator remains at VDD. After starting single-shot programming, switch S1 is disconnected. Since the voltage across capacitor C will not change suddenly, the voltage at the P port of the comparator will change with the voltage on the bit line BL. When the magnetic tunnel junction is broken down, the resistance drops sharply, and the voltage on the bit line BL also drops rapidly. The comparator output flips and shuts off the write path to prevent the broken-down storage cell path from taking away most of the write current.

[0027] The one-time programmable memory circuit based on the magnetic tunnel junction of the embodiment of the present invention has the following beneficial effects:

[0028] (1) The magnetic tunnel junction-based one-time programmable memory circuit of the present invention can be used as a normal memory or a one-time programmable memory to store confidential information. The Monte Carlo (MC) method is used to evaluate the impact of process fluctuations on circuit performance, while considering the statistical distribution of global and local transistor parameters. According to the simulation results, the proposed memory circuit can reduce the programming voltage to 2.5V in the one-time programmable mode, which is cheaper and faster than the expensive and time-consuming traditional solution.

[0029] (2) The magnetic tunnel junction-based single-time programmable memory circuit of the present invention adopts 55nm FDSOI process and 78nm MTJ design. In the single-time programmable mode, a write self-termination circuit is used to ensure the programming accuracy and realize multi-bit simultaneous programming. The write self-termination circuit shuts down the write path in advance to complete the writing, which can save 5% of the energy consumption for each bit of writing. Compared with writing a single bit each time, 32-bit simultaneous programming can save 98% of the writing time.

[0030] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0032] Figure 1 A schematic diagram of a single-time programmable memory circuit structure based on a magnetic tunnel junction provided according to an embodiment of the present invention;

[0033] Figure 2 A diagram showing the relationship between the magnetic tunnel junction state and the write voltage according to an embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of the structure of a 3T-1M storage unit according to an embodiment of the present invention;

[0035] Figure 4 A timing waveform diagram of reading "0" and "1" in a read amplification module according to an embodiment of the present invention;

[0036] Figure 5 is a timing waveform diagram of a write self-termination module according to an embodiment of the present invention;

[0037] Figure 6 A waveform comparison of whether or not to use a write self-termination circuit for parallel programming in an embodiment of the present invention;

[0038] Figure 7 A diagram comparing energy consumption and time for parallel programming according to an embodiment of the present invention;

[0039] Figure 8 FIG. 4 is a schematic diagram of a storage array according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0041] Figure 1 The present invention is a schematic diagram of a single-time programmable memory circuit structure based on a magnetic tunnel junction provided in accordance with an embodiment of the present invention.

[0042] like Figure 1 As shown, the single-time programmable memory circuit based on the magnetic tunnel junction includes: a read amplifier circuit, a write self-termination circuit, a dual-operation mode write circuit and a latch circuit;

[0043] The read amplifier circuit is used to amplify the voltage signal and read the storage data of the storage unit. The read amplifier circuit includes a read reference resistor and multiple storage units. The read reference resistor is used to output a reference signal during the read operation. The magnetic state in the storage unit is obtained by comparing the reference signal size with the signal size output by the memory in the same path. Each storage unit is composed of a magnetic tunnel junction and three NMOS tubes as memory access transistors. In the normal read-write mode, only one NMOS tube is turned on, and in the single-time programmable mode, three memory access transistors are turned on at the same time. The read amplifier circuit reads the storage information according to the resistance characteristics of the magnetic tunnel junction under different magnetization states;

[0044] The latch circuit and the read amplifier circuit are connected by leads and are used to detect the voltage difference change and save the data after it stabilizes;

[0045] The dual-mode write circuit is used for normal writing and single-time programming OTP operation;

[0046] The write self-termination circuit is used to detect the voltage change on the bit line of the storage unit when the dual-operation mode write circuit completes writing or programming, and sends a write termination signal to the dual-operation mode write circuit after detecting the voltage change.

[0047] In one embodiment of the present invention, MRAM is used as a new generation of non-volatile memory, and a magnetic tunnel junction MTJ is used to store information. The memory cell is composed of one magnetic tunnel junction MTJ and three N-type field effect transistors NMOS as memory access transistors, which is called a 3T-1M memory cell. The magnetic tunnel junction of the memory cell is composed of a fixed layer and a free layer with magnetic properties, and a non-magnetic oxide isolation layer; the fixed reference layer is thick, and its magnetic moment direction does not change; the free layer is thin, and its magnetic moment direction is either the same as or opposite to that of the fixed layer, which can be used to represent binary information 0 and 1. The relative magnetization direction of the fixed layer and the free layer of the magnetic tunnel junction MTJ and whether the isolation layer is broken down determine the state of the magnetic tunnel junction MTJ. Figure 2As shown in the figure, when current flows through both the bit line and the additional write information line, the combined magnetic field they generate can reverse the magnetic moment of the free layer and write information. Due to the giant magnetoresistance effect, when the directions of the magnetic moments of the free layer and the fixed reference layer are the same, the resistance of the MTJ is small, and when they are in opposite directions, the resistance of the MTJ is large. When the write current from the antiparallel AP state to the parallel P state continues to increase, the MTJ will first complete the state transition from the antiparallel AP state to the parallel P state and then be broken down from the parallel P state, and the resistance of the MTJ will decrease rapidly.

[0048] When the memory cell is used as a normal memory cell, the state of the MTJ is antiparallel AP or parallel P, and it can be written or read through the normal read-write mode; after the memory cell is programmed in the single-time programmable OTP mode, the state of the magnetic tunnel junction is antiparallel AP or breakdown state, and it can no longer be written subsequently, and can only be read through the normal read mode; when the direction of the free layer of the magnetic tunnel junction MTJ is parallel to the fixed layer, the magnetic resistance of the magnetic tunnel junction MTJ is low to R P ; When the magnetization direction of the free layer is antiparallel to the fixed layer, the magnetic resistance is high R AP ;When the oxide isolation layer of the magnetic tunnel junction MTJ is electrically broken down, the magnetic resistance can be ignored;

[0049] The memory cell access operation is controlled by the bit lines BL and BLB, the source lines SL and SLB, the word lines WL and OTPWL;

[0050] In one embodiment of the present invention, the read amplifier circuit and the latch circuit are connected by a lead SA1 and a lead SA2; the read amplifier circuit amplifies the voltage signal and reads the stored data, and includes two parts, a current-type sensitive amplifier CSA and a latch circuit, and the current-type sensitive amplifier is composed of four PMOS tubes, eight NMOS tubes and two capacitors; the gates of the two PMOS tubes are connected to the clamping voltage LOW to ensure that the data in the storage unit is not rewritten, and the gates of the two NMOS tubes are connected to the read enable signal READEN to control the operation of the read amplifier circuit, and the two capacitors can record the offset voltage in the pre-charging stage and eliminate the offset voltage in the amplification stage. In the amplification stage, the two NMOS tubes and the two PMOS tubes form a positive feedback circuit to amplify the voltage difference between the storage unit resistor and the reference resistor, and output the data in the storage unit at SA1 and SA2 in the form of high and low levels. According to whether the storage unit is programmed in the one-time programmable OTP mode, the reference resistor of the read amplifier circuit is selected through the OTPEN signal to achieve the maximum read margin.

[0051] In one embodiment of the present invention, a latch circuit is used to detect the voltage difference change and save data after stabilization, and is composed of 5 PMOS tubes, 5 NMOS tubes and 1 inverter. The specific connection method is that the input data SA1 and SA2 (SA1 and SA2 are two output signals of the reading amplifier circuit in the amplification stage, and these two output signals are input into the latch circuit as input signals in the latch stage) pass through two transmission gates composed of 1 PMOS and 1 NMOS respectively, and the obtained results are connected to the two ends of a cross-coupled inverter composed of 3 PMOS tubes and 3 NMOS tubes, so that the voltages of the left and right nodes of the cross-coupled inverter remain stable.

[0052] In one embodiment of the present invention, a dual-operating mode write circuit is used to perform normal writing or single-time programmable operations on a storage cell, and is composed of two voltage converters, two transmission gates, and a simple logic circuit. The specific connection method is that the output of the logic circuit is input into the voltage converter, and the obtained result is connected to the bit line BL and the source line SL of the storage cell through two transmission gates respectively, thereby completing the writing or single-time programming of the storage cell.

[0053] In one embodiment of the present invention, in the readout amplifier mode, when the memory cell is read out, the read amplifier circuit starts to work, only one group of memory cells is activated by a WL, only data under one address is read out and at this time only one of the three memory access transistors of the memory cell is turned on; the operation of the read amplifier circuit is as follows:

[0054] In the pre-charge stage, since WL is not activated, there is no closed loop in the read amplifier circuit, and there is no current flowing from the power supply through the storage unit to the ground. The capacitor in the read amplifier circuit will record the offset voltage and the threshold voltage of the PMOS tubes M1 and M2; when WL and AMP (AMP is the abbreviation of AMPLIFY, representing the amplification stage enable signal) become high, the amplification stage begins, and PRE (PRE is the abbreviation of PREPARE, representing the pre-charge stage enable signal) becomes low; both sides of the read amplifier circuit are turned on at the same time, and the voltage V at the node SA1 SA1 and the voltage V at node SA2 SA2 It will rise rapidly first and then discharge. Due to the resistance difference between the storage unit and the reference resistor at both ends of the read amplifier circuit, the discharge speed will be different and V SA1 and V SA2 A voltage difference related to the resistance difference between the two ends will be generated; a positive feedback circuit composed of two NMOS tubes and two PMOS tubes will further amplify this voltage difference and obtain a stable voltage difference at the end of the amplification stage; at the end of the amplification stage, V SA1 and V SA2They are stored on both sides of the two transmission gates of the latch respectively; in the second stage amplification, when the LAT (LAT is the abbreviation of LATCH, representing the latch stage enable signal) signal voltage in the latch is pulled high, the latch stage begins; the voltages of nodes SA1 and SA2 are sent to the latch for amplification, and the output of the latch circuit is the reading result.

[0055] In one embodiment of the present invention, in the normal write mode, the dual working mode write circuit is in the normal write mode, only one group of storage cells is activated by a WL, only one of the three memory access transistors of the storage cell is turned on and multiple storage cells are written at one time; in the normal write mode, the OTPEN (OTPEN is OTP ENABLE representing the OTP mode enable signal) of the dual working mode write circuit is high, the PMOS tube M3 is turned off, and the two voltage converters can be regarded as symmetrical and apply a voltage difference to the bit line BL and the source line SL of the storage cell according to the input Din0 and Din1 signals and generate a write current, completing the state conversion of the magnetic tunnel junction MTJ from anti-parallel AP to parallel P or parallel P to anti-parallel AP.

[0056] In one embodiment of the present invention, in the one-time programmable OTP mode, the dual working mode write circuit corresponding to the selected storage cell is in the one-time programming OTP mode, only one group of storage cells is activated by a WL, the three memory access transistors of the storage cell are all turned on and multiple storage cells are written at one time; the dual working mode write circuit corresponding to the unselected storage cell is in the normal write mode, and the MTJ is written to the anti-parallel AP state; in the one-time programmable OTP mode, the OTPEN of the dual working mode write circuit is low, the PMOS tube M3 is turned on, and the output high level of the level converter on the left will be higher than the output high level in the normal write mode; in the one-time programmable OTP mode, the programming current direction of the storage cell is fixed, the level converter on the left applies a high level, and the level converter on the right applies a low level, and the magnetic tunnel junction MTJ can be ensured to be broken down by reducing the voltage division of the memory access transistor and increasing the write voltage.

[0057] In one embodiment of the present invention, the write self-termination circuit is composed of a capacitor C, a comparator COMP, an inverter, and a switch S1 between two input terminals of the comparator. The N port of the comparator is connected to VDD. The write self-termination circuit is used to detect whether the magnetic tunnel junction is broken down in the single-time programmable OTP mode and close the write path of the storage unit that has been broken down. The working principle of the write self-termination circuit is as follows:

[0058] Before starting single-shot programming, S1 is closed and the voltage across the comparator remains at VDD. After starting single-shot programming, S1 is disconnected. Since the voltage across capacitor C will not change suddenly, the voltage at the P port of the comparator will change with the voltage on the bit line BL. When the magnetic tunnel junction MTJ is broken down, the resistance drops sharply, and the voltage on the bit line BL also drops rapidly. The comparator output flips and shuts off the write path to prevent the broken-down storage cell path from taking away most of the write current.

[0059] like Figure 1 As shown in the figure, a memory cell of MRAM consists of a magnetic tunnel junction MTJ and three NMOS transistors. Only the selected memory cell in the one-time programmable (OTP) mode will turn on the three NMOS transistors at the same time. At other times, only one NMOS transistor will be turned on in the selected memory cell. Due to the reduction of the voltage divider of the memory access transistor, the memory circuit can reduce the programming voltage to 2.5V in the one-time programmable mode. Its specific structure is as follows Figure 3 As shown. The read amplifier circuit can read the stored information according to the resistance characteristics of the MTJ under different magnetization states. The latch circuit latches the data when it recognizes that the voltage difference between the data unit and the reference resistor reaches the threshold. The dual-mode write circuit can perform both normal writing and single-time programming (OTP). The write self-termination circuit can shut down the write path that completes the writing in the OTP mode.

[0060] In the read amplifier circuit, the access operation of the memory cell is controlled by the bit line (BL and BLB), source line (SL and SLB), word line (WL) and read enable (REN). In the pre-charge stage, BL and BLB are charged at a high level under the control of the signals PRE and AMP. Since WL is not activated, there is no closed loop and no current flows through the entire circuit. When WL and AMP become high levels, the amplification stage begins. In the amplification stage, two NMOS tubes and two PMOS tubes form a positive feedback circuit to amplify the voltage difference between the memory cell resistance and the reference resistance, and output the data in the memory cell at SA1 and SA2 in the form of high and low levels. When the memory circuit has not been OTP programmed, R1 is always selected as the reference resistor when reading, and the resistance value of R2 is approximately (R AP +R P ) / 2; When LAT is high, the latching phase begins. The voltages at SA1 and SA2 are sent to the latch for a second amplification. The output of the latch is the result of two-stage amplification. The timing of the read amplifier circuit is as follows Figure 4 shown.

[0061] In the dual working mode write circuit, OTPEN controls the writing circuit working mode. When OTPEN is low, PMOS tube M3 is turned on, and the output high level of the level converter on the left will be higher than the output high level in the normal writing mode. The timing of the writing self-termination circuit is as follows Figure 5As shown, before the start of single-shot programming, the voltage VP and VN of the comparator are kept at VDD. After the start of single-shot programming, the voltage VP of the comparator P port will change with the change of the voltage on the bit line BL. When the magnetic tunnel junction MTJ is broken down, the resistance drops sharply, the voltage on the bit line BL also drops rapidly, and the comparator output signal WS flips. Using a write self-termination circuit for parallel OTP programming can prevent the write path that has been broken down from being shunted, keep the write current of the remaining storage cells that have not been written to the critical breakdown current, and continue to complete the writing; if there is no write self-termination circuit, the broken down storage cell will take away most of the current, and the write current of the storage cell that has not been written to the breakdown will not reach the current required for breakdown. Figure 6 A comparison of waveforms showing parallel programming with and without write self-termination circuitry.

[0062] Figure 7 The energy consumption and time comparison chart of parallel programming is shown. Parallel programming can save 98% of programming time. Compared with bit-by-bit serial programming, it can save energy for updating address and data signals, and each bit of programming can save 5% of energy. Figure 8 The schematic diagram of the storage array formed by adding a decoding circuit, a word line driver, a bit line driver, etc. to the single-time programmable memory circuit based on the magnetic tunnel junction of the present invention is shown.

[0063] The single-time programmable memory circuit based on a magnetic tunnel junction proposed in an embodiment of the present invention has two working modes: a normal read-write mode and a single-time programmable OTP mode. The memory cell is composed of a magnetic tunnel junction and three memory access transistors. In the normal read-write mode, only one memory access transistor is turned on; in the single-time programmable mode, the other two memory access transistors are also turned on to reduce the voltage division and increase the programming current. At the same time, multi-bit parallel programming is realized through the peripheral self-termination write circuit to ensure the success rate of writing. The proposed memory circuit can reduce the programming voltage to 2.5V in the single-time programmable mode. The self-termination write circuit can save 5% of the energy consumption per bit of writing, and 32-bit parallel programming can save 98% of the programming time.

[0064] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0065] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "N" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

Claims

1. A single-time programmable memory circuit based on a magnetic tunnel junction, characterized in that: include: Read amplifier circuit, write self-termination circuit, dual working mode write circuit and latch circuit; The read amplifier circuit is used to amplify the voltage signal and read the storage data of the storage unit. The read amplifier circuit includes a read reference resistor and multiple storage units. The read reference resistor is used to output a reference signal during the read operation. The magnetic state in the storage unit is obtained by comparing the reference signal size with the signal size output by the memory in the same path. Each storage unit is composed of a magnetic tunnel junction and three NMOS tubes as memory access transistors. In the normal read-write mode, only one NMOS tube is turned on, and in the single-time programmable mode, three memory access transistors are turned on at the same time. The read amplifier circuit reads the storage information according to the resistance characteristics of the magnetic tunnel junction under different magnetization states; The latch circuit and the read amplifier circuit are connected by leads and are used to detect the voltage difference change and save data after it stabilizes; The dual working mode write circuit is used for performing normal writing and single programming OTP operation; The write self-termination circuit is used to detect the voltage change on the bit line of the storage unit when the dual working mode write circuit completes writing or programming, and sends a write termination signal to the dual working mode write circuit after detecting the voltage change.

2. The magnetic tunnel junction-based single-time programmable memory circuit according to claim 1, characterized in that: The magnetic tunnel junction of the storage unit is composed of a fixed layer, a free layer and an oxide isolation layer made of magnetic media; the magnetic moment direction of the fixed reference layer does not change; the magnetic moment direction of the free layer is the same as or opposite to that of the fixed layer. The relative magnetization direction of the fixed layer and the free layer of the magnetic tunnel junction and whether the oxide isolation layer breaks down determine the state of the magnetic tunnel junction; When the memory cell is used as a normal memory cell, the state of the magnetic tunnel junction is antiparallel AP or parallel P, and it can be written or read through the normal read-write mode; after the memory cell is programmed in the single-time programmable OTP mode, the state of the magnetic tunnel junction is antiparallel AP or breakdown state, and it can no longer be written subsequently, and can only be read through the normal read mode; when the direction of the free layer of the magnetic tunnel junction is parallel to the fixed layer, the magnetic resistance of the magnetic tunnel junction is low to R P ; When the magnetization direction of the free layer is antiparallel to the fixed layer, the magnetic resistance is high R AP ;When the oxide isolation layer of the magnetic tunnel junction is electrically broken down, the magnetic resistance can be ignored; The memory cell access operation is controlled by the bit lines BL and BLB, the source lines SL and SLB, and the word lines WL and OTPWL.

3. The single-time programmable memory circuit based on a magnetic tunnel junction according to claim 1, characterized in that: The read amplifier circuit includes two parts: a current-type sensitive amplifier CSA and a latch circuit. The current-type sensitive amplifier is composed of four PMOS tubes, eight NMOS tubes and two capacitors. The gates of the two PMOS tubes are connected to a clamping voltage LOW to ensure that the data in the storage unit is not rewritten. The gates of the two NMOS tubes are connected to a read enable signal READEN to control the operation of the read amplifier circuit. The two capacitors record the offset voltage in the pre-charging stage and eliminate the offset voltage in the amplification stage. In the amplification stage, the two NMOS tubes and the two PMOS tubes form a positive feedback circuit to amplify the voltage difference between the storage unit resistance and the read reference resistance, and output the data in the storage unit in the form of high and low levels at the leads SA1 and SA2 of the latch circuit and the read amplifier circuit. According to whether the storage unit is programmed in the one-time programmable OTP mode, the reference resistance of the read amplifier circuit is selected through the OTPEN signal to achieve the maximum read margin.

4. The single-time programmable memory circuit based on a magnetic tunnel junction according to claim 1, characterized in that: The latch circuit is composed of 5 PMOS tubes, 5 NMOS tubes and 1 inverter. The specific connection method is that the two input data of the read amplifier circuit pass through two transmission gates composed of 1 PMOS and 1 NMOS respectively, and the obtained results are connected to the two ends of a cross-coupled inverter composed of 3 PMOS tubes and 3 NMOS tubes, so that the voltages of the left and right nodes of the cross-coupled inverter remain stable.

5. The magnetic tunnel junction based single-time programmable memory circuit according to claim 1, characterized in that: The dual working mode write circuit is composed of 2 voltage converters, 2 transmission gates and 1 logic circuit. The specific connection method is that the output of the logic circuit is input into the voltage converter, and the obtained result is connected to the bit line BL and the source line SL of the storage cell through two transmission gates respectively to complete the writing or single programming of the storage cell.

6. The magnetic tunnel junction based single-time programmable memory circuit according to claim 1, characterized in that: In the readout amplifier mode, when the memory cell is read out, the read amplifier circuit starts to work, only one group of memory cells is activated by one word line WL, only the data under one address is read out and at this time only one of the three memory access transistors of the memory cell is turned on; the operation of the read amplifier circuit is as follows: In the pre-charge stage, since the word line WL is not activated, there is no closed loop in the read amplifier circuit, and there is no current flowing from the power supply through the storage cell to the ground. The capacitor in the read amplifier circuit will record the offset voltage and the threshold voltage of the PMOS tube M1 and the PMOS tube M2; When the word line WL and the amplification stage enable signal AMP become high, the amplification stage begins. At this time, the precharge stage enable signal PRE becomes low. Both sides of the read amplifier circuit are turned on at the same time, and the voltage V at the lead node SA1 SA1 and the voltage V at the lead node SA2 SA2 It will rise rapidly first and then discharge. Due to the resistance difference between the storage unit at both ends of the read amplifier circuit and the read reference resistor, the discharge speed is different and the voltage V SA1 and voltage V SA2 A voltage difference will be generated that is related to the difference in resistance between the two ends; A positive feedback circuit composed of two NMOS tubes and two PMOS tubes further amplifies the voltage difference and obtains a stable voltage difference at the end of the amplification stage; At the end of the amplification phase, the voltage V SA1 and voltage V SA2 They are stored on both sides of the two transmission gates of the latch; In the second stage of amplification, the latching phase begins when the LAT signal voltage in the latch is pulled high; The voltages of the lead nodes SA1 and SA2 are sent to the latch for amplification, and the output of the latch circuit is the reading result.

7. The magnetic tunnel junction based single-time programmable memory circuit according to claim 1, characterized in that: In the normal write mode, the dual working mode write circuit is in the normal write mode, only one group of storage cells is activated by a WL, only one of the three memory access transistors of the storage cell is turned on and multiple storage cells are written at one time; in the normal write mode, the OTP mode enable signal of the dual working mode write circuit is high, the PMOS tube M3 is turned off, the two voltage converters are regarded as symmetrical and apply a voltage difference to the bit line BL and the source line SL of the storage cell according to the input Din0 and Din1 signals and generate a write current, completing the state conversion of the magnetic tunnel junction from antiparallel AP to parallel P or parallel P to antiparallel AP.

8. The magnetic tunnel junction based single-time programmable memory circuit according to claim 1, characterized in that: In the one-time programmable OTP mode, the dual-operating mode write circuit corresponding to the selected storage cell is in the one-time programming OTP mode, only one group of storage cells is activated by a WL, the three memory access transistors of the storage cell are all turned on and multiple storage cells are written at one time; the dual-operating mode write circuit corresponding to the unselected storage cell is in the normal write mode, and the magnetic tunnel junction is written to the anti-parallel AP state; in the one-time programmable OTP mode, the OTPEN of the dual-operating mode write circuit is low, the PMOS tube M3 is turned on, and the output high level of the level converter on the left will be higher than the output high level in the normal write mode; in the one-time programmable OTP mode, the programming current direction of the storage cell is fixed, the level converter on the left applies a high level, and the level converter on the right applies a low level, and the magnetic tunnel junction is ensured to be broken down by reducing the voltage division of the memory access transistor and increasing the write voltage.

9. The magnetic tunnel junction based single-time programmable memory circuit according to claim 1, characterized in that: The write self-termination circuit is composed of a capacitor C, a comparator COMP, an inverter and a switch S1 between two input terminals of the comparator. The N port of the comparator is connected to VDD. The write self-termination circuit is used to detect whether the magnetic tunnel junction is broken down in the single-time programmable OTP mode and close the write path of the storage unit that has been broken down. The working principle of the write self-termination circuit is as follows: Before starting single-shot programming, switch S1 is closed and the voltage across the comparator remains at VDD. After starting single-shot programming, switch S1 is disconnected. Since the voltage across capacitor C will not change suddenly, the voltage at the P port of the comparator will change with the voltage on the bit line BL. When the magnetic tunnel junction is broken down, the resistance drops sharply, and the voltage on the bit line BL also drops rapidly. The comparator output flips and shuts off the write path to prevent the broken-down storage cell path from taking away most of the write current.

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