Voltage determination circuit and memory

Abstract

The application discloses a voltage determination circuit and a memory. The voltage determination circuit comprises a first determination module, a second determination module and a third determination module. The second determination module determines a second read potential value of a word line based on a target error number and a first read potential value provided by the first determination module. The third determination module determines a third read potential value of a second word line based on the first read potential value or the second read potential value. Therefore, the storage unit can be applied with more accurate read voltage according to the first read potential value, the second read potential value and the third read potential value, and the accuracy of the read voltage is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, in particular to a voltage determination circuit and a memory. BACKGROUND

[0002] In a three-dimensional phase change memory, a read voltage applied to a memory cell is closely related to data extraction of a final product, device power consumption and service life.

[0003] Therefore, how to accurately determine the read voltage becomes a problem to be solved. SUMMARY

[0004] The present application provides a voltage determination circuit and a memory to alleviate the technical problem of low accuracy of the read voltage.

[0005] In a first aspect, the present application provides a voltage determination circuit, which is applied to a memory, the memory comprising a first bit line, a second bit line, a word line, a first memory cell and a second memory cell, the first memory cell being connected with the first bit line and the word line, the second memory cell being connected with the second bit line and the word line, the voltage determination circuit comprising a first determination module, a second determination module and a third determination module, the first determination module being configured to determine a first read potential value of the first bit line; the second determination module being connected with the first determination module, the second determination module being configured to determine a second read potential value of the word line based on a target error number and the first read potential value; the third determination module being connected with at least one of the first determination module and the second determination module, the third determination module being configured to determine a third read potential value of the second bit line based on the first read potential value or the second read potential value.

[0006] In a second aspect, the present application provides a memory, which comprises a first bit line, a second bit line, a word line, a first memory cell, a second memory cell and the above-mentioned voltage determination circuit, the first memory cell being connected with the first bit line and the word line, the second memory cell being connected with the second bit line and the word line.

[0007] The voltage determination circuit and the memory provided by the present application can apply a relatively accurate read voltage to the memory cell according to the first read potential value, the second read potential value and the third read potential value, thereby improving the accuracy of the read voltage. BRIEF DESCRIPTION OF DRAWINGS

[0008] The technical solutions and other advantages of the present application will be apparent from the following detailed description of the specific embodiments of the present application, taken in conjunction with the accompanying drawings.

[0009] Figure 1 A structural schematic diagram of a storage array in the related art.

[0010] Figure 2 A schematic diagram of a normal distribution of threshold voltages of storage units.

[0011] Figure 3 A first principle block diagram of a voltage determination circuit provided by an embodiment of the present application.

[0012] Figure 4 A first principle block diagram of a second determination module.

[0013] Figure 5 A schematic diagram of a relationship between a cumulative error number and a read voltage provided by an embodiment of the present application.

[0014] Figure 6 A principle block diagram of a first acquisition unit provided by an embodiment of the present application.

[0015] Figure 7 A first principle block diagram of a third determination module provided by an embodiment of the present application.

[0016] Figure 8 A second principle block diagram of a second determination module.

[0017] Figure 9 A principle block diagram of a second acquisition unit provided by an embodiment of the present application.

[0018] Figure 10 A second principle block diagram of a third determination module provided by an embodiment of the present application.

[0019] Figure 11 A schematic diagram of a relationship between a read voltage and a bit line voltage provided by an embodiment of the present application.

[0020] Figure 12 A second principle block diagram of a voltage determination circuit provided by an embodiment of the present application.

[0021] Figure 13 A principle block diagram of a memory provided by an embodiment of the present application. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative work fall within the scope of protection of the present application.

[0023] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Features thus defined as "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more unless otherwise explicitly specified.

[0024] Figure 1 The diagram shows the structure of a storage array in a three-dimensional phase-change memory. The storage array includes a first bit line BL1, a second bit line BL2, a word line WL, a first storage cell PCM1, and a second storage cell PCM2. The first storage cell PCM1 is connected to the first bit line BL1 and the word line WL, and the second storage cell PCM2 is connected to the second bit line BL2 and the word line WL. Notably, the first storage cell PCM1 and the second storage cell PCM2, located in the same column, share the same word line WL. This reduces the number of word lines WL used and also helps to reduce the number of power supplies required to provide the corresponding voltage to the word line WL.

[0025] Figure 2 This diagram illustrates the normal distribution of threshold voltages for memory cells. The vertical axis, Count, represents the number of memory cells, and the horizontal axis, Vt, represents the threshold voltage of the memory cells. Curve W1 represents the normal distribution of threshold voltages in the SET state, and curve W2 represents the normal distribution of threshold voltages in the RESET state. It can be seen that the minimum threshold voltage shown by curve W2 is greater than the maximum threshold voltage shown by curve W1.

[0026] As the memory usage time increases, both the first curve W1 and the second curve W2 will shift to the right. To ensure that the correct data "1" can be read from the memory cell shown by the first curve W1 and the correct data "0" can be read from the memory cell shown by the second curve W2, the read voltage Vread can be selected as a value between the maximum threshold voltage shown by the first curve W1 and the minimum threshold voltage shown by the second curve W2, for example, Vt in the RESET state. -3.5σ The value of . This ensures that the correct data "0" is read from the storage cell shown by the second curve W2, while allowing sufficient time for the first curve W1 to drift.

[0027] In this process, gradually increasing the read voltage Vread applied to the memory cell in the RESET state will result in reading erroneous data "1" from the memory cell shown by the second curve W2. The number of erroneous data "1" read is the cumulative number of errors.

[0028] This embodiment provides a voltage determination circuit 100. Please refer to [link / reference]. Figures 3 to 11 ,likeFigure 3 As shown, the voltage determination circuit 100 comprises a first determination module 10, a second determination module 20, and a third determination module 30. The first determination module 10 is configured to determine a first read potential value Vb1 of the first bit line BL1. The second determination module 20 is connected with the first determination module 10, and is configured to determine a second read potential value Vb2 of the word line WL based on the target error number and the first read potential value Vb1. The third determination module 30 is connected with at least one of the first determination module 10 and the second determination module 20, and is configured to determine a third read potential value Vb3 of the second bit line BL2 based on the first read potential value Vb1 or the second read potential value Vb2.

[0029] It can be understood that, by means of the voltage determination circuit 100 provided in the embodiment, the second determination module 20 determines the second read potential value Vb2 of the word line WL based on the target error number and the first read potential value Vb1 provided by the first determination module 10, and the third determination module 30 determines the third read potential value Vb3 of the second bit line BL2 based on the first read potential value Vb1 or the second read potential value Vb2, so that the storage unit can be applied with a more accurate read voltage Vread according to the first read potential value Vb1, the second read potential value Vb2, and the third read potential value Vb3, and thus the accuracy of the read voltage Vread is improved.

[0030] It should be noted that the first read potential value Vb1 can be preset or fixed. The target error number corresponds to the cumulative error number, and both represent the number of error data "1" read from the storage unit shown in the second curve W2, wherein the target error number is a preset integer value.

[0031] In some embodiments, as shown in FIG. 2, the first determination module 10 comprises a first error number determination module 11 and a first read potential value determination module 12. The first error number determination module 11 is configured to determine the target error number based on the cumulative error number and the first read potential value Vb1. The first read potential value determination module 12 is connected with the first error number determination module 11, and is configured to determine the first read potential value Vb1 based on the target error number. Figure 4As shown, the second determining module 20 comprises a first obtaining unit 21, a first determining unit 22 and a first adding unit 23. The first obtaining unit 21 is configured to obtain a first parameter curve of the first storage unit PCM1 and a second parameter curve of the second storage unit PCM2. The first parameter curve is a curve of the cumulative error number of the first storage unit PCM1 and the read voltage Vread, and the second parameter curve is a curve of the cumulative error number of the second storage unit PCM2 and the read voltage Vread. The first determining unit 22 is connected with the first obtaining unit 21. The first determining unit 22 is configured to determine a first target read voltage value of the first storage unit PCM1 according to the target error number and the first parameter curve, and determine a second target read voltage value of the second storage unit PCM2 according to the target error number and the second parameter curve. The first adding unit 23 is connected with the first determining module 10 and the first determining unit 22. The first adding unit 23 is configured to calculate a sum of the first read potential value Vb1 and the first target read voltage value as a second read potential value Vb2.

[0032] It should be noted that the cumulative error number of the first storage unit PCM1 can be equal to the cumulative error number of the second storage unit PCM2, or the cumulative error number of the first storage unit PCM1 can be greater than or less than the cumulative error number of the second storage unit PCM2.

[0033] Figure 5 The relationship between the cumulative error number and the read voltage Vread provided by the embodiment of the present application is shown in the figure.

[0034] In the figure, the vertical axis EN1 represents the cumulative error number, and the horizontal axis Vread represents the read voltage Vread. S1 represents the first parameter curve, S2 represents the second parameter curve, and SD1 represents the ideal curve of the cumulative error number and the read voltage Vread. Vread1 represents the first target read voltage value, Vread2 represents the second target read voltage value, and MEN1 represents the target error number.

[0035] In some embodiments, as shown in the figure, Figure 6 The first obtaining unit 21 comprises a first scanning sub-unit 211 and a first statistical sub-unit 212. The first scanning sub-unit 211 is configured to gradually increase the second read potential value Vb2 for the first storage unit PCM1 and the second storage unit PCM2 respectively. The first statistical sub-unit 212 is connected with the first scanning sub-unit 211 and the first determining unit 22. The first statistical sub-unit 212 is configured to statistically obtain the cumulative error number of the first storage unit PCM1 and the read voltage Vread, and the cumulative error number of the second storage unit PCM2 and the read voltage Vread based on the second read potential value Vb2, and obtain the first parameter curve and the second parameter curve.

[0036] It should be noted that the manner of obtaining the first parameter curve and the second parameter curve provided in this embodiment is only for example, and is not limited thereto, and other manners capable of obtaining the first parameter curve and the second parameter curve can also be used.

[0037] In some embodiments, as shown in FIG. 1, the third determining module 30 includes a first subtraction unit 31 and a second subtraction unit 32. Figure 7 The first subtraction unit 31 is connected with the first determining unit 22, and is configured to calculate a first difference value between the first target read voltage value and the second target read voltage value; the second subtraction unit 32 is connected with the first determining module 10 and the first subtraction unit 31, and is configured to calculate a second difference value between the first read potential value Vb1 and the first difference value as a third read potential value Vb3.

[0038] It should be noted that the determination of the second read potential value Vb2 and the third read potential value Vb3 is realized through corresponding calculation, and in the process of calculation, the compensation of the second read potential value Vb2 and the third read potential value Vb3 is also realized, thereby improving the accuracy of the second read potential value Vb2 and the third read potential value Vb3. The read voltage Vread of the first storage unit PCM1 is obtained by subtracting the first read potential value Vb1 from the second read potential value Vb2, and the read voltage Vread of the second storage unit PCM2 is obtained by subtracting the third read potential value Vb3 from the second read potential value Vb2. In this way, the read voltage Vread of the first storage unit PCM1 and the read voltage Vread of the second storage unit PCM2 are also compensated, thereby improving the accuracy of the read voltage Vread of the first storage unit PCM1 and the read voltage Vread of the second storage unit PCM2.

[0039] In some embodiments, as shown in FIG. 1, the second determining module 20 includes a second acquisition unit 24, a second determining unit 25, and a second addition unit 26. Figure 8 The second acquisition unit 24 is configured to acquire a first parameter curve of the first storage unit PCM1, the first parameter curve being a relationship curve between the cumulative error number and the read voltage Vread of the first storage unit PCM1; the second determining unit 25 is connected with the second acquisition unit 24, and is configured to determine the first target read voltage value of the first storage unit PCM1 according to the target error number and the first parameter curve; the second addition unit 26 is connected with the first determining module 10 and the second determining unit 25, and is configured to calculate the sum of the first read potential value Vb1 and the first target read voltage value as the second read potential value Vb2.

[0040] It should be noted that the second determining module 20 in this embodiment reduces the process of obtaining the second parameter curve, which is beneficial to improve the efficiency of voltage determination.

[0041] In some embodiments, as shown in Figure 9 The second obtaining unit 24 includes a second scanning sub-unit 241 and a second statistical sub-unit 242. The second scanning sub-unit 241 is configured to gradually raise the second read potential value Vb2 of the first storage unit PCM1. The second statistical sub-unit 242 is connected with the second determining unit 25. The second statistical sub-unit 242 is configured to count the cumulative error number and the read voltage Vread of the first storage unit PCM1 according to the first read potential value Vb1 and the second read potential value Vb2, and obtain the first parameter curve.

[0042] It should be noted that the second obtaining unit 24 in this embodiment scans the second read potential value Vb2 of the second storage unit PCM2, and reduces the statistics of the second parameter curve, which is beneficial to improve the efficiency.

[0043] In some embodiments, as shown in Figure 10 The third determining module 30 includes a third obtaining unit 33, a third determining unit 34, and a third subtraction unit 35. The third obtaining unit 33 is configured to obtain the second parameter curve of the second storage unit PCM2. The second parameter curve is a relationship curve between the cumulative error number and the read voltage Vread of the second storage unit PCM2. The third determining unit 34 is connected with the third obtaining unit 33. The third determining unit 34 is configured to determine the second target read voltage value of the second storage unit PCM2 according to the target error number and the second parameter curve. The third subtraction unit 35 is connected with the second addition unit 26 and the third determining unit 34. The third subtraction unit 35 is configured to calculate a third difference value between the second read potential value Vb2 and the second target read voltage value as a third read potential value Vb3.

[0044] It should be noted that the third read potential value Vb3 is obtained by scanning the voltage of the second bit line BL2 of the second storage unit PCM2 in this embodiment, which can accurately find the critical value of the read voltage Vread, effectively avoid overcompensation and undercompensation phenomenon, and increase the read window of time drift.

[0045] Figure 11A schematic diagram of the relationship between the read voltage Vread and the bit line voltage is provided for the embodiments of the present application. The Vbl shown on the horizontal axis is the potential of the first bit line BL1 or the potential of the second bit line BL2, and the Vread shown on the vertical axis represents the read voltage Vread. The line represented by Q1 represents the ideal shift curve of the read voltage Vread when the voltage of the bottom bit line is -2.4V, and the voltage of the bottom bit line changes by 100mV, and the corresponding read voltage Vread also changes by 100mV. The line represented by Q2 represents the change trend of the read voltage Vread of the top storage unit actually measured. Delta-Vr represents the difference between Q1 and Q2 when Vbl is 2.4V.

[0046] Since the read voltage Vread of the storage unit can change with the bit line voltage, direct compensation of the bit line voltage by the difference can result in under-compensation or over-compensation. As shown in the figure, direct compensation of the bit line voltage results in the intersection of the dashed line and Q1, i.e., F2, but at this bit line voltage, the actual read voltage Vread is the intersection of Q2 and the dashed line, i.e., F1, which results in over-compensation. By using the working mode of the third determination module 30 shown in Figure 10 , the cumulative error number and the read voltage Vread can be scanned as shown by SD1 in Figure 5 , so that a more suitable read voltage Vread can be found, thereby improving or avoiding the phenomenon of over-compensation or under-compensation.

[0047] In some embodiments, as shown in Figure 12 , the voltage determination circuit 100 further includes a storage module 40, which is connected with the first determination module 10, the second determination module 20 and the third determination module 30, and the storage module 40 is configured to store the first read potential value Vb1, the second read potential value Vb2 and the third read potential value Vb3.

[0048] It should be noted that the present embodiment can archive the read potential values by the storage module 40, so as to conduct subsequent research and use of the read potential values.

[0049] In some embodiments, please continue to refer to Figure 1 , the first storage unit PCM1 is one of the top storage unit and the bottom storage unit in the same column, and the second storage unit PCM2 is the other one of the top storage unit and the bottom storage unit in the same column.

[0050] It should be noted that the first storage unit PCM1 is a top layer storage unit in the same column, and the first bit line BL1 is a top layer bit line; the second storage unit PCM2 is a bottom layer storage unit in the same column, and the second bit line BL2 is a bottom layer bit line. Alternatively, the first storage unit PCM1 is a bottom layer storage unit in the same column, and the first bit line BL1 is a bottom layer bit line; the second storage unit PCM2 is a top layer storage unit in the same column, and the second bit line BL2 is a top layer bit line. The word line WL is located between the top layer bit line and the bottom layer bit line.

[0051] In some embodiments, please refer to Figure 1 and Figure 3 , the embodiments provide a memory, which comprises a first bit line BL1, a second bit line BL2, a word line WL, a first storage unit PCM1, a second storage unit PCM2, and the voltage determination circuit 100 described above, the first storage unit PCM1 is connected with the first bit line BL1 and the word line WL, and the second storage unit PCM2 is connected with the second bit line BL2 and the word line WL.

[0052] It can be understood that, since the memory provided by the embodiments comprises the voltage determination circuit 100 described above, the second determination module 20 can also determine the second read potential value Vb2 of the word line WL based on the target error number and the first read potential value Vb1 provided by the first determination module 10, and the third determination module 30 determines the third read potential value Vb3 of the second bit line BL2 based on the first read potential value Vb1 or the second read potential value Vb2, so that a more accurate read voltage Vread can be applied to the storage unit according to the first read potential value Vb1, the second read potential value Vb2 and the third read potential value Vb3, thereby improving the accuracy of the read voltage Vread.

[0053] It should be noted that the memory in the embodiments can be, but is not limited to, a three-dimensional phase change memory, and can also be a two-layer or more three-dimensional phase change memory, or other applicable three-dimensional memory.

[0054] In some embodiments, as shown in Figure 13 , the memory further comprises a first power supply 70, a second power supply 80 and a third power supply 90, the first power supply 70 is connected with the first bit line BL1 and the storage module 40, and is configured to provide a voltage for the first bit line BL1 according to the first read potential value Vb1 in the read operation; the second power supply 80 is connected with the word line WL and the storage module 40, and is configured to provide a voltage for the word line WL according to the second read potential value Vb2 in the read operation; the third power supply 90 is connected with the second bit line BL2 and the storage module 40, and is configured to provide a voltage for the second bit line BL2 according to the third read potential value Vb3 in the read operation.

[0055] It should be noted that the embodiment can apply appropriate and accurate read voltage Vread to each storage unit through three power supplies, compared with the scheme of using two power supplies for the same word line WL, and one power supply is used to provide corresponding voltage for the word line WL, thereby reducing the number of power supplies.

[0056] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0057] The voltage determination circuit and the memory provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples. The above embodiment is only used to help understand the technical solutions and core ideas of the present application; those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A voltage determination circuit, characterized by, The voltage determination circuit is applied to a memory, the memory comprising a first bit line, a second bit line, a word line, a first storage unit and a second storage unit, the first storage unit being connected with the first bit line and the word line, the second storage unit being connected with the second bit line and the word line, the voltage determination circuit comprising: a first determination module configured to determine a first read potential value of the first bit line; a second determination module connected with the first determination module, the second determination module being configured to determine a second read potential value of the word line based on a target error number and the first read potential value; a third determination module connected with at least one of the first determination module and the second determination module, the third determination module being configured to determine a third read potential value of the second bit line based on the first read potential value or the second read potential value.

2. The voltage determination circuit of claim 1, wherein, The second determination module comprises: a first acquisition unit configured to acquire a first parameter curve of the first storage unit and a second parameter curve of the second storage unit, the first parameter curve being a relationship curve between a cumulative error number and a read voltage of the first storage unit, the second parameter curve being a relationship curve between a cumulative error number and a read voltage of the second storage unit; a first determination unit connected with the first acquisition unit, the first determination unit being configured to determine a first target read voltage value of the first storage unit according to the target error number and the first parameter curve, and determine a second target read voltage value of the second storage unit according to the target error number and the second parameter curve; a first addition unit connected with the first determination module and the first determination unit, the first addition unit being configured to calculate a sum of the first read potential value and the first target read voltage value as the second read potential value.

3. The voltage determination circuit of claim 2, wherein, The first acquisition unit comprises: a first scanning sub-unit configured to gradually raise the second read potential value for the first storage unit and the second storage unit respectively; a first statistical sub-unit connected with the first scanning sub-unit and the first determination unit, the first statistical sub-unit being configured to statistically acquire cumulative error numbers and read voltages of the first storage unit and the second storage unit based on the second read potential value, and obtain the first parameter curve and the second parameter curve.

4. The voltage determination circuit of claim 2, wherein, The third determination module comprises: a first subtraction unit connected with the first determination unit, the first subtraction unit being configured to calculate a first difference value between the first target read voltage value and the second target read voltage value; a second subtraction unit, connected with the first determination module and the first subtraction unit, configured to calculate a second difference value between the first reading potential value and the first difference value as the third reading potential value.

5. The voltage determination circuit of claim 1, wherein, The second determination module comprises: a second acquisition unit, configured to acquire a first parameter curve of the first storage unit, the first parameter curve being a relationship curve between cumulative error number and reading voltage of the first storage unit; a second determination unit, connected with the second acquisition unit, configured to determine a first target reading voltage value of the first storage unit according to the target error number and the first parameter curve; a second addition unit, connected with the first determination module and the second determination unit, configured to calculate a sum of the first reading potential value and the first target reading voltage value as the second reading potential value.

6. The voltage determination circuit of claim 5, wherein, The second acquisition unit comprises: a second scanning sub-unit, configured to gradually raise the second reading potential value for the first storage unit; a second statistical sub-unit, connected with the second determination unit, configured to statistically acquire cumulative error number and reading voltage of the first storage unit according to the first reading potential value and the second reading potential value, and obtain the first parameter curve.

7. The voltage determination circuit of claim 5, wherein, The third determination module comprises: a third acquisition unit, configured to acquire a second parameter curve of the second storage unit, the second parameter curve being a relationship curve between cumulative error number and reading voltage of the second storage unit; a third determination unit, connected with the third acquisition unit, configured to determine a second target reading voltage value of the second storage unit according to the target error number and the second parameter curve; a third subtraction unit, connected with the second addition unit and the third determination unit, configured to calculate a third difference value between the second reading potential value and the second target reading voltage value as the third reading potential value.

8. The voltage determination circuit according to any one of claims 1 to 7, characterized in that The voltage determination circuit further comprises a storage module, connected with the first determination module, the second determination module and the third determination module, configured to store the first reading potential value, the second reading potential value and the third reading potential value.

9. A memory, comprising: The memory comprises: a first bit line, a second bit line, a word line, a first storage unit and a second storage unit, the first storage unit being connected with the first bit line and the word line, the second storage unit being connected with the second bit line and the word line; The voltage determination circuit according to any one of claims 1-8.

10. The memory of claim 9, wherein, The memory further comprises: a first power supply, connected with the first bit line and the storage module, configured to provide a voltage for the first bit line according to the first read potential value in a read operation; a second power supply, connected with the word line and the storage module, configured to provide a voltage for the word line according to the second read potential value in a read operation; a third power supply, connected with the second bit line and the storage module, configured to provide a voltage for the second bit line according to the third read potential value in a read operation.

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